EE315A

VLSI Signal Conditioning Circuits

- Autumn 2014 -

Boris Murmann
Stanford University
[email protected]

Table of Contents

Chapter 1 Introduction
Chapter 2 Precision Techniques
Chapter 3 Switched Capacitor Gain Stages
Chapter 4 Operational Transconductance Amplifiers I
Chapter 5 Operational Transconductance Amplifiers II
Chapter 6 Continuous Time Filters: Biquads
Chapter 7 Continuous Time Filters: Ladders
Chapter 8 Integrator Realization & Nonidealities
Chapter 9 Switched Capacitor Filters
Chapter 10 Physical Layout
(This page is intentionally left blank)
 Introduction

Boris Murmann
Stanford University
[email protected]
Copyright © 2014 by Boris Murmann

B. Murmann EE315A - Chapter 1 1

Mixed Signal System

EE252 EE214A,B EE264

EE312 EE314A,B EE315B EE371
... EE315A ...

Signal
A/D
Conditioning
Analog
Digital
Media and
Processing
Transducers Signal
D/A
Conditioning

Sensors, Actuators,
Antennas, Storage Media, ...

B. Murmann EE315A - Chapter 1 2

 Signal Conditioning

(′sig·nəl kən′dish·ən·iŋ) (communications) Processing the form or mode

of a signal so as to make it intelligible to or compatible with a given
device, such as a data transmission line, including such manipulation
as pulse shaping, pulse clipping, digitizing, and linearizing.
[www.answers.com]

In electronics, signal conditioning means manipulating an analogue

signal in such a way that it meets the requirements of the next stage
for further processing.
Signal conditioning can include amplification, filtering, converting,
range matching, isolation and any other processes required to make
sensor output suitable for processing after conditioning.
[http://en.wikipedia.org]

B. Murmann EE315A - Chapter 1 3

Example: Cellular Phone

B. Murmann EE315A - Chapter 1 4

 The Vision – "Software Radio"

[Schreier, "ADCs and DACs: Marching Towards the Antenna," GIRAFE workshop, ISSCC 2003]

B. Murmann EE315A - Chapter 1 5

ADC for Software Radio

24

22
DVD 1kW
20 Audio
18 1W Software
Radio
Resolution [bits]

16 Audio
14 GSM Base
GSM Rx
1mW DSL
12 Ultra-
sound
10 Motor DTV Dig. Scope
Controls DVC
Video
8 Teleph.
HDD
6
1µW
4
Wireline Interface
2
1kHz 10kHz 100kHz 1MHz 10MHz 100MHz 1GHz 10GHz
Bandwidth

• Ouch!

B. Murmann EE315A - Chapter 1 6

 Reality

[Schreier, "ADCs and DACs: Marching Towards the Antenna," GIRAFE workshop, ISSCC 2003]

B. Murmann EE315A - Chapter 1 7

Example: Hard Disk Drive

[Bloodworth, JSSC 11/1999]

B. Murmann EE315A - Chapter 1 8

 Example: Neural Field Potential Amplifier

Electroencephalography (EEG) =
recording of electrical activity along
the scalp produced by the firing of
neurons within the brain

[Avestruz, JSSC 12/2008]

B. Murmann EE315A - Chapter 1 9

Example: MEMS Accelerometer

[Lemkin, JSSC 4/1999]

B. Murmann EE315A - Chapter 1 10

 Canonical Sensing System

• Front-end amplification boosts the sensor’s signal above the noise

floor of the interface electronics
• Filtering rejects interference, noise, provides antialiasing
• System level optimization is needed
– Don’t want to waste power, money, area, accuracy, etc.
B. Murmann EE315A - Chapter 1 11

Interface Features/Properties

• Extract the desired features of the signal and convert them to a

form that is easily processed
– Includes special functions like biasing, tuning...
– Processing usually occurs in the digital domain
• Some analog processing may reduce overall system requirements
• The interface should not be a bottleneck
– Typically want to perform near the sensor’s intrinsic precision
– In the words of Kofi Makinwa: “Do no harm! Digitize early! Be
dynamic!”
• Accuracy and resolution of the interface electronics are often
referred back to the sensor input (e.g. +/-1° for an angle sensor)

B. Murmann EE315A - Chapter 1 12

 Course Objective

• Acquire a thorough understanding of the basic principles,

challenges and limitations in signal conditioning circuit design
– Focus on concepts that are unlikely to expire
– Preparation for further study of state-of-the-art "fine-tuned"
realizations
• Strategy
– Acquire basic intuition by studying a selection of commonly
used circuit and design techniques
– Acquire depth through a design project that entails design,
optimization and thorough characterization of a signal
conditioning circuit in modern technology

B. Murmann EE315A - Chapter 1 13

Staff and Website

• Teaching assistant
– Jihoon Jang, [email protected]
• Administrative support
– Ann Guerra, Allen 207, [email protected]
• Web page
– http://coursework.stanford.edu/homepage/F14/F14-EE-315A-01.html
– Check regularly, especially the "Forums" section
• Lecture videos are provided on the web (by SCPD), but please
come to class to keep the discussion intercative

B. Murmann EE315A - Chapter 1 14

 Preparation

• Course prerequisites
– EE214B or equivalent
• Device physics and models
• Transistor level analog circuits, elementary gain stages
• Frequency response, feedback, noise
– Prior exposure to Spice, Matlab
– Basic signals and systems
• Laplace and z-transforms
• Please talk to me if you are not sure if you have the required
background

B. Murmann EE315A - Chapter 1 15

Analog Circuit Sequence

Design of mixed-signal
and RF building blocks

Analog IC Fundamentals Analysis and design of

for undergraduates and high-performance EE314A
entry-level graduate circuits in advanced
RF Integrated Circuit
Design
students technologies

EE314B
Advanced RF
Integrated Circuit
EE114/EE214A EE214B Design
Fundamentals of Advanced Analog
Analog Integrated Integrated Circuit
Circuit Design Design EE315A
VLSI Signal
Conditioning Circuits

EE315B
VLSI Data
Conversion Circuits

B. Murmann EE315A - Chapter 1 16

 Assignments

• Homework: (30%)
– Handed out on Thu, due following Thu after lecture (1 pm)
– Lowest HW score is dropped in final grade calculation
– Absolutely positively no deadline extensions
• Project: (30%)
– Design of a high performance amplifier circuit (CDS stage)
– Project report in the format of an IEEE journal paper
• Final Exam (40%)

B. Murmann EE315A - Chapter 1 17

Honor Code

• Please remember you are bound by the honor code

– I will trust you not to cheat
– I will try not to tempt you
• But if you are found cheating it is very serious
– There is a formal hearing
– You can be thrown out of Stanford
• Save yourself and me a huge hassle and be honest
• For more info
– http://www.stanford.edu/dept/vpsa/judicialaffairs/guiding/pdf/
honorcode.pdf

B. Murmann EE315A - Chapter 1 18

 Tools and Technology
• Primary tools
– Cadence Virtuoso Schematic Editor
– Cadence Virtuoso Analog Design Environment
– Cadence SpectreRF simulator
– You can use your own tools/setups “at own risk“
• Getting started
– Read “remote connection” tutorial
– Read “virtuoso tutorial”
– All tool related documents are in the “CAD” section of the website
• EE315A Technology
– 0.18-µm CMOS
– BSIM3v3 models provided under /usr/class/ee315a/models
– Same models are used in EE214B

B. Murmann EE315A - Chapter 1 19

Reference Books
• Chan Carusone, Johns, Martin, Analog Integrated Circuit Design,
2nd Edition, Wiley, 2011
• Schauman, Xiao and Van Valkenburg, Design of Analog Filters, 2nd
Edition, Oxford University Press, 2009
• Deliyannis, Sun, and Fidler, Continuous-Time Active Filter Design,
CRC Press 1998, http://www.crcnetbase.com/isbn/9780849325731
• Gray, Hurst, Lewis and Meyer, Analysis and Design of Analog
Integrated Circuits, 5th Edition, Wiley, 2008 (Chapter 12)
• Laker and Sansen, Design of Analog Integrated Circuits and Systems,
McGraw-Hill, 1994
• Gregorian and Temes, Analog MOS Integrated Circuits for Signal
Processing, Wiley, 1986
• Williams and Taylor, Electronic Filter Design Handbook, 3rd edition,
McGraw-Hill, 1995
• Zverev, Handbook of Filter Synthesis, Wiley, 1967

B. Murmann EE315A - Chapter 1 20

 Course Topics
• Precision techniques
– Chopping, autozeroing, correlated double sampling
• Switched capacitor gain stages
– Charge conservation analysis
– Noise analysis
• Design of Operational Transconductance Amplifiers (OTAs)
– Analysis and design of fully differential implementations
– Gm/ID-based optimization (BW – noise – power dissipation)
• Continuous time filters
– Biquad and ladder-based designs
– Active-RC and Gm filters
• Switched capacitor filters
– Approximation errors
– Circuit simulation (periodic ac and noise analysis)
– Noise analysis
• Layout techniques

B. Murmann EE315A - Chapter 1 21

Precision Techniques: Motivational Example

http://www.phantomscales.com/ohaus/valor1000.php

• Four digits means we want to resolve 1 in 10,000

B. Murmann EE315A - Chapter 1 22

 Under the Hood: Wheatstone Bridge

Precise reference
voltage (bandgap)

http://www.allaboutcircuits.com/vol_1/chpt_9/7.html

  Δ   Δ 1 Δ

 
௥௘௙ 

2 2 2  ௥௘௙

• A typical bridge will produce about 2mV/V at full scale load

• With Vref = 10V, this means the full scale output range is about 20 mV

B. Murmann EE315A - Chapter 1 23

Typical Readout Circuit

Signal Conditioning Front-End
“Instrumentation Amplifier”

Calibration
Button

Digital
Processor

http://www.planetanalog.com/document.asp?doc_id=527950
http://cds.linear.com/docs/en/application-note/an43f.pdf

• Calibration at start-up eliminates any static errors in the circuit

• However, the noise and offset drift of the amplifier front-end
must be less than 20mV/10,000 = 2µV (!)

B. Murmann EE315A - Chapter 1 24

 Amplifier Noise and Offset Drift

• The instrumentation amplifier

will most certainly employ
differential pairs at its input
• Let’s see if we can design a vn2

differential pair that has less vIP vIM

VOS
than 2µV input referred noise
and offset drift 2ID

• Assume that we design for

0.5µVrms for each nonideality

B. Murmann EE315A - Chapter 1 25

Thermal Noise

1

௡,௧௛
ଶ
= 2 ⋅ 4 Δ
Vn,th2
௠
gm gm vIM
vIP α = excess noise factor
(due to active loads, etc.)

2ID γ ≅ 0.85 in our technology

• Assuming an observation bandwidth of 100 Hz (set by RC filter):

ଶ
௡,௧௛ 0.5
50

= = 4⋅4  1
Δ 100  . . ஽ = ଶ ⋅ = 1.5
50

15 
2 ⋅4 Δ 1 
஽ = ଶ
⋅
௡,௧௛ ௠
஽
Not a big dealL
Δ

B. Murmann EE315A - Chapter 1 26

 Flicker Noise (1)

Δ

௡,௙௟
ଶ ௙௡
= 2௙௟ ⋅
௢௫

Vn,fl2 αfl= excess noise factor

gm gm (due to active loads, etc.)
vIP vIM

௙௡ = 0.5 ⋅ 10ିଶହ  ଶ 
2ID ିଶହ  ଶ 
௙௣ = 0.25 ⋅ 10

௢௫ = 8.42
ଶ

௙మ


௡,௙௟ =  2 ⋅ = 2 ⋅
ଶ ௙ ௙ ଶ
⋅ 2.3
௢௫ ௢௫ ଵ
௙భ

B. Murmann EE315A - Chapter 1 27

Flicker Noise (2)

• Useful number to compute: Flicker noise in one frequency

decade for WL = 1 µm2

௙௟ = 2 ⋅
௙
⋅ 2.3
1ଶ ⋅ ௢௫

0.5 ⋅ 10ିଶହ  ଶ 
. . ௙௟ =4⋅ ⋅ 2.3 = 5.46 ⋅ 10ିଵଵ  ଶ
8.42 

௙௟ = 7.4௥௠௦

• Now suppose we want to have a stable measurement for about

20 minutes
f1 ≅ 1/(20 min) ≅ 1 mHz
• With f2 = 100 Hz, this means that we are covering 5 frequency
decades

B. Murmann EE315A - Chapter 1 28

 Flicker Noise (3)

• To get the flicker noise below 0.5 µVrms, we need

ଶ
7.4
>5⋅ ⋅ 1ଶ = 1095ଶ
0.5

• For example, we can make L = 1 µm and W = 1095 µm

– Huge device, and we need multiple devices of this size to
complete the amplifier
• This can be OK in rare cases, but we would ideally like to have
a way to reduce flicker noise without brute-force sizing

B. Murmann EE315A - Chapter 1 29

Input-Referred Offset (1)

VOS

2ID All mismatch 2ID

absorbed into VOS

ଶ௏்

 Δ் = ௏் = 5

ఉଶ

 Δ = ఉ = 1%

B. Murmann EE315A - Chapter 1 30

 Input-Referred Offset (2)
• For simplicity, consider only offset contribution from input pair
– Active loads and downstream circuitry will contribute as well
• The input offset variance is then

ଶ ଶ ଶ ଶ௏் ఉଶ !஽
ଶ
= + = +
௏ைௌ ௏ைௌ,୼ఉ ௏ைௌ,୼௏்
௠

!஽
ଶ
1
ଶ
= ଶ௏் + ఉଶ Usually negligible*
௏ைௌ
௠

*To see this, evaluate: ఉ = 1% ⋅

ூವ ଵ
ೄ = 0.67
௚೘ ଵହ
ಲ

B. Murmann EE315A - Chapter 1 31

Input-Referred Offset (3)

• Typical numbers
௏்
௏ைௌ ≅

5
= = 5
1ଶ
௏ைௌଵ

5
= = 1.58
10ଶ
௏ைௌଶ

5
= = 0.5
100ଶ
௏ைௌଷ

B. Murmann EE315A - Chapter 1 32

 Input-Referred Offset (4)

• How much “static” offset can we handle?

• We can subtract some static offset in the digital domain, but it
costs dynamic range
– The signal chain must process 20mV + VOS and maintain the
same resolution
– A couple of millivolts VOS are acceptable in this case
• In applications where the signal range is smaller, then a few
millivolts of offset can be very painful and often must be “nulled”
before amplification

B. Murmann EE315A - Chapter 1 33

Input Referred Offset Drift (1)

• Interestingly, it turns out that the input offset due to VT mismatch
shows almost no drift
– Explained by the fact that this is a charge phenomenon,
directly at the gate
– See P. Andricciola and H.P. Tuinhout, “The Temperature
Dependence of Mismatch in Deep-Submicrometer Bulk
MOSFETs,” IEEE Electron Device Letters, June 2009
• However, there is substantial drift due to the ∆β term
– Even though the mismatch itself is relatively stable, it refers
to the input via the temperature dependent gm

Δ ஽

ைௌ,୼ఉ =
 ௠

B. Murmann EE315A - Chapter 1 34

 Input Referred Offset Drift (2)

• In weak inversion
Δ ஽ Δ  Δ
ைௌ,୼ఉ

ைௌ,୼ఉ = =   =
 ௠   

• Same result holds for a BJT: The temperature coefficient of VOS

is the initial offset due to ∆β mismatch, divided by temperature
– Example: 1mV/300K = 3.3 µV/K
• In strong inversion, assuming ID is constant, we have
௔
௠ ∝  ଵ/௕  = 1…2 ∝  = 2…3

 Δ ஽ 
ைௌ,୼ఉ
=
  ௠ 

• Typically on the order of 10L20 µV/K

B. Murmann EE315A - Chapter 1 35

Summary

• Building a MOS input pair with µV-level input flicker noise

(integrated over a few frequency decades) is very painful
– Very large devices needed
• Building a MOS input pair with µV-level input offset drift is
simply hopeless
– Typical TC of 10 µV/K means that only a tenth of a degree
change in temperature gives an input offset change of 1 µV

B. Murmann EE315A - Chapter 1 36

 Commercial Instrumentation Amplifier

http://www.ti.com/lit/ds/symlink/ina333.pdf

B. Murmann EE315A - Chapter 1 37

Quick Check
• This amplifier looks promising for our application
• Offset
– The guaranteed offset bound is 25 µV
– Easily removed during start-up calibration
• Offset drift
– Specified at 0.1 µV/K; can handle tens of degrees
temperature change before we drift out of spec
• Thermal noise
– Input PSD is 50 nV/rt-Hz, OK for our application
• Flicker noise
– No mention, must be negligible
– How do they do this?

B. Murmann EE315A - Chapter 1 38

 Secret Sauce

• We’ll demystify this in Chapter 2L

B. Murmann EE315A - Chapter 1 39

 Precision Techniques

Boris Murmann
Stanford University
[email protected]
Copyright © 2014 by Boris Murmann

B. Murmann EE315A - Chapter 2 1

Outline

• Dynamic offset cancellation

• Dynamic element matching
• Sensor interface example

B. Murmann EE315A - Chapter 2 2

 Motivation

• Analog MOS circuits come with a variety of low frequency artifacts

that can easily ʺswamp outʺ DC or low-frequency signals of interest

1/
fn
oi
se

B. Murmann EE315A - Chapter 2 3

Basic Options
• Offset mitigation
– Use large transistors
• Generally undesired (extra area, power)
– Use trimming or start-up calibration
• Won’t address offset drift, ~110 µV/K
• Flicker noise mitigation
– Use large transistors PMOS
– Use PMOS
• Helps if device has a buried channel
– Use resistive degeneration
• Mostly useful for current sources
Degen.
• For most precision applications, applying
these techniques alone is inadequate [Denison, JSSC 2007]

B. Murmann EE315A - Chapter 2 4

 Dynamic Techniques

• Chopping
• Autozeroing
• Correlated double sampling (ʺdiscrete time autozeroingʺ)
• Offset stabilization (ʺcontinous time autozeroingʺ)
• Combinations of chopping and autozeroing

B. Murmann EE315A - Chapter 2 5

Where Are These Techniques Useful?

• Sensor interfaces requiring DC accuracy (µV, nV level offsets)

• Low frequency signal conditioning (e.g. biomedical electronics)
• High-resolution data converters (ADC, DAC)

[Medtronic]

B. Murmann EE315A - Chapter 2 6

 Chopping is An Old Idea

B. Murmann EE315A - Chapter 2 7

Chopping is An Old Idea

B. Murmann EE315A - Chapter 2 8

 Chopping – Main Idea

• Input is modulated to higher frequencies, amplified, then demodulated

• Amplifier nonidealities are modulated to higher frequencies by the
output chopper, then filtered out by a lowpass filter

B. Murmann EE315A - Chapter 2 9

Time Domain Perspective

modulation signal
fchop

LPF
in out

DC signal offset

Zero

• DC input passes through the amplifier as a square wave and gets

demodulated back to DC by the output chopper
• Amplifier DC offset is amplified and modulated to a square, then
filtered by the LPF (filtering is not perfect
chopper ripple)
• Residual DC offset occurs if the modulation clock is not 50% duty
cycle (use a flip flop to ensure nearly perfect duty cycle)

B. Murmann EE315A - Chapter 2 10

 Frequency Domain Perspective

SVin square(t)

VA VB +1
LPF
Vin + A Vout signal
time
-1
f Tchop
Vos+Vn

SVA SVB modulated

modulated SVos+SVn
signal LPF chopping
SVos+SVn artifacts
demodulated
signal
S0
fchop 2fchop 3fchop 4fchop 5fchop fchop 2fchop 3fchop 4fchop 5fchop f
f

B. Murmann EE315A - Chapter 2 11

Residual Low Frequency Noise

• Consists of two components

– Thermal noise mixed down from odd multiples of fchop
• Conversion gain for baseband is (2/π)2
• Conversion gain dies quickly for sidebands (1/n2)
• The end result is that the thermal noise floor is unchanged
– Flicker noise mixed down from odd multiples of fchop
• Results in a nearly white PSD that scales with fcorner/fchop
• Good approximation for baseband noise after chopping
(see Enz, 1996):

௖௢௥௡௘௥

௏஻  =
଴ 1 + 0.85
௖௛௢௣

B. Murmann EE315A - Chapter 2 12

 Example

[Enz, 1996]

௖௢௥௡௘௥  ௖௛௢௣  1

B. Murmann EE315A - Chapter 2 13

Finite Amplifier Bandwidth

VA VB LPF
Vin A(s) Vout
DC input

• Finite amplifier bandwidth reduces the effective amplifier gain and

introduces chopping artifacts at even multiples of fchop
• Phase response of the amplifier and phase between the two
chopper signals also affects the gain (see Enz, 1996)

B. Murmann EE315A - Chapter 2 14

 Chopper Amplifier with Feedback

R2
Cm
fchop fchop
R1
Vout

Vin

Cm

• Feedback ensures well defined gain

• Miller compensation around A1 provides filter function
• High voltage gain in Gm1 suppresses input referred offset due to A1

B. Murmann EE315A - Chapter 2 15

Chopped Folded Cascode Amplifier

VDD
• Popular topology
Vbias1
• Output chopper placed
at low impedance node
PMOS (fast transients)
fchop

Vbias2
• PMOS choppers
demodulate the signal
Vod • NMOS choppers
Vbias3 provide dynamic
element matching for
Vid NMOS current sources (more
fchop
later)
Vbias4
fchop
[Sanduleanu, 1998]
VSS

B. Murmann EE315A - Chapter 2 16

 Basic Chopping Circuit (At Input)

[Enz, 1996]

• Key issue: Transient spikes due mismatched charge injection

and clock feedthrough

B. Murmann EE315A - Chapter 2 17

Residual Offset Due to Spikes

VA VB LPF
Vin A(s) Vout
DC input

• Spike demodulation by the output chopper results in residual DC offset

as well as chopping artifacts at even multiples of fchop
• Residual offset = 2௖௛௢௣ ௦௣௜௞௘ ௦௣௜௞௘
– Typical values are on the order of 1,10µV
– Can reduce by limiting the amplifier bandwidth
filters spikes
– τspike depends on the source impedance (e.g. feedback resistors)

B. Murmann EE315A - Chapter 2 18

 Summary of Basic Design Considerations
• Guarantee 50% chopping duty cycle with a flip flop
• Input chopper design is key for minimizing residual offset
– Minimum size switches for minimum charge injection and
clock feedthrough
– Symmetric layout to minimize mismatch in charge injection
and clock feedthrough
• Choice of chopping frequency is a tradeoff
– Definitely need fchop larger than flicker noise corner
– Making fchop very large leads to increased residual offset
• Choice of amplifier bandwidth is a tradeoff
– Want low bandwidth for low power, as well as spike filtering
and the associated improvement in residual offset
– Want high bandwidth to reduce gain error and even order
chopping artifacts

B. Murmann EE315A - Chapter 2 19

Advanced Techniques

• Reduce residual offset due to spikes

– Nested chopping
– Deadbanding
– Bandpass filtering
– ...
• Reduce chopper ripple
– AC coupling
– SC filtering
– Auxiliary feedback loop
– ...

B. Murmann EE315A - Chapter 2 20

 Nested Chopping

[Bakker, 2000]

• Inner choppers run at high frequency to remove flicker noise

• Outer choppers modulate the inner spikes, remove DC content
– Residual offset = 2௖௛௢௣௟௢௪ ௦௣௜௞௘ ௦௣௜௞௘
• Achieve ~100nV offset, but bandwidth is limited (a fraction of fchoplow)

B. Murmann EE315A - Chapter 2 21

Spike Dead-Banding

• Hold the output during the major

portion of the spike transient
– Reduces the DC component of
the demodulated spikes
– Some noise and gain
degradation from sample and
hold operation
• Can achieve ~200nV offset, don’t
have to sacrifice bandwidth
[Menolfi, 2000]

B. Murmann EE315A - Chapter 2 22

 Spike Bandpass filtering

• Spike is much more wideband than the input signal

• Bandpass filters spike considerably, not the signal

B. Murmann EE315A - Chapter 2 23

Ripple Reduction Using AC Coupling

[Drawing by K. Makinwa]

• AC coupling blocks the amplifier’s offset and prevents it from

being modulated
• Hard to make the required RC time constant in an IC

B. Murmann EE315A - Chapter 2 24

 Ripple Reduction Using SC Filter

[Bakker, 1997]
[Burt, 2006]

[Drawing by K. Makinwa]

• Integrated square wave is triangular, can be sampled at zero

crossing to eliminate ripple
• Filter introduces delay and a small noise penalty

B. Murmann EE315A - Chapter 2 25

Digital Filtering

[Drawing by K. Makinwa]

• Use a digital filter with notches at fchop

B. Murmann EE315A - Chapter 2 26

 Ripple Reduction Loop
[Wu, 2009]

• Use an auxiliary feedback loop to sense the output ripple and

null DC offset currents before they are chopped and filtered
– Ripple can be suppressed below the amplifier’s noise floor

B. Murmann EE315A - Chapter 2 27

Dynamic Techniques

• Chopping
• Autozeroing
• Correlated double sampling (ʺdiscrete time autozeroingʺ)
• Offset stabilization (ʺcontinous time autozeroingʺ)
• Combinations of chopping and autozeroing

B. Murmann EE315A - Chapter 2 28

 Input Autozeroed Amplifier
Vos Vn

Vout
Φ2
DC AC
Vin Φ1

Φ1
Caz

• Model the real (nonideal) amplifier by an ideal amp with input

referred noise and offset sources
• Two phase nonoverlapping clocks
– Autozero phase Φ1
– Amplification phase Φ2

B. Murmann EE315A - Chapter 2 29

Φ1 Autozero phase
DC Analysis
Vos
DC Analysis: Vn → 0
Vaz
DC
Vaz = A0 Vos ‒ Vaz

A0
∴ Vaz = V
1 + A0 os
Vaz Caz

• The amplifier‘s offset is stored on the autozero capacitor Caz

• Finite gain determines the maximum achievable accuracy
• The amplifier is unavailable for signal amplification

B. Murmann EE315A - Chapter 2 30

 Φ2 Amplification phase
DC Analysis
Vos
DC Analysis: Vn → 0
Vout
DC A0
Vout = A0 Vin + Vos ‒ V
Vin 1 + A0 os

Vos
∴ Vout = A0 Vin +
Vaz Caz 1 + A0

• The input signal is amplified, the amplifier‘s output is valid

• The offset is suppressed by (1+A0)

B. Murmann EE315A - Chapter 2 31

Input Autozeroed Amplifier

AC Analysis

• The amplifier‘s noise and drift are sampled and held on Caz
– The residual noise at Vout is the difference between the sampled
noise and the present value of the noise
– Low frequency noise doesn‘t change rapidly
good rejection
– High frequency noise is aliased, folds back to baseband

B. Murmann EE315A - Chapter 2 32

 Continuous Time Noise Analysis

Sampling Zero-order hold

Duty cycling

B. Murmann EE315A - Chapter 2 33

Noise Aliasing in Sampling Path

Zero-order hold
δ(t-nTs) Sinc in the frequency domain
m=∞
Vn(t) VSH(t) VSH ݂ = HZOH ݂ ෍ Vn f − mfs
ZOH
m=−∞
Noise aliasing

• High frequency noise is aliased back into baseband due to sampling

• Noise samples are then held by the ZOH
Sinc shaping

B. Murmann EE315A - Chapter 2 34

 Overall Baseband Noise Transfer Function

• The noise in the un-sampled signal path is simply duty-cycled

m=∞
Vnull  =  am Vn f − mfs
m=−∞

am : Fourier coefficients of rectangular pulse

• The total baseband noise (m=0) follows from the difference of

the two components

Vout  = a0 Vn  ‒ HZOH  Vn  = 
2 2
2 TΦ2 2 sin ωTΦ2 1 ‒ cos ωTΦ2
H0 f = 1‒ +
Ts ωTΦ2 ωTΦ2

B. Murmann EE315A - Chapter 2 35

Overall Baseband Noise Transfer Function

• Strong attenuation of low-frequency noise, make fs > fcorner

B. Murmann EE315A - Chapter 2 36

 Impact of Circuit Nonidealities

• Finite amplifier gain

– Limits maximum suppresion for input-referred schemes
• Finite amplifier bandwidth
– Dynamic settling errors degrade AC suppresion
• Can be complicated, since Caz isn‘t reset each cycle
• Charge injection from switches (discussed in a different module)
– Creates residual DC offset
– Can be mitigated to some degree
• Large Caz values, small switches
• Fully differential design
• Clock edge rates
• Dummy switches

B. Murmann EE315A - Chapter 2 37

Output Referred Autozeroing

• Here finite gain doesn‘t limit the maximum supression

– But maximum gain is limited, the amplified offset can rail the amp
• Charge injection from the autozero switches is less severe
– Input refers through the amplifier‘s gain

B. Murmann EE315A - Chapter 2 38

 Multistage Offset Cancellation

Switches turn off in sequence S1,

S2, .SN
Residual offset due
[Enz, 1996] to charge injection (and also
kT/C noise) only from last stage

• Autozero each stage of a multi-stage design

– High resolution comparator preamplifiers
– Distributed gain stages
B. Murmann EE315A - Chapter 2 39

Comparator Example
• Mehr & Dalton, JSSC 7/1999

B. Murmann EE315A - Chapter 2 40

 Comparator Example
• Mehr & Dalton, JSSC 7/1999

B. Murmann EE315A - Chapter 2 41

Correlated Double Sampling

• The discrete time version of autozeroing
• Common in switched capacitor circuits, data converters
• Simple example: Unity gain SC S/H stage

Output is sampled
by next stage

B. Murmann EE315A - Chapter 2 42

 Noise Transfer Function

௦ V
Vn t out k    1‒
‒ഝమ
Σ

‒ഝమ

‒ഝమ

B. Murmann EE315A - Chapter 2 43

Noise Rejection and Aliasing

• Noise is filtered by HCDS(s) and folds into fs/2

• Residual noise spectrum is approximately flat

log SVn log SVout

log |HCDS(f)|2 noise floor

increases due to
sampling

fs/2 log f fs/2 log f

B. Murmann EE315A - Chapter 2 44

 SC Gain Stage And Integrator with CDS

More later.

B. Murmann EE315A - Chapter 2 45

Offset Stabilized Amplifier

Am gain of main amplifier

An gain of nulling amplifier
Ap gain through nulling port

Aoverall = Am + An Ap
[Enz, 1996]

• Also called continous time autozero amplifier

• Use an autozeroed amplifier in an auxillary path
• Can achieve very high DC gain
• Noise performance usually dictates large off-chip caps C1, C2

B. Murmann EE315A - Chapter 2 46

 Implementation Example

• Scale gm2/gm1 to attenuate kT/Ch

B. Murmann EE315A - Chapter 2 47

Autozeroing In Chopping Amplifier

[Pertjis, 2009]

• Reduces chopper ripple by cancelling offset before it is modulated

B. Murmann EE315A - Chapter 2 48

 Chopping in Autozeroing Amplifier

http://electronicdesign.com/analog/chopper-stabilized-op-amps

B. Murmann EE315A - Chapter 2 49

Summary

• Chopping
– Can achieve 50nV-10µV residual offsets
– Technique of choice when noise is most important
• No sampling
no thermal noise penalty
– Well suited to continuous time applications
• The amplifier output is always valid/available
– Some fundamental loss of amplifier bandwidth
• Autozeroing and correlated double sampling
– Can achieve 1-10µV residual offset
– Sampled data technique
• Well suited to discrete time systems (data converters, SC filters)
• Noise aliasing increases thermal noise floor
– Can achieve uninterrupted continuous time operation with
appropriate topology

B. Murmann EE315A - Chapter 2 50

 References (1)
• K. Makinwa, "Dynamic offset cancellation techniques in CMOS," ISSCC
Tutorial, Feb. 2007.
• C.C. Enz, and G.C. Temes, “Circuit techniques for reducing the effects of
opamp imperfections: autozeroing, correlated double sampling and chopper
stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584 -1614, Nov. 1996.
• R. Burt, and J. Zhang, “A micropower chopper-stabilized operational
amplifier using a SC notch filter with synchronous integration inside the
continuous-time signal path,” Digest ISSCC, pp. 354 - 355, Feb. 2006.
• H. Takahashi, T. Noda et al, "A 1/2.7-in 2.96 MPixel CMOS image sensor
with double CDS architecture for full high-definition camcorders," Solid-
State Circuits, IEEE Journal of , vol.42, no.12, pp. 2960-2967, Dec. 2007.
• R. Wu, K.A.A. Makinwa, J.H. Huijsing, "A chopper current-feedback
instrumentation amplifier with a 1mHz noise corner and an AC-coupled
ripple reduction loop," IEEE J. Solid-State Circuits, pp. 3232-3243, Dec.
2009.
• J.H. Huijsing, “Dynamic Offset Cancellation in Operational Amplifiers and
Instrumentation Amplifiers” Book Chapter, M. Steyaert et al. (eds.), Analog
Circuit Design, Springer, 2009.

B. Murmann EE315A - Chapter 2 51

References (2)
• M. Sanduleanu et al., “A low noise, low residual offset, chopped amplifier
for mixed level applications,” Proc. ICECS, pp. 333-336, 1998.
• A. Bakker and J.H. Huijsing, “A CMOS chopper opamp with integrated low-
pass filter,” Proc. ESSCIRC, pp. 200-203, 1997.
• A. Bakker, K. Thiele, and J.H. Huijsing, “A CMOS nested chopper
instrumentation amplifier with 100nV offset,” IEEE J. Solid-State Circuits,
pp. 1877-1883, Dec. 2000.
• C. Menolfi and Q. Huang, “A 200nV 6.5 nV/Hz noise PSD 5.6kHz chopper
instrumentation amplifier,” ISSCC Digest of Tech. Papers, pp. 362 - 363,
Feb. 2000.
• M.A.P. Pertijs and W.J. Kindt, "A 140dB-CMRR current-feedback
instrumentation amplifier employing ping-pong auto-zeroing and chopping,"
ISSCC Digest of Tech. Papers, pp. 324-325, Feb. 2009.

B. Murmann EE315A - Chapter 2 52

 Outline

• Dynamic offset cancellation

• Dynamic element matching
• Sensor interface example

B. Murmann EE315A - Chapter 2 53

DEM Concept

To filter
[Pelgrom]

• I3 and I4 have the same average, equal to I

B. Murmann EE315A - Chapter 2 54

 DAC Application Example

To signal switches

[Pelgrom]

B. Murmann EE315A - Chapter 2 55

Outline

• Dynamic offset cancellation

• Dynamic element matching
• Sensor interface example

B. Murmann EE315A - Chapter 2 56

 Sensor Interface Example:
CMOS Temperature Sensor

[Pertijs, 2005]

• High accuracy CMOS temperature sensor

– 3σ inaccuracy of +/-0.1°C over -55°C to 125°C
– Outperforms commercial offerings of CMOS temp sensors
• Based on substrate PNP band gap reference
• One shot operation, the sensor is queried then goes back to sleep

B. Murmann EE315A - Chapter 2 57

Bandgap Reference Principle

• To 1st order VBE and ∆VBE are linearly related to temperature

– VBE is complementary to absolute temperature (CTAT)
– ∆VBE is proportional to absolute temperature (PTAT)
• VBE + α∆VBE is temperature independent given the right α
B. Murmann EE315A - Chapter 2 58
 Temperature Sensor Principle

• An ADC converts the VBE and ∆VBE information to digital format

• Compares PTAT ∆VBE to temp independent VREF = VBE + α∆VBE
– The resulting Dout is a digital thermometer

B. Murmann EE315A - Chapter 2 59

Sigma Delta Modulator

10001000
1000..

• A sigma delta modulator is used to compute the ratio

• A clocked comparator selects whether to integrate -VBE or ∆VBE in
each clock cycle
– Negative feedback drives the integrator output toward zero
• The average value ‘µ’ of the output bit stream is the desired ratio
B. Murmann EE315A - Chapter 2 60
 Temp Sensor Block Diagram

• An off-chip digital filter processes the bit stream to produce Dout

• Circuit errors are reduced to very low levels to achieve the full
accuracy of the temperature sensor system
– Their strategy is to reduce all circuit errors to 0.01°C level
• Offset in ∆VBE readout
• Mismatch in 1:p current ratio and error in α factor
• Offset in the sigma delta modulator
• A single temperature trim corrects for process spread of VBE
B. Murmann EE315A - Chapter 2 61

DEM Current Source Rotation

• Dynamic element matching is used to create accurate 1:p ratio

– Need <0.011% error in the ratio for 0.01°C sensor referred error
– Current sources are rotated each sample period, the sigma delta
integrator averages out the error
• The p·Ibias and Ibias sources are also swapped between QL and QR to
average out QL/QR offset from the ∆VBE measurement

B. Murmann EE315A - Chapter 2 62

 Sigma Delta Integrator

• Switched capacitor integrator used in the sigma delta loop

• DEM is used to create an accurate α gain factor for α·∆VBE
– Sampling capacitors are rotated each sample period
• Autozeroing during the sampling period φ1 is used to cancel the
offset of the integrator and reduce 1/f noise
B. Murmann EE315A - Chapter 2 63

Full Sigma Delta Architecture

• System level chopping reduces the total offset below 0.01°C

B. Murmann EE315A - Chapter 2 64

 Final Measured Error of 24 Samples

• Several other techniques are needed to get the final performance

– β insensitive Ibias generation
– Curvature correct of the VBE temperature response
• Slightly PTAT VREF reference voltage, nonlinear decimation filter
– VBE averaging between QL and QR
B. Murmann EE315A - Chapter 2 65
 Switched Capacitor Gain Stages

Boris Murmann
Stanford University
[email protected]
Copyright © 2014 by Boris Murmann

B. Murmann EE315A - Chapter 3 1

Introduction

• Switched capacitor (SC) circuits come in may different variants

• Coarse classification
– SC filters
– SC gain stages (no filtering)
• The purpose of this chapter is to review the basic operation of
SC gain stages, some of which we have already seen in the
previous chapter
• We’ll look at SC filters in chapter 9

B. Murmann EE315A - Chapter 3 2

 Outline

• Charge redistribution analysis

• Noise analysis
– Passive T/H
– Active boxcar sampler
– Charge redistribution stage
– Charge redistribution stage with CDS

B. Murmann EE315A - Chapter 3 3

Fully Differential SC Gain Stage

Non-overlapping
clock signals

φ1e (“early”) switch turns off slightly before φ1
see EE315B

B. Murmann EE315A - Chapter 3 4

 Half Circuit Model

φ1
Vin
Vout
φ2 φ1e φ2B

• In EE315A we will not worry about the exact implementation of

the switches
– Will be covered in great detail in EE315B
• For now, we will also assume that the amplifier has infinite gain

B. Murmann EE315A - Chapter 3 5

Charge Conservation Analysis (1)

Cf

φ1 Cs
X
Vin
Vout
φ2 φ1e φ2B

• During φ1, the circuit samples the input

• The total charge at node X is

ܳ௑ଵ = −ܸ௜௡ ‫ܥ‬௦ + 0 ⋅ ‫ܥ‬௙

B. Murmann EE315A - Chapter 3 6

 Charge Conservation Analysis (2)

Cf

φ1 Cs
X
Vin
Vout
φ2 φ1e φ2B

• During φ2, the charge at node X is

ܳ௑ଶ = 0 ⋅ ‫ܥ‬௦ − ܸ௢௨௧ ‫ܥ‬௙

B. Murmann EE315A - Chapter 3 7

Charge Conservation Analysis (3)

• Since no charge can escape when we switch from φ1 to φ2, we

can write

ܳ௑ଵ = ܳ௑ଶ

−ܸ௜௡ ‫ܥ‬௦ + 0 ⋅ ‫ܥ‬௙ = 0 ⋅ ‫ܥ‬௦ − ܸ௢௨௧ ‫ܥ‬௙

V௢௨௧ ‫ܥ‬௦
=
ܸ௜௡ ‫ܥ‬௙

B. Murmann EE315A - Chapter 3 8

 Unity Gain CDS Stage

• Similar operation, except that charge is sampled and kept on C

(no charge redistribution)
– This is called “flip around” or “direct charge transfer”

B. Murmann EE315A - Chapter 3 9

SC Gain Stage with CDS

• Same charge redistribution equations apply for input to output

transfer function
– Gain from input to output is C1/C2
• The transfer function from VOS to the output is a discrete time
highpass filter, as analyzed in chapter 2
“deglitch cap” – usually not needed

B. Murmann EE315A - Chapter 3 10

 Noise Analysis

• Get started with switch and capacitor alone, then expand analysis

φ1
Vin
φ2 φ1e φ1

φ
Elementary
Vin Vout Track and
Hold Circuit

B. Murmann EE315A - Chapter 3 11

Early Days of SC Noise Analysis

φ
VC
(2) (1) (2)

(1) Sampled and zero- (2) Wideband resistor

order held noise noise at 25% duty cycle

C.-A. Gobet and A. Knob, “Noise Generated in Switched Capacitor

Networks,” Electronics Letters, vol.16, no. 19, pp. 734-735, Sep. 1980.

B. Murmann EE315A - Chapter 3 12

 Early Days of SC Noise Analysis (2)

C.-A. Gobet and A. Knob, “Noise Generated in Switched Capacitor

Networks,” Electronics Letters, vol.16, no. 19, pp. 734-735, Sep. 1980.

B. Murmann EE315A - Chapter 3 13

A Different Planet
• In the 1980’s, discrete time signal processing was still
uncommon in electronics
• As a result, early SC noise analysis looks the problem from a
continuous time perspective
CLK

CT Circuit SC Circuit CT Circuit

vin(t) vout(t)

Fourier/Laplace description

B. Murmann EE315A - Chapter 3 14

 Anatomy of a Modern System
CLK

CT
SC pre- CT
Front-
Sampler processing ADC DSP DAC Recon-
End
(CDS, etc.) struction
Circuit

Fourier/Laplace Discrete time abstraction Fourier/Laplace

(z-domain)

• In a modern system, SC circuits have continuous time interfaces

only at the system boundaries
• For the majority of circuits, we need a discrete time description
of the noise

B. Murmann EE315A - Chapter 3 15

Discrete Time Abstraction

Irrelevant

VC

... VC(n-1) VC(n) VC(n+1) ...

• All we care about is the discrete time sequence that describes

the noise samples VC(k)
• Two properties
– Variance (power)
– Autocorrelation (defines the spectrum, i.e. how the power is
distributed in frequency, 0>fs/2)

B. Murmann EE315A - Chapter 3 16

 Passive T/H Circuit

Using Parseval’s theorem, the variance of the noise samples is:

∞ 2
1 1 kT
var [ VC1(n)] = 2
v C1,tot = ∫ 4kTR ⋅ df = 4kTR =
0
1 + j2πf ⋅ RC1 4RC1 C1

B. Murmann EE315A - Chapter 3 17

Alternative Derivation

• The equipartition theorem says that each “degree of freedom"

(typically a quadratic energy variable) of a system in thermal
equilibrium holds an average energy of kT/2
• In our system, the degree of freedom is the energy stored on the
capacitor

1 1
Cv C12 = kT
2 2
kT
v C12 =
C

B. Murmann EE315A - Chapter 3 18

 Spectrum of Noise Samples

• Strategy
– Realize that discrete time noise samples are essentially
instantaneous values (mTs apart) of the continuous time
noise process during φ1
– Spectrum follows from Fourier transform of the process'
autocorrelation function (Wiener-Khintchin)
• Samples show no correlation
white spectrum
• Samples are correlated
colored spectrum

B. Murmann EE315A - Chapter 3 19

Analysis (1)

• Calculate autocorrelation function

Rxx ( τ ) = δ ( 0 ) ⋅ 2kTR Ryy ( τ ) = R xx ( τ ) ∗ h ( τ ) ∗ h ( −τ )

1 −t / RC
h (t ) = e
RC

τ
kT − RC
Ryy ( τ ) = e
C1
n⋅mTs
kT − Covariance of samples
∴ Ryy ( n ) = e RC
separated by n clock cycles
C1

B. Murmann EE315A - Chapter 3 20

 Analysis (2)
• Apply discrete time Fourier transform
∞
X ( ω ) = ∑ Ryy ( n ) e j ω⋅nTs
−∞

2 kT 1 − e −2 M mTs “number of RC
X (f ) = M= time constants
fs C1  f  RC1 in mTs”
1 − 2e − M cos  2π +e
−2 M

 fs 
2.5
M=1
2 M=3 • Spectrum of noise samples is
X(f) / (2/f *kT/C)
1

M=5
1.5 essentially “white” for M>3
s

1
• Practical circuits tend to use
0.5 M=10 or larger
0
0 0.1 0.2 0.3 0.4 0.5
f/f s

B. Murmann EE315A - Chapter 3 21

Simulation Schematic
0.4*Ts/C1/M
R4

C1 = 1pF
Ts = 1us
M = 1, 3, 5, 7

Run PSS & PNOISE (more info later)

B. Murmann EE315A - Chapter 3 22

 Simulation Result
Noise PSD Noise Integral

≅64uVrms

M=1
M=1

M=7

M=7

B. Murmann EE315A - Chapter 3 23

Noise Folding Interpretation

1
fENB =
2kTR 2RC1

Ken Kundert, “Simulating

Switched-Capacitor Filters with
SpectreRF,” http://www.designers-
guide.org/Analysis/sc-filters.pdf

2 kT
fs C1

B. Murmann EE315A - Chapter 3 24

 Effective Noise Bandwidth


4 ⋅  =

1 ௦
 = ⋅ = (settling)
4 2

௦
 = ⋅
2

• Very undesired result

– Usable signal bandwidth is 0>fs/2 (discrete time signal)
– Noise bandwidth is M times larger than signal bandwidth
• M is the number of settling time constants, typically around 10

B. Murmann EE315A - Chapter 3 25

Aside: Boxcar Sampler

• Basic idea
– Apply a windowed (timed) integration to the signal
• First proposed in
– L. R. Carley and T. Mukherjee, "High-speed low-power
integrating CMOS sample-and-hold amplifier architecture“
Proc. CICC, pp. 543-546, 1995.
Gm
• For analysis see
– A. Mirzaei, S. Chehrazi, R. Bagheri, and A.A. Abidi, “Analysis
of First-Order Anti-Aliasing Integration Sampler,” IEEE TCAS
1, Oct. 2008.
– C.D. Ezekwe, and B.E. Boser, “A Mode-Matching Σ∆ Closed-
Loop Vibratory Gyroscope Readout Interface With a 0.004 /s/
Hz Noise Floor Over a 50 Hz Band,” IEEE JSSC, Dec. 2008.

B. Murmann EE315A - Chapter 3 26

 Effective Noise Bandwidth

[Ezekwe]

• Noise bandwidth = signal bandwidth = fs/2 !

B. Murmann EE315A - Chapter 3 27

Application Example

[Ezekwe]

B. Murmann EE315A - Chapter 3 28

 Application Example

(Still have kT/C reset

[Van der Goes, ISSCC 2014] noise, but after large gain)

B. Murmann EE315A - Chapter 3 29

Noise Analysis of SC Gain Stage

(actual implementation is typically fully differential)

• When φ1e goes low, the signal charge (Qx) is acquired at node X
• During φ2, this charge is redistributed onto Cf

B. Murmann EE315A - Chapter 3 30

 Noise Analysis During φ1
Cf

Cs
X
Vout
Cpar φ1e

• Need to find the total noise charge at node X after the φ1e
switch has turned off
• Very tedious to calculate using piece-by-piece integration of all
three noise sources

B. Murmann EE315A - Chapter 3 31

Equipartition to the Rescue

Cf

Cs
X
Vout
Cpar φ1e

(see Siddharth Seth’s

PhD thesis for a formal
proof)

1 q2x 1 q2x
=
2 Ceff 2 Cs + Cf + Cpar q2x = kT Cs + Cf + Cpar
( )
1 q2x 1 Cpar can deteriorate noise
= kT performance!
2 Cs + Cf + Cpar 2

B. Murmann EE315A - Chapter 3 32

 Noise Analysis During φ2

• Signal and noise charge acquired during φ1 is redistributed onto Cf

• Additional noise from Ron and OTA is added

B. Murmann EE315A - Chapter 3 33

Single Stage OTA Model

i2eq = 4kTγgmn + 4kTγgmp

Gm
4kTγ  gmp  4kTγ
v 2eq = 1+ = α
gmn  gmn  Gm
v 2eq
B. Murmann EE315A - Chapter 3 34
 φ2 Noise

4kTRon ∆f

1
R≅
βGm

4kTRon1∆f 4kTγ
α ∆f
Gm

• In a proper design, Ron1 and Ron2 will be much smaller than

1/βGm, else the switches would significantly affect the dynamics,
which would be very wasteful
– It is much easier to design switches with low on-resistance
than an amplifier with very large Gm

B. Murmann EE315A - Chapter 3 35

Output Referred Noise Comparison

2
C  2
• Ron1 noise referred to vo N1 = 4kTRon1∆f ⋅  s  ⋅ H( jω)
 Cf 
2
• Ron2 noise referred to vo N2 = 4kTRon2 ∆f ⋅ H( jω)

2
4kTγ  C  2
• Amplifier noise referred to vo Na = α ∆f ⋅  1 + s  ⋅ H( jω)
Gm  Cf 
2
 Cs 
1 +  2
Na αγ  Cf  Na αγ  Cs 
= >> 1 = 1+  >> 1
N1 GmRon1  C 2 N2 GmRon2  Cf 
s
 
C
 f 

• Amplifier noise dominates over noise due to Ron1, Ron2

B. Murmann EE315A - Chapter 3 36

 Total Integrated Amplifier Noise
Cf

vo
Cs Gm
1 CL
R≅
βGm
4kTγ
α ∆f
Gm

1 β Gm
BW = =
RCLtot CLtot

4kTγ 1 BW 1 kT
v o2 = α⋅ 2 ⋅ = αγ
Gm β 4 β CLtot

B. Murmann EE315A - Chapter 3 37

Adding up the Noise Contributions

Cf
φ1 φ2

q2x = kT ( Cs + Cf )
Cs Gm
CL

2 q2x  Cs + C f  kT  Cs  2 1 kT
v o,1 = = kT   = 1+  v o,2 ≅ αγ
C2f  C2 C  Cf 
β CLtot
 f  f

2 kT  Cs  1 kT
v o,tot = 1 +  + αγ
Cf  Cf  β CLtot

B. Murmann EE315A - Chapter 3 38

 Noise in Differential Circuits

• In differential circuits, the noise power is doubled (because there

are two half circuits contributing to the noise)
• But, the signal power increases by 4x
– Looks like a 3dB win?
2

DRsingle
Vˆ 2
∝ o DRdiff ∝
( 2Vˆ )
o
=2
Vˆ o2
kT kT kT
2
C C C

• Yes, there’s a 3dB win in DR, but it comes at twice the power
dissipation (due to two half circuits)
• Can get the same DR/power in a single ended circuit by
doubling all cap sizes and gm

B. Murmann EE315A - Chapter 3 39

SC Noise Simulation
• There are at least three ways to simulate noise in switched
capacitor circuits
• Basic .ac/.noise Spice simulations
– Simulate noise in each clock phase separately
• Activate φ1 switches, run .noise and integrate noise
charge at relevant node over all frequencies and refer to
output
• Activate φ2 switches, run .noise and integrate noise over
all frequencies at the output
• Sum integrated noise from the two phases
– This is analogous to the way we carried out the hand
analysis

B. Murmann EE315A - Chapter 3 40

 SC Noise Simulation
• Periodic Steady State Simulation
– First run PSS analysis to find the periodic operating point
• Analogous to .op for .ac/noise
– Next run PNOISE analysis
• Computes total noise, taking all clock phases, noise
aliasing, noise correlations, etc. into account
• Transient Noise
– Direct simulation of all noise sources using a transient
simulation
– Most physical way of simulating noise

B. Murmann EE315A - Chapter 3 41

Example Circuit
• OTA Gm chosen such than (Ts/2) / τOTA = 10
• Switches sized 5 times faster, i.e. N = 5·10 = 50
vic

vic

Cfp

Clp
cf

cl
voc

vocs
vdd
p1

voc
vdd
vocs
Csm
cs
Csp
cs
p1

Cfm

Clm
cf

cl
vic

vic

fs = 100 MHz, α = 2, γ = 1
Cs = Cf = 100 fF, CL = 500 fF, Cpar ≅ 0

B. Murmann EE315A - Chapter 3 42

 .Noise Simulation (φ1)
• *** Compute noise charge at node X and refer to output via Cf
• en vno 0 vcvs vol =( cs*v(x,s) + cf*v(x,f) )/cf
• .ac dec 100 100 1000Gig
• .noise v(vno) vdummy

(showing half circuit for simplicity)

B. Murmann EE315A - Chapter 3 43

.Noise Simulation (φ1)

-15
10
PSD [V2/Hz]

-20
10

-25
10 2 4 6 8 10 12
10 10 10 10 10 10
Frequency [Hz]
-4
x 10
6
Integral [uVrms]

4 406µVrms
2

0 2 4 6 8 10 12
10 10 10 10 10 10
Frequency [Hz]

B. Murmann EE315A - Chapter 3 44

 .Noise Simulation (φ2)
-15
10

PSD [V2/Hz]
-20
10

-25
10 2 4 6 8 10 12
10 10 10 10 10 10
Frequency [Hz]
-4
x 10
4
Integral [uVrms]

266µVrms
2

0 2 4 6 8 10 12
10 10 10 10 10 10
Frequency [Hz]

2
v out,tot = ( 406µVrms )2 + ( 266µVrms )2 = 485µVrms

B. Murmann EE315A - Chapter 3 45

PSS Simulation Setup

Set “tstab” if your circuit needs time

to reach steady state
(e.g. clock bootstrap circuits)

Under “options” set “maxacfreq” to

the highest frequency from which
you expect noise to fold down

B. Murmann EE315A - Chapter 3 46

 PSS Waveforms (Clocks)

4.75ns

B. Murmann EE315A - Chapter 3 47

PNOISE Simulation Setup

Numsidebands ≅ fmax/fs, where fmax is the

maximum frequency from which you expect
significant noise folding

“timedomain” means simulator computes

spectrum of discrete time noise samples at
the specified sampling instant

Sampling instant (4.75ns in this example)

B. Murmann EE315A - Chapter 3 48

 How to Chose Parameters

• Maxacfreq must be set commensurate with the speed

of the switches
– Common pitfall: Use nice 1mΩ switches
must
consider noise from “DC to daylight”
• In our example

1 10
Maxacfreq ≅ 10 ⋅ = ⋅ N ⋅ fs
2πRonC π

Maxacfreq ≅ 3 ⋅ 50 ⋅ 100MHz = 15GHz

B. Murmann EE315A - Chapter 3 49

How to Chose Parameters

• In traditional PSS/PNOISE simulators (such as
SpectreRF), simulation time increases rapidly for large
values of Numsidebands
• Berkeley Design Automation (BDA) Analog FastSPICE
(AFS) automatically includes an infinite number of
sidebands at significantly reduced simulation times

Maxacfreq 15GHz
Numsidebands ≅ = = 150
fs 100MHz

B. Murmann EE315A - Chapter 3 50

 PNOISE Result (SpectreRF)

Sampled Noise PSD Integrated Noise

B. Murmann EE315A - Chapter 3 51

Transient Noise
• Simulated 1000 samples
• Only one critical setting: noisefmax = 15 GHz

B. Murmann EE315A - Chapter 3 52

 Comparison
• Very good agreement between hand calculation and all three
simulation approaches

φ1 Noise φ2 Noise Total

Method Comment
[µVrms] [µVrms] [µVrms]
Calculation 406 245 474 Neglected switch noise during φ2

smaller value than .NOISE
.NOISE 406 266 485
PNOISE - - 475 Somewhat smaller than .NOISE
due to finite Maxacfreq and
Numsidebands
TRAN - - 477 Somewhat smaller than .NOISE
NOISE due to statistical fluctuations (can
use more samples)

B. Murmann EE315A - Chapter 3 53

Advantages of TRAN NOISE

• Takes advantage of rapid advancements in very fast,

spice-accurate transient simulators (such as BDA AFS)
– Can handle much larger circuits compared to
PSS/PNOISE (PSS tends to have convergence issues
for large circuits)
• Intuitive inspection of waveforms
• No need to combine noises manually
– Compared to .ac/.noise simulation flow
• Applicable also to non-periodic circuits

B. Murmann EE315A - Chapter 3 54

 Noise in SC Gain Stage with CDS
• The same principles apply
– See e.g., K. Ragab, M. Kozak, Nan Sun, "Thermal Noise Analysis of a
Programmable-Gain Switched-Capacitor Amplifier With Input Offset
Cancellation," IEEE TCAS2, vol.60, no.3, pp. 147-151, March 2013.

• We’ll take a closer look in a homework assignment

B. Murmann EE315A - Chapter 3 55

Summary
• Modern SC noise analysis is based on discrete time models
• The basic passive SC track and hold comes with a large noise
penalty (ENBW = M times signal bandwidth)
– The boxcar architecture fixes this problem
• SC gain stage noise analysis: Analyze total integrated noise in
both phases and combine
• SC noise simulation takes time to get used to, but is generally
manageable (PNOISE or TRAN NOISE are robust and well
understood)
– In any case, always try to match simulations to a known
result from hand analysis (start with a “hello world” circuit>)

B. Murmann EE315A - Chapter 3 56

 References
• C.-A. Gobet and A. Knob, “Noise Generated in Switched Capacitor
Networks,” Electronics Letters, vol.16, no. 19, pp. 734-735, Sep. 1980.
• J. H. Fischer, "Noise sources and calculation techniques for switched
capacitor filters," IEEE J. Solid-State Circuits, vol. 17, no. 4, pp. 742-
752, Aug. 1982
• C.-A. Gobet and A. Knob, "Noise analysis of switched capacitor
networks," IEEE Trans. Circuits and Systems, vol. 30, no. 1, pp. 37-
43, Jan 1983
• J. Goette and C.-A. Gobet, "Exact noise analysis of SC circuits and an
approximate computer implementation," IEEE Trans. Circuits and
Systems, vol. 36, no. 4, pp.508-521, Apr. 1989.
• R. Schreier, et al., "Design-oriented estimation of thermal noise in
switched-capacitor circuits," IEEE Trans. Circuits and Systems I, vol.
52, no. 11, pp. 2358-2368, Nov. 2005
• K. Kundert, “Simulating Switched-Capacitor Filters with SpectreRF,”
http://www.designers-guide.org/Analysis/sc-filters.pdf
B. Murmann EE315A - Chapter 3 57

References
• B. Murmann, "Thermal Noise in Track-and-Hold Circuits:
Analysis and Simulation Techniques," IEEE Solid-State Circuits
Magazine, vol. 4, no. 2, pp. 46-54, June 2012.
• K. Ragab, M. Kozak, Nan Sun, "Thermal Noise Analysis of a
Programmable-Gain Switched-Capacitor Amplifier With Input
Offset Cancellation," IEEE TCAS2, vol.60, no.3, pp. 147-151,
March 2013.
• A. Dastgheib and B. Murmann, “Calculation of Total Integrated
Noise in Analog Circuits,” IEEE TCAS1, vol. 55, no. 10, pp.
2988-2993, Oct. 2008.
• Lennart Mathe and David C. Lee, "Analog-to-Digital Converter
Performance Signoff with Analog FastSPICE Transient Noise at
Qualcomm," Berkeley Design Automation, www.berkeley-
da.com.

B. Murmann EE315A - Chapter 3 58

 Operational Transconductance Amplifiers
- Part 1 -

Boris Murmann
Stanford University
[email protected]
Copyright © 2014 by Boris Murmann

B. Murmann EE315A - Chapter 4 1

Outline
• Basic considerations
– OTAs vs. OpAmps
– Application requirements for OTAs
– The case for fully differential circuits
– Gm/ID-based design
• Analysis of the basic differential pair topology
– CMFB, linear half circuit model
– Feedback analysis, linear settling
– Slewing
– Noise analysis
– Feedback factor optimization
• Topologies for increased gain and signal swing
– Telescopic architecture
– Current mirror architecture
– Folded cascode architecture
• Folded cascode OTA design example

B. Murmann EE315A - Chapter 4 2

 Classification of “OpAmps” (1)

• Type
– Operational Amplifier
• Ideally a voltage-controlled voltage source
• Typically contains an output stage that can drive “arbitrary”
loads, including small resistances
• Predominantly used for board-level circuitry
– Operational Transconductance Amplifier (OTA)
• Ideally a voltage controlled current source
• Typically restricted to capacitive (or moderate resistive) loads
• Primarily used in integrated circuits

B. Murmann EE315A - Chapter 4 3

OTA versus OpAmp

OpAmp Symbol
OpAmp

OTA Symbol
(Fully Differential)

OTA

B. Murmann EE315A - Chapter 4 4

 Classification of “OpAmps” (2)

• Output configuration
– Single ended
– Differential
• Predominantly used for integrated high-performance or high-
precision amplifiers
• Requires common mode feedback circuit
– Class-A
• Output cannot source/sink currents larger than quiescent point
bias current
– Class-AB
• Output can provide large drive currents “on demand”
– Dynamic, comparator-based
• Still a research topic)

B. Murmann EE315A - Chapter 4 5

Fully Differential vs. Single Ended

vin

vout

• Symmetrical • Lower complexity

– Immune to coupling and – Important for PCB design
power supply noise • Can build non-inverting unity
– Easy to analyze gain buffer without any feedback
• Can invert signal via wire crossing components
• Requires common mode
feedback (CMFB)

B. Murmann EE315A - Chapter 4 6

 Coupling Noise

Single Ended Signaling Differential Signaling

• Similar arguments can be made regarding the rejection of

supply noise, ground bounce, substrate noise, etc.

B. Murmann EE315A - Chapter 4 7

Fully Differential vs. Single Ended

• Most analog ICs targeting precision signal processing are based

on fully differential stages
– Filters, data converters, etc.
• In contrast, printed circuit board circuits tend to be single ended
– Want minimum complexity and component count
• Since this class emphasizes integrated circuit design, we will
tailor our analyses toward fully differential implementations

B. Murmann EE315A - Chapter 4 8

 OTA Application in Filters

Active RC C Gm-OTA-C

R
RL

( )

CI
Switched Capacitor
φ1 Cs φ2
φ2
φ2 φ1e
CL

B. Murmann EE315A - Chapter 4 9

Requirements (1)

Active RC Gm-OTA-C SC

High gain X X X

Low noise X X X

High BW X X X

Capacitive loads X X X

Resistive loads X

Fast settling X

B. Murmann EE315A - Chapter 4 10

 Requirements (2)

• Special requirements in active-RC and SC circuits

– Tend to narrow design space
• Active RC
resistive loads
– Difficult to achieve sufficient gain with a single-stage OTA
• SC
fast transient settling
– Must stay away from “tricks” such as pole-zero cancellation
• Pole zero doublets can cause long setting tails (more later)
– Hard to achieve fast settling for three or more stages

B. Murmann EE315A - Chapter 4 11

Loading Considerations (1)

ron||rop
vo
Single-ended OTA model

vi RL CL

• Low load resistance will "destroy" the gain of our amplifier

– RL may be an explicit load or due to loading from the
feedback network
• But, we want large (loop) gain for good precision

B. Murmann EE315A - Chapter 8 12

 Loading Considerations (2)

Single-ended OpAmp model

• Adding a buffer allows us to drive resistive loads and still

achieve high gain
• But
– Buffer can be difficult to build
– Is costly in terms of headroom (e.g. source follower)
– Adds additional area, power

B. Murmann EE315A - Chapter 8 13

Loading Considerations (3)

Single-ended model of
a two-stage OTA

• Resistive load "destroys" gain of second stage only

– First stage sees capacitive load
• Costs additional area, power and must sacrifice stage 2 gain
• Can work acceptably well for moderate resistive loads

B. Murmann EE315A - Chapter 8 14

 Transistor Sizing

Gm = gm1a = gm1b

• Typical problem
– Want to realize a certain amount of gm
– Need to determine W, L, ITAIL
• Classical square-law equations are very inaccurate for modern
technologies

W
gm = 2ID μCox
L

B. Murmann EE315A - Chapter 4 15

The Problem

Specifications

Square Law Hand Calculations

Circuit

BSIM or PSP Spice

Results

• Since there is a disconnect between actual transistor behavior

and the simple square law model, any square-law driven design
optimization will be far off from Spice results

B. Murmann EE315A - Chapter 4 16

 The Solution

 Use pre-computed spice data in hand calculations

B. Murmann EE315A - Chapter 4 17

Simulation Data in Matlab

% data stored in /usr/class/ee315a/matlab
>> load 180nch.mat;
>> nch Four-dimensional arrays
nch =
ID: [4-D double]
VT: [4-D double]
GM: [4-D double]
GMB: [4-D double]
஽ , ீௌ , ஽ௌ , ௌ 
GDS: [4-D double]
CGG: [4-D double]
CGS: [4-D double] ௧ , ீௌ , ஽ௌ , ௌ 
CGD: [4-D double]
CGB: [4-D double]
CDD: [4-D double]
CSS: [4-D double]
௠ , ீௌ , ஽ௌ , ௌ 
VGS: [73x1 double]
VDS: [73x1 double]
VS: [11x1 double]
…
L: [22x1 double]
W: 5

>> size(nch.ID)

ans =
22 73 73 11

B. Murmann EE315A - Chapter 4 18

 Lookup Function (For Convenience)

>> lookup(nch, 'ID', 'VGS', 0.5, 'VDS', 0.5)

ans = 8.4181e-006

>> help lookup

Rev. 20140820, Boris Murmann

The function "lookup" extracts a desired subset from the 4-dimensional
simulation data. The function interpolates when the requested points lie off
the simulation grid

There are three usage modes:

(1) Simple lookup of parameters at some given (L, VGS, VDS, VSB)
(2) Lookup of arbitrary ratios of parameters, e.g. GM_ID, GM_CGG at given (L,
VGS, VDS, VSB)
(3) Cross-lookup of one ratio against another, e.g. GM_CGG for some GM_ID

In usage modes (1) and (2) the input parameters (L, VGS, VDS, VSB) can be
listed in any order and default to the following values when not specified:

L = min(data.L); (minimum length used in simulation)

VGS = data.VGS; (VGS vector used during simulation)
VDS = max(data.VDS)/2; (VDD/2)
VSB = 0;

B. Murmann EE315A - Chapter 4 19

Figures of Merit for Design

Square Law
• Transconductance efficiency gm 2
– Want large gm, for as little =
current as possible ID VOV

• Transit frequency
gm 3 µVOV
– Want large gm, without large Cgg ≅
Cgg 2 L2

• Intrinsic gain
– Want large gm, but no go gm 2
≅
go λVOV

B. Murmann EE315A - Chapter 4 20

 Design Tradeoff: gm/ID and fT
40

fT
gm/ID [S/A], f T [GHz]
30 Moderate Inversion

gm/ID
20
Weak Inversion Strong Inversion

10

0
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
VOV [V]

• Weak inversion: Large gm/ID (>20 S/A), but small fT

• Strong inversion: Small gm/ID (<10 S/A), but large fT

B. Murmann EE315A - Chapter 4 21

Product of gm/ID and fT

250

200
gm/ID⋅f T [S/A⋅GHz]

150 Moderate Inversion

100

50
Weak Inversion Strong Inversion

0
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
VOV [V]

• Interestingly, the product of gm/ID and fT peaks in moderate inversion

• Operating the transistor in moderate inversion is optimal when we value
speed and power efficiency equally
– Not always the case

B. Murmann EE315A - Chapter 4 22

 Transit Frequency Chart

L=0.18um

L=0.5um

B. Murmann EE315A - Chapter 4 23

Intrinsic Gain Chart

L=0.5um

L=0.18um

B. Murmann EE315A - Chapter 4 24

 Current Density Chart

L=0.18um

L=0.5um

B. Murmann EE315A - Chapter 4 25

Extrinsic Capacitances
NMOS, L=0.18um
1
Cdd/Cgg
Cgd/Cgg
0.8
 Typically OK to
0.60 work with
0.6 estimates taken
at VDD/2
0.4
0.24
0.2

0
0 0.5 1 1.5
VDS [V]

B. Murmann EE315A - Chapter 4 26

 Generic Design Flow

1) Determine gm (from design objectives)

2) Pick L
 Short channel
high fT (high speed)
 Long channel
high intrinsic gain
3) Pick gm/ID (or fT)
 Large gm/ID
low power, large signal swing, low VDSsat ≅ 2/(gm/ID)
 Small gm/ID
high fT (high speed)
4) Determine ID (from gm and gm/ID)
5) Determine W (from ID/W)

Many other possibilities exist (depending on circuit specifics, design

constraints and objectives)

B. Murmann EE315A - Chapter 4 27

Basic Differential Pair OTA

VDD

MP1a MP1b
MPB

Vom - Vod + Vop

Vip Vim
MN1a MN1b

IT/2 IT

• Suppose that in the operating point Vip=Vim, i.e. Vid=0

• What is the output common mode voltage Voc = (Vom+Vop)/2 ?

B. Murmann EE315A - Chapter 4 28

 Operating Point Sensitivity

• The operating point is very sensitive to small changes in the

device characteristics
• Solution: Common mode feedback (CMFB)

B. Murmann EE315A - Chapter 4 29

CMFB

• Common mode feedback loop adjusts ∆I such that VOC is very

close to the desired voltage

B. Murmann EE315A - Chapter 4 30

 Idealized CMFB Implementation

∆I

∆I
Voc = Voc,des + = Voc,des for GCMFB → ∞
GCMFB

B. Murmann EE315A - Chapter 4 31

CMFB Implementation

• In practice, we won’t be able to let GCMFB
∞ for loop stability

– Nonetheless, the loop will get us to within a few mV of where
we need to be
– Good enough to suppress variations in device characteristics
• In the first module on OTA design, we will use the idealized
common mode feedback circuit (as shown previously) to avoid
distraction from the main design task
• Practical CMFB implementation examples (using transistors) will
follow in the next module

B. Murmann EE315A - Chapter 4 32

 Differential Mode Small Signal Half Circuit

• With the circuit at the proper operating point, we can analyze its
small-signal behavior using a differential mode half circuit model
• Note that (to first order) the CMFB loop does not influence the
behavior of the differential mode signals

B. Murmann EE315A - Chapter 4 33

OTA with Capacitive Feedback

• Let’s get started by placing our simple OTA into a capacitive

feedback loop (as encountered in an SC circuit)
• Questions
– What is the phase margin?
– What is the closed loop transfer function?
– How fast does this circuit settle (in response to a step)?
– What is the total integrated output noise?

B. Murmann EE315A - Chapter 4 34

 Half Circuit Model

Gm = gmn
Cftot
Ro = rop ||ron

Co = Cdbp + Cdbn

Cx = Cgsn + Cgbn

B. Murmann EE315A - Chapter 4 35

Return Ratio Analysis

vx =  ∙ vo

Cftot
β=
Cftot + Cs + Cx

“Feedback factor”

1
vo = ‒it · Ro || CLtot = CL + Co + 1‒ β Cftot
sCLtot

ir 1 β·Gm Ro β·a0
T s = ‒ = β·Gm · Ro || = =
it sCLtot 1 + sRo CLtot 1 + sRo CLtot

B. Murmann EE315A - Chapter 4 36

 Frequency Response of T(s)

T ( jω ) Ro→∞
T0 = βGm Ro
T0
1
ωpo =
Ro CLtot
ω
ω po ωc

βGm Ro βGm βGm 1 ω

T s = = ≌ for Ro ≫ ⇔ ≫1
1 + sRo CLtot 1 + sC sCLtot sCLtot ωpo
Ro Ltot

βGm Gm
Ro is irrelevant for

=1 ⇒ ωc ≌ β understanding the high-frequency
jωc CLtot CLtot
behavior around ωc

B. Murmann EE315A - Chapter 4 37

Phase Margin

T jω Ro→∞ βGm Ro
T jω = ω
T0 1+j
ωpo

βGm Ro
T jωc = ω
ω 1+j c
ωpo ωc ωpo

|ω=ω = ‒ tan‒1
∡ T jω ωc
∡ T jω c ≌ ‒ 90°
ωpo
ωpo
0° ω
−45° PM ≌ 180° ‒ 90° ≌ 90°

−90° Boring result)

B. Murmann EE315A - Chapter 4 38

 Closed Loop Transfer Function

vo T s d
A s = = Aஶ +
vi 1+T s 1+T s

• Need to find A∞ and d

– Let’s start with A∞ Gm → ∞ ⇒ vx → 0 ⇒ ix → 0

Cftot 0 = vi sCs + vo sCftot

Cs
vi vx vo

vo Cs
Aஶ = = ‒
ix Ro CL+Co vi G →∞ Cftot
m
Cx Gmvx

“Ideal closed-loop gain”

B. Murmann EE315A - Chapter 4 39

Finding d at Low Frequencies

• Capacitors are open circuits

ቤ
vo
d0 = =0
vi
Gm =0

B. Murmann EE315A - Chapter 4 40

 Low-Frequency Closed-Loop Gain

T0 d0 Cs
A0 = Aஶ + Aஶ = ‒ T0 = βGm Ro d0 = 0
1 + T0 1 + T0 Cftot
Cs 1
⇒ A0 = ‒
Cftot 1
1+
βGm Ro

• Error in low-frequency closed-loop gain

A0 ‒ Aஶ A T0 1 1 1
ε0 = = 0 ‒1= ‒1= ‒1≌ 1‒ ‒1=‒
Aஶ Aஶ 1 + T0 1 T0 T0
1+
T0
1
ε0 ≌ Gain Error = 1/Loop Gain
T0

B. Murmann EE315A - Chapter 4 41

d at High Frequencies

Cs
ieq = v i ⋅ sCftot = v i β ⋅ sCs Ceq = (1 − β ) Cftot
Cs + Cx + Cftot

vo 1 i eq C
d= = =β s
vi Gm = 0 (
v i s Ceq + CL + Co CLtot )

B. Murmann EE315A - Chapter 4 42

 High-Frequency Closed-Loop Gain (1)

T( s ) d
A(s ) ≅ A∞ +
1+ T ( s ) 1+ T ( s )
βGm βCs C s
1 − s ftot
Cs sCLtot CLtot Cs Gm Cs 1 − z
≅− + =− =−
Cftot βGm βGm Cftot
CLtot Cftot 1 − s
1+ 1+ 1+ s
sCLtot sCLtot βGm p

• Pole frequency:
As expected.
β Gm β GmRo (Feedback moves poles
ωp ≅ ≅ ωc ≅ ≅ T0 ⋅ ω po
CLtot RoCLtot by same the same factor
it reduces the gain)

B. Murmann EE315A - Chapter 4 43

High-Frequency Closed-Loop Gain (2)

Cftot s
1− s
Cs Gm Cs 1 − z
A( s ) = − =−
Cf 1 + s CLtot Cf 1 − s
βGm p

• Zero frequency:

Gm ωz C
ωz = = Ltot usually >> 1
Cftot ωp βCftot

• Therefore, the closed-loop -3dB frequency is approximately

βGm
ω−3dB ≅ ωp ≅
CLtot

B. Murmann EE315A - Chapter 4 44

 Putting it All Together

s
Cs 1 1 − z
A(s ) ≅ −
Cf 1 + 1 1 − s
T0 p

T0 = βGm R0

βGm
p≅−
CLtot

Gm
z≅+
Cftot

Cftot
β=
Cftot + Cs + Cx

B. Murmann EE315A - Chapter 4 45

Settling Performance

Vin φ1 φ2
φ2
φ1
φ2 φ1e
Vout
φ2
CL

time

• In switched capacitor circuits the amplifier is subjected to

transient pulses
• Output must “settle” within the ϕ2 clock phase, so that a proper
voltage level is sampled on CL

B. Murmann EE315A - Chapter 4 46

 Analysis

Assuming that the switches

are properly sized, we can
assume that the OTA
determines the dynamic
response

• Assuming a single stage OTA, we have

Vout ( s ) C 1 1 Gm
A (s ) = ≅− s ⋅ T0 = β ⋅ Gm Ro ωc ≅ β ⋅
Vin ( s ) Cf 1 + 1 1 + s CLtot
T0 ωc

B. Murmann EE315A - Chapter 4 47

Step Response

Vout ( s ) = A( s ) ⋅Vin ( s )

Vout (t ) = L−1 { A(s ) ⋅Vin (s )}

 Vstep  Cs T 1
Vout ( t ) = L−1  A( s ) ⋅
 s 
=−
Cf 1 + T0
(
⋅ Vstep ⋅ 0 ⋅ 1 − e −t / τ ) τ=
ωc

Ideal Due to Due to

Response Finite DC Finite
Loop Gain Bandwidth

• Finite DC loop gain results in a static error ε0

• Finite bandwidth results in a dynamic error εd that decays with time

B. Murmann EE315A - Chapter 4 48

 Graphical Illustration
Dynamic Static
Error εd(t) Error ε0

0.8
out,ideal

0.6
/V
out
V

0.4

0.2

0
0 2 4 6 8 10
t/τ

B. Murmann EE315A - Chapter 4 49

Design Considerations (1)

• Need large DC loop gain for small static error

– |ε0| ≅ 1/T0
– E.g. need T0 > 1000 for better than 0.1% precision
• Need small τ (large bandwidth) for fast settling
• Can define “settling time” based on tolerable dynamic error

−εd ,tol = −e −ts / τ

ts = −τ ⋅ ln ( εd ,tol )

B. Murmann EE315A - Chapter 4 50

 Design Considerations (2)

εd,tol ts/τ

1% 4.6

0.1% 6.9

0.01% 9.2

10-6 13.8

• Going from 1% dynamic precision to 10-6 necessitates only ~3x

increase in settling time

B. Murmann EE315A - Chapter 4 51

Design Considerations (3)

• A switched capacitor circuit operates in two clock phases
• Fitting the required number of time constants within ½ period
lets us relate fs to a minimum bandwidth requirement
1 11 fc 1
ts = − ⋅ ln ( εd ,max ) < > − ln ( εd ,max )
2π ⋅ fc 2 fs fs π

εd fc/fs
1% 1.5
0.1% 2.2
0.01% 2.9
10-6 4.4

B. Murmann EE315A - Chapter 4 52

 Simulation Example

• Using single stage OTA

• Parameters
– Cs=Cf=500fF, CL=10pF, β=0.48, Gm=1mS, GmRo=85, Vidstep=-10mV

B. Murmann EE315A - Chapter 4 53

Result

1 CL + (1 − β ) Cf Vod ,final = −Vidstep

β ⋅ Gm R0
= 9.76mV
τ= = 21ns
β Gm 1 + β ⋅ Gm R0

10

8
Voltage [mV]

4
-V
id
Vod (simulation)
2
Vod (theory)
0

0 50 100 150 200

Time [ns]

B. Murmann EE315A - Chapter 4 54

 Another Run
• Changed CL from 10pF to 300fF

10

-V
id
Vod (simulation)
Voltage [mV]

5
Vod (theory?)

-5
0 5 10 15 20 25
Time [ns]
• What's this ?

B. Murmann EE315A - Chapter 4 55

Capacitive Feedforward
• In the first instant after the input step has been applied, the
output is completely determined by capacitive voltage division
• Half circuit during initial transient

Vodstep Cs Cf
= ⋅
Vidstep Cf CL Cf + CL
Cs + Cin +
Cf + CL

B. Murmann EE315A - Chapter 4 56

 Analysis
• Can analyze this effect in two (equivalent) ways
– Using capacitive divider to find new starting point of
exponential
– Using inverse Laplace transform of A(s) with high frequency
zero included
• Recall that A(s) is more precisely given by

s Gm
1− z=
Cs 1 z Cf
A (s ) = −
Cf 1 + 1 s
1− βGm
T0 p p=−
CLtot

B. Murmann EE315A - Chapter 4 57

New Result

 Vstep  Cs T   p 
Vod (t ) = L−1  A(s ) ⋅ =− ⋅Vidstep ⋅ 0 ⋅  1 − 1 −  e −t / τ 
 s  Cf 1 + T0   z 

New

p CL + (1 − β ) Cf + βCf CL + Cf 1
1− = = =
z CL + (1 − β ) Cf CL + (1 − β ) Cf 1 − β Cf
Cf + CL
• For our example:
1
= 1 .4 ⇒ Vod ( t = 0 ) ≅ 10mV (1 − 1.4 ) = −4mV
500fF
1 − 0.48
500fF + 300fF

• Good agreement with simulation

B. Murmann EE315A - Chapter 4 58

 New Settling Time

  Cf  
ts = −τ ⋅ ln  εd ,tol 1 − β ⋅ 
 Cf + CL  
 

<1

• Settling time for given precision increases due to feedforward,

since the settling range is artificially enlarged
• E.g., in our simulation example, the time to settle within 0.1%
dynamic error increases from 6.9τ to 7.3τ
– Not all that significant, especially when β is low and CL is at
least comparable to Cf

B. Murmann EE315A - Chapter 4 59

Another Simulation

• Set Vidstep=-1V (CL=10pF ⇒ insignificant feedforward to output)

1000

800
-Vid
Voltage [mV]

600 Vod (simulation)

Vod (theory?)
400

200

0 50 100 150 200

Time [ns]
• What causes this discrepancy ?

B. Murmann EE315A - Chapter 4 60

 Capacitive Divider at OTA Input
• Half circuit during initial transient:

Vxdstep/2
Cf

Cs
Vim Vop
500fF

500fF Vodstep/2
Vidstep/2 Cin CL
40fF 10pF

Cs 500fF
Vxdstep = Vidstep ≅ −1V = −480mV
CC 500fF + 40fF + 500fF
Cs + Cin + f L
Cf + CL

• Initially -480mV across differential pair input!

B. Murmann EE315A - Chapter 4 61

Differential Pair Characteristics

• Differential output current saturates for |Vid| > 2 ⋅VOV
•  than that predicted
Beyond this point, current will be much less
by linear model (slope at origin)

1
Slope = 1

2
Iod/ITAIL 0 VOV = VGS − Vt ≅
gm
ID

1
2 1 0 1 2
-√2 Vid/VOV √2

B. Murmann EE315A - Chapter 4 62

 Differential Pair Input Voltage vs. Output Current

0
-100
"Slewing" "Linear Settling"
Vxd [mV]
-200
-300
2 2
-400 −
gm
-500 ID
0 50 100 150
Time [ns]
0
Diff. pair I od [µA]

-100

-200

-300
0 50 100 150
Time [ns]

B. Murmann EE315A - Chapter 4 63

Slewing

• During "slewing", the amplifier drives its output with an

approximately constant current (equal to tail bias)
• The slewing behavior ends when |Vid| has become smaller than
about 1.4·(2/gm/ID)
– This is the point when the diff pair re-enters its "linear region"
– Hence, the remaining portion of the settling is often called
"linear settling"
• Note that this is not meant to say that the output changes with a
constant rate during this time; it settles with a (1-et/τ)
relationship
• The total settling time of the amplifier in presence of slewing can
be calculated as shown in the following derivation

B. Murmann EE315A - Chapter 4 64

 Slew Rate

• In order to find the time it takes to complete slewing, we can first

calculate the "ramp speed" at which the output changes
– This quantity is called "Slew Rate" (SR)

dVod ITAIL
SR = =
dt CLtot

B. Murmann EE315A - Chapter 4 65

Slewing Time
• The input of the differential pair changes at a rate equal to β·SR,
where β is given by the usual capacitive feedback divider
• Hence, the time it takes to complete slewing is given by

Vxstep − 2.8 / ( gm / ID )
tslew ≅
β ⋅ SR

• In our example, we have

ITAIL 200µA V
SR = ≅ = 20
CLtot 10 pF µs

480mV − 280mV
tslew = = 21ns
V
0.48 ⋅ 20
µs

B. Murmann EE315A - Chapter 4 66

 Subsequent Linear Settling
• Once slewing is completed, the differential output voltage is

Vod ,slew = Vod ,final − Vod ,lin = tslew ⋅ SR = 420mV

• The final settling value in our example is roughly 1V

– Almost half way there after slewing
• This means that the dynamic error budget for the remaining
settling portion (Vod,lin) has increased
– E.g. if we wanted to settle within 0.1% of the final value
(~1V), we only need to complete the remaining transient to
within 0.1%·1V/0.58V = 0.17%
– Not a very big change, usually a negligible change in the
number of required time constants
• 0.1%
6.9τ versus 0.17%
6.4τ

B. Murmann EE315A - Chapter 4 67

Complete Expression for Settling Time

Vxdstep − 2.8 / ( g m / ID )  V 
ts = tslew + tlin ≅ − τ ln  εd ,tol od ,final 
β ⋅ SR  Vod ,lin
 

Cs Cs
Vxdstep = Vidstep ≅ Vidstep
Cf CL Cs + Cin + Cf
Cs + Cin +
Cf + CL
<1

• Note that circuits with large closed loop gain tend to slew less
– Since Vid,step cannot be larger than Vod,final/Gain
– E.g. Vod,final=2V, Gain =8 ⇒ Vxdstep < Vidstep < 250mV
• The circuit won’t slew at all if gm/ID < 2.8/250mV = 11.2 S/A

B. Murmann EE315A - Chapter 4 68

 Design Considerations (1)

• In circuits with significant slewing (large inputs, small closed-

loop gain), it is best to design using a “divide and conquer”
strategy
1. Start by assuming a certain slewing time, e.g. 50% of total
settling time
2. Design the circuit such that linear settling completes within
remaining time (apply small steps only during test)
3. Now apply large step, measure actual slewing time
4. Go back to step 1 and redesign (if needed)
• This procedure converges to a viable design in 2-3 iterations
– Easy to handle, especially in a systematic, script-driven
design methodology

B. Murmann EE315A - Chapter 4 69

Design Considerations (2)

• Should I try to minimize the slewing time?

– The answer depends on the design objective
• In low-to-moderate speed circuits (operating far from technology
limits), slewing actually improves the power efficiency
– Intuition: The class-A bias current is put to best used when it
runs directly into the load, i.e. during slewing
• In high-speed circuits (close to process limits), one may have to
lower the slewing time by biasing the input pair at lower gm/ID
– Increase ID, keep gm constant
– Slewing performance improves, because of larger ID and also
because the differential pair input range increases (~1/[gm/ID])
– Small signal performance remains virtually unchanged or
improves if fT is a limiting factor (since fT increases)
– Issue: Power efficiency deteriorates
B. Murmann EE315A - Chapter 4 70
 Noise Analysis (1)

OK to use half circuit

model since tail current
noise is common mode.
1
R≅
βg mn Neglect finite output
resistance of the
MOSFETs.

2
v o2 1
∆f
(
= 4kT γ n g mn + γ p g mp ⋅ R )
j ω CLtot
2
 γ p g mp  R
= 4kT γ n g mn  1 + ⋅
 γ n g mn  1 + j ω RCLtot

B. Murmann EE315A - Chapter 4 71

Noise Analysis (2)

2
∞
 γ p g mp  R
v o2 = ∫ 4kT γ n g mn  1 + ⋅ df
0  γ n g mn  1 + j ω RCLtot

 γ p g mp  2 1
= 4kT γ n g mn  1 + ⋅R ⋅
 γ n g mn  4RCLtot

 γ p g mp  1 1
= 4kT γ n g mn  1 + ⋅ ⋅
 γ n g mn  β g mn 4CLtot

 
   g mp 
Want small
1 kT  γ p g mp  1 kT  γp ID  gmp/ID
= γn 1 + = γn 1 + 
β CLtot  1 γ n g mn  β CLtot  γ n g mn 
 424 3
 14243 ID 
  
 
Excess noise due
to active load

B. Murmann EE315A - Chapter 4 72

 Output Swing
VDD
VDsatp • Unfortunately, small
gmp/ID means reduced
output swing
Voc
Vavail 2
ܸ஽௦௔௧௣ ≅
݃௠௣ /‫ܫ‬஽
VDsatn
• There exists an optimum
choice of gmp/ID that
maximizes the circuit’s
dynamic range

ଶ
1 2 2
ܲ௦௜௚,௠௔௫ 2 ܸ௔௩௔௜௟ − ݃௠௡ /‫ܫ‬஽ − ݃௠௣ /‫ܫ‬஽
‫= ܴܦ‬ =
ܲ௡௢௜௦௘ ݇ܶ ߛ௣ ݃௠௣ /‫ܫ‬஽
2‫ܥ‬ ߛ௡ 1 + ߛ ⋅
௅௧௢௧ ௡ ݃௠௡ /‫ܫ‬஽

B. Murmann EE315A - Chapter 4 73

Optimum Choice (Example)

ଶ
K / max(K) (dB)

2 2 -1
ܸ௔௩௔௜௟ − −
݃௠௡ /‫ܫ‬஽ ݃௠௣ /‫ܫ‬஽
‫=ܭ‬
ߛ௣ ݃௠௣ /‫ܫ‬஽ -2
1+ ⋅
ߛ௡ ݃௠௡ /‫ܫ‬஽ Vavail=1.4V
-3 Vavail=1.0V
Vavail=0.6V
Example: -4
5 10 15 20 25 30
gmp/ID (S/A)
γp/γn = 1
gmn/ID = 15 S/A Conclusion: Optima are shallow
Vavail = 0.6, 1.0, 1.4 V
Start with gmp/ID = gmn/ID in a typical low
voltage design

B. Murmann EE315A - Chapter 4 74

 Feedback Factor Optimization (1)

ࢼ‫ܩ‬௠ 1 ‫ܥ‬௙
‫∝ ܹܤ‬ ‫∝ ܴܦ‬ ߚ=
‫ܥ‬௅௧௢௧ 1 ݇ܶ ‫ܥ‬௙ + ‫ܥ‬௦ + ࡯࢏࢔
ࢼ ‫ܥ‬௅௧௢௧

• Large β helps improve BW and DR Cf

• However, large β also implies small

Cin, which means small Gm and Cs
Vout
reduced BW Gm
– Since Gm = ωTCgs = ωTCin Cin CL

• There exists an optimum vale for Cin

that optimizes the product of BW and
DR

B. Murmann EE315A - Chapter 4 75

Optimum Cin
ߚ‫ܩ‬௠
‫ܥ‬௅௧௢௧ ௙
‫∝ ܴܦ ⋅ ܹܤ‬ ∝ ߚ ଶ ‫ܩ‬௠
= ௠ =  ் ࢏࢔
݇ܶ ௙ + ௦ + ࢏࢔
βC୐୲୭୲
ଶ ௙
1
‫∝ ܴܦ ⋅ ܹܤ‬ ࡯࢏࢔
௜ௗ௘௔௟ =
‫ܥ‬௙ + ‫ܥ‬௦ + ࡯࢏࢔ ௙ + ௦

‫ܥ‬௜௡,௢௣௧ = ‫ܥ‬௙ + ‫ܥ‬௦

Normalized BW⋅DR

0.8
ߚ௜ௗ௘௔௟
0.6 ߚ௢௣௧ =
2
0.4
If the tradeoff between power
0.2 and bandwidth was perfectly
0.5 1 1.5 2 2.5 3 3.5 4
linear, then this would also be
Cin / (Cs+Cf)
the optimum of BW*DR/P

B. Murmann EE315A - Chapter 4 76

 Feedback Factor Optimization (2)
Cf
Look at exact tradeoff and try to find optimum

ߚ‫ܩ‬௠ 1
⋅ Cs
‫ܥ‬௅௧௢௧ 1 ݇ܶ Vout
‫ܴܦ ⋅ ܹܤ‬ ߚ ‫ܥ‬௅௧௢௧ ‫ܩ‬௠ Gm
∝ ∝ ߚଶ
ܲ ‫ܫ‬஽ ‫ܫ‬஽
‫ܩ‬௠ ⋅
‫ܩ‬௠ Cin CL=kCf

‫ܥ‬௙ 1 ‫ܥ‬௦ ‫ܩ‬௠

ߚ= = ‫=ܩ‬ ‫ܥ‬௜௡ =
‫ܥ‬௙ + ‫ܥ‬௦ + ‫ܥ‬௜௡ 1 + ‫ ܩ‬+ ‫ܥ‬௜௡ ‫ܥ‬௙ ்߱
‫ܥ‬௙
1 1
ߚ= = ߱ ߚ‫ܩ‬௠ ߚ‫ܩ‬௠ ߚ‫ܩ‬௠
‫ܩ‬௠ 1 1+‫ܩ‬+‫ ⋅ݎ‬௨
1+‫ܩ‬+ ⋅ ்߱ ߱௨ = = =
‫ܥ‬௙ ߱ ் ‫ܥ‬௅௧௢௧ ‫ܥ‬௙ + 1 − ߚ ‫ܥ‬௙ ݇ + 1 − ߚ ‫ܥ‬௙
߱௨
݇+1−ߚ 1− ݇+1 ‫ܩ‬௠ ݇+1−ߚ
்߱
‫=ݎ‬ ߚ= ߱ = ߱௨ ⋅
ߚ ‫ܩ‬+1− ௨ ‫ܥ‬௙ ߚ
்߱
(approaches βideal for ωT→∞)

B. Murmann EE315A - Chapter 4 77

Feedback Factor Optimization (2)

‫ܩ‬௠ Γ ‫ܩ‬௠
= Γ= ⋅ ߱ ் = ܿ‫ݐݏ݊݋‬. (assuming square law)
‫ܫ‬஽ ்߱ ‫ܫ‬஽

‫ܩ‬௠ ߱௨ Γ ߱௨
= ⋅ ∝ ߱௨ = ܿ‫ݐݏ݊݋‬. (assume ωu is a given spec)
‫ܫ‬஽ ߱ ் ߱௨ ߱ ்

߱௨ ଶ
‫ܴܦ ⋅ ܹܤ‬ ‫ܩ‬௠ ݇+1 −1 ߱௨
்߱
∝ ߚଶ ∝ ߱
ܲ ‫ܫ‬஽ ‫ܩ‬+1− ௨ ்߱
்߱

߱௨
݇+1 −1
்߱
ߚ= ߱ Plot this3
‫ܩ‬+1− ௨
்߱

B. Murmann EE315A - Chapter 4 78

 Optimum (for G=2, as an example)

Normalized BW⋅DR/P
1

0.5 k=1
k=2
0
2 4 6 8 10 12 14
ω T/ω u

1
β/βiideal

0.5

0
2 4 6 8 10 12 14
ω T/ω u

B. Murmann EE315A - Chapter 4 79

Optimum versus G

10
(ωT/ωu)opt

4
0 2 4 6 8 10
G

0.72
k=1
βopt/βiideal

0.7 k=2
0.68

0.66
0 2 4 6 8 10
G

B. Murmann EE315A - Chapter 4 80

 Optimum versus k=CL/Cf

(ωT/ωu)opt 40

Line for G=2:

20 2.5 + 3k
G=2
G=4 Very useful for estimating fT
0 requirements!
0 2 4 6 8 10
k

0.7
βopt/βiideal

Bottom line: optimal feedback

0.68 factor for a single stage design
is about 0.7, independent of
gain and loading
0.66
0 2 4 6 8 10
k

B. Murmann EE315A - Chapter 4 81

Outline
• Basic considerations
– OTA vs. OpAmps
– Application requirements for OTAs
– The case for fully differential circuits
• Analysis of the basic differential pair topology
– CMFB, linear half circuit model
– Feedback analysis, linear settling
– Slewing
– Noise analysis
– Feedback factor optimization
• Topologies for increased gain and signal swing
– Telescopic architecture
– Current mirror architecture
– Folded cascode architecture
• Folded Cascode OTA Design Example

B. Murmann EE315A - Chapter 4 82

 Problem with Simple OTA: Swing

• Can get reasonable swing

only if input and output
common mode adjusted
such that all devices operate
at "edge" of active region
• Unfortunately, the choice of
Vic and Voc are sometimes
dictated by the circuits that
interface with the amplifier
– E.g. Vic = Voc = VDD/2

(
Vodpp,max = 2 VDD − VDsatp − VDsatn − VDsat,tail )

B. Murmann EE315A - Chapter 4 83

Example Vic=Voc=VDD/2

• Assuming that we are limited by Vminn, and Vminn~VOV, the

available differential peak-to-peak swing is ~4Vt
• Since the transition to triode is smooth, which criterion should
we use find the "exact" output range of an amplifier?

B. Murmann EE315A - Chapter 4 84

 Gain vs. Output Swing DC Simulation

90

80
Vod/Vid [V/V] -30%
70

60

Vodpp,max
50

40
-1.5 -1 -0.5 0 0.5 1 1.5
Vod [V]

• Typically define the output range as the peak-to-peak swing that

causes no more than 30% drop in Vod/Vid

B. Murmann EE315A - Chapter 4 85

How Much Gain Can We Get?

• Small signal gain (around Vid=Vod=0)

ron ⋅ rop 1 1
a0 = gmn ⋅ = a0n = a0n
ron + rop r gmp a0n
1 + on 1+
rop gmn a0p
1
a0 = a0n
( gm / ID )p a0n
1+
( gm / ID )n a0p

a0 = a0n || a0p for ( gm / ID )p = ( gm / ID )n

• E.g. a0n=a0p=50, (gm/ID)n= (gm/ID)p ⇒ a0=25

• Static gain error ~1/To ~1/a0 ~1/25 = 4%
– Not precise enough for many applications

B. Murmann EE315A - Chapter 4 86

 Telescopic OTA

• Voltage gain ~ (gmro)2, but smaller output range
useless for

low-voltage design

B. Murmann EE315A - Chapter 4 87

Current Mirror OTA with Cascodes

• Gm = M⋅gm1
• Input-referred noise
1 2
~4 1+
௠ଵ

M does not help
• Non-dominant pole
due to mirror scales
gm1 as 1/M
• Useful for mostly for
low-bandwidth
applications
– See e.g. Yao,
JSSC 11/04

B. Murmann EE315A - Chapter 4 88

 Folded Cascode OTA

• High- and low-frequency

behavior similar to
telescopic OTA
– But noise is worse
than telescopic
• Advantage: Input
common mode can be
chosen without taking
away output signal range
• If slewing is not an issue,
the current in the output
branches can be reduced
below ITAIL/2

B. Murmann EE315A - Chapter 4 89

Half Circuit Model with Capacitive Feedback

• Cgdn sees significant Miller

amplification at low
frequencies
– Since Zc ~ 1/gm only at
high frequencies
– See circuit textbooks for
a detailed analysis
• Solution: Neutralization

B. Murmann EE315A - Chapter 4 90

 Neutralization

Gray & Meyer, 5th ed., p.837

B. Murmann EE315A - Chapter 4 91

High Frequency Loop Gain

v x iy iz vo
T (s ) = − ⋅ ⋅ ⋅
vo v x iy iz

1 −1
= −β ⋅ Gm ⋅ ⋅
s sCLtot
1−
p2

gm '
p2 = −
Cy

Cy ≅ Cgs + 2Cdb ≅ 3Cgs

ωT
⇒ ω p2 ≅
3

B. Murmann EE315A - Chapter 4 92

 Example: fp2 = 5fc

• Phase margin ~ 80
degrees
– Non-dominant pole
p2 is not an issue in
this case
• Since ωp2 ~ωT/3, this
means that ωc (and
hence closed-loop BW)
cannot be higher than
~ωT/15 in this scenario

B. Murmann EE315A - Chapter 4 93

Example: fp2 = fc/5

• Phase margin ~ 28
degrees
– Not acceptable in
practice
• How much phase
margin should we
design for?

B. Murmann EE315A - Chapter 4 94

 Time Domain Perspective (1)

Step Response

[Yang & Allstot, IEEE TCAS 3/90]

B. Murmann EE315A - Chapter 4 95

Time Domain Perspective (2)

Settling Time, Relative to PM=90deg

ε d,spec=0.01%
1.6
ε d,spec=0.1%
1.4
ε d,spec=1% • Typically want to
1.2 shoot for phase
1 margin ~70-75
degrees
0.8

0.6
0.4

0.2

0
50 60 70 80 90
Phase Margin [deg]

B. Murmann EE315A - Chapter 4 96

 Phase Margin as a Function of ωp2
• At the crossover frequency, the dominant pole has shifted the
phase by about -90°
• The non-dominant pole's phase at ωc is given by -tan-1(ωc/ωp2)

 ω   ω p2 
PM ≅ 180° − 90° − tan −1  c  PM ≅ tan −1  
 ω p2   ωc 
 

ωp2/ω c Approximate PM
1 45°
2 63°
3 72°
4 76°
5 79°

B. Murmann EE315A - Chapter 4 97

“Load Compensation”

• Nondominant pole is fixed at roughly ωT/3

• The loop crossover frequency is given by

Gm
ωc = β
CLtot

• Increasing CLtot will lower ωc and increase ωp2/ωc, which

translates into larger phase margin
• A feedback circuit in which adding additional load capacitance
improves stability is often called “load compensated”
– Meaning that the load compensates or reduces the impact
of phase shift from p2

B. Murmann EE315A - Chapter 4 98

 How Fast Can We Go?

• Let’s say we design for fc ~ 1/3 fp2 ~ 1/9 fT

• At a reasonable bias, the NMOS transit frequency in 0.18um
technology is roughly 20 GHz (nominal process and
temperature)
• Assume 0.01% settling and no slewing

1 fT f 20 GHz
fs,max = ⋅ ≅ T = = 666 MHz
2.9 9 30 30

• In practice, it is hard to go faster than 200 MHz in 0.18um CMOS

– Slewing
– Timing overhead (have somewhat less time than Ts/2)
– Margins for process variation, wiring caps, etc.

B. Murmann EE315A - Chapter 4 99

Noise From Cascodes

• Detailed analysis shows

1 kT  g ω 
v o2 = γ 1 + m2 c 
β CLtot  g m1 ω p 2 


g m1 gm 2
ωc = β ω p2 =
CLtot Cx

• To minimize noise from M2

– Maintain large phase margin (large ωp2/ωc)
– Make gm2 as small as possible
• Requires small gm/ID and costs headroom

B. Murmann EE315A - Chapter 4 100

 Circuit Example

ωc = 1.94 GHz
PM = 70.1 deg

B. Murmann EE315A - Chapter 4 101

Noise Simulation

PSD M1
Total
M2 noise rolls in at high freq.
CT: Noise may be filtered out
SC: Noise will alias

Total
Integral
M1

M2

B. Murmann EE315A - Chapter 4 102

 Design Example:
Folded Cascode OTA for SC Circuit

(Switches not shown)

(CMFB not shown)

B. Murmann EE315A - Chapter 4 103

Specifications (65nm CMOS)

Parameter Value Comment

Cs 2Cf Closed-loop gain G = 2
CL Cs/G Near optimum for pipeline ADC
Output swing 800mVpp Differential
Total integrated
400µVrms Differential
output noise
Phase margin 75°
Pick based on non-dominant pole
Linear settling time Minimize (2nd priority)
Ignore slewing for simplicity
Dynamic settling
0.1%
error
No hard constraint Try to get reasonable gain; add
DC loop gain
(for simplicity) gain boosters if more is needed

Power dissipation Minimize (1st priority)

B. Murmann EE315A - Chapter 4 104

 Nondominant Pole Estimate
2xMP2
Cddn1 + 2Cddp2 + Cssp2
1
gmp2 + gmbp2
MP2
MN1

gmp2 + gmbp2 gmp2 + gmbp2

ωp2 ≅ ≅
Cddn1 + 2Cddp2 + Cssp2 2Cddp2 + Cssp2

1 gmp2 + gmbp2
ωc ≤ For PM ≥ 75°
4 2Cddp2 + Cssp2

B. Murmann EE315A - Chapter 4 105

Nondominant Pole Estimate

• To maximize speed, we should use the shortest length
and smallest possible gm/ID for the cascodes
– This gives the highest gm/C values
65nm PMOS, VDS = 0.6V, VBS = 0.2V

25
L=0.06um

20

1 gm + gmb
f p2 [GHz]

15
2π 2Cdd + Css
10

L=0.25um
5

L=1um
0
5 10 15 20
gm/I D [S/A]

B. Murmann EE315A - Chapter 4 106

 Tradeoff between Swing and ωp2

• Unfortunately we can’t use small gm/ID due to swing constraints

• Using the shortest L is also problematic due the resulting low gain
• As a compromise (not necessarily optimal), we decide to go for:
L = 0.25µm, (gm/ID) = 15 S/A
1.2V

1V

LP2=0.25µm
gm/ID=15 Swing ~± 400mV
0.6V
Differential
0.4V
0.2V

LN2=0.25µm
gm/ID=15

B. Murmann EE315A - Chapter 4 107

Resulting Nondominant Pole

and OTA Speed
65nm PMOS, VDS = 0.6V, VBS = 0.2V
6

4 1 gm
1 gm + gmb fT =
2π Cgg
[GHz]

2π 2Cdd + Css 3
(for comparison)
2
fp2 = 1.8GHz
1

5 10 15 20
gm/I D [S/A]

1 1  1 
fc = fp2 = 450MHz ts = ⋅ ln   = 2.4ns
4 2πfc ε
 d,spec 

B. Murmann EE315A - Chapter 4 108

 Next Steps

• The main unknowns at this point are

– Capacitor sizes (set by noise spec)
– Required transconductance (follows from caps and fc)
– Differential pair parameters (gm/ID, ID)
• To proceed, we list the pertinent design equations and devise
an optimization strategy
– Many options exist; the best solution depends on your
preference and experience

B. Murmann EE315A - Chapter 4 109

Design Equations

Capacitor Ratios Cs = G ⋅ Cf = G ⋅ CL

Feedback Cf 1
β= =
Factor Cf + Cs + Cgg1 1 + G + Cggn1 / Cf

Total Load CLtot = CL + (1 − β ) Cf = Cf ( 2 − β )

Capacitance

Total Integrated 1 kT  ( gm / ID )2 
Ntot = 2γ 1+ 2  γ ≅ 0.8
Noise β CLtot  ( g / I ) 
 m D 1 

Loop Unity Gain 1 gmn1 1 gmn1

fc ≅ β ≅ β
Frequency 2π CLtot 2π CLtot

B. Murmann EE315A - Chapter 4 110

 Optimization Strategy

• One way to “untangle” this set of equations:

1. Pick LN1, (gm/ID)1

2. Guess the feedback factor β (must be smaller than 1/3)
3. Calculate CLtot from noise spec
4. Calculate gmn1 based on fu
5. Now the actual β can be calculated (gm/ID and gm uniquely
define Cgg)
6. Iterate until the guess and actual β are equal
7. Repeat for different LN1, (gm/ID)1 and search for minimum current

B. Murmann EE315A - Chapter 4 111

Matlab Script (Excerpt)

% Try all channel lengths and gm_ID1; iterate over beta
for i = 1:length(LL)
for j = 1:length(gm_id1);
wt1 = lookup(nch, 'GM_CGG', 'GM_ID', gm_id1(j), 'L', LL(i));
for beta_guess = linspace(1/3, 0.1, 200)
cltot = 2*gamma/beta_guess*k*T/Ntot*(1+2*gm_id2/gm_id1(j));
gm1 = 2*pi*fu/beta_guess*cltot;
cgg1 = gm1/wt1; cf = cltot/(2-beta_guess);
beta_actual = 1/(1+G+cgg1/cf);
if beta_guess < beta_actual
id1(i,j) = gm1/gm_id1(j); beta(i,j) = beta_actual; break;
end
end
end
end

B. Murmann EE315A - Chapter 4 112

 Resulting Plots
-3
x 10
2
L=606250nm
1.5

I D1 [A] 1

0.5

0
5 10 15 20 Chosen 25
(g /I ) [S/A]
m D 1 Point

0.3
0.25 L=606250nm
β

0.2
0.15
0.1
5 10 15 20 25
(gm/I D)1 [S/A]

B. Murmann EE315A - Chapter 4 113

Current Density Look-Up

id_wn1 = lookup(nch, 'ID_W', 'GM_ID', gm_id1_cho, 'L', LL(idx_len));

wn1 = id_cho/id_wn1

id_wn2 = lookup(nch, 'ID_W', 'GM_ID', gm_id2, 'L', L2);

wn2 = id_cho/id_wn2

id_wp2 = lookup(pch, 'ID_W', 'GM_ID', gm_id2, 'L', L2);

wp2 = id_cho/id_wp2

>> wn1 = 1.4048e+02

>> wn2 = 7.3439e+01
>> wp2 = 1.4050e+02

B. Murmann EE315A - Chapter 4 114

 OTA Schematic
vdd

mp2ta mp2tb mbp

vbp vbp
l:lp2 l:lp2 l:lp2 V3
w:2*wp2 w:2*wp2 w:wp2 vdc:vcasp
vda
vdb

mp2ca mp2cb mbcp

vdd vbpc vdd vdd vbpc
l:lp2 l:lp2 l:lp2
w:wp2 w:wp2 w:wp2

mn1a mn1b vop I4

vip vom vop idc:id
vip l:ln1 l:ln1 vom
w:wn1 w:wn1

vim mn2ca mn2cb mbcn

vim gnd vbnc gnd gnd vbnc
l:ln2 l:ln2 l:ln2
w:wn2 w:wn2 w:wn2
V2 I2
vdc:vdd idc:2*id V4
mn2ba mn2bb mbn vdc:vcasn
vbn
l:ln2 l:ln2 l:ln2
w:wn2 w:wn2 vbn w:wn2

gnd

G0
+ voc vom
ggain:gcmfb vcm vm
-
V5
vdc:vdd/2 ideal_balun
vod vop
vdm vp
gnd I5

B. Murmann EE315A - Chapter 4 115

Testbench Schematic
Cfp

Clp
cf

cl
Rsm
r:rs
Csm
cs
Csp
cs
Rsp
r:rs

Cfm

Clm
cf

cl

Large dummy resistors

(100MΩ) to set initial
condition

B. Murmann EE315A - Chapter 4 116

 AC Simulation

fu = 250 MHz
(too low)

PM = 79 deg
(too high)

B. Murmann EE315A - Chapter 4 117

Error Analysis

• The unity crossover is off by (251-450)/450 = −44%

• There are two errors causing this
• First, the amplifier has “self loading capacitance” that was not
considered in the design
– The operating point reveals that the junction and overlap
capacitances at the output amount to about 150fF (adds
about 40% to CLtot)
• Second, fc is “pulled” toward lower frequencies by the
nondominant pole (about 5-10% error, depending on phase
margin)
• Decision: reduce CL by 150fF to compensate for the extra
capacitance

B. Murmann EE315A - Chapter 4 118

 AC Simulation (with reduced CL)

fu = 356 MHz
(better)

PM = 74.5 deg
(OK)

B. Murmann EE315A - Chapter 4 119

Transient Settling

B. Murmann EE315A - Chapter 4 120

 Transient Settling (Zoom)

±0.1%
ts=1.7ns

• The settling time is very good and better than expected

(~1.7ns), thanks to the help from the nondominant pole. Done.
B. Murmann EE315A - Chapter 4 121

Noise Simulation

B. Murmann EE315A - Chapter 4 122

 Meeting the Noise Spec

• The total integrated noise is 527µVrms (spec was 400µVrms)

• Error due to flicker noise and a high frequency noise
contribution from the cascodes (not included in calculation)
• Decision: Scale capacitors, current and all widths by (527/400)2
• Result
– Noise is exactly 400µVrms
– No change in phase margin and settling time

• Done!

B. Murmann EE315A - Chapter 4 123

Conclusion From Design Example

• The errors in the initial design point are due to the first-order
nature of our design equations, which must omit second order
effects to be useful
– This why we still run simulations_
• But, as we have seen, the design can be scaled to spec with
only a few iterations in the simulator
– If desired, the information learned from these iterations can
be included into the Matlab script for the next design_

B. Murmann EE315A - Chapter 4 124

 Operational Transconductance Amplifiers
- Part 2 -

Boris Murmann
Stanford University
[email protected]
Copyright © 2014 by Boris Murmann

B. Murmann EE315A - Chapter 5 1

Outline

• Review of frequency compensation techniques

• Two-stage Miller-compensated OTA
– Slewing
– Noise
– Design example
• Gain boosting
• Common mode feedback implementation

B. Murmann EE315A - Chapter 5 2

 Frequency Compensation Techniques
• Single-stage amplifiers are easy to stabilize
– Load compensation
• When more stages (more gain) are needed, one needs to get
more creative about making the loop stable
• Techniques covered in EE214B
– Narrowbanding
– Feedback zero compensation
– Miller compensation
– Ahuja compensation
– Nested Miller compensation
– Feedforward compensation
• Many more techniques exist7

B. Murmann EE315A - Chapter 5 3

EE214B Summary on Frequency

Compensation
Technique Internal External Lead Lag Comments

Narrowbanding X X X Practical mostly in single-stage

amplifiers
Feedback zero X X Preferred method whenever
applicable (feedback R);
highest bandwidth efficiency
Miller X X Easy to design and robust
when zero is moved to infinity
Ahuja X X Hard to design, but potentially
large gains in achievable
bandwidth
Feedforward X X Do not use in circuits that
demand fast and precise
transient settling

B. Murmann EE315A - Chapter 5 4

 Building Blocks

Transconductor
-gm (e.g. CS or CE stage, differential pair)

gm Current Buffer
(CG or CB stage)
1/gm

1/gm
Voltage Buffer
Av 1
(CD or CC stage)

B. Murmann EE315A - Chapter 5 5

Conceptual Schematic of a
Two-Stage Amplifier

vo
gm1 -gm2
βvo
C1 R1 C2 R2

߱௣ଵ ߱௣ଶ

ܽ଴ = ݃௠ଵ ܴଵ ݃௠ଶ ܴଶ

B. Murmann EE315A - Chapter 5 6

 Bode Plot of Loop Gain

Mag ( jω ) β ⋅ a (s )
a2 ( s )

a1 ( s ) • If ωp1 and ωp2 are

ω close to each
ω p1 ω p 2 other, the loop will
Phase ( jω ) have a very small
phase margin
β ⋅ a (s )
0°
−90°

−180° ω

B. Murmann EE315A - Chapter 5 7

Narrowbanding Compensation

T0

• Idea: Make one of the loop poles dominant, leave the other
poles unchanged
• Wasteful if ωp2 is at a low frequency
• Acceptable if ωp2 is at a high frequency
– Like in a load compensated amplifier, where the second
stage is really just a wideband current buffer

B. Murmann EE315A - Chapter 5 8

 Load Compensated OTA

߱௣ଶ ߱௣ଵ
-gm gm
Cgs CL
1/gm

T0
߱௨ ≅ ܶ଴ ߱௣ଵ ߱௣ଶ

1
߱௨ᇱ ≅ ܶ଴ ߱௣ଵ ≅ ߱௣ଶ
3

• GBW is some fraction of ωp2, typically very large

B. Murmann EE315A - Chapter 5 9

Miller Compensation

Cc

gm1 -gm2
C1 R1 C2 R2

• Purposely connect a capacitor across the second transconductor

• Two interesting things happen
– Low frequency input capacitance of second stage becomes large

moves the first pole to a lower frequency
– Qualitatively, at high frequencies, Cc turns the second stage into a
“diode connected device” – low impedance, i.e. large ωp2

B. Murmann EE315A - Chapter 5 10

 Poles and Zeros with CC
1
p1 ≅ −
R1 C1 + Cc (1 + gm2R2 ) + R2 (C2 + Cc ) gm2
z=+
CC
R1 C1 + Cc (1 + gmR2 ) + R2 (C2 + Cc )
p2 ≅ − RHP zero
R1 R2 (C1C2 + C1Cc + C2Cc )

We can approximate further as shown below

 C1C2 
1 gm2Cc g 1  C C   C + C2 
ωp1 ≅ ωp2 ≅ ≅ m2 ≅  1 + 2  1+ 1 
gm2R2 R1CC C1C2 + Cc (C1 + C2 ) C2 ωp2  gm2 gm2   Cc 
 
 
β gm1R1gm2R2 βgm1
GBW ≅ ωp1T0 ≅ =
gm2R2 R1CC CC

B. Murmann EE315A - Chapter 5 11

“Pole Splitting”

Increasing Cc reduces ωp1, and increases ωp2

− A very nice “knob” for adjusting the phase margin of the circuit

c
c c

~gm2/C2

B. Murmann EE315A - Chapter 5 12

 Intuitive Derivation of Pole Split Using
a Two-Port Model for the Inner Loop

gm2R2R1
a(s) = −
f(s) = −sCc (1 + sR1 [C1 + Cc ]) (1 + sR2 [C2 + Cc ])

Mag ( jω ) -gm2
a(s)
C1+Cc R1 C2+Cc R2

1
f(s)
ω

B. Murmann EE315A - Chapter 5 13

RHP Zero
• Unfortunately, the right half plane zero due to Cc can destroy the PM

RHP LHP

ωz −ωz

ω ω
1− j → − 90 o 1+ j → + 90 o
ωz ωz
Phase Phase
ωz ω
0° + 90°

− 45° + 45°
− 90° 0°
ωz ω

B. Murmann EE315A - Chapter 5 14

 Issue with RHP Zero

• The RHP zero can

destroy the phase
margin if it occurs
before or near the
ωz crossover frequency

B. Murmann EE315A - Chapter 5 15

Mitigating the Impact of RHP Zero

• Somehow create “unilateral” feedback through Cc

– Source follower from output to drive Cc
• Additional power & swing reduction issues
– Introduce a nulling resistor
• Most popular approach
– Ahuja compensation (also called cascode compensation)
• Ahuja, IEEE JSSC, 12/1983
• Ribner, IEEE JSSC, 12/1984

B. Murmann EE315A - Chapter 5 16

 Nulling Resistor

Rz Cc

gm1 -gm2
C1 R1 C2 R2

• The new transfer function becomes

 1 
1 − sCc  − Rz 
a ( s ) ≅ av0 ⋅  gm2 
 s   s   s 
1 −  ⋅ 1 −  ⋅ 1 − 
 p1   p2   p3 

• p1 and p2 unchanged, new pole p3, and a “knob” to tune the zero

B. Murmann EE315A - Chapter 5 17

Implementation Example

Carusone, page 243

B. Murmann EE315A - Chapter 5 18

 Location of the Zero

• Rz = 1/gm2 pushes the zero to +∞

• Rz ≅ (1+C2/Cc)/gm2 places the zero such that it cancels p2!

B. Murmann EE315A - Chapter 5 19

Third Pole
1
ωp3 ≅
R z C1

gm2
• For Rz = 1/gm2 ωp3 ≅ ≅ ωT
C1
gm2 ωT
• For Rz = (1+C2/Cc)/gm2 ωp3 ≅ ≅
 C2   C2 
1+  C1 1+ 
 Cc   Cc 

• Thus, as we try to cancel the second pole, the third pole moves to a lower
frequency, and may move to a frequency that is comparable to the original
ωp2 before cancellation
• My recommendation: Simply push the zero to infinity
• Typical textbook recommendation: Spice-monkey the zero into the LHP and
try to squeeze out some phase margin

B. Murmann EE315A - Chapter 5 20

 Process Insensitive Implementation of Rz

gm=KVOV
Carusone, page 260

Ron=1/(KVOV)=1/gm

B. Murmann EE315A - Chapter 5 21

Nested Miller Compensation

Mag ( jω ) Cm2
Cm1

gm1, gm2

gm0, gm1, gm2

B. Murmann EE315A - Chapter 5 22

 Transient Behavior

• Hard to analyze and hard to design for a robust solution

PM = 85 deg !

R. Nguyen and B. Murmann, “The Design of Fast-Settling Three-Stage

Amplifiers Using the Open-Loop Damping Factor as a Design Parameter,”
IEEE Trans. Circuits Syst. I, vol. 57, no. 6, pp. 1244-1254, Jun. 2010.

B. Murmann EE315A - Chapter 5 23

Feedforward Compensation

[e.g. Thandri, JSSC 2/2003]

• Parallel path through gm3 dominates

|a(jω)|
transfer function at high frequencies
and returns the circuit behavior back
to first order

ω
• Very large achievable bandwidth
|p1| |p2| |z1|
• Potential issue
φ(jω)
ω
– The doublet p1, z1 can make it
– π/2 difficult to achieve a fast
–π transient response
• See Kamath, JSSC 12/1974

B. Murmann EE315A - Chapter 5 24

 Issues with Pole-Zero Doublet (1)

B.Y.T. Kamath, R.G. Meyer and P.R. Gray, "Relationship between frequency response and
settling time of operational amplifiers," IEEE JSSC, Vol. 9, No. 6, pp.347–352, Dec. 1974.

B. Murmann EE315A - Chapter 5 25

Issues with Pole-Zero Doublet (2)

For fast and accurate settling, need either

small pole-zero spacing or large wz

B.Y.T. Kamath, R.G. Meyer and P.R. Gray, "Relationship between frequency response and
settling time of operational amplifiers," IEEE JSSC, Vol. 9, No. 6, pp.347–352, Dec. 1974.

B. Murmann EE315A - Chapter 5 26

 Example of a Feedforward OTA

[Shibata et al., JSSC 12/2012]

B. Murmann EE315A - Chapter 5 27

(Basic) Two-Stage OTA

VDD

VBP • High gain

M3a M3b ~ (gmro)2
M2b
M2a • Large output
Vxm Vxp range
M1a M1b Vom Ideal Vod
Vop • With cascodes
Balun
in stage 1 the
VBN
gain becomes
M4b M4a ~(gmro)3
Voc
+
GCMFB
- Voc,des

B. Murmann EE315A - Chapter 5 28

 Slewing in a Two-Stage Miller OTA

Slew Rate
SR- = ITAIL/2CC

~ “ac” ground

B. Murmann EE315A - Chapter 5 29

Slewing Time

• Same as in a single-stage OTA

– Except that Cc defies the slew rate

ITAIL
SR =
Cc

 2 2
 0 for Vxdstep <
 g m / ID
tslew = 2 2
 Vxdstep −
 g m / ID
else
 β ⋅ SR

B. Murmann EE315A - Chapter 5 30

 Watch out for Asymmetric Slewing!

• Want Vom to slew up at the same rate

that Vop slews down
– Otherwise amplifier sees a large
common mode and bias point
disturbance
• Symmetric slewing requires

IB2 I /2
≥ TAIL
CLtot + Cc Cc

ITAIL  CLtot 
IB2 ≥ 1+ 
2  Cc 

B. Murmann EE315A - Chapter 5 31

Proper Waveforms (Symmetric Slewing)

iOP vOP
vO1P

vO1M
vOC

iOM
vOM

B. Murmann EE315A - Chapter 5 32

 Bad Waveforms (Asymmetric Slewing)

iOP vOP

vO1P

vOC
vO1M
iOM

vOM

B. Murmann EE315A - Chapter 5 33

Noise Analysis of Miller OTA

• Noise from 2nd stage

M3 M4 may be significant for
Rz=1/gm2
small CLtot
Cc vo
• Want to minimize
vi=-βvo
gm3/gm1 and gm4/gm2 for
M1 M2 CLtot
low noise
– Sometimes not
possible due to
swing constraints
1 kT  γ p gm 3  kT   γ p gm 4  (small gm4 means
v o2 ≅ ⋅ γ n 1 + + 1 + γ n  1 + 
β Cc  γ n g m1  CLtot   γ n g m 2   small (gm/ID)4, large
VDSsat4)
A. Dastgheib and B. Murmann, "Calculation of total integrated noise in
analog circuits," IEEE Trans. on Circuits and Systems I, Vol. 55, pp.
2988-2993, Nov. 2008

B. Murmann EE315A - Chapter 5 34

 Dynamic Range
2
Psignal ,max 0.5 ⋅Vod ,peak
DR = =
Pnoise 2
v od
VDD
1
VDSsatP Vo,peak ≤ (VDD − VDSsatP − VDSsatN )
M4 2
Vo,peak
Vod ,peak ≤ (VDD − VDSsatP − VDSsatN )

 2 2 
M2 ≤ VDD − − 
VDSsatN  
 ( g m / I D ) P ( g m / I D )N 

• For VDD=1.8V, Vod,peak ~ 1V is practical

– Leaves 400mV headroom across loads, restricts gm/ID > 5

B. Murmann EE315A - Chapter 5 35

Design Example
Cf
CL
Cs
+ -
Vsd Vid Vod
- +
Cs
CL
Cf

Specifications:
Dynamic range = 75 dB
Settling time = 10 ns
Dynamic Settling Error ≤ 0.1%
Static Settling Error ≤ 0.5%
CL= 1pF, Cs = Cf = 1pF

B. Murmann EE315A - Chapter 5 36

 Divide and Conquer Design Flow
• Optimization in Matlab
– Step 1: Small-signal design
• Ignore slewing; take into account only small-signal behavior
– Step 2: Large-signal design
• Compute slewing time; re-optimize design
• Simulation and implementation
– Simplify simulation circuit as much as possible (while preserving
all important signal path features)
• Initially use ideal common mode feedback
• Do not worry about exact finger partitioning of transistors
• Do not worry about exact structure of bias network
• O

B. Murmann EE315A - Chapter 5 37

Prototype Amplifier

2x M4a M4b

CMFB
Vip Vim
M1a M1b ID2 Vom

ID1 Vop
Cn=Cgd1

M3a M3b Cc Cc

M2a M2b

• 11 Variables: ID1, W1, L1, W3, L3, ID2, W2, L2, W4, L4, Cc

B. Murmann EE315A - Chapter 5 38

Summary of Design Equations (Small-Signal)

2
0.5 ⋅Vod ,peak 1 kT  γ p g m 3  kT   γ p gm 4 
DR = v o2 ≅ ⋅ γ n 1 + + 1 + γ n  1 + 
2
v od β Cc  γ n g m1  CLtot   γ n g m 2  

g m1 Cf
ωc ≅ β β=
− 0 .7 Cc Cs + Cf + Cgg1
ts ≅ ln( εd ,spec )
ωc
gm 2
 −1  ω p 2 ω p2 ≅
(No slewing, PM≅75°) PM ≅ tan   C1CLtot
 ωc  + C1 + CLtot
Cc

1 g m1 gm2
εs ≅ T0 = β ⋅ ⋅
T0 gds1 + gds 3 gds 2 + gds 4

B. Murmann EE315A - Chapter 5 39

Optimization Approach

• Impossible to find a closed form solution to this design problem

– Solution must be found iteratively
• Iterations can be easily done using Matlab
– Using table-lookup of device parameters (gm/ID, fT, C)
• Partition space into “primary” and “secondary” variables
– Primary variables are the main knobs in your design; these have
the largest impact on the critical tradeoffs
– Secondary variables can be set using reasonable design
choices and heuristics; subject to optimization in an “outer loop”

B. Murmann EE315A - Chapter 5 40

 Optimization Flow

1. Set values for secondary variables

– L1, L2 (based on gain requirement)
– gm3/gm1, gm4/gm2
– C
2. Main iteration loop
1. Pick relative sizes of Cgg1, Cgg2
2. Compute estimates of extrinsic capacitances
3. Calculate Cc based on noise spec
4. Find gm, fT based on bandwidth and phase margin
5. Table lookup of gm/ID for required fT
6. Compute total current (based on gm, gm/ID)
3. Iterate over secondary variables, using different choices in step 1

B. Murmann EE315A - Chapter 5 41

Initial Guess for Cgg1

g m1 Cf
ωc ≅ β β=
Cc Cf + Cs + Cgg1

• Small Cgg1 helps increase ωc

– But, diminishing return if Cgg1 becomes small compared to Cs+Cf
• Because small Cgg1 means smaller device, less gm1
• A reasonable initial guess: Cgg1 = Cf+Cs
– Optimum choice for a single-stage OTA
• See e.g. [Boser & Howe, IEEE JSSC 3/96]

B. Murmann EE315A - Chapter 5 42

 Initial Guess for Cgg2

 CLtot Cgg 2 
 
gm2 1  Cgg 2 CLtot  Cgg 2 + CLtot 
ωp2 ≅ ≅ +  1+
CLtot Cgg 2 ω p2  gm 2 gm2  Cc 
+ Cgg 2 + CLtot 
Cc 
 
“parallel combination”

• A reasonable initial guess: Cgg2 = CLtot

• For a given ωp2 target and fixed CLtot
– Choosing Cgg2 much smaller than CLtot means excess
ωT2=gm2/Cgg2 and therefore small gm/ID
– Choosing Cgg2 much larger than CLtot will cost excess gm2 (power)
to meet ωp2 target

B. Murmann EE315A - Chapter 5 43

Matlab Design Script (1)

% design_script.m % dc gain requirement

%technology data a0 = 1/spec.es/beta_guess;
load techchar.mat
% split gain equally
% specifications gm_gds = 2*sqrt(a0)
spec.dr = 75;
spec.ts = 10e-9; % pick L to achieve the computed
... value of gm_gds for all devices
(using intrinsic gain charts)
% design choices choices.L1 = 0.4e-6;
% noise choices.L2 = 0.3e-6;
choices.gm3_gm1 = 0.5; choices.L3 = choices.L2;
choices.gm4_gm2 = 0.5; choices.L4 = choices.L1;
... ...

B. Murmann EE315A - Chapter 5 44

 Matlab Design Script (2)

% primary optimization variables

cgg1_cs_plus_cf = 1;
cgg2_cltot = 1;

% compute required current for given design choices

% this function contains all relevant equations…
[idtotal, m1, m2, m3, m4, other] =
two_stage_miller(cgg1_cs_plus_cf, cgg2_cltot, choices, tech);

>> idtotal
idtotal =
0.0010447

B. Murmann EE315A - Chapter 5 45

Matlab Design Script (3)

m1 = m2 =
cgg: 2.0000e-012 cgg: 1.7500e-012
cdd: 8.4569e-013 cdd: 8.6409e-013
gm: 0.0059 gm: 0.0161
ft: 4.7039e+008 ft: 1.4597e+009
gmid: 18.8069 gmid: 21.9751
id: 3.1431e-004 id: 7.3040e-004
idw: 0.5368 idw: 1.0039
W: 5.8551e-004 W: 7.2755e-004
cgd: 3.7701e-013 cgd: 3.4988e-013

• Large devices, biased close to weak inversion, lots of self loading

– Interesting to try smaller values of Cgg1/(Cs+Cf) and Cgg2/CLtot

B. Murmann EE315A - Chapter 5 46

 Contour Plot

-4
x 10
• Near-optimum
10 design point
– Cgg1/(Cs+Cf)=0.3
8 – Cgg2/CLtot =0.3
I Dtotal

– IDtotal = 534uA
6

4
1
1
0.5
0.5
C /C 0 0
gg2 2 C /(C +C )
gg1 s f

B. Murmann EE315A - Chapter 5 47

Regions with Asymmetric Slewing

B. Murmann EE315A - Chapter 5 48

 Parameter File for Cadence Simulation
*** ota_parameters.scs ****

parameters CS = 1.000000e-012
parameters CF = 1.000000e-012
parameters CL = 1.000000e-012
parameters CC = 2.689790e-012
parameters CN = 1.061561e-013
parameters RZ = 1.643900e+002 Include this as a
parameters W1 = 1.648643e-004 model library file
parameters L1 = 4.000000e-007
parameters ID1 = 2.430537e-004
parameters W2 = 1.890538e-004
parameters L2 = 3.000000e-007
parameters ID2 = 2.909095e-004
parameters W3 = 8.528657e-006
parameters L3 = 3.000000e-007
parameters W4 = 9.233185e-005
parameters L4 = 4.000000e-007

B. Murmann EE315A - Chapter 5 49

Simulation Results (1)

• Target
f c=67.81MHz, PM=77.77deg, T0=736
– fc = 77 MHz
Magnitude [dB]

80
60 – PM = 75°
40
20 – T0 > 200
0
-20 • Discrepancies in fc
-40 -2 0 2 4 and PM due to
10 10 10 10
f [MHz] inaccuracy in
capacitance
Phase [degrees]

0 estimates, VDS
-50 dependencies etc.
-100 – Easy to track
-150 down (and
-2 0 2 4 potentially fix)
10 10 10 10
f [MHz]

B. Murmann EE315A - Chapter 5 50

 Simulation Results (2)

PSD [V2/Hz]

• Target
– DR = 75 dB
-20
10
• Discrepancy
10
5
10
10
mostly due to
f [Hz] flicker noise
Sqrt(Integral) [µVrms]

Integral=139.55uVrms, DR=74.09dB (for Vodmax=1.00V) (neglected in

calculation)
100

0 5 10
10 10
f [Hz]

B. Murmann EE315A - Chapter 5 51

Simulation Results (3)

10 • Response to
Vod [mV]

small transient
5 step (10mV)

0 • Target
0 5 10 15 20 25
Time [ns]
– ts = 10ns
es=-0.14%, ts=12.33ns • Discrepancy
mostly due to
Error [%]

0 error in fc, PM
-0.2
-0.4
8 10 12 14 16
Time [ns]

B. Murmann EE315A - Chapter 5 52

 Remaining Tasks
• Try different architectures
– E.g. NMOS input stage, PMOS in output stage
– Very easy to run Matlab iterations for different architectures
• Run large signal simulations
– Check for asymmetric slewing (and fix if needed)
– Re-optimize to meet settling time specs with worst case slewing
(largest signal)
• Refine biasing network (finger all devices)
• Implement CMFB, check for stability
• Run process corners
• C

B. Murmann EE315A - Chapter 5 53

Gain Boosting

• Use an auxiliary feedback loop around cascode

device to increase Rout and thus low-frequency
gain of the overall cascode stage
– Can be applied to either telescopic or folded
Rout cascode OTA architectures
a(s)
VB • References
M2
– B. J. Hosticka, “Improvement of the gain of MOS amplifiers,”
IEEE J. Solid-State Circuits, pp. 1111-1114, Dec.1979.
– K. Bult, G.J.G.M. Geelen, “A fast-settling CMOS op-amp for SC
M1 circuits with 90-dB DC gain,” IEEE J. Solid-State Circuits, pp.
1379-1384, Dec. 1990.
– D. Flandre et al., “Improved synthesis of gain-boosted
regulated-cascode CMOS stages using symbolic analysis and
gm/ID methodology,” IEEE J. Solid-State Circuits, pp. 1006–
1012, July 1997.
– M. Das, “Improved design criteria of gain-boosted CMOS OTA
with high-speed optimizations,” IEEE Trans. Ckts. and Systems
II, pp. 204-207, March 2002.

B. Murmann EE315A - Chapter 5 54

 Basic Low Frequency Analysis

• Can use Blackman’s impedance formula

– See e.g. Gray & Meyer, 5th edition, p. 608

1 + T ( port shorted )
Z port = Z port ( k = 0 ) ⋅
1 + T ( port open )
Rout
a0
VB Rout ( a0 = 0 ) ≅ ro 2 (1 + g m 2r01 )
M2
gm2
T ( port shorted) ≅ a0 ≅ a0
g m 2 + g mb 2
M1
T ( port open ) = 0

Rout ≅ ro 2 (1 + g m 2r01 ) ⋅ ( a0 + 1)

B. Murmann EE315A - Chapter 5 55

High Frequency Analysis (1)

• Focus on simplest possible

circuit first
• Assume ro
∞
– Finite ro does not impact high
frequency behavior
• Neglect backgate effect of M2
• Neglect Cgs2 and all extrinsic
capacitances for simplicity
• It turns out that the key issues
are still retained with these
simplifications

B. Murmann EE315A - Chapter 5 56

 High Frequency Analysis (2)

• Loop gain

gm3 1 ω 1
T (s ) = = u
sC2 Cgs 3 s Cgs 3
1+ s 1+ s
gm2 gm 2

• For reasonable phase margin, we

need
gm 2
= ω p 2 > ωu
Cgs 3

gm2
= k ⋅ ωu k = 2...4
Cgs 3

B. Murmann EE315A - Chapter 5 57

Voltage Transfer Function of the Stage

KCL-based analysis gives:

[Das]
s
1+
v out gm1 ωz
=
v in sCL s s2
1+ + 2 “Pole-zero doublet”
ω 0Q ω 0

1
௭ = ௨ ଴ = ௨ =


  < 0.5 ⇒  > 4

⇒  ,    ,    ௭

B. Murmann EE315A - Chapter 5 58

 Observations – Gain Boosting

• Assuming that fast and accurate transient settling is required

– The unity gain frequency of the auxiliary amplifier (ωu) must be
at a high frequency to avoid pole-zero doublet issues
– On the other hand, we need ωu < ωp2 = gm2/Cgs3 for stability
(large k)
• Resulting practical design outcome
– Place ωu beyond unity gain frequency of outer loop
– Non-dominant poles from booster automatically lie beyond ωp2
• Practical design outcomes have shown that gain boosting adds
only about 20-30% to the total power dissipation of an OTA
– Mostly because booster cap C2 < overall load cap CL

B. Murmann EE315A - Chapter 5 59

Implementation Examples (1)

[Bult]

B. Murmann EE315A - Chapter 5 60

 Implementation Examples (2)

M.M. Ahmadi, “A New Modeling and

Optimization of Gain-Boosted Cascode
Amplifier for High-Speed and Low-Voltage
Applications,” IEEE TCAS II, pp. 169-173,
March 2006.

B. Murmann EE315A - Chapter 5 61

Implementation Examples (3)

[Chiu et al., ISSC 2004]

• Gain boosted gain boosters!

• Gain ~ gmro6, design achieved av0=130dB in 0.18µm technology

B. Murmann EE315A - Chapter 5 62

 Implementation Examples (4)

[Yang et al., JSSC 12/2001]

• Differential pair (instead of CS stages) and separate common

mode feedback in second stage

B. Murmann EE315A - Chapter 5 63

Common Mode Feedback

• Implementation aspects
– How to sense
– How to compare to desired value
– How to provide a "knob" for adjusting Voc

B. Murmann EE315A - Chapter 5 64

 Knob

• Typically generate ~50% of tail current with fixed bias, leave

remaining 50% as tuning range for CMFB loop

B. Murmann EE315A - Chapter 5 65

Comparison Circuit

• Low frequency loop gain T0 ≅ gmx·rop1/2 ·(gmp2/2)/(gmx/2)

– Loop will control Voc more accurately if Mp1 is cascoded

B. Murmann EE315A - Chapter 5 66

 Sensing

• Using a resistive divider may “destroy” differential gain

• Solutions
– Use source followers to drive divider (headroom issue)
– Purely capacitive sensing

B. Murmann EE315A - Chapter 5 67

Resistor-Based CMFB (CT Circuit)

R. Schreier, et al., "A 375-mW Quadrature Bandpass Delta Sigma ADC With 8.5-MHz BW and
90-dB DR at 44 MHz," IEEE J. Solid-State Circuits, vol. 41, no. 12, pp.2632-2640, Dec. 2006.

B. Murmann EE315A - Chapter 5 68

 SC CMFB Implementation Example

• Circuit uses switched

capacitors (CM) to set the
voltage across sensing
capacitors (CCM)

[Feldman et al., JSSC 10/1998]

B. Murmann EE315A - Chapter 5 69

"Passive" CMFB (1)

• During φ1: Initialize voltage across Ccmfb to Voc,desired - VB

• During φ2: Activate feedback loop
– If Voc>Voc,desired, Vcntrl becomes >VB and lowers Voc

B. Murmann EE315A - Chapter 5 70

 "Passive" CMFB (2)

• OTA cannot be used during φ1, because the common mode

feedback mechanism is inactive
– Often not a problem in switched capacitor circuits, where the
OTA is active only during one half-cycle
• Can use switched capacitor scheme shown previously to enable
uninterrupted common mode feedback
• Unfortunately, this simple circuit cannot be used if an additional
inversion is needed in the common mode feedback loop
– E.g. won't work for a two-stage OTA that uses a single
common mode feedback loop
– Will work for the two-stage OTA with separate CMFB loops
(by Yang et al.)

B. Murmann EE315A - Chapter 5 71

Common Mode Half Circuit

• Low frequency loop gain

gmx Ccmfb
T0 ≅ rop ⋅
2 C
Ccmfb + x
2
• Loop crossover frequency

1 Ccmfb gmx
ωc ≅
2C Cx C ⋅ 0.5Cx
cmfb + CL + cmfb
2 Ccmfb + 0.5Cx

• Nondominant pole
gmn
ωp 2 ≅
Cy

B. Murmann EE315A - Chapter 5 72

 CMFB Design Considerations
• The required bandwidth of the common mode loop strongly
depends on the amount of expected imbalance, common mode
transients or ac components
– In an ideal world, the common mode is not affected by the
signal and hence stays constant
• In this case, the bandwidth of the CMFB loop is unimportant
• For robustness in practical implementations, the bandwidth of
the common mode loop is often chosen to be about 30% of the
differential signal path bandwidth
– In a typical switched capacitor circuit with 10 time constants
differential settling, this means that the common mode has
about 3 time constants to settle
• Enough time to remove 95% of common mode disturbance

B. Murmann EE315A - Chapter 5 73

Proper Waveforms (Symmetric Slewing)

iOP vOP
vO1P

vO1M
vOC

iOM
vOM

B. Murmann EE315A - Chapter 5 74

 Summary
• The two-stage Miller OTA is a good choice for low-voltage, high
gain OTAs for SC circuits
• A few gotchas to watch
– Asymmetric slewing
– Noise from stage 2
• Cascoding and gain boosting in stage 1 can be used to extract
more gain
– Booster design requires proper positioning of pole-zero
doublet
• CMFB design
– Go for ~50% of nominal current in CMFB device
– Make CMFB bandwidth about 30% of differential BW
– Sense output common mode using switched capacitors

B. Murmann EE315A - Chapter 5 75

 Continuous Time Filters: Biquads

Boris Murmann
Stanford University
[email protected]
Copyright © 2014 by Boris Murmann

B. Murmann EE315A - Chapter 6 1

Outline

• Introduction to filter design

• Implementation of second order sections
• Sensitivity analysis

B. Murmann EE315A - Chapter 6 2

 The Filter Approximation Problem
• Ideal Filter • Practical filter
– Brick-wall characteristic – Ripple in either or both
– Flat magnitude response the passband and
in the passband stopband
– Infinite attenuation in the – Limited attenuation in the
stopband stopband

|H(j )| |H(j )|

Passband Stopband

B. Murmann EE315A - Chapter 6 3

Filter Design

• Ideal filters are non-causal or otherwise impractical

• No global optimization techniques known
• In practice, chose from several known solutions
– Butterworth, Elliptic, Bessel, +
• The overall goal of filter design is to approximate the ideal
response by one that implements a reasonable compromise
between filter complexity (number of poles and zeros) and
approximation error
• Filter design, in general, requires a compromise between
magnitude response, phase response, step response,
complexity, etc.

B. Murmann EE315A - Chapter 6 4

 Lowpass Filter Template

|H(j )| Passband
Ripple
Maximum/
Apmax Transition
minimum
passband Apmin band
gain

Stopband
As
gain

p s

• Magnitude response is fully specified by Apmin, Apmax, As, ωp, ωs

B. Murmann EE315A - Chapter 6 5

Second Order Lowpass Filter

Qp=0.5
0
Qp=1/sqrt(2)
Qp=1
Magnitude [dB]

-10
1
H(s) =
s s2
-20 1+ + 2
ωPQP ωP

-30

-40 4 5 6
10 10 10
f [Hz]

• Magnitude response is “maximally flat” (no peaking) for

QP = 1/sqrt(2)

B. Murmann EE315A - Chapter 6 6

 Pole Positions

• The poles are the roots of the denominator polynomial

  Location in the s-plane
1  0 for QP > 0.5




s1 jω



 
0.5 ,   1   4
  1 ωP
2

Complex Conjugate Poles cos-1(1/2QP) σ


ωP/2QP
 
 0.5 ,   1  1  4

2

Carusone, p. 164

Real Poles

s2

B. Murmann EE315A - Chapter 6 7

Pole Positions
5 5 5
x 10 x 10 x 10
6 6 6

4 4 4

2 2 2
Imaginary

Imaginary

Imaginary

1
0 QP = 0.5 0 QP = 0 QP = 1
2
-2 -2
-2

-4 -4
-4
-6 -6
-6
-6 -4 -2 0 -6 -4 -2 0 -6 -4 -2 0
Real x 10
5 Real x 10
5 Real x 10
5

 1   1   1 
ψ = cos−1  =0
o
ψ = cos−1   = 45
o
ψ = cos−1   = 60
o
2Q
 P 2Q
 P 2Q
 P

B. Murmann EE315A - Chapter 6 8

 Improvements

• A maximally flat response is great, but how can we make the

roll-off steeper?
• Let’s look at
– Imaginary zeros
– Increasing the filter order
– High-Q poles
– High-Q poles and imaginary zeros

B. Murmann EE315A - Chapter 6 9

Adding Zeros on the Imaginary Axis

“pegs”

B. Murmann EE315A - Chapter 6 10

 Bode Plot

no zeros
0
zeros on imaginary axis 2
 s 
-5 1+  
 ωZ 
Magnitude [dB]

-10 H(s) = 2
-15 s  s 
1+ + 
-20 ωPQP  ωP 
-25
2
-30 ω 
H( jω ) ω→∞ = P 
 ωZ 
-35
-40 4 5 6 7
10 10 10 10
f [Hz]

• Steeper roll-off at the expense of reduced stopband rejection

B. Murmann EE315A - Chapter 6 11

Adding Another Pole

0
H(s) = H1(s) ⋅ H2 (s)
-5
1
H1(s) =
Magnitude [dB]

-10 2
s  s 
-15 1+ + 
ωPQP  ωP 
-20
1
-25 H1(s), QP=1/sqrt(2) H2 (s) =
 s 
-30 H2(s), ω P*=ω P 1+  
-35 H1(s) ⋅H2(s)
 ωP* 
-40 4 5 6
10 10 10
f [Hz]

• As expected, steeper roll-off, but transition is not all that sharp

• Can fix this issue by increasing QP of H1(s)!

B. Murmann EE315A - Chapter 6 12

 Utilizing Peaking in H1(s)

0
H(s) = H1(s) ⋅ H2 (s)
-5
1
H1(s) =
Magnitude [dB]

-10 2
s  s 
-15 1+ + 
ωPQP  ωP 
-20
1
-25 H1(s), QP=1 H2 (s) =
 s 
-30 H2(s), ω P*=ω P 1+  
-35 H1(s) ⋅H2(s)
 ωP* 
-40 4 5 6
10 10 10
f [Hz]

• Win-win improvement
– Passband flat, roll-off steeper

B. Murmann EE315A - Chapter 6 13

nth Order Generalization

• Stephen Butterworth showed in 1930 that the magnitude
response of an nth order maximally flat lowpass filter is given by
1
H(jω) =
2n
 ω 
1+  
 ωP 
• This magnitude response is monotonically decreasing and
satisfies k
d H(jω)
=0 for 1 ≤ k ≤ 2n − 1
dω k
ω=0

• The corresponding pole locations can be determined using

2 1 j(2k −1)π
H(s) = H(s) ⋅ H( −s) = − s2 1/n
 −s 2 
n = ( −1) =e n k = 1,2,3...,n
1+  2  ωP2
 ω
 P 

B. Murmann EE315A - Chapter 6 14

 Pole Locations
• The poles lie equally spaced (in angle) on a circle in the s-plane
centered at the origin with radius ωP
• The LHP roots are taken to be the poles of H(s), while those in
the RHP are regarded as the poles of H(–s)

ωP = 1
1 1 1 1

0.5 0.5 0.5 0.5

n =1 n=2 n=3 n=4

Imaginary

0 0 0 0

-0.5 -0.5 -0.5 -0.5

-1 -1 -1 -1
-1 -0.5 0 -1 -0.5 0 -1 -0.5 0 -1 -0.5 0
Real Real Real Real

B. Murmann EE315A - Chapter 6 15

Magnitude Response and Coefficients

http://en.wikipedia.org/wiki/Butterworth_filter

ωP = 1

n Denominator Polynomial
1 (s + 1)
2 s2 + 1.4142s + 1
3 (s + 1)(s2 + s + 1)
4 (s2 + 0.7654s + 1)(s2 + 1.8478s + 1)
5 (s + 1)(s2 + 0.6180s + 1)(s2 + 1.6180s + 1)
6 (s2 + 0.5176s + 1)(s2 + 1.4142s + 1)(s2 + 1.9319s + 1)
7 (s + 1)(s2 + 0.4450s + 1)(s2 + 1.2470s + 1)(s2 + 1.8019s + 1)
8 (s2 + 0.3902s + 1)(s2 + 1.1111s + 1)(s2 + 1.6629s + 1)(s2 + 1.9616s + 1)

B. Murmann EE315A - Chapter 6 16

 A Closer Look at n=4

2 H(s) = H1(s) ⋅ H2 (s)

0 1
H1(s) =
Magnitude [dB]

2
s  s 
-2 1+ + 
ωP1QP1  ωP1 
-4
H1(s), QP1=0.541, ω P1=1 1
-6 H2(s), QP2=1.307, ω P2=1
H2 (s) = 2
s  s 
H1(s) ⋅H2(s) 1+ + 
-8 ωP2QP2  ωP2 
-10 -4 -2 0
10 10 10
ω [rad/sec]

 1  1 1
ψ = cos−1   QP1 = = 0.541 QP2 = = 1.307
 2QP  (
2cos 22.5o ) (
2cos 67.5o )
B. Murmann EE315A - Chapter 6 17

Increasing QP2
10

5
Magnitude [dB]

H1(s), QP1=0.541, ω P1=1

-5 H2(s), QP2=3, ω P2=1
H1(s) ⋅H2(s)

-10 -4 -2 0
10 10 10
ω [rad/sec]

• Helps make the roll-off steeper, but introduces peaking

• We can try to alleviate this problem this by reducing ωP1

B. Murmann EE315A - Chapter 6 18

 Increased QP2, Reduced ωP1

10

Magnitude [dB] 0

H1(s), QP1=0.541, ω P1=0.7

-5
H2(s), QP2=3, ω P2=1
H1(s) ⋅H2(s)
-10 -4 -2 0
10 10 10
ω [rad/sec]

• This may not a bad choice of we can tolerate some peaking or ripple

B. Murmann EE315A - Chapter 6 19

Comparison with Original Butterworth

0
Magnitude [dB]

-2

-4

-6
Butterworth
-8 QP2=3, ω P1=0.7

-10 -2 -1 0 1
10 10 10 10
ω [rad/sec]

• How can we optimize this situation, i.e. minimize the transition

band for a given tolerable peaking (or “ripple”) in the passband?

B. Murmann EE315A - Chapter 6 20

 Chebyshev1 Filter Approximation
• Fortunately someone has already figure this out
• The “Chebyshev1” filter approximation minimizes the error
between the idealized response and the actual filter, with the
passband ripple as a parameter (1dB for examples below)

1 1 1 1

0.5 0.5 0.5 0.5

Imaginary

0 0 n=3 0 0 n=5
n=2 n=4

-0.5 -0.5 -0.5 -0.5

-1 -1 -1 -1
-1 -0.5 0 -1 -0.5 0 -1 -0.5 0 -1 -0.5 0
Real Real Real Real

B. Murmann EE315A - Chapter 6 21

Matlab Code
wp = 1; % Edge of passband
R = 1; % Passband ripple in dB
[z, p, k] = cheby1(4, R, wp, 's'); 4
sys = zpk(z, p, k);
2
w = logspace(-2, 1, 1000);
1 dB
[mag, phase] = bode(sys, w); 0
Magnitude [dB]

db = 20*log10(reshape(mag, 1, length(w)));
-2
figure(1)
-4
semilogx(w, db, 'linewidth', 2); hold on;
plot([w(1) w(end)], [0 0], '--'); -6
plot([w(1) w(end)], [-1 -1], '--');
-8
set(gca, 'fontsize', 14);
xlabel('\omega [rad/sec]') -10 -2 -1 0 1
ylabel('Magnitude [dB]'); 10 10 10 10
ω [rad/sec]
axis([min(w) max(w) -10 4])
grid;

B. Murmann EE315A - Chapter 6 22

 Elliptic (Cauer) Filter Approximation
• The Elliptic filter approximation combines our previous ideas and
adds imaginary zeros to sharpen the transition band
• This approximation has the passband ripple and stopband attenuation
as a parameter (1dB and 20dB, respectively, for example below)
3 3 3 3

2 2 2 2

1 1 1 1
Imaginary

0 0 0 0

-1 -1 -1 -1

-2 -2 -2 -2
n=2 n=3 n=4 n=5
-3 -3 -3 -3

-1 -0.5 0 -1 -0.5 0 -1 -0.5 0 -1 -0.5 0

Real Real Real Real

B. Murmann EE315A - Chapter 6 23

Matlab Code

-5
Magnitude [dB]

wp = 1; % Edge of passband
Rp = 1; % Passband ripple in dB
-10
Rs = 20; % Stopband attenuation
[z, p, k] = ellip(4, Rp, Rs, wp, 's'); -15

-20

-25 -2 -1 0 1
10 10 10 10
ω [rad/sec]

B. Murmann EE315A - Chapter 6 24

 Chebyshev2 Filter Approximation
• No ripple in the passband, but finite stopband attenuation and ripple
due to imaginary zeros
• This approximation takes the stopband attenuation as a parameter
(20 dB in the example below)
3 3 3 3

2 2 2 2

1 1 1 1
Imaginary

0 0 0 0

-1 -1 -1 -1

-2 -2 -2 -2
n=2 n=3 n=4 n=5
-3 -3 -3 -3

-1 -0.5 0 -1 -0.5 0 -1 -0.5 0 -1 -0.5 0

Real Real Real Real

B. Murmann EE315A - Chapter 6 25

Design Example

wp=2*pi*1e6; % Passband edge

ws=2*pi*2e6; % Stopband edge
0
Rp=1; % Passband ripple
Rs=40; % Stopband attenuation
-10
Magnitude [dB]

% Determine required order and synthesize

[N, wp] = ellipord(wp, ws, Rp, Rs, 's'); -20
[z, p, k] = ellip(N, Rp, Rs, wp, 's');

-30
sys = zpk(z, p, k);
f = logspace(4, 7, 1000);
[mag, phase] = bode(sys, 2*pi*f); -40
db = 20*log10(reshape(mag, 1, length(f)));
figure(1)
-50 4 5 6 7
semilogx(f, db, 'linewidth', 2); 10 10 10 10
Frequency [Hz]

B. Murmann EE315A - Chapter 6 26

 Filter Order for Rp=1dB, Rs=40dB

12
Butterworth
Elliptic
10
Chebyshev 1 & 2

8
Required Order

0
2 3 4 5 6 7 8 9 10
ω s/ω p

• Why not always use an Elliptic filter?

B. Murmann EE315A - Chapter 6 27

Step Response of Design Example

1.2

0.8
Output

0.6

0.4

0.2

0
0 1 2 3 4 5 6
Time [µsec]

• Overshoot and other forms of pulse deformation can be problematic

– Consider e.g. oscilloscopes, pulse-based data links, etc.
• The pulse deformation is mostly due to the fact that different frequency
components pass the filter with different time delays
– This is called phase distortion
• Let’s first have a look at the phase response of our filter

B. Murmann EE315A - Chapter 6 28

 Phase Response of Design Example

Magnitude [dB] -20

-40

-60 4 5 6 7
10 10 10 10
Frequency [Hz]

0
Phase [degrees]

-100

-200 Rapid phase

Phase jumps
change
-300
4 5 6 7
10 10 10 10
Frequency [Hz]

B. Murmann EE315A - Chapter 6 29

Phase Jumps due to Imaginary Zeros

‫ݏ‬ ‫ݏ‬ ‫ݏ‬ଶ (݆߱)ଶ ߱ଶ

1− 1− = 1 + ଶ == 1 + = 1 −
+݆߱௭ −݆߱௭ ߱௭ ߱௭ଶ ߱௭ଶ

Complex conjugate pair on

the imaginary axis

߱ଶ 0° ߱ ≤ ߱௭
=൜
߱ > ߱௭
∡ 1−
߱௭
ଶ 180°

• As seen on the previous slide, the phase jumps occur at the

frequencies of the zeros

B. Murmann EE315A - Chapter 6 30

 Phase of a High-Q Pole Pair
40

Magnitude [dB]
Qp=1
20
Qp=10
0 Qp=100
-20
-40 -1 0 1
10 10 10
ω /ω P

0
Qp=1
Phase [deg]

-50 Qp=10
-100 Qp=100
-150

-1 0 1
10 10 10
ω /ω P

• The phase of a complex pole pair changes more abruptly for higher QP
– Can show that the phase slope is QP·(-45°/decade) at ω=ω P
• For QP→∞ (poles approaching the imaginary axis), the phase approaches an
abrupt jump, just like the imaginary zeros we looked at

B. Murmann EE315A - Chapter 6 31

Phase Distortion (1)

• Consider a filter with transfer function

H( jω) = H( jω) e jφ( ω )

• Apply two sine waves at different frequencies

v in (t) = A1 sin ( ω1t ) + A 2 sin ( ω2t )

v out (t) = A1 H( jω1) sin ( ω1t + φ(ω1)) + A 2 H(jω2 ) sin ( ω2t + φ(ω2 ) )
  φ(ω1)     φ(ω2 )  
= A1 H( jω1) sin  ω1  t +   + A 2 H(jω2 ) sin  ω2  t + 
 ω1    ω2  
   

Phase delay τd1 Phase delay τd2

B. Murmann EE315A - Chapter 6 32

 Phase Distortion (2)
• Assuming that the difference between |H(jω1)| and |H(jω2)| is
small, the “shape” of the time-domain output signal will be
preserved as long as

φ(ω1) φ(ω2 )
− =0
ω1 ω2

• This condition is satisfied for

φ(ω) = T ⋅ ω T = constant

• A filter with this characteristic is called “linear phase”

B. Murmann EE315A - Chapter 6 33

Delay with Linear Phase

t t (e.g. φ1 = π/2 & ω2= 2ω1)

Linear
Phase (φ1 = π/2)
Filter
t
0 ω1 ω2 ω1

φ1 ∂φ (φ2 = 2φ1 =π)

−
∂ω t
φ2 ω2= 2ω1

∂φ ω1 ω2
∂ω T (Fixed delay)

[U. Moon]

B. Murmann EE315A - Chapter 6 34

 Delay with Nonlinear Phase
(φ1 = π/2)
0 ω1 ω2 t
ω1

∂φ (φ2 < 2φ1 = π)

φ1 −
∂ω t
ω2= 2ω1

φ2
ω1 ω2

unmatched
φ(ω1) φ(ω2 )
≠
ω1 ω2

• Phase distortion occurs whenever the phase is nonlinear, i.e.

the derivative of the phase is not constant
• The (negative) derivative of the phase is also called “group
delay” or τg
• Note that for a linear phase filter, we have τg = τd = const.

B. Murmann EE315A - Chapter 6 35

Group Delay
• The name group delay (or envelope delay) comes from the fact
that it specifies the delay experienced by a narrow-band “group‘”
of sinusoidal components within some ∆ω around a carrier wc
• The width of ∆ω is limited to a range over which dφ/dω is
approximately constant
• For example, for an AM modulated signal, the carrier
experiences a delay of τp (phase delay) and the envelope sees
a delay of τg (group delay)
• For a proof, see e.g.
– http://ccrma-www.stanford.edu/~jos/fp2/Derivation_Group_Delay_Modulation.html

• In this course, we are using the term group delay merely to refer
-dφ/dω (and not to argue about group delay per se)

B. Murmann EE315A - Chapter 6 36

 Bessel Filter Approximation

• All poles
• Poles are relatively low Q
• Maximally flat group delay
• Poor magnitude roll-off
Order (N) Re Part (-σ) Im Part (±jω)
1 1.0000
2 1.1030 0.6368
1.0509
3 1.0025
1.3270
1.3596 0.4071
4
0.9877 1.2476
1.3851
0.7201
5 0.9606
1.4756
1.5069

http://www.rfcafe.com/references/electrical/bessel-poles.htm

B. Murmann EE315A - Chapter 6 37

Group Delay Comparison

B. Murmann EE315A - Chapter 6 38

 Comparison: Bessel vs. Chebyshev1

• Lowpass filters with 100

kHz passband
• Both filters are 4th order
with the same -3 dB
frequency
• Passband ripple of 1dB
for Chebyshev I

[H. Khorramabadi]

B. Murmann EE315A - Chapter 6 39

Phase and Group Delay

B. Murmann EE315A - Chapter 6 40

 Step Response

B. Murmann EE315A - Chapter 6 41

Pulse Response

B. Murmann EE315A - Chapter 6 42

 Intersymbol Interference

B. Murmann EE315A - Chapter 6 43

Beyond Lowpass Filtering

[H. Khorramabadi]

B. Murmann EE315A - Chapter 6 44

 Lowpass to Highpass Transformation
jω
1 L.P. H.P.
s HP
= unit circle
sLP x x
o
o x σ
x o
o
o o
3-zeros at ∞ x x
3-zeros at origin
(e.g. Butterworth n=3)

L.P. H.P.
x x [U. Moon]
x
o
o
o
o
x
2-zeros at ∞ (e.g. Arbitrary n=2)
x x 2-zeros at origin

The s-domain poles and zeros simply become inverted. As shown by the
examples, zeros at infinity move to the origin, and finite-valued poles become
|1/poleLP| in magnitude and become conjugates (flips between quadrant II &
III). The mapping boundary is the unit circle.

B. Murmann EE315A - Chapter 6 45

Lowpass to Bandpass Transformation

2
sLP ± j 1−
 sLP  ≈ sLP ± j fm
= “Q” ; f m =
s = where a = f 1 f 2 ; ∆f = f 2 − f 1
BP 2a  2a  2a ∆f

1
circle
2a
o
unit circle xo
L.P. x B.P. x
xo

[U. Moon]
x

(e.g. “Narrowband” n=3)
xo
x x
o xo

For a “narrowband” approximation, the s-domain poles and zeros simply become
replicated at ±jω with a smaller unit circle of radius 1/2a. To realize a wideband
filter, use a cascade of highpass and lowpass filters.

B. Murmann EE315A - Chapter 6 46

Architectural Options for High-Order Filters

• Cascades of (active) first and second-order sections

• Ladder filters (passive or emulated using active components)

• Specialized architectures, typically emphasizing low complexity

– Watch out for sensitivity issues (more later)

B. Murmann EE315A - Chapter 6 47

Building Block Options

[Kuhn, IEEE TCAS II, 10/2003]

B. Murmann EE315A - Chapter 6 48

 Example

• An interesting filter
that combines three
different approaches
– Passive LC
– Active RC
– Switched capacitor

[Schreier, JSSC 12/2002]

B. Murmann EE315A - Chapter 6 49

The Challenge

• Way too many options available

• Deciding on which implementation is “best” may only be
possible once several options have been thoroughly compared
– In terms of both first-order properties and second-order
nonidealities, which aren’t always easy to understand
• The following discussion starts from the most basic ideas, and
derives some of the most popular solutions used in practice
• For now, we will focus on the realization of second order
sections, and cover ladder-based implementations in chapter 3
– The treatment of second order sections will help us
understand why we may ultimately want to go for a ladder
implementation

B. Murmann EE315A - Chapter 6 50

 Passive LC Lowpass Filter

1
sC 1 1
H
= = =
1 1 + sRC + s2 LC s s2
+ R + sL 1+ +
sC P QP  2
P

1 1 L
ωP = QP =
LC R C

B. Murmann EE315A - Chapter 6 51

On-Chip Capacitors

Metal-Insulator-Metal (MIM) Vertical Parallel Plate (VPP)

[Ng, Trans. Electron Dev., 7/2005] [Aparicio, JSSC 3/2002]

• Typically 1-2 fF/µm2 (10-20 fF/µm2 for advanced structures)

– For 1 fF/µm2, a 10 pF capacitor occupies ~100µm x 100µm
• Both MIM and VPP capacitors have good electrical properties
– Mostly worry about parasitic caps
– Series and parallel resistances are often not a concern

B. Murmann EE315A - Chapter 6 52

 On-chip Inductors

~1mm

[Mohan, JSSC 10/1999]

[Bevilacqua, ISSCC 2004]

• Many nonidealities, hard to model, low “Q”

• Area inefficient, typically achieve L < 10nH
• Sometimes bondwires are used as an alternative, L ~ 1nH/mm

B. Murmann EE315A - Chapter 6 53

Inductor Quality Factor

1 X( ω )
In general Y= ⇒ Q=
R + jX( ω ) R

1 ωL
Y= ⇒ QL =
Rs + j ωL Rs

• On-chip inductors typically achieve QL < 5-10 at our frequencies

of interest (EE315A)

B. Murmann EE315A - Chapter 6 54

 LC Lowpass Example

• Assuming that we (very generously) use C=100pF, L=10nH

1
ωP = = 2π ⋅ 160MHz
LC

• Integrated passive LC filters become practical for

f > 200-500MHz
• For our LC lowpass, if we assume R=Rs (i.e. we only use the
parasitic resistor of the inductor, no explicitly added resistance)

ωL 1 L QL L ω
QL = QP = = = QL P
Rs R C ωL C ω

• This means that at ω=ωP, the magnitude peaking that we can

get is limited to the QL of the inductor (~5-10); not all that great

B. Murmann EE315A - Chapter 6 55

Summary

• On-chip capacitors are great, even though they’re usually not as

large as we would like them to be
• On-chip inductors tend to be avoided whenever possible, and
are typically not useful in a filter with poles at frequencies below
< 200-500 MHz
• The solution to this problem is to “simulate” the inductors using
active components

B. Murmann EE315A - Chapter 6 56

 Gyrators

• Gyrators are “active inductors”

T. L. Deliyannis, J. K. Fidler and Y. Sun,

Continuous-Time Active Filter Design

http://www.engnetbase.com/ej
ournals/books/book_summary/
summary.asp?id=475
(Section 3.5)

• The above circuit is not all that useful for our lowpass filter; we
need a “floating” inductor
− Don’t want the inductance to be ground referenced

B. Murmann EE315A - Chapter 6 57

Floating Gyrator

http://www.engnetbase.com/ej
ournals/books/book_summary/
summary.asp?id=475
(Section 6.4)

• Floating gyrators are pretty complex (and sensitive to parasitics)

– There must be a better way to solve this problem+

B. Murmann EE315A - Chapter 6 58

 Integrators

• A circuit that we can build without much sweat is an active

integrator, e.g. using an OTA
– Many more options exist (more later)
• Assuming the availability of an ideal amplifier, we have

1 v in (t )
C∫ R
vout (t ) = − dt

1
Vout ( s ) = − V (s)
sRC in

B. Murmann EE315A - Chapter 6 59

State-Space Realization

State variables
(integrator outputs)

1 1
C∫ L∫
vc (t ) = ic (t )dt iL (t ) = v L (t )dt

1 1
Vc ( s ) = I (s) IL ( s ) = VL ( s )
sC c sL

1 1
Vc = Ic = I = Vout
sC sC L

1 1
IL = VL = (Vin − ILR − Vout )
sL sL

B. Murmann EE315A - Chapter 6 60

 Block Diagram

• Looks promising, but the problem with this realization is that the
first integrator takes a voltage at the input and produces a
current at the output
– We need the opposite if we want to realize the circuit with an
RC integrator

B. Murmann EE315A - Chapter 6 61

Modified (Equivalent) Block Diagrams

B. Murmann EE315A - Chapter 6 62

 Implementation

A1 A2 A3

Vout
‒1
H s = =
Vin s 1 + sRC + s2 LC

• One remaining issue is that the transfer function is inverted

– We could fix that (if needed) using a fourth amplifier
– Or by pushing A2 toward the input, and utilizing both its
inverting and non-inverting input
• The latter trick is used in the so-called KHN biquad

B. Murmann EE315A - Chapter 6 63

KHN Biquad

W.J. Kerwin, L.P. Huelsman, R.W Newcomb, "State-Variable Synthesis for Insensitive Integrated Circuit Transfer
Functions," IEEE JSSC, vol.2, no.3, pp. 87-92, Sep. 1967.

http://www.engnetbase.com/ejournals/books/book_summary/summary.asp?id=475 (Section 4.9)

1 R1 R2 + R1 R3 + R2 R3
ωo = Q=
Vo VLP K′ RC 2R1 R3
= =
Vi Vi s s2 2R2 R3 R 1
1+ +
ωo Q ωo 2 K′ = = 2∙
R1 R2 + R1 R3 + R2 R3 R1 Q

B. Murmann EE315A - Chapter 6 64

 Highpass and Bandpass Output

• An interesting feature of some biquads (including the HKN) is

that they provide additional highpass and bandpass outputs for
“free”

τ τ τ = RC

s 2 τ2 −s τ HLP ( s ) =
1
HHP ( s ) = HBP ( s ) =
s s2 s s2 s s2
1+ + 2 1+ + 2 1+ + 2
ωPQP ωP ωPQP ωP ωPQP ωP

B. Murmann EE315A - Chapter 6 65

The General KHN Biquad

HP

LP

BP

GENERAL

b2s 2 + b1s + b0 Implements arbitrary

HGENERAL ( s ) =
s s2 poles and zeros
1+ + 2
ωPQP ωP

B. Murmann EE315A - Chapter 6 66

 Tow-Thomas Biquad

[B. Boser]

P. E. Fleischer and J. Tow, “Design Formulas for biquad active filters using three operational
amplifiers,” Proc. IEEE, vol. 61, pp. 662-3, May 1973.

• General biquad using only three amplifiers

B. Murmann EE315A - Chapter 6 67

Tow-Thomas Transfer Functions

Vo1 ( b a − b ) s + ( b2a0 − b0 )
= −k 2 2 1 2 1
Vin s + a1s + a0
Vo 2 b2s 2 + b1s + b0
= 2
Vin s + a1s + a0
Vo 3 1 ( b0 − b2a0 ) s + ( a1b0 − a0b1 )
=−
Vin k1 a0 s 2 + a1s + a0

• Vo2/Vin implements a general biquad section with arbitrary poles

and zeros
• Vo1/Vin and Vo3/Vin realize the same poles but are limited to at
most one finite zero

B. Murmann EE315A - Chapter 6 68

 Tow-Thomas Design Equations

R8 For given ai , bi , ki , C1, C2 and R8 :

b0 =
R3R5R7C1C2 1
R1 =
1  R8 R1R8  a1C1
b1 =  − 
R1C1  R6 R4R7  k1
R2 =
R8 a0 C2
b2 =
R6 1 1
R3 = R8
R8 k1k 2 a0 C1 ωP =
a0 = R2R3R7C1C2
R2R3R7C1C2 1 1 1
R4 =
1 k 2 a1b2 − b1 C1 QP = ωP R1C1
a1 =
R1C1 k1 a0
R5 =
R2R8C2 b0C2
k1 =
R3R7C1 R8
R6 =
R7 b2
k2 =
R8 R7 = k 2R8

B. Murmann EE315A - Chapter 6 69

Sallen-Key LPF
G
H s =
s s2
1+ +
ωp Qp ωp 2

[B. Boser] 1
ωp =
R1 C1 R2 C2
R.P. Sallen and E. L. Key “A Practical Method of Designing RC Active
Filters.” IRE Trans. Circuit Theory, Vol. CT-2, pp. 74-85, 1955
ωp
Qp =
• Single gain element 1 1 1‒ G
+ +
R1 C1 R2 C1 R2 C2
– typically 1 ≤ G ≤ 10
• Poles only, no zeros
• Sensitive to parasitic capacitances
• Versions exist for HP, BP, .
– http://en.wikipedia.org/wiki/Sallen_Key_filter

B. Murmann EE315A - Chapter 6 70

 Tow-Thomas or Sallen-Key?

• Suppose we now wanted to realize a biquad that has poles only

• Should we use a Tow-Thomas or Sallen-Key realization?
• Clearly, from the perspective of complexity, we would probably
want to go for Sallen-Key
• Unfortunately, the Sallen-Key realization comes with
disadvantages in terms of sensitivity to component variations
• Let’s take a closer look+

B. Murmann EE315A - Chapter 6 71

Sensitivity
• The sensitivity of any variable y to any parameter x is defined as
(See e.g. Gray & Meyer, Section 4.2)
 ∆y / y  x ∆y x ∂y
Sxy = lim   = lim =
∆x → 0  ∆x / x  y ∆x →0 ∆x y ∂x

• In order to relate fractional changes in y to fractional changes in

x we can then write
∆y ∆x
≅ Sxy
y x

• Example
∆x ∆y
Sxy = 10 = 2% ⇒ ≅ 20%
x y

• Common sense: sensitivity is a first order approximation,

accurate only for “small” errors

B. Murmann EE315A - Chapter 6 72

 Parameter Variations (1)

• Discrete resistors and capacitors

• Come in many different shapes and sizes and accuracies

– E.g. metal film resistors, ~0.1% accurate, 5ppm/°C
– E.g. C0G dielectric capacitors, 2% accurate, very small
temperature dependence

B. Murmann EE315A - Chapter 6 73

Parameter Variations (2)

• Integrated resistors and capacitors

Poly resistor MIM Capacitor

• Important to distinguish between

– Global process variations
On the order of +/- 20% !
– Device-to-device mismatch
On the order of 1% or less

B. Murmann EE315A - Chapter 6 74

 Sensitivity to Global Variations

Tow-Thomas Sallen-Key
1 1
ωP = ∝
R8 1 R1C1R2C2 RC
ωP = ∝
R2R3R7C1C2 RC

ωP
QP = ωP R1C1 ∝ 1 QP = ∝1
1 1 1− G
+ +
R1C1 R2C1 R2C2

• QP is independent of global variations in both realizations

– Assuming all R and C use the same device structure,
respectively
• ωP varies with the RC product of the components

B. Murmann EE315A - Chapter 6 75

Sensitivity to Mismatch (Sallen-Key)

1
SRωP1 = SRωP2 = SCωP1 = SCωP2 = −
1 2
ωP =
R1C1R2C2 1 R 2C2
SRQ1P = −SRQ2P = − + QP
2 R1C1
ωP 1  R1C2 R 2 C2 
QP = SQC1P = −SCQ2P = − + QP  + 
1 1 1− G 2  RC R1C1 
+ +  2 1
R1C1 R2C1 R2C2
R1C1
SQGP = QPG
R 2C2

• Sensitivity depends on QP and “component spread” i.e. the

ratios of the resistors and capacitors, respectively

B. Murmann EE315A - Chapter 6 76

 Example (1)

• Want to design a Sallen-Key filter with QP=10

• Choice 1: All R and C are the same ⇒ G = 3 -(1/QP) = 2.9
– Very nice from the perspective of component spread, but
bad for sensitivity, e.g.

1
SRQ1P = −SRQ2P = − + QP = 9.5
2

• Choice 2: Reduce sensitivity by accepting large component spread

– Can show that G=1 is a good choice
• See e.g. http://www.maxim-ic.com/appnotes.cfm/an_pk/738
• Note: The expression for SQK is incorrect this application note (R3 and R1 should be
interchanged in this expression to match the result on the previous slide)

B. Murmann EE315A - Chapter 6 77

Example (2)
• For G=1, we have
ωP
QP =
1 1
+
R1C1 R2C1
and it follows that
1 R2
SRQ1P = −SRQ2P = − + =0 for R1 = R2
2 R1 + R2

• Unfortunately, in this case

C1
= 4QP2 = 400 for QP = 10
C2

• Bottom line: The Sallen-Key realization suffers from a strong

tradeoff between sensitivity and component spread

B. Murmann EE315A - Chapter 6 78

 Case Studies

MAXIM APPLICATION NOTE 738

Minimizing Component-Variation Sensitivity in Single Op Amp Filters
http://www.maxim-ic.com/appnotes.cfm/an_pk/738/

B. Murmann EE315A - Chapter 6 79

Sensitivity to Mismatch (Tow-Thomas)

R8 1
ωP = SRωP2 = SRωP3 = SRωP3 = −SRωP8 = SCω1P = SCωP2 = −
R2R3R7C1C2 2
SRQ1P = 1
R8C1 1
QP = ωP R1C1 = R1 SRQ2P = SRQ3P = SRQ7P = −SRQ8P = −SCQ1P = SCQ2P = −
R2R3R7C2 2

• Constant sensitivities, independent of Q and component spread

– Much nicer!

B. Murmann EE315A - Chapter 6 80

 Conclusions

• Biquads can be realized in numerous different ways

• Implementation and component sizing have a big impact on
sensitivity to variations
• No theory for finding a low-sensitivity architecture
– Use proven circuits & check!
• Tow-Thomas biquad
– Arbitrary poles and zeros, three amplifiers
– Well-behaved sensitivities
• Sallen-Key biquad
– Only poles, one amplifier
– Sensitivities trade off with component spread
• Typically use G=1 and use this circuit only for “low Q” poles

B. Murmann EE315A - Chapter 6 81

Example1: WCDMA Receiver

1

0.5

A 0 B
-0.5
[Yee, ESSCIRC 2000]
-1
-1 -0.5 0
Real

A
B

B. Murmann EE315A - Chapter 6 82

 Example 2: CDMA/GPS Receiver

• Channel select filters

(CSF)
– 640 kHz passband,
lowpass
– 0.5 dB passband ripple
– > 40 dB stopband
attenuation at 900 kHz
• 5th order elliptical filter
• Phase distortion can be
tolerated in this application
Lim et al., “A Fully Integrated Direct-Conversion Receiver for
CDMA and GPS Applications,” IEEE JSSC, Nov. 2006

B. Murmann EE315A - Chapter 6 83

Matlab Synthesis Result

204155.1855 (s^2 + 2.786e013) (s^2 + 5.715e013)
--------------------------------------------------------------------------
(s+1.89e006) (s^2 + 2.217e006s + 1.034e013) (s^2 + 5.315e005s + 1.664e013)

(s^2/2.786e013 + 1) (s^2/5.715e013 + 1)
= ----------------------------------------------------------------------------------------
(s/1.89e006 + 1) (s^2/1.034e013 + s/4.6640e+006 + 1) (s^2/1.664e013 + s/3.1308e+007 + 1)

0 0

-10 -0.5
Magnitude [dB]

Magnitude [dB]

-1
-20
-1.5
-30
-2

-40 -2.5

-50 4 -3
5 6 7 5 6
10 10 10 10 10 10
Frequency [Hz] Frequency [Hz]

B. Murmann EE315A - Chapter 6 84

 Pole and Zero Locations

1.5

1
ωP QP

0.5 p1,2 -42.30 ± j647.83 kHz 649.21 kHz 7.6748

Im a g [M H z]

p3,4 -176.45 ± j480.30 kHz 511.68 kHz 1.4499

0
p5 -300.80 kHz

-0.5
z1,2 ± j1203.2 kHz

-1 z3,4 ± j840.1 kHz

-1.5
-0.6 -0.4 -0.2 0
Real [MHz]

B. Murmann EE315A - Chapter 6 85

Pairing Options for p1,2 (High-Q)

• Pairing with nearby zero • Pairing with remote zero

(s^2/2.786e013 + 1) (s^2/5.715e013 + 1)
------------------------------------ -----------------------------------
(s^2/1.664e013 + s/3.1308e+007 + 1) (s^2/1.664e013 + s/3.1308e+007 + 1)

10 10
Magnitude [dB]

Magnitude [dB]

0 0

-10 -10

-20 4 5 6 7
-20 4 5 6 7
10 10 10 10 10 10 10 10
f [Hz] f [Hz]

B. Murmann EE315A - Chapter 6 86

 Pole-Zero Pairing
• Pairing high-Q poles with nearby zeros is desirable from a
dynamic range perspective
– Say that the amplifier at the output of the biquad can handle
a maximum signal of 1 Vpeak
– If the biquad response peaks 20 dB above unity, this means
that we can only process inputs with 100 mV amplitude near
the frequency of the peak (which lies in the passband)
– The signal is therefore reduced relative to the thermal noise
of the circuit, which is highly undesirable

± 1V

B. Murmann EE315A - Chapter 6 87

Response of the Individual Sections

First-order section Low-Q biquad High-Q biquad

10 10 10

5 5 5
Magnitude [dB]

Magnitude [dB]

Magnitude [dB]

0 0 0

-5 -5 -5

-10 -10 -10

-15 -15 -15

-20 4 6
-20 4 6
-20 4 6
10 10 10 10 10 10
f [Hz] f [Hz] f [Hz]

• In which order should we cascade these sections?

B. Murmann EE315A - Chapter 6 88

 Biquad Ordering

In Out

Ordering the Biquads from low-Q to high-Q generally yields “smooth” transfer functions from the
input to the intermediate nodes, and often helps minimize harmonic distortion, but the output will
have significant noise peaking near the corner frequency due to the last stage with high-Q.

In Out

Reversing the ordering will allow the later stages to filter out the noise peaking near corner
frequency. May also filter out harmonics (but not intermodulation).

In practical filter design, it would be worthwhile giving some thoughts to the options that you
may have for the ordering of the biquads. In a non-lowpass filter application, inherent ac-
coupling may also be used to your advantage to suppress offset accumulation.

(Some good system-level discussions in Schaumann/Ghausi/Laker.) [U. Moon]

B. Murmann EE315A - Chapter 6 89

Intermediate Outputs for Low-Q
High-Q

5 5 5
Magnitude [dB]

Magnitude [dB]

Magnitude [dB]

0 0 0

-5 -5 -5

-10 4 5 6
-10 4 5 6
-10 4 5 6
10 10 10 10 10 10 10 10 10
f [Hz] f [Hz] f [Hz]

• This ordering is most frequently used in practice

B. Murmann EE315A - Chapter 6 90

Intermediate Outputs for High-Q
Low-Q

10 10 10
Magnitude [dB]

Magnitude [dB]

Magnitude [dB]
5 5 5

0 0 0

-5 -5 -5

-10 4 5 6
-10 4 5 6
-10 4 5 6
10 10 10 10 10 10 10 10 10
f [Hz] f [Hz] f [Hz]

• At first glance this looks bad, but the noise from the high-Q
biquad is filtered before it reaches the output
– We will revisit this situation in the context of noise analysis

B. Murmann EE315A - Chapter 6 91

Dynamic Range Scaling

• Suppose we decided that the second ordering is what we want
to use for our design
• In this case, we need to think about a proper gain distribution
that avoids “clipping” in the individual amplifiers
• For this purpose, we introduce gain scale factors for each
section, while keeping the overall gain constant (K1K2K3 = 1 in
this example)

(s^2/2.786e013 + 1) (s^2/5.715e013 + 1) 1
----------------------------------- ----------------------------------- ----------------
(s^2/1.664e013 + s/3.1308e+007 + 1) (s^2/1.034e013 + s/4.6640e+006 + 1) (s/1.89e006 + 1)

K1*(s^2/2.786e013 + 1) K2*(s^2/5.715e013 + 1) K3
----------------------------------- ----------------------------------- ----------------
(s^2/1.664e013 + s/3.1308e+007 + 1) (s^2/1.034e013 + s/4.6640e+006 + 1) (s/1.89e006 + 1)

B. Murmann EE315A - Chapter 6 92

 Analysis (1)
1⋅ H1 Vˆmax 1⋅ H2 1⋅ H 3

• Suppose we chose K1=K2=K3=1 and assume that we will apply

single sine waves with arbitrary frequencies to the input
• Since H1 has significant peaking (|H1|max ≅ 3.19 ≅ 10 dB), we can
guarantee proper operation only for input amplitudes up to
Vˆmax 1V
e.g. = 314mV
H1 max 3.19

• Since the overall gain is unity (with no peaking above 1), this
means Vout swings only 314mV, meaning that we are “wasting”
available signal range

B. Murmann EE315A - Chapter 6 93

Analysis (2)

• A more desirable outcome may be to scale K1, K2, K3 such that all
stages utilize the maximum available swing as the input tone is
swept across all frequencies
– Note that in general, the maximum output swings for each
stage may not occur at the same frequency

K1H1 Vˆmax K 2H2 Vˆmax K 3H3 Vˆmax

B. Murmann EE315A - Chapter 6 94

 Analysis (3)

• This is achieved for

K1 H1 max = K1K 2K 3 H1H2H3 max

K1K 2 H1H2 max = K1K 2K 3 H1H 2H3 max

• In our example

K1K 2K 3 = 1 H1 max = 3.19 H1H2 max = 2.3 H1H2H3 max = 1

and therefore

1 1 1 3.19 1 3.19 ⋅ 2.3

K1 = = K2 = = K3 = =
H1 max 3.19 K1 H1H2 max 2.3 K1K 2 3.19

B. Murmann EE315A - Chapter 6 95

Intermediate Outputs After DR Scaling

0 0 0

-5 -5 -5
Magnitude [dB]

Magnitude [dB]

Magnitude [dB]

-10 -10 -10

-15 -15 -15

-20 4 5 6
-20 4 5 6
-20 4 5 6
10 10 10 10 10 10 10 10 10
f [Hz] f [Hz] f [Hz]

B. Murmann EE315A - Chapter 6 96

 Arguments Against “Sinusoidal” DR Scaling

• If the input signal is wide-band (as in many telecommunication

systems), the node with peaking may not saturate due to limited
signal power in that frequency region
– May want to optimize the gain distribution based on a power
spectral density “template” of the incoming signal
• Aligning the peaks for each output perfectly will require non-
integer component ratios
– But we may want to use integer ratios to improve matching
• For a discussion on why sinusoidal dynamic range scaling may
not always the best choice, see Behbahani, JSSC 4/2000

B. Murmann EE315A - Chapter 6 97

Expressions for Implementation

0.3133*(s^2/2.786e013 + 1) 1.3865*(s^2/5.715e013 + 1) 2.3021

----------------------------------- ----------------------------------- ----------------
(s^2/1.664e013 + s/3.1308e+007 + 1) (s^2/1.034e013 + s/4.6640e+006 + 1) (s/1.89e006 + 1)

2x Tow-Thomas

Vo 2 b2s 2 + b1s + b0
= 2 b1 = 0
Vin s + a1s + a0

B. Murmann EE315A - Chapter 6 98

 Tow-Thomas Component Values (b1=0)
1 k1 1 1
R1 = R2 = R3 =
a1C1 a0 C2 k1k2 a0 C1

1 1 1 k1 a0 R8
R4 = R5 = R6 = R7 = k 2R8
k 2 a1b2 C1 b0C2 b2

R6 R8
ωZ = ωP = QP = ωP R1C1
R3R5R7C1C2 R2R3R7C1C2

• a0, a1, b0, b1, b2 are known; can pick k1, k2, C1, C2 and R8
• Reasonable starting values
– k1 = k 2 = 1
– Set C1 = C2 to a reasonable value that is easily
implemented, e.g. 1pF
– Set R8 to a reasonable value that is easily implemented and
represents an integer multiple or fraction of R2, R3 or R7
B. Murmann EE315A - Chapter 6 99

Example Design Flow

• First cut component calculation using reasonable starting values

for k1, k2, C1, C2 and R8
• Dynamic range scaling of internal amplifier outputs by adjusting
k1 and k2
• Thermal noise scaling using ideal amplifiers
– Increase all capacitors and reduce all resistors until noise
specification is met
• Design amplifiers
• Repeat thermal noise scaling to accommodate amplifier noise
• Analyze sensitivity to component variations and devise tuning
mechanism (if needed)

B. Murmann EE315A - Chapter 6 100

 Dynamic Range Scaling of Internal Nodes

−k 2
( b2a1 − b1 ) s + ( b2a0 − b0 ) b2s 2 + b1s + b0
s 2 + a1s + a0 s 2 + a1s + a0

1 ( b0 − b2a0 ) s + ( a1b0 − a0b1 )

−
k1 a0 s 2 + a1s + a0

• Scale k1 and k2 such that peak magnitude at Vo1 and Vo2

corresponds to maximum available amplifier swing

B. Murmann EE315A - Chapter 6 101

Sensitivity Analysis

• Ideally, we would like to have an

analytical expression that
0 relates “interesting points” of the
-0.5 response to variations in all
components
Magnitude [dB]

-1
– E.g. calculate variations in
-1.5
the passband ripple as a
-2 function of the percent error
-2.5 in R2
-3
5 6
• This is almost impossible or at
10 10
Frequency [Hz] least impractical to do in
practice

B. Murmann EE315A - Chapter 6 102

 Sensitivity Analysis – Monte Carlo
• Monte Carlo Analysis
– Have a statistical model for all components
– Run a large number of simulations (Matlab or Spectre) to
capture many statistical outcomes and create overlay plot
from all runs

MAXIM APPLICATION NOTE 738: Minimizing

Component-Variation Sensitivity in Single Op Amp Filters
http://www.maxim-ic.com/appnotes.cfm/an_pk/738/

• Such an analysis is very useful for validation, but perhaps too

much work for intuition building and/or design guidance
B. Murmann EE315A - Chapter 6 103

Basic Sensitivity Analysis

• Say we just want to get a basic feel for the sensitivities
• Look at impact of
– Global process variations
– Component mismatch
• For global process variations, we have already seen that

R6 1 R8 1
ωZ = ∝ ωP = ∝ QP = ωP R1C1 ∝ 1
R3R5R7C1C2 RC R2R3R7C1C2 RC

• If all R and C vary by the same percentage, the filter “shape” is

preserved and shifted back and forth along the frequency axis
• If this is a problem for the application, we can “tune” either R or
C to bring the filter response back to the desired location

B. Murmann EE315A - Chapter 6 104

 Mismatch Analysis

R6 R8
ωZ = ωP = QP = ωP R1C1
R3R5R7C1C2 R2R3R7C1C2

• Suppose we had resistors and capacitors that deviate from their

nominal component value (which is subject to global variations)
by a standard deviation of 1%
• Since
1
SRωP2 = SRωP3 = SRωP3 = −SRωP8 = SCω1P = SCωP2 = −
2
this means
1
σ ∆ωP /ωP = 6 ⋅ 1% = 1.22%
2

3σ ∆ωP /ωP = 3.67% ≅ 4%

B. Murmann EE315A - Chapter 6 105

Passband with Pole Errors (1)

• ± 4% change in ωP of first order section

4
+4%
2 -4%

0
Magnitude [dB]

-2

-4

-6

-8

-10 4 5 6
10 10 10
Frequency [Hz]

B. Murmann EE315A - Chapter 6 106

 Passband with Pole Errors (2)

• ± 4% change in ωP of low-Q section

0
Magnitude [dB]

-2
Worse.
-4

-6
+4%
-8
-4%

-10 4 5 6
10 10 10
Frequency [Hz]

B. Murmann EE315A - Chapter 6 107

Passband with Pole Errors (3)

• ± 4% change in ωP of high-Q section

0
Magnitude [dB]

-2 Bad !
-4

-6
+4%
-8
-4%

-10 4 5 6
10 10 10
Frequency [Hz]

B. Murmann EE315A - Chapter 6 108

 Continuous Time Filters: Ladders

Boris Murmann
Stanford University
[email protected]
Copyright © 2014 by Boris Murmann

B. Murmann EE315A - Chapter 7 1

Sensitivity Problem with Cascaded Biquads

x
x
x
In Out
x
x
x
x
x
[U. Moon]
x
x

• Passband response is sensitive to shifts in the pole positions

– Especially for high Q
• Typically, integrated continuous time filters use biquads to realize filters
only up to ~5th order

B. Murmann EE315A - Chapter 7 2

 Conceptual View of a Biquad Cascade

• Individual sections are actively decoupled

– Variations in individual components affect only one pair of poles
(and/or zeros)
• Ideally, we would like all the poles (and zeros) to “move together”
– This would at least preserve the “shape” of the filter response

B. Murmann EE315A - Chapter 7 3

Doubly Terminated LC Ladder Filters

x
x

x
x

• The passband response of ladder filters is much less sensitive

to component variations when compared to a biquad cascade
– Poles “tend” to move together
• For a sensitivity analysis, see e.g.
– G. C. Temes and H. J. Orchard, “First order sensitivity and worst-case
analysis of doubly terminated reactance two-ports,” IEEE Trans. Circuit
Theory, 20 (5), pp. 567–571, 1973.

B. Murmann EE315A - Chapter 7 4

 Basic Intuition

• In the passband, the gain from Vin to Vout is maximum (0.5)

• Any detuning of L and C can only reduce the passband gain
• Therefore, the passband gain is convex in L and C, and the
sensitivity is zero around the nominal design point!

Sensitivity = 0 (!)
Passband gain

L, C

B. Murmann EE315A - Chapter 7 5

Analysis Example (1)

i 4 = v outY4 = i3
v 2 = i3Z3 + v out
i 2 = v 2Y2
i1 = i 2 + i 3
v in = i1Z1 + v 2
= (v 2Y2 + v outY4 ) Z1 + v 2

= ([Y4Z3v out + v out ]Y2 + v outY4 ) Z1 + v outY4Z3 + v out

v out 1
=
v in ([Y4Z3 + 1]Y2 + Y4 ) Z1 + Y4Z3 + 1
1
=
Y4Z3Y2Z1 + Y4Z3 + Y4Z1 + Y2Z1 + 1

B. Murmann EE315A - Chapter 7 6

 Analysis Example (2)

• E.g. for Z1 = R1 Z3 = sL3

Y2 = sC2 Y4 = sC4
it follows that
v out 1
= 3 2
v in s C4L3C2R1 + s C4L3 + s (C4R1 + C2R1 ) + 1

• A third order lowpass filter

• Zeros can be realized by utilizing parallel and series
combinations of inductors and capacitors
• Analysis is doable
− But very tedious!

B. Murmann EE315A - Chapter 7 7

LC Ladder Synthesis
• Filter tables
– A. Zwerev, Handbook of filter synthesis, Wiley, 1967
– R. Saal, Handbook of filter synthesis, AEG-Telefunken, 1979
– A. B. Williams and F. J. Taylor, Electronic filter design, 3rd edition,
McGraw-Hill, 1995
• CAD tools
– http://www.circuitsage.com/filter.html
• Comprehensive list of available tools
– http://tonnesoftware.com/elsie.html
• Free version of Elsie supports ladder synthesis up to 7th order
– http://www.nuhertz.com/download.html
• FilterFree – up to 3rd order
• FilterSolutions – $$$
– Agilent ADS

B. Murmann EE315A - Chapter 7 8

 Butterworth Filter Table

• Denormalization

R
Li ,den = Li
ω −3dB

1
Ci ,den = Ci
ω −3dB ⋅ R

• R is the desired
value of the source
and termination
resistor
[Schaumann]

B. Murmann EE315A - Chapter 7 9

5th Order Elliptic Filter Table (1)

ω 
θ = sin−1  p 
 ωs 

0.17dB passband ripple

[Williams & Taylor]

Table 11-56

B. Murmann EE315A - Chapter 7 10

 5th Order Elliptic Filter Table (2)

B. Murmann EE315A - Chapter 7 11

Back to Our Design Example

• Channel select filters

(CSF)
– 640 kHz passband,
lowpass
– 0.5 dB passband ripple
– > 40 dB stopband
attenuation at 900 kHz
• 5th order elliptical filter

Lim et al., “A Fully Integrated Direct-Conversion Receiver for

CDMA and GPS Applications,” IEEE JSSC, Nov. 2006

B. Murmann EE315A - Chapter 7 12

 Synthesis Result (Using Elsie)

L2 L4

C2 C4

C1 C3 C5

• Termination resistors arbitrarily set to 10kΩ

B. Murmann EE315A - Chapter 7 13

Spice Simulation Result

-10 -6

-6.5
Magnitude [dB]
Magnitude [dB]

-20
-7

-30 -7.5

-8
-40
-8.5

-50 4 5 6 7 4 5
10 10 10 10 10 10
Frequency [Hz] Frequency [Hz]

• 6 dB passband attenuation due to resistive termination

– Easy to change to 0dB in an active realization

B. Murmann EE315A - Chapter 7 14

 20% Variation in L2

-5
+20% +20%
-10 -20% -20%
-5.5
Magnitude [dB]

Magnitude [dB]
-20 -6

-6.5
-30

-7
-40
-7.5

-50 4 5 6 7 4 5 6
10 10 10 10 10 10 10
Frequency [Hz] Frequency [Hz]

• Only a very small change in the passband response; moderate

degradation in the stopband
– Smaller (i.e. more realistic) variations than 20% can be
easily handled through overdesign

B. Murmann EE315A - Chapter 7 15

State-Space Description for C1

C2 C4

I2 I4
+ + +
Vin V1 V3 V5 Vout
- - -

I1 1  Vin − V1 
V1 = =  − I2 + [V3 − V1 ] sC2 
sC1 sC1  R 

 C   V − V1  1 C
V1  1 + 2  =  in − I2  + V3 2
 C1   R  sC1 C1

1  Vin V1 V2 
V1 = − − + + − V3sC2 
s (C1 + C2 )  R R Rx 2 

B. Murmann EE315A - Chapter 7 16

 Implementation of C1 Integrator

1  Vin V1 V2 
V1 = − − + + − V3sC2 
s (C1 + C2 )  R R R x 2 

B. Murmann EE315A - Chapter 7 17

Implementation of L2 Integrator

C2 C4
1
I2 = ( V1 − V3 )
sL 2
I2 I4
+ + +
Vin Vout R 2x2  V1 V 
V1
-
V3
-
V5
-
V2 = I2R x2 = − − + 3 
sL 2  R x2 R x2 

B. Murmann EE315A - Chapter 7 18

 Remaining Integrators

1  V2 V 
V3 = − − + 4 − V1sC2 − V5sC4 
s (C2 + C3 + C4 )  R x 4 R x 4 

Rx24  V3 V 
V4 = I4R x 4 = − − + 5 
sL4  Rx 4 Rx 4 

1  V5 V4 
Vout = V5 = −  − − V3sC4 
s (C4 + C5 )  R R x 4 

B. Murmann EE315A - Chapter 7 19

Complete Realization

B. Murmann EE315A - Chapter 7 20

 Signal Inversion

-1
Symbol

Realization in a single-ended circuit

-
(need only one shared circuit per state)

V1p V2p
Realization in a differential circuit
V1m V2m

• In a first-cut (single-ended) simulation, signal inversion can also

be achieved using negative resistors and capacitors

B. Murmann EE315A - Chapter 7 21

Simulation Setup

• AC analysis with 1V
applied at the input
• Amplifiers are ideal,
with an open loop gain
of 106
• Set Rx2=Rx4=R=10kΩ
– Somewhat arbitrary
at this point

B. Murmann EE315A - Chapter 7 22

 Frequency Response

1.6
1.4
1.2 V4
Magnitude

|V1|max = 0.8505 V
1
V2
|V2|max = 1.5585 V
0.8
|V3|max = 0.9039 V
0.6 |V4|max = 1.7072 V
0.4 |Vout|max = 0.5000 V
0.2 V1 V3
Vout
0 5 6
10 10
Frequency [Hz]

B. Murmann EE315A - Chapter 7 23

Node Voltage Scaling

• To scale the peak output voltage of an integrator by a factor of k,
scale all resistors and capacitors connected to the input and
output node as shown below
• Feedback R and C remain unchanged
– Will be scaled together with all other components to adjust
the thermal noise (more later)

B. Murmann EE315A - Chapter 7 24

Frequency Response After 0dB Scaling

0.8

Magnitude
0.6

0.4

0.2

0 5 6
10 10
Frequency [Hz]

B. Murmann EE315A - Chapter 7 25

Component Values After 0dB Scaling

% feedback R [Ω] and C [F]
ci1 = 4.3711e-011
• Resistors
ri1 = 10000
ci2 = 2.5416e-011
– Rmin = 2.93 kΩ
ci3 = 7.4108e-011
ci4 = 1.7567e-011
– Rmax = 34.1 kΩ
ci5 = 4.8692e-011
ri5 = 10000 • Capacitors
% coupling R [Ω] – Cmin = 6.47 pF
rin = -8.5052e+003
r12 = -1.8324e+004 – Cmax = 48.7 pF
r21 = 5.4573e+003
r23 = -5.7997e+003
r32 = 1.7242e+004
• Component spread ~10
r34 = -1.8888e+004
r43 = 5.2944e+003
– Manageable in practice
r45 = -2.9287e+003
r54 = 3.4145e+004
– May be able to reduce spread by
scaling integration capacitors,
% zero C [F]
c13 = -6.4665e-012 subject to noise constraints
c31 = -7.3035e-012
c35 = -3.6888e-011 • A very complex optimization
c53 = -1.1287e-011 problem!

B. Murmann EE315A - Chapter 7 26

 Schematic

r12 r32 r34 r54

ci2 ci4

c13 ci3 c35

ci1 ci5
ri1 ri5
c31 c53

rin r21 r23 r43 r45

B. Murmann EE315A - Chapter 7 27

20% Variation in Ci2

• Only small passband variations despite large component variation

• Active realization of ladder retains low sensitivity of passive prototype
• More analysis is needed to determine the actual precision requirements
for all components
– E.g. through a Monte Carlo simulation

B. Murmann EE315A - Chapter 7 28

 Summary

• Higher-order filter realization

– Cascade of biquads
• High sensitivity often problematic for order ≥ 5
– Ladder filters
• Based on LC prototypes
• Low sensitivity
• Active RC simulation retains low sensitivity

B. Murmann EE315A - Chapter 7 29

 Integrator Realization & Nonidealities

Boris Murmann
Stanford University
[email protected]
Copyright © 2014 by Boris Murmann

B. Murmann EE315A - Chapter 8 1

Outline

• Impact of finite amplifier bandwidth and gain in active RC

integrators
• Thermal noise
– Passive filters
– Active RC filters
• Alternative integrator realizations
• Parameter tuning

B. Murmann EE315A - Chapter 8 2

Amplifier Model with First Order Nonidealities

- a0

p
Rnoise Ra
-a0 1
1
noiseless ωp = ωu ≅ a0 ⋅ω p
Ca RaCa

a0 aω ω
a( s ) = − ≅− 0 p ≅− u for ω >> ω p
s s s
1+
ωp

B. Murmann EE315A - Chapter 8 3

RC Integrator with Nonideal Amplifier

• Using return ratio analysis, we can write

1 ω Vout (s ) T (s )
A∞ = − =− 0 A(s ) = = A∞
sRC s Vin (s ) 1 + T (s )
s
R a0 ω0 ωu
T (s ) = −a(s ) = ωp ≅
1 s s a0
R+ 1+ 1+
sC ωp ω0

• As long as T(s) is large, the transfer function A(s) is close to the

desired ideal transfer function (A∞)

B. Murmann EE315A - Chapter 8 4

 a0→∞, ωu=100ω0

100 A

Magnitude [dB]
∞
50 T(s)
0 A(s)

-50
-100 -6 -4 -2 0 2 4
10 10 10 10 10 10
ω /ω 0

A
150
Phase [deg]

∞
“phase lag” A(s)
100

50

0 -6 -4 -2 0 2 4
10 10 10 10 10 10
ω /ω 0

B. Murmann EE315A - Chapter 8 5

a0=10,000, ωu→∞

100 A
Magnitude [dB]

∞
50 T(s)
0 A(s)

-50
-100 -6 -4 -2 0 2 4
10 10 10 10 10 10
ω /ω 0

A
150
Phase [deg]

∞
“phase lead” A(s)
100

50

0 -6 -4 -2 0 2 4
10 10 10 10 10 10
ω /ω 0

B. Murmann EE315A - Chapter 8 6

 a0=10,000, ωu=100ω0

100 A

Magnitude [dB]
∞
50 T(s)
0 A(s)

-50
-100 -6 -4 -2 0 2 4
10 10 10 10 10 10
ω /ω 0

A
150
Phase [deg]

∞
A(s)
100

50

0 -6 -4 -2 0 2 4
10 10 10 10 10 10
ω /ω 0

B. Murmann EE315A - Chapter 8 7

RC Integrator with Finite ωu

• Ignoring finite DC gain for the time being, i.e. using

ωu
a(s ) = −
s

• The equations from slide 4 yield for this case

ω 1 1
Aactual (s ) = − o
s ω s


A ideal
1+ 0 1+
ωu ω o + ωu



Magnitude error Undesired pole
(Magnitude and phase error)

• The first error term modifies only the magnitude, and effectively
alters the integration time constant (RC = 1/ω0)

B. Murmann EE315A - Chapter 8 8

 Significance of ω0 (Biquad Example)

L
Ci1 =
Rx2 Ci 2 = C

1 1 1 1
H(s) = − 2
=− 2
ωP = = = ω01 ⋅ ω02
1+ sRC + s LC s s LC RxCi1RxCi2
1+ + 2
ωPQP ωP

• Integrator ω0 typically not too far off from pole frequency ωP

B. Murmann EE315A - Chapter 8 9

Baseline Requirement for ωu

ω 1 1
Aactual (s ) = − o
s ω s


A ideal
1+ 0 1+
ωu ω o + ωu



Magnitude error Undesired pole
(Magnitude and phase error)

• High-Q filters will be sensitive to variations and uncertainty in

the “effective” value of ω0
• In a practical design, we therefore require ωu >> ω0, typically
ωu = 10…50⋅ω0
• Assuming that we comply with this guideline, we are left with

ωo 1
Aactual (s ) ≅ −
s 1+ s
ωu

B. Murmann EE315A - Chapter 8 10

 Effect on Filter Response

• For a filter that uses ideal integrators, we know that

H filter (s ) s = p →∞
ideal

• For the case with finite ωu

  s 
H filter  s  1 +   →∞

  ωu   s = pactual

and therefore

 p  pideal = α i ± j β i
pideal = pactual  1 + actual 
 ωu  pactual = α a ± j β a

B. Murmann EE315A - Chapter 8 11

Solving for pactual (1)

 α + j βa 
αi + jβi = ( αa + jβa )  1 + a 
 ωu 

• Equating real and imaginary parts, we find

 αa  βa2  α 
αi = α a  1 + − βi = βa  1 + 2 a 
 ωu  ωu  ωu 

• To proceed, it makes sense to customize the analysis for high-Q

poles, which should represent the most critical case

1 ωPideal
QPideal = − >> 1 ωPideal = αi2 + βi2 ≅ βi
2 αi
1 ωPactual
QPactual = − >> 1 ωPactual = α a2 + βa2 ≅ βa
2 αa

B. Murmann EE315A - Chapter 8 12

 Solving for pactual (2)

 α  β2  α 
αi = α a  1 + a  − a βi = βa  1 + 2 a 
 ωu  ωu  ωu 

• We can now simplify using

α a << ωPactual ≅ ω0 << ωu

to obtain
βa2
αi ≅ α a − βi ≅ βa
ωu
βa2
α a ≅ αi + β a ≅ βi
ωu

• Negligible change in the pole’s imaginary part; real part affected

by finite ωu

B. Murmann EE315A - Chapter 8 13

Effect on Pole Locations

βa2
jω α a ≅ αi +
ωu

1 ωPactual 1 ωPideal 1 ωPideal 1

QPactual = − ≅− =−
2 β 2
2 ω 2
2 αi ω2
αi + a αi + Pideal 1 + Pideal
σ ωu ωu αiωu
αi αa
1  ω 
= QPideal ≅ QPideal  1 + 2QPideal Pideal 
ωPideal  ωu 
1 − 2QPideal
ωu

• Example for QPideal = 30, <2% (0.17dB) increase in QPactual

ωPideal ωu
2 ⋅ 30 ⋅ < 2% > 3000 (!)
ωu ωPideal

B. Murmann EE315A - Chapter 8 14

 Corresponding Phase Error

• For ωu = 3000ω Pideal and ω Pideal ≅ ω0

we can estimate the phase error of the integrator at ω0 using

 
 1   ω   ω  1 1 180

φerr = ∡  ≅ ∡ arg  1 − j Pideal  = tan−1  − Pideal  ≅ − =− ⋅ = −0.02

 1 + j ω0   ωu   ωu  3000 3000 π
 ωu 
 
Magnitude [dB] 100 A
∞
50 T(s)
0 A(s)

-50
-100 -6 -4 -2 0 2 4
10 10 10 10 10 10
ω/ω0

A
150
Phase [deg]

∞
A(s)
100

50 Phase = 89.98º
0 -6 -4 -2 0 2 4
10 10 10 10 10 10
ω/ω0

B. Murmann EE315A - Chapter 8 15

Pole-Zero Cancellation (1)

1 + sRzC
H (s ) = −
 s  s
sRC  1 + + (1 + sRzC )
 ωu  ωu
1 1 + sRzC
= −
sRC s 1

 1+ + (1 + sRzC )
Ideal response ωu ωu RC


Should be 1

ωo 1 + sRzC
=−
s ω s  Rz 
1+ o + 1+
ωu ωu  R 
ωo 1 1 + sRzC
=−
s ω
1+ o  Rz 
1+ R 
1+ s  
ωu
 ωo 
ωu  1 + 
 ωu 

B. Murmann EE315A - Chapter 8 16

 Pole-Zero Cancellation (2)

 Rz 
1+ R 
• We can achieve “ideal” operation by letting   =RC
 ω 
z

ωu  1 + o 
 ωu 

1
• Assuming ωu >> ω0, this is accomplished for Rz ≅
ωuC

• In high-speed filters, this trick typically helps reduce the amplifier

bandwidth requirements by more than an order of magnitude
− Note that the requirements do not drop to “zero” because we
still need to maintain ωu >> ω0
− Practicality issue: How to ensure that RZ tracks variations in ωu
and C, for both global variations and random mismatch errors

B. Murmann EE315A - Chapter 8 17

Auxiliary Amplifiers

Rf
A∞ = −
Rs Rf 1
A(s ) = −
Rs s  Rf 
ω u Rs 1+ 1 + 
T (s ) ≅ ω u  Rs 
s Rs + Rf

• No (good) way to cancel error from inverting or summing amplifiers

– But these amplifiers also contribute to the overall phase shift

B. Murmann EE315A - Chapter 8 18

 “Tweaking” a Tow-Thomas Biquad

L. C. Thomas, “The Biquad: Part I -Some Practical Design

Considerations,” IEEE Trans. Ckt. Theory, Vol. CT-l, No. 3, May 1971.

• May be able to cancel the phase error from all stages by

introducing a “strategically” tuned zero
– Practicality questionable

B. Murmann EE315A - Chapter 8 19

RC Integrator with Finite Gain

a(s ) = −a0

R sRC
T (s ) = a0 = a0
1 sRC + 1
R+
sC

1 1 1 1 1
Aactual (s ) = − =− = −ω 0
sRC 1 + 1 sRC 1 + 1 + sRC  1 ω
s 1+  + 0
T (s ) a0sRC
 a0  a0

B. Murmann EE315A - Chapter 8 20

 Effect on Filter Response

• For the case of finite gain, we can therefore write

 1 ω
pideal = pactual  1 +  + 0
 a0  a0

• For the case of high-Q poles, it can then be shown that

1  Q 
QPactual ≅ QPideal ≅ QPideal  1 − 2 Pideal 
Q  a0 
1 + 2 Pideal
a0

• Example for Qpideal = 30, <2% (0.17dB) decrease in QPactual

30
2⋅ < 2% a0 > 3000
a0

B. Murmann EE315A - Chapter 8 21

Summary

• Finite amplifier bandwidth leads to QP enhancement

– Typically seen as excess peaking in the filter’s magnitude
response
• Finite amplifier gain leads to QP degradation
– Typically seen as droop in the filter’s magnitude response

• Wait!
– Can’t we cancel the QP enhancement against the QP
degradation?

B. Murmann EE315A - Chapter 8 22

 Q-Tuning

V. Gopinathan et al., “Design Considerations for High-Frequency Continuous-Time

Filters and Implementation of an Anti-aliasing Filter for Digital Video,” IEEE JSSC,
Vol. 25, No. 6, Dec. 1990.

B. Murmann EE315A - Chapter 8 23

Noise

Filter
Signal

Noise

1 2
Psignal v̂ out
SNR = =f 2
Pnoise 2 2
v
∫ ∆outf ⋅ df
f 1

B. Murmann EE315A - Chapter 8 24

 RC Lowpass Filter

f2 2
1
2
vout = ∫ 4kTR ⋅ df
f
1 + j 2πf ⋅ RC
1

f2
df du
= 4kTR ∫ 2
; ∫ 1 + u 2 = tan
−1
u
f1 1 + ( 2πfRC )

B. Murmann EE315A - Chapter 8 25

Total Integrated Noise

∞ 2
1
,tot = ∫ 4kTR ⋅
2
v out df
0
1 + j 2πf ⋅ RC

∞
df du
= 4kTR ∫ 2
; ∫ 1 + u 2 = tan
−1
u
0 1+ ( 2πfRC )
1
= 4kTR ⋅
4RC
kT
=
C

B. Murmann EE315A - Chapter 8 26

 LC Lowpass Filter

2 1
ωP =
∞ LC
1
,tot = ∫ 4kTR ⋅
2
vout df
s s2
0 1+ + 2 1 L
ωPQP ωP QP =
R C

B. Murmann EE315A - Chapter 8 27

Useful Integrals

A. Dastgheib and B. Murmann, "Calculation of total integrated

noise in analog circuits," IEEE Trans. on Circuits and Systems I,
Vol. 55, pp. 2988-2993, Nov. 2008.

B. Murmann EE315A - Chapter 8 28

 Total Integrated Noise of LC Filter

∞
1 1
,tot = ∫ 4kTR ⋅
2
vout 2
df ωP =
0 s s LC
1+ +
ωPQP ωP2
1 L
QP =
ωPQP R C
= 4kTR
4
1
kT ωPQP =
= RC
C

B. Murmann EE315A - Chapter 8 29

The Nyquist Theorem

Christian C. Enz and Eric A. Vittoz, Charge-Based MOS Transistor Modeling: The EKV Model for
Low-Power and RF IC Design, Wiley, 2006 (p. 106)

௡ଶ
= 4 ·  ( 2 ) PSD
Δ
ஶ

௡ଶ = 4 ·  ( 2 ) Variance

଴

B. Murmann EE315A - Chapter 8 30

 The Bode Theorem

Christian C. Enz and Eric A. Vittoz, Charge-Based MOS Transistor Modeling: The EKV Model for
Low-Power and RF IC Design, Wiley, 2006 (p. 107)

1 1
= lim  · () = lim  · ()
ஶ ௦→ஶ ଴ ௦→଴

1 1

௡ଶ =  · −
ஶ ଴

• Let’s you calculate the total integrated noise of passive networks

without sweating through integrals!

B. Murmann EE315A - Chapter 8 31

Example: LC Ladder
1
ஶ = 43
Rs
=0
଴
Rt 

௡ଶ = = 9.7௥௠௦
ஶ
10k

Simulation with and without Rs (makes no difference!)

**** the results of the sqrt of integral (v**2 / freq) **** the results of the sqrt of integral (v**2 / freq)
**** total output noise voltage = 9.6683u volts **** total output noise voltage = 9.6683u volts
-15 -15
10 10

-16
Rs=∞ -16
Rs=10k
10 10
Noise PSD [V ]

Noise PSD [V ]
2

-17 -17
10 10

-18 -18
10 10

-19 -19
10 10
4 5 6 7 4 5 6 7
10 10 10 10 10 10 10 10
Frequency [Hz] Frequency [Hz]

B. Murmann EE315A - Chapter 8 32

 Active RC Lowpass
R

Rs
Vin - Vout

2
∞
1 1  R
∫ 4kT  R + Rs  ⋅ 1 + j 2πf ⋅ RC df
2
vout ,res =
0

2
∞
  R  1
= ∫ 4kT  R 1 +   ⋅ df
 R 1 + j 2 π f ⋅ RC
0   s  

kT  R 
= 1 +  (noise due to resistors only)
C  Rs 

B. Murmann EE315A - Chapter 8 33

Amplifier Noise Analysis (1)

v n2 = 4kTRnoise ∆f
vx

s
1+
ωu vx Rs 1 ω0
vout = − (v + v n ) = =
s x vout Rs +
1
1+
R
1+
s
1 Rs ωx
+ sC
R

1 1
ω0 = ωx = Rx = R Rs
RC RxC

B. Murmann EE315A - Chapter 8 34

 Amplifier Noise Analysis (2)

• Solving for vout/vn yields

s
1+
vout R ωx
=−
vn Rx  1 R 1  s2
1+ s  +  +
 ωu R x ω 0  ω u ω 0
2
s
2 1+
∞
 R  ωx
2
vout ,amp = ∫ 4kTRnoise ⋅   df
 Rx  1 + s  1 R + 1  + s
2
0
 
 ωu Rx ω0  ωu ω0
2
−1
1+
s  1 R 1 
ω Q ω2  ωnQ =  +
∞
z 
∫ df = n  1 + n2   ωu Rx ω0 
s s2 4  z 
0 1+ + 2 
ωnQ ωn ωn2 = ωu ω0 z = −ωx

B. Murmann EE315A - Chapter 8 35

Amplifier Noise Analysis (3)

 
 R  ωnQ  ω2n   R    ω ω 
2 2
1
2
v out = 4kTRnoise    1 +  = kTRnoise     1+ u 0 
  ω2x 
,amp
R
 x 4  2
z   x 
R 1 R 1
 ω R + 
 u x ω0 
 ω R  
2
 1+ u  x   Note: The same result
ω0  R   can be obtained by
= kTRnoise ωu  ≅ kTRnoise ωu approximating vout/vn as
 R  ω R 
a single pole response
 x 1+ u x
 
 R  ω R 
before carrying out the
 0 integral.

kT Rnoise ωu
≅
C R ω0

B. Murmann EE315A - Chapter 8 36

 Total Noise for Active RC Filter

2 2 2 kT  R Rnoise ωu 
vout ,tot = vout ,res + v out ,amp ≅ 1+ + 
C  Rs R ω0 

• Amplifier noise contribution is large for large ωu/ω0

– But, unfortunately, we need ωu >> ω0 to maintain an accurate
transfer function
• Given that we need ωu >> ω0 , the only option we have is to
choose Rnoise << R to minimize amplifier noise
– In a transistor-level implementation, this requires large gm
(and large IBIAS), since Rnoise ~ 1/gm

B. Murmann EE315A - Chapter 8 37

Frequency Response with Finite ωu

Magnitude [dB]

0
ω u=1000 ω 0
-50
ω u=10ω 0

-100 -5 0 5
10 10 10
ω /ω 0
Phase [deg]

150
ω u=1000 ω 0
100
ω u=10ω 0
50
0 -5 0 5
10 10 10
ω /ω 0

B. Murmann EE315A - Chapter 8 38

 Amplifier Noise Contribution (Rnoise=0.1R)

PSD/(4kTRnoise*(R/Rx) )
2
0
10
ω u=100ω 0
ω u=10ω 0

-4 -2 0 2 4 6
10 10 10 10 10 10
ω /ω 0

10
ω u=100ω 0
Integral/(kT/C)

8
ω u=10ω 0
6
4
2

-4 -2 0 2 4 6
10 10 10 10 10 10
ω /ω 0

B. Murmann EE315A - Chapter 8 39

Active Second Order Lowpass

1
i n 2 = 4kT
1
∆f H( s ) =
Rx s s2
1+ + 2
ωPQP ωP

1
ωP =
LC
1 L
 2
i n1 = 4kT 
R 
+ 2  ∆f
QP =
R
 x R 
x 
R C

 QP  Q
1+ s  s P
vout Rx v out ωP  ωP
= 2 =R  2
≅R
i n1 s s in2 s s s s2
1+ + 2 1+ + 2 1+ + 2
ωPQP ωP ωPQP ωP ωPQP ωP

(after some algebra)

B. Murmann EE315A - Chapter 8 40

 Analysis

2 2
s
∞
 2 R  Rx ∞
QP2 R 2
∫ 4kT  Rx + R 2  ⋅
2
= ωP
vout ,1 2
df 2
vout ,2 = ∫ 4kT ⋅ df
0  x  1+ s
+
s
0
Rx s s2
1+ + 2
ωPQP ωP2 ωPQP ωP

ωPQP QP2 ωPQP

= 4kT ( 2Rx + R ) = 4kT
4 Rx 4
kT 2Rx + R
= kT R 2
C R = Q
C Rx P
kT  Rx 
= 1 + 2 R 
C  

• For high QP, we definitely need to make R << Rx

B. Murmann EE315A - Chapter 8 41

Optimum
1 Rx
N = (1 + 2k ) + QP2 k=
k R
dN 1
= 2 − QP2 2 = 0
dk k

QP
kopt =
2

kT   2   kT
2
vout 2
= vout 2
,1 + vout ,1 = 1+ 
C   2
+ 2  QP  =
  C
1 + 2 2QP ( )

• In a properly designed filter (and for large QP,) the noise will be
roughly proportional to QP
• For a poorly designed filter, the noise can be proportional to QP2

B. Murmann EE315A - Chapter 8 42

 Tow-Thomas Noise Example

[B. Boser]

B. Murmann EE315A - Chapter 8 43

Frequency Response (BP Output)

Mag [dB]

QP=7

QP=30
R1 = R4 = 42kΩ
10kΩ
QP = 30
7
Phase [deg]

900 1100
Frequency [Hz]

B. Murmann EE315A - Chapter 8 44

 Noise versus QP (Noiseless Amplifier)

Noise drops by √ 30/7

[V/rt-Hz], [Vrms] 2.8µVrms
1.2µVrms

10 1k 100M 10G
Frequency [Hz]

B. Murmann EE315A - Chapter 8 45

Noisy Amplifiers

Unfortunately the amplifiers add

significant noise at high frequency
20.6µV

2.8µV
[V/rt-Hz], [Vrms]

Noise from the passband

dominates this integral

10 1k 100M 10G
Frequency [Hz]

B. Murmann EE315A - Chapter 8 46

 Adding an RC Filter

1kΩ / 5nF RC LPF

Corner at 32kHz
0.9µVrms noise from 5nF is negligible

B. Murmann EE315A - Chapter 8 47

Frequency Response with RC Filter

Without RC
Mag [dB]

RC provides negligible attenuation.

But that’s not the point.
Let’s look at the noise …
Phase [deg]

10 1k 100M 10G
Frequency [Hz]

B. Murmann EE315A - Chapter 8 48

 Noise after RC Filter

[V/rt-Hz], [Vrms]

RC filter reduces total noise

from 20µVrms to 5µVrms
(With noiseless amplifier ~3µVrms)

10 1k 100M 10G
Frequency [Hz]

B. Murmann EE315A - Chapter 8 49

Summary

• The total integrated thermal noise of filter circuits is related to

capacitor size
– Usually a multiple of kT/C
• In filters, noise is proportional to the filter order, QP, and strongly
dependent on the implementation
• Amplifiers can contribute significantly to (if not dominate the)
overall filter noise
– Minimizing the amplifier noise contribution costs power
• Need small Rnoise, i.e. large gm (IBIAS)

B. Murmann EE315A - Chapter 8 50

 Alternative Integrator Realizations

• Thus far, we have primarily employed active RC integrators in

our filter implementations
• Next, we’ll consider a number of alternative implementations
that have found their use in practice
– MOSFET-C
– Gm-OTA-C
– Gm-C

B. Murmann EE315A - Chapter 8 51

MOSFET-C Integrator
C
• MOSFET in triode used to replace
R resistor
Vin - Vout
• Advantages
– Continuous tuning mechanism
C for integrator time constant
VC
– Potentially cheaper fabrication
process
Vin - Vout
• Disadvantages
– Large parasitics, distributed RC
W  VDS 
ID = µCox VGS − Vt − 2 VDS along channel
L  
– Bias point sensitivity
1 dID W
= = µCox (VGS − Vt − VDS ) – Weakly nonlinear
RMOS dVDS L

B. Murmann EE315A - Chapter 8 52

 Czarnul Circuit

Z. Czarnul, "Modification of Banu-Tsividis

continuous-time integrator structure," Circuits
and Systems, IEEE Trans. Ckt. Syst., pp. 714-
716, July 1986.

• Mitigates bias point

sensitivity and cancels
harmonic distortion (to
Assuming Va = 0 (without loss of generality)
first order)
W
IO1 = ID1 + ID 2 = µCox
L
(
[VA − Vt ]Vin − Vin2 + [VC − Vt ] ( −Vin ) − Vin2 ) • Remaining issues
W – Backgate effect
IO 2 = ID 3 + ID 4 = µCox
L
(
[VC − Vt ]Vin − Vin2 + [VA − Vt ] ( −Vin ) − Vin2 )
– Short channel
W
IO1 − IO 2 = 2µCox [VA − VC ]Vin effects
L

B. Murmann EE315A - Chapter 8 53

Gm-OTA-C Integrator

• Transconductor replaces resistor

– Built e.g. using a differential pair
C
• Advantages
– Main amplifier sees only
Vin Gm - Vout capacitive loads
• Can use OTA
Iin = GmVin
– Continuous tuning mechanism
for integrator time constant
Gm • E.g. via IBIAS of Gm cell
H (s ) ≅ −
sC – Potentially cheaper process
1
R↔ • Disadvantages
Gm
– Nonlinearity of Gm cell
– Extra power dissipation

B. Murmann EE315A - Chapter 8 54

 Example (1)

C.A. Laber, P.R. Gray, "A 20-MHz sixth-order BiCMOS parasitic-insensitive continuous-
time filter and second-order equalizer optimized for disk-drive read channels ," IEEE J.
Solid-State Circuits, vol. 28, no. 4, pp.462-470, Apr. 1993.

B. Murmann EE315A - Chapter 8 55

Example (2)

C.A. Laber, P.R. Gray, "A 20-MHz sixth-order

BiCMOS parasitic-insensitive continuous-time
filter and second-order equalizer optimized for
disk-drive read channels ," IEEE J. Solid-State
Circuits, vol. 28, no. 4, pp.462-470, Apr. 1993.

B. Murmann EE315A - Chapter 8 56

 Gm-C Integrator

• Advantages
– No OTA, no op-amp!
• Lower power
• Less phase shift!
– Continuous tuning mechanism
for integrator time constant
For Ro → ∞ • Via IBIAS of Gm cell
Gm • Disadvantages
H (s ) ≅
sC – Nonlinearity of Gm cell
– Sensitive to finite output
resistance (Ro)
– Sensitive to parasitics

B. Murmann EE315A - Chapter 8 57

Original Paper

H. Khorramabadi and P. R. Gray, "High-frequency CMOS

continuous-time filters," IEEE J. Solid-State Circuits, vol.19, no.6,
pp. 939-948, Dec. 1984.

B. Murmann EE315A - Chapter 8 58

 First-Order Gm-C Filters

[Deliyannis, Section 9.2]

B. Murmann EE315A - Chapter 8 59

Gm-C Biquad

B. Murmann EE315A - Chapter 8 60

 5th-Order Gm-C Ladder Filter

_
_

_
+

+
+

+
Gm Gm Gm Gm Gm Gm

_
_

_
+

+
+

+
_

_
+

+
+
Vin Gm Gm Gm Gm Gm Vout
_

_
+

+
C2 C4
_ _ _ _ _
+ + + + +
V1 I2 V3 I4 V5
C1 L2 C3 L4 C5

• Can show that capacitor network is unchanged from passive

ladder prototype

B. Murmann EE315A - Chapter 8 61

Choosing an Implementation

Discrete active
RC filters

Switched-capacitor filters

Integrated active RC filters

Integrated active Gm-C filters

Passive LC filters (discrete) Passive LC filters

(integrated)

Distributed (waveguide) filters

1kHz 1MHz 10MHz 100MHz 1GHz 10GHz

B. Murmann EE315A - Chapter 8 62

 Active RC versus Gm-C

• Active RC filters
– Superior linearity
– Dynamic range ~60-90 dB
– Usable signal BW typically up to few tens of MHz
• Gm-C
– Linearity limited
• Usually have to use degeneration, etc.
– Dynamic range ~40-70 dB
– Distortion performance limited to ~60 dB level
– Usable signal BW up to a few hundred MHz
• Both implementations typically require some form of tuning

B. Murmann EE315A - Chapter 8 63

Transconductor Implementation

• Hundreds of papers on "linearized" Gm cells

• Bottom line
– Very hard to beat a basic differential pair with (or without)
degeneration
• Let’s look at a few ideas that have been proposed over the
years…

B. Murmann EE315A - Chapter 8 64

 Linearized Gm-Stage Using Triode Device

W 
+ −≅
(V GS −VTH )V in − 21V 2in 
1
io = io − io = µc OX 
L 
R MOSFET
Vin Io + Io− Vin
+ −
2 2
Second-order nonlinear term is cancelled by a
duplicate MOSFET with small VGS control voltage:
VC
W 
i o = µc OX 
L 
(V GS1−VTH )V in − 21V in2 
W 
Io + Io−
− µc OX 
L 
(V GS 2 −VTH )V in − 21V in2 
Vin Vin
+ VC2 −
2 2 W
= µc OX
L
((V GS1−V GS 2)V in )
VC1 “ VGS1> VGS2 ” because VC1>VC2

Z. Czarnul, Y. Tsividis, “MOS tunable transconductor,” Electronics Letters, June 19, 1986, pp. 721-722.

B. Murmann EE315A - Chapter 8 65

Composite Gm-Stage to Increase Input Range

Wu & Schaumann Gm

Io+ Io−

Vin 1 1 Vin
+ X X 1X −
2 4 4 2

Vin

The net result is increased input range.

Linearity is unchanged.
Schmook/DeVeirman

Io+ Io−

Vin
1X
1
X
1
1X
Vin Bipolar implementation by Schmook (1975)
+ 4 X −
2 4 2 and later modified/improved version by
DeVeirman (1992).

B. Murmann EE315A - Chapter 8 66

 Nauta Cell

B. Nauta, “A CMOS Transconductance-C Filter Technique for Very High Frequencies”,

IEEE J. Solid-State Circuits, Feb. 1992.

B. Murmann EE315A - Chapter 8 67

Source-Follower Based Filter

S. D’Amico et al., “A 4.1mW 79dB-DR 4th order Source-Follower-Based Continuous-Time Filter for
WLAN Receivers”, IEEE J. Solid-State Circuits, Dec. 2006.

B. Murmann EE315A - Chapter 8 68

 Parameter Tuning

• Various objectives
– Tune out circuit nonidealities such as phase lead/lag
– Absorb global process variations
• Gm, R, C
– Vary filter bandwidth
– Vary other filter parameters
• E.g. “boost” in disk drive filters

B. Murmann EE315A - Chapter 8 69

Q-Tuning

V. Gopinathan et al., “Design Considerations for High-Frequency Continuous-Time

Filters and Implementation of an Anti-aliasing Filter for Digital Video,” IEEE JSSC,
Vol. 25, No. 6, Dec. 1990.

B. Murmann EE315A - Chapter 8 70

 Finite go (Ro) Tuning

Dehaene et al., “A 50-MHz Standard CMOS Pulse Equalizer

for Hard Disk Read Channels,” IEEE J. Solid-State Circuits, July1997.

B. Murmann EE315A - Chapter 8 71

Tuning of the Filter Time Constants

• Lock R (1/Gm) or
frequency (Gm/C,
1/RC) in a replica to
a reference
Built using
same RC or
• Slave replica's
Gm–C cell control voltage into
used in main main filter circuit
filter

Y.P. Tsividis, "Integrated continuous-time

filter design - an overview," IEEE Journal of
Solid-State Circuits, vol. 29, no. 3, pp.166-
176, March 1994.

B. Murmann EE315A - Chapter 8 72

 VCO Tuning Example

“Vc” controls resistance

Vin Main Filter Vout
VC
(slave) R3
−1
R4

C1
C2
R1
ref Vc _ R2 oscillator
Dummy Filter _
(master) +
+

−1 −1

s R1C1 s R2C 2 G1G 2
TF ( s ) = =
1 1 1 2
s C1C 2 + s C 2G 4 + G 2G3
1+ +
s R 4C1 s R3C1 s R 2C 2 0
osc. phase C.P.
(master) Vc Without R4
D ( s ) = s C1 C 2 + G 2 G3 ≡ 0
2
freq
detector
G 2G3
poles at ± j Banu (1985)
fREF C1C 2

B. Murmann EE315A - Chapter 8 73

VCF Tuning Approach

 Use of a low-pass filter, instead of an oscillator, as the reference for tuning

 Two phases into XOR gate is offset by 90o when phase-locked

K ωo2 fω Low-pass filter

LP( s ) = o
C.P. Vc
ω (master) XOR
s 2 + o s + ωo2
Q

1

∠LP( s )| = ∠ = −90
s = j ωo ωo2 2
− ωo2 + j + ωo
Q

V. Gopinathan et al., “Design Considerations for High-Frequency Continuous-Time Filters and Implementation
of an Anti-aliasing Filter for Digital Video,” IEEE JSSC, Vol. 25, No. 6, Dec. 1990.

B. Murmann EE315A - Chapter 8 74

 Discrete Frequency Programming/Tuning

 Switch in/out capacitors or resistors to control corner frequencies.

C3 Possible settings/frequencies:
C2 C1, C2, C3, C1+C2, C1+C3,
C2+C3, and C1+C2+C3
C1

_


+

B. Murmann EE315A - Chapter 8 75

Example (1)

H. Khorramabadi, “Baseband Filters for 6-95

CDMA Receiver Applications Featuring Digital
Automatic Frequency Tuning,” ISSCC 1996.

B. Murmann EE315A - Chapter 8 76

 Example (2)

H. Khorramabadi, “Baseband Filters for 6-95

CDMA Receiver Applications Featuring Digital
Automatic Frequency Tuning,” ISSCC 1996.

B. Murmann EE315A - Chapter 8 77

Tuning Gm Over a Wide Range

To main circuit

G. Bollati et al., “An Eighth-Order CMOS Low-Pass Filter with 30–120 MHz Tuning
Range and Programmable Boost,” IEEE J. Solid-State Circuits, July 2001.

B. Murmann EE315A - Chapter 8 78

 Reference Papers (1)
• Y. Tsividis, "Integrated continuous-time filter design—an overview," IEEE
J. Solid-State Circuits, pp. 15-30, Mar. 1994.
• Y. Tsividis, M. Banu, and J. Khoury, “Continuous-Time MOSFET-C Filters in
VLSI”, IEEE J. Solid State Circuits, Feb. 1986, pp. 15-30; and IEEE Trans.
Circuits and Systems, Feb. 1986, pp. 125-140.
• Z. Czarnul, “Modification of the Banu-Tsividis Continuous-Time Integrator
Structure,” IEEE Transactions on Circuits and Systems, Vol. CAS-33, No. 7, pp.
714-716, July 1986.
• U.-K. Moon, and B.-S. Song, “Design of a Low-Distortion 22-kHz Fifth Order
Bessel Filter,” IEEE Journal of Solid State Circuits, Vol. 28, No. 12, pp. 1254-
1264, Dec.1993.
• H. Khorramabadi and P.R. Gray, “High Frequency CMOS continuous-time
filters,” IEEE Journal of Solid-State Circuits, pp.939-948, Dec. 1984.
• K.S. Tan and P.R. Gray, “Fully integrated analog filters using bipolar FET
technology,” IEEE, J. Solid-State Circuits, pp. 814-821, December 1978.
• J. Schmook, “An input stage transconductance reduction technique for high-slew
rate operational amplifiers,” IEEE J. Solid-State Circuits, pp. 407-411, Dec.
1975.

B. Murmann EE315A - Chapter 8 79

Reference Papers (2)

• A. Durham, J. Hughes, and W. Redman- White, “Circuit Architectures for High
Linearity Monolithic Continuous-Time Filtering,” IEEE TCAS, pp. 651-657, Sept. 1992.
• C. Laber and Gray, “A 20MHz 6th Order BiCOM Parasitic Insensitive Continuous
Time Filter and Second Order Equalizer Optimized for Disk Drive Read Channels,”
IEEE J. of Solid State Circuits, Vol. 28, pp. 462-470, April 1993.
• H. Khorramabadi et al., “Baseband Filters for IS-95 CDMA Receiver Applications
Featuring Digital Automatic Frequency Tuning,” ISSCC 1996, pp. 172-173.
• R. Castello, I. Bietti and F. Svelto, "High-Frequency Analog Filters in Deep-Submicron
CMOS Technology," ISSCC Digest of Technical Papers, Feb. 1999, pp.74-75.
• Y. Tsividis, Z. Czarnul and S.C. Fang, “MOS transconductors and integrators with
high linearity,” Electronics Letters, vol. 22, pp. 245-246, Feb. 27, 1986.
• I. Mehr and D.R. Welland, “A CMOS Continuous-Time Gm-C Filter for PRML Read
Channel Applications at 150 Mb/s and Beyond”, IEEE J. of Solid-State Circuits,
Vol.32, No.4, April 1997, pp. 499-513.
• R. Alini, A. Baschirotto, and R. Castello, “Tunable BiCMOS Continuous-Time Filter for
High-Frequency Applications,” IEEE Journal of Solid State Circuits, Vol. 27, No. 12,
pp. 1905-1915, Dec. 1992.

B. Murmann EE315A - Chapter 8 80

 Reference Papers (3)
• J. Khoury, “Design of a 15-MHz CMOS Continuous-Time Filter with On-Chip Tuning”,
IEEE J. Solid-State Circuits, Dec. 1991.
• B. Nauta, “A CMOS Transconductance-C Filter Technique for Very High Frequencies”,
IEEE J. Solid-State Circuits, Feb. 1992.
• G. DeVeirman and R. Yamasaki, “Design of a bipolar 10-MHz continuous-time 0.05deg
equiripple linear phase filter,” IEEE J. Solid-State Circuits, pp. 324-331, Mar. 1992.
• M. Banu and Y. Tsividis, “An elliptical continuous-time CMOS filter with on-chip
automatic tuning,” IEEE J. Solid-State Circuits, pp. 1114-1121, Dec. 1985.
• Y. Tsividis and B. Shi, “Cancellation of distortion of any order in integrated active RC
filters,” Electron. Lett., pp. 132-134, Feb. 1985.
• B. Song, “CMOS RF circuits for data communication applications,” IEEE J. Solid-State
Circuits, pp. 310-317, Apr. 1986.
• P. Wu and R. Schaumann, “A tunable operational transconductance amplifier with
extremely high linearity over a very large input range,” Electron. Lett., pp. 1254-1255,
Jul. 1991.
• V. Gopinathan, Y. Tsidivis, K-S Tan, R. Hester, “Design Considerations for High-
Frequency Continuous-Time Filters and Implementation of an Antialiasing Filter for
Digital Video,” IEEE J. Solid State Circuits, pp. 1368-1378, Dec. 1990.

B. Murmann EE315A - Chapter 8 81

Reference Papers (4)

• K. Martin and A. Sedra, “Design of signal-flow-graph (SFG) active filters,” IEEE Trans.
Circuits Syst., pp. 185-195, 1978.
• F. Behbahani, T. Weeguan, A. Karimi-Sanjaani, A. Roithmeier, and A.A. Abidi, “A
broadband tunable CMOS channel-select filter for a low-IF wireless receiver,” IEEE J.
Solid-State Circuits, pp. 476–489, Apr. 2000.
• G. Bollati, S. Marchese, M. Demicheli, and R. Castello, "An eighth-order CMOS low-
pass filter with 30-120 MHz tuning range and programmable boost," IEEE Journal of
Solid-State Circuits, pp.1056-1066, July 2001.
• S. Pavan, Y.P. Tsividis, and K. Nagaraj, "Widely programmable high-frequency
continuous-time filters in digital CMOS technology," IEEE Journal of Solid-State
Circuits, vol.35, no.4, pp.503-511, April 2000.
• W. Dehaene, M.S.J. Steyaert, and W. Sansen, "A 50-MHz standard CMOS pulse
equalizer for hard disk read channels ," IEEE Journal of Solid-State Circuits, vol.32,
no.7, pp. 977-988, July 1997.
• D. Chamla, A. Cathelin, S. Dedieu, and A. Kaiser, "Digital Tuning of Gm-C Baseband
Filters in Configurable Radio Receivers," Proc. ESSCIRC, pp.340-343, Sept. 2006.
• S. D’Amico et al., “A 4.1mW 79dB-DR 4th order Source-Follower-Based Continuous-
Time Filter for WLAN Receivers”, IEEE J. Solid-State Circuits, Dec. 2006.

B. Murmann EE315A - Chapter 8 82

 Switched Capacitor Filters

Boris Murmann
Stanford University
[email protected]
Copyright © 2014 by Boris Murmann

B. Murmann EE315A - Chapter 9 1

Outline

• History
• Basic concepts
• SC integrators
• SC biquads
• Nonidealities

B. Murmann EE315A - Chapter 9 2

 History: 1873
• Maxwell recognized that a switched capacitor behaves like a
resistor in terms of average current
– James C. Maxwell, A treatise on electricity and magnetism. Oxford:
Clarendon Press, 1873, vol. 2, pp. 374-375
• http://www.archive.org/stream/electricandmag02maxwrich#page/n405/mode/2up

B. Murmann EE315A - Chapter 9 3

History: 1968

W. Kuntz, "A new sample-and-hold device and its

application to the realization of digital filters," Proc.
IEEE , vol.56, no.11, pp. 2092- 2093, Nov. 1968.

B. Murmann EE315A - Chapter 9 4

 History: 1972

D.L. Fried, "Analog sample-data filters," IEEE J. Solid-

State Circuits, vol.7, no.4, pp. 302- 304, Aug. 1972.

B. Murmann EE315A - Chapter 9 5

History: 1977

B. J. Hosticka, R. W. Brodersen, and P. R.

Gray, “MOS sampled data recursive filters
using switched capacitor integrators,” IEEE
Journal of Solid-State Circuits, vol. 12, no. 6,
pp. 600-608, Dec. 1977.

B. Murmann EE315A - Chapter 9 6

 Emulating a Resistor

V1 − V2
i=
R

∆q = C (V1 − V2 )

∆q ∆q
iavg = = = fs ⋅ C (V1 − V2 )
∆t Ts

1
Ravg = (Note: current flows in “bursts”)
fs ⋅ C

B. Murmann EE315A - Chapter 9 7

Switched Capacitor Circuits

SC low-pass filter (passive)

SC integrator

SC gain stage

(Actual implementations are differential)

B. Murmann EE315A - Chapter 9 8

 Discussion
• One of the most significant inventions in the history of ICs
• Predominant approach for precision signal processing in CMOS
– CMOS technology provides good switches & capacitors
• SC circuits have many advantages over RC implementations
– Transfer function set by ratio of capacitors
• RC product suffers from large process variations
– Corner frequencies (of filters) can be adjusted by changing
clock frequency
– Can make large time constants without using large resistors
• RC lowpass, 100Hz: R=16MΩ, C=100pF
• SC lowpass, 100Hz: f=10kHz, C1=6.25pF, C2=100pF
• Reference
– R. Gregorian et al., "Switched-Capacitor Circuit Design,"
Proceedings of the IEEE, Vol. 71, No. 8, August 1983.

B. Murmann EE315A - Chapter 9 9

“Parasitic Sensitive” Configurations

1
Ravg =
fs ⋅ C

1
Ravg =
fs ⋅ C

• Ravg is affected by parasitic capacitances (e.g. wire capacitance,

junction capacitance, etc.)

B. Murmann EE315A - Chapter 9 10

 Inverting Configuration

φ1 C φ2
V1 + - V2

During φ1: During φ2:

φ2 φ1
q1 = CV1 q2 = −CV2

∆q = −CV2 − CV1 = C ( −V1 − V2 ) iavg = fsC ( −V1 − V2 )

• Compared to the circuit on slide 7, the effect of V1 is “inverted”

because C is flipped upside down during φ2 (+ terminal at GND)
– Provides signal inversion

B. Murmann EE315A - Chapter 9 11

RC and SC Filter Transient Analysis (1)

3.1831M
R0

vrc

C0
1p

clock_gen p1! p2!

s1 s4
Iclk vsc
p1!
ideal ideal
p2!
V0 C1 C2
314.16f 1p
vo:0
va:1
freq:3K

fs = 1MHz, fc = 50kHz, fin=3kHz

B. Murmann EE315A - Chapter 9 12

 RC and SC Filter Transient Analysis (2)

• SC output is a “staircase
approximation” of the RC
filtered signal
RC
– Slightly delayed

SC

B. Murmann EE315A - Chapter 9 13

Waveform Details

p2 p1 p2 p1 p2

Vin

VC1 VC1 New Output

tracks held output held
input value

B. Murmann EE315A - Chapter 9 14

Waveforms with Larger Ron (1Ω
100kΩ)

p1 p2 p1 p2 p1

B. Murmann EE315A - Chapter 9 15

Frequency Response ?
• Looking at the transient waveforms is fun, but what can we say
about the frequency response of the SC circuit?
• Looks like a tough question since the output signal looks
“complicated”
– Not just a sine wave with shifted phase and altered
magnitude, as in the RC case
– Instead we have a staircase waveform with “rounded” edges
(due to finite switch resistance)
• Part of the problem is that SC circuits are time variant
– The configuration is periodically switched between two
states
• Time variant circuits, in principle, introduce new frequencies
– Think about spectral components caused by the voltage
“steps” at the output

B. Murmann EE315A - Chapter 9 16

 First Pass Analysis

t1 t2

• Let’s try to find the relationship between Vin(t1) and Vout(t2)

– This means we are looking at the relationship between
“discrete time samples” of the voltages and ignore the fact
that the output is really a continuous time signal

B. Murmann EE315A - Chapter 9 17

Circuit Analysis (1)

• During φ1, VC1 tracks Vin

• If we assume that the tracking is reasonably fast, such that there

is only a negligible difference between the input and VC1, we can
write
VC1(t1 ) = Vin (t1 )

QC1(t1 ) = C1Vin (t1 )

B. Murmann EE315A - Chapter 9 18

 Circuit Analysis (2)

• During φ2, the output voltage and VC1 are equalized

t1

t0 t2

• Again, assuming that the circuit settles precisely, we can write

VC1(t 2 ) = Vout (t2 ) QC1(t2 ) + QC 2 (t2 ) = (C1 + C2 )Vout (t2 )

• The sum of the charges must be equal to the charges that were
previously on C1 and C2, before the φ2 switch turned on, i.e.

QC1( t2 ) + QC 2 ( t 2 ) = QC1( t1 ) + QC 2 ( t0 )

B. Murmann EE315A - Chapter 9 19

Circuit Analysis (3)

QC1(t 2 ) + QC 2 (t 2 ) = QC1(t1 ) + QC 2(t0 )

(C1 + C2 )Vout (t2 ) = C1Vin (t1 ) + C2Vout (t0 )

C1 C2
Vout (t 2 ) = Vin (t1 ) + Vout (t0 )
C1 + C2 C1 + C2

C1  T  C2
Vout (t 2 ) = Vin  t 2 − s  + V (t − T )
C1 + C2  2  C1 + C2 out 2 s

• Laplace Transform
V(t ) → V( s )

V(t − ∆t ) → V( s )e − s ∆t

B. Murmann EE315A - Chapter 9 20

 Circuit Analysis (4)

Ts
C1 −s C2
Vout ( s ) = Vin ( s ) e 2 + Vout ( s ) e − sTs
C1 + C2 C1 + C2

Ts
 C2  C1 −s
Vout ( s )  1 − e −sTs  = Vin ( s ) e 2
 C1 + C2  C1 + C2
T
−s s
Vout ( s ) e 2
H( s ) = =
Vin ( s ) 1 + C2 1 − e − sTs
C1
( )
• Let’s plot this frequency response and compare to the simple
RC filter

B. Murmann EE315A - Chapter 9 21

Frequency Response
Magnitude [dB]

0
-10 SC
-20 RC

-30 3 4 5 6 7
10 10 10 10 10
f [Hz] Close only for f << fs
200
Phase [deg]

-200 3 4 5 6 7
10 10 10 10 10
f [Hz]

B. Murmann EE315A - Chapter 9 22

 First Order Approximation
T
−s s
Vout ( s ) e 2
H( s ) = =
Vin ( s ) 1 + C2 1 − e − sTs
C1
( )
T
− jω s
Vout ( j ω ) e 2 f
H( j ω ) = = ωTs = 2π
Vin ( j ω ) 1 + C2 1 − e − j ωTs fs
C1
( )
e jx = cos( x ) + j sin( x ) ≅ 1 + jx (for small x)

Ts f
1− jω 1− j π
Vout ( j ω ) 2 fs
≅ =
Vin ( j ω ) 1 + C2 j ωT 1+ jω
1
C
C1 s
fs ⋅ C1 2
1 23
" Ravg "

B. Murmann EE315A - Chapter 9 23

fs = 5MHz (Previously 1MHz)

Magnitude [dB]

-20 SC
RC
-40 3 4 5 6 7
10 10 10 10 10
f [Hz] Better!
200
Phase [deg]

-200 3 4 5 6 7
10 10 10 10 10
f [Hz]

B. Murmann EE315A - Chapter 9 24

 Linear Frequency Axis

Magnitude [dB] 0

-20
SC
RC
-40
2 4 6 8 10 The transfer
f [Hz] x 10
6
function is periodic
200 with period fs
Phase [deg]

Why?
0

-200
0 2 4 6 8 10
f [Hz] x 10
6

B. Murmann EE315A - Chapter 9 25

Aliasing (1)

1
fs = = 1000kHz
Amplitude

Ts

fin = 101kHz

Time

 f 
v in ( t ) = cos ( 2π ⋅ fin ⋅ t ) v in ( n ) = cos  2π ⋅ in ⋅ n 
 fs 

n  101 
t → n ⋅ Ts = = cos  2π ⋅ ⋅n
fs  1000 

B. Murmann EE315A - Chapter 9 26

 Aliasing (2)

1
fs = = 1000kHz
Amplitude

Ts

fin = 899kHz

Time

 899    899    101 

v in ( n ) = cos  2π ⋅ ⋅ n  = cos  2π ⋅  − 1 ⋅ n  = cos  2π ⋅ ⋅n
 1000   1000    1000 

B. Murmann EE315A - Chapter 9 27

Aliasing (3)

1
fs = = 1000kHz
Amplitude

Ts

fin = 1101kHz

Time

 1101    1101    101 

v in ( n ) = cos  2π ⋅ ⋅ n  = cos  2π ⋅  − 1 ⋅ n  = cos  2π ⋅ ⋅n
 1000   1000    1000 

• Bottom line
– The frequencies fin and N·fs ± fin (N integer), are
indistinguishable when the signal is represented using
discrete times samples at a rate of fs

B. Murmann EE315A - Chapter 9 28

 Spectrum of Continuous Time Output
• The previous analysis allows us to reason about the output
values at discrete time instances (falling edge of φ2)
• What can we say about the spectrum of the continuous time
waveform?
• Let’s first simplify this question by assuming a very “sharp”
staircase waveform, i.e. assume Ron
0

B. Murmann EE315A - Chapter 9 29

Zero-Order Hold Signal

• A basic way to think about this is to

assume that the discrete time values
are held for one cycle to generate a
continuous time staircase
Amplitude

– For simplicity, we’ll ignore details relating

to the “phase” position of the hold pulse
relative to the discrete time sample and
focus on the magnitude response

• What will the spectrum of the

continuous time signal look like?
• We'll analyze this in two steps
– First look at infinitely narrow
pulses in continuous time

B. Murmann EE315A - Chapter 9 30

 Dirac Pulses

• Vdirac(t) is zero between pulses

– Note that the discrete time
sequence is undefined at
Amplitude

these times
∞
Vdirac ( t ) = Vin ( t ) ⋅ ∑ δ( t − nTs )
n =−∞

• Multiplication in time means

convolution in frequency
– Resulting spectrum

1 ∞  n 
Vdirac ( f ) = ∑ Vin  f − T 
Ts n =−∞  s 

B. Murmann EE315A - Chapter 9 31

Spectrum

• Spectrum of Dirac Signal contains replicas of Vin(f) at integer

multiples of the sampling frequency

B. Murmann EE315A - Chapter 9 32

 Effect of Finite Hold Pulse

• Consider the general case with a

rectangular pulse 0 < Tp ≤ Ts
• The time domain signal follows from
convolving the Dirac sequence with a
Amplitude

rectangular unit pulse

• The spectrum follows from multiplication
with the Fourier transform of the pulse

sin( πfTp ) − j πfTp

H p ( f ) = Tp ⋅e
πfTp
Tp sin( πfTp ) − j πfTp
∞  n 
VZOH ( f ) = ⋅e ∑ Vin  f − T 
Ts πfTp n =−∞  s 

Amplitude Envelope

B. Murmann EE315A - Chapter 9 33

“Sinc” Envelope with Tp=Ts

0.9

0.8

0.7
Magnitude [dB]

0.6
Tp sin( πfTp )
0.5
Ts πfTp
0.4

0.3

0.2

0.1

0
1 2 3 4 5 6 7 8 9 10
f [Hz] x 10
6

B. Murmann EE315A - Chapter 9 34

 Overall Filter Magnitude Response

Discrete Time Output ZOH Output (Continuous Time)

0
0

-10
-5
Magnitude [dB]

Magnitude [dB]
-20

-10 -30

-40
-15
-50

-20
2 4 6 8 10 -60
2 4 6 8 10
f [Hz] x 10
6
f [Hz] x 10
6

B. Murmann EE315A - Chapter 9 35

Logarithmic Frequency Axis

Note: These magnitude plots must be looked at
with a “grain of salt” (since the system we’re
looking at is not LTI). They are not really
ZOH Output (Continuous Time) “transfer functions” in the traditional sense.

Example 1: When you apply an input tone at

0
2kHz, you get the same frequency at the output
(scaled by the shown magnitude), PLUS other
-10 tones around multiples of fs (due to the ZOH
operation). These additional tones will have
Magnitude [dB]

amplitudes scaled by the sinc envelope (as

-20
shown in the plot to the left).

-30 Example 2: When you apply an input tone at

1010kHz, the signal aliases down to 10kHz
upon sampling. The “main” tone at the output is
-40
therefore at 10kHz, scaled by the magnitude at
that frequency. Of course, you will also get the
-50 additional tones around multiples of fs (as per
the previous examples. Note that one of these
additional tones will be at 1010kHz; i.e. the
-60 3 4 5 6 7 frequency you actually applied at the input.
10 10 10 10 10
f [Hz]
We will usually not apply signals at high
frequencies. In fact, we will try to remove such
frequencies prior to sampling using an anti-alias
filter4

B. Murmann EE315A - Chapter 9 36

 Periodic AC Analysis

• Can we simulate this frequency response using a circuit

simulator?
• Spice
– .op (operating point)
.ac (ac analysis)
– Works only for time invariant circuits
• SpectreRF
– PSS (periodic operating point)
PAC (periodic ac analysis)
– Works for periodically varying circuits
• Reference
– http://www.designers-guide.org/Analysis/sc-filters.pdf

B. Murmann EE315A - Chapter 9 37

Setup for PAC Analysis (1)

3.1831M
R0

vrc

C0
1p
R2

R3

clock_gen Is1
s1 p1! s4 p2!
1

Iclk vsc vsc_samp

p1! Pin Pout
ideal ideal C1
p2! 1p ideal sampler
C2 Nin Nout
314.16f

Is2
vi vi_samp
Pin Pout

ideal sampler
V0 Nin Nout

B. Murmann EE315A - Chapter 9 38

 Setup for PAC Analysis (2)

B. Murmann EE315A - Chapter 9 39

PAC Magnitude Response

vrc

vsc

B. Murmann EE315A - Chapter 9 40

 R3 Changed to 300kΩ (from 1Ω)

vrc

Droop

vsc

B. Murmann EE315A - Chapter 9 41

Transient Waveforms

vsc

vsc_samp

B. Murmann EE315A - Chapter 9 42

 Response After Output Sampler

vsc_samp

B. Murmann EE315A - Chapter 9 43

Sampled Input (“Dummy” Sinc)

vi_samp

B. Murmann EE315A - Chapter 9 44

 Sinc Corrected Response

vsc_samp/vi_samp

• Matches Matlab result exactly

– But, of course, in SpectreRF we can now study nonidealities at the
circuit level&
B. Murmann EE315A - Chapter 9 45

Anatomy of a Complete SC Filter

• All signals in this processing chain are continuous in time (as all
physical signals)
• However, the core of the filter ( “sampled data filter” block) can typically
be modeled as a “discrete time” system
z-transform
– The core takes voltage samples at the input and produces samples
at the output
– The internal transients that generate these samples are irrelevant,
as long as they have settled at the time the sample is taken

B. Murmann EE315A - Chapter 9 46

 Signal Nomenclature

time
Continuous Time Signal

T/H Signal
("Sampled Data Signal")

Clock

Discrete Time Signal

Abstraction

B. Murmann EE315A - Chapter 9 47

z-Domain Representation of Simple SC Filter

T
−s s
Vout ( s ) e 2
H( s ) = = z = esTs
Vin ( s ) 1 + C2 1 − e −sTs
C1
( )
1
−
V (z) z 2
H( z ) = out =
Vin ( z ) 1 + C2 1 − z −1
C1
( )

B. Murmann EE315A - Chapter 9 48

 Noninverting Integrator Analysis (1)

n-1/2 n+1/2 n+3/2

φ2

φ1

t/Ts n-1 n n+1

Sample Output held at end value

Vi from previous half cycle
• Output can be sampled during
either φ1 or φ2 Charge
redistribution
• Sampling at φ1 means that there (output ready at
end of this phase)
will be an additional ½ clock cycle
delay (z-1/2)

B. Murmann EE315A - Chapter 9 49

Noninverting Integrator Analysis (2)

n-1/2 n+1/2 n+3/2

t/Ts n-1 n n+1

t/Ts Qs QI
n-1 Cs·Vi(n-1) CI·Vo(n-1)=CI·Vo(n-3/2)
n-1/2 0 CI·Vo(n-1/2) = CI·Vo(n-3/2) + Cs·Vi(n-1) Vo2
n Cs·Vi(n) CI·Vo(n) = CI·Vo(n-1) + Cs·Vi(n-1) Vo1
n+1/2 & &

B. Murmann EE315A - Chapter 9 50

 Noninverting Integrator Analysis (3)

 1  3
CIVo 2  n −  = CIVo 2  n −  + CsVi ( n − 1)
 2  2
1 3
− −
CIVo 2 ( z )z 2 =z 2 C V ( z ) + z −1C V ( z )
I o2 s i

1
−
V ( z ) Cs z 2 “LDI Integrator”
H2 ( z ) = o 2 = (Lossless Digital Integrator)
Vi ( z ) CI 1 − z −1

Vo1( z ) Cs z −1 “DDI Integrator”

H1( z ) = =
Vi ( z ) CI 1 − z −1 (Direct Digital Integrator)

• What is the frequency response of this integrator?

– First look at H2(z)

B. Murmann EE315A - Chapter 9 51

Frequency Response (H2)

−1
C z 2 Cs 1
H2 ( ω ) = H2 ( z ) z = e j ωTs = s =
CI 1 − z −1 CI 1
−
1
z = e j ωTs z 2 −z 2
z = e j ωTs = cos ( ω Ts ) + j sin ( ω Ts )

Cs 1
=
CI  ωT   ω Ts   ω Ts   ω Ts 
cos  s  + j sin  2  − cos  2  + j sin  2 
 2       
Cs 1 ω Ts C 1 ω Ts f
= ≅ s for = π << 1
CI j ω Ts  ω T  CI j ω Ts 2 fs
14 24 3 2 sin  s 
Ideal
14  2 3
4244
Magnitude error

• Behaves like an RC integrator for low frequencies (f << fs)

– R replaced by 1/(fsCs), as before

B. Murmann EE315A - Chapter 9 52

 Frequency Response (H1)

Cs z −1
H1( ω ) = H1( z ) z = e j ωTs =
CI 1 − z −1
z = e j ω Ts

1
− ω Ts
C z 2 Cs 1 ωTs −j
= s = e 2
CI 1 1 CI j ωTs  ωT  1
424
3
z 2 −z
−
2 14 24 3 2 sin  s  Phase error
z = e j ωTs Ideal
14  2 3
4244
Magnitude error

• Magnitude error as before, but now there’s also a phase error

– Bad news if we are looking to build a high Q filter
• Numerical example for f=fs/32
– Magnitude error = 0.16%
may not be a problem
– Phase error = -5.6 degrees
big problem!

B. Murmann EE315A - Chapter 9 53

Inverting Integrator

n-1/2 n+1/2 n+3/2

φ2

φ1

t/Ts n-1 n n+1

Input induces Next cycle

charge change
Cs 1 (output ready at the
H1( z ) = −
CI 1 − z −1 end of this phase)

1 Reset Cs
−
2 (output held
Cs z at previous value)
H2 ( z ) = − “LDI”
CI 1 − z −1

B. Murmann EE315A - Chapter 9 54

 General Building Block
Ci phi1

phi1 phi2

C1 Vo1
phi1c
Vi1

phi2c
phi2 phi1 Vo2

phi2

phi1 phi1

C2
Vi2

phi2 phi2

C3
Vi3

C1 z −1 C 1 C
Vo1 ( z ) = 1
Vi 1 ( z ) − 2 1
Vi 2 ( z ) − 3 Vi 3 ( z )
Ci 1 − z − Ci 1 − z − Ci
−1 −1
C z 2 C2 z 2 C
Vo 2 ( z ) = 1 1
Vi1 ( z ) − 1
Vi 2 ( z ) − 3 Vi 3 ( z )
Ci 1 − z − Ci 1 − z − Ci

B. Murmann EE315A - Chapter 9 55

Let’s Build a Biquad

RLC Prototype
1
−
1 z 2
→
s 1 − z −1

• Key objective
– Avoid integrator phase errors
• Conceptually two possible solutions
– Try to use only LDI integrators
– Combine delaying (DDI) and non-delaying integrator to
achieve LDI behavior

B. Murmann EE315A - Chapter 9 56

 Realization

p1! p1!

Cf
p1! p1!

p2!

p2!
Cr1
p2!

p2!
clock_gen
Iclk
p1!

p2!

Ci1

Ci2
vx2

vo2
A1 A2
p1! p1! p1! p2! Is1
I31
vx1 gain_ideal vo1 gain_ideal vo_samp
Pin Pout
G:-1e+06 G:-1e+06
Cs1

Cs2
p2!

p2!

p2!

p1!
ideal sampler
Nin Nout

1 z-1
Is2
vi vi_samp
Pin Pout
V0
ideal sampler
Nin Nout

B. Murmann EE315A - Chapter 9 57

Component Values

Target: ω P := 2 ⋅π ⋅ 10kHz QP := 5

Pick: C := 10pF Rx := 1MΩ fs := 1MHz

1 1
LC component values: R := = 318.31 ⋅kΩ L := = 25.33 H
ω P ⋅ QP ⋅ C 2
ω P ⋅C
SC component values:
1
Ci2 := C = 10 ⋅ pF Cs1 := = 1 ⋅ pF
f s ⋅ Rx

L R
Ci1 := = 25.33 ⋅ pF Cr1 := = 0.318 ⋅ pF
2 2
Rx f s ⋅ Rx

1 1
Cf := = 1 ⋅pF Cs2 := = 1 ⋅ pF
f s ⋅ Rx f s ⋅ Rx

B. Murmann EE315A - Chapter 9 58

 PAC Output

B. Murmann EE315A - Chapter 9 59

Linear Frequency Axis

B. Murmann EE315A - Chapter 9 60

 High Frequency Behavior

• Our RLC prototype filter has two zeros at infinity

– Where did these go in the SC realization?
• It would be great to have some zeros at high frequencies
– E.g. fs/2 would be a great place!
– This can help improve the stopband attenuation, especially
when we’re trying to minimize fs
• Need to think about how exactly frequencies are mapped from
the continuous time prototype to the switched capacitor
realization

B. Murmann EE315A - Chapter 9 61

CT – SC Integrator Comparison

• RC and SC (LDI) integrator transfer functions

−1
1 1 C z 2 C 1
HRC ( s ) = = HSC ( z ) = s 1
= s
sRC 2πjfRC RC Ci 1 − z − Ci 2 j sin ( πfSCTs )

• In our LDI-based design, we set the RC time constant equal to the

approximate SC time constant, i.e.
Ci
RC =
fsCs

• Setting HRC(fRC) = HSC(fSC) therefore gives

fs  f 
fRC = sin  π SC 
π  fs 

B. Murmann EE315A - Chapter 9 62

 Frequency Warping (LDI)

fs  f 
1 fRC = sin  π SC 
π  fs 
0.9

0.8

0.7 • Frequency mapping is

0.6
accurate only for fRC<< fs
f SC/f s

0.5 • RC frequencies up to fs/π

0.4 map to “physical SC”
0.3 frequencies
0.2 • Mapping is symmetric
0.1 about fs/2 (aliasing)
0
0 0.1 0.2 0.3 0.4
f RC/f s

B. Murmann EE315A - Chapter 9 63

A Closer Look at Integration Methods

• LDI integrators apply a

Signal Amplitude

“midpoint integration
• A much more accurate way to
integrate is using a trapezoidal
(“bilinear”) integration rule

v o ( nTs ) = v o ( nTs − Ts )
Signal Amplitude

Ts
+ v i ( nTs ) + v i ( nTs − Ts ) 
2 

• Many others exist, e.g. Euler,

Runge Kutta, Gear, K

B. Murmann EE315A - Chapter 9 64

 Bilinear Integrator

Ts
v o ( nTs ) = v o ( nTs − Ts ) + v i ( nTs ) + v i ( nTs − Ts ) 
2 

1 − z −1  Vo ( z ) = Ts 1 + z −1  Vi ( z )
  2  

Vo ( z ) Ts 1 + z −1
HBL ( z ) = =
Vi ( z ) 2 1 − z −1

• Bilinear transform
2 1 − z −1
s→
Ts 1 + z −1

B. Murmann EE315A - Chapter 9 65

Frequency Warping (Bilinear)

1
= HBL ( z )
0.5 s s = 2πjfRC z = e2 πjfBLTs

0.4 fs  f 
⇒ fRC = tan  π BL 
π  fs 
0.3
f BL/f s

• No frequencies are lost

0.2 – E.g. zeros at infinity
will be mapped to fs/2
0.1 • Can show that bilinear
transform maps jω axis
0 in s plane onto unit circle
0 1 2 3 4 5
f RC/f s
in z-plane

B. Murmann EE315A - Chapter 9 66

 Possible Design Procedure
• Pre-warp “important” frequencies, e.g. passband edge and/or
stopband edge using
fs  f 
fRC = tan  π BL 
π  fs 
• Note that pre-warping is important mostly for filters that try to
aggressively push toward minimum fs
• Determine continuous time prototype filter function H(s) using
pre-warped frequency specifications
• Substitute 2 1 − z −1
s→
Ts 1 + z −1

• Implement z- transfer function using a known (and well-

understood) Biquad realization, ladder, etc.

B. Murmann EE315A - Chapter 9 67

Alternative
• Let Matlab do all of thisK
• Design filter in z-domain, e.g.

[B,A] = BUTTER(N, fc_fs)

• Matlab will then automatically

• Pre-warp the frequency specifications
• Carry out a bilinear transform (using function (“bilinear”)
• Give you the z-transfer function of the filter

B. Murmann EE315A - Chapter 9 68

 Martin-Sedra Biquad

K. Martin and A. S. Sedra, “Strays-insensitive switched-capacitor filters based on the

bilinear z transform,” Electron. Lett., vol. 19, pp. 365-6, June 1979.

B. Murmann EE315A - Chapter 9 69

“Low-Q” Biquad

R. Gregorian, K.W. Martin, and

G.C. Temes, “Switched-Capacitor
Circuit Design,” Proceedings of
the IEEE, vol. 71, no. 8, pp. 941-
966, Aug. 1983.

B. Murmann EE315A - Chapter 9 70

 “Hi-Q” Biquad

R. Gregorian, K.W. Martin, and

G.C. Temes, “Switched-Capacitor
Circuit Design,” Proceedings of
the IEEE, vol. 71, no. 8, pp. 941-
966, Aug. 1983.

B. Murmann EE315A - Chapter 9 71

Lowpass Example Using Bilinear Transform

• Specs: fPBL=10kHz, QP=5, fs=1MHz

• Pre-warping (not all that significant in this exampleK)

fs  f  1MHz  10kHz 
fPRLC = tan  π P  = tan  π  = 10.002MHz
π  fs  π  1MHz 

1 2 1 − z −1
H( s ) = s→
s s2 Ts 1 + z −1
1+ + 2
ωPRLCQP ωPRLC

• Compute H(z)
• Implement using Biquad
• Simulate, plot frequency responseK

B. Murmann EE315A - Chapter 9 72

 Frequency Response

-20
Magnitude [dB]

-40

-60

Notch at fs/2
-80

-100 2 3 4 5 6
10 10 10 10 10
f [Hz]

B. Murmann EE315A - Chapter 9 73

Linear Frequency Axis

-20
Magnitude [dB]

-40

-60

-80

-100
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
f [Hz] x 10
6

B. Murmann EE315A - Chapter 9 74

 LDI versus Bilinear Transform
• LDI transform
– Realized by “standard” SC integrators
– High frequency zeros are lost
– Simple filter synthesis
• Replace RC integrators with SC integrators, ensuring proper delays
around integrator loops (z-1/2 per integrator)
• Bilinear transform
– Does not lose high frequency zeros
– Biquad-based synthesis
• Direct coefficient comparison with known realizations
– Ladders
• See e.g. R.B. Datar and A.S. Sedra, “Exact design of strays-
insensitive switched capacitor high-pass ladder filters,” Electronics
Letters, vol. 19, no. 29, pp. 1010-1012, Nov. 1983.

B. Murmann EE315A - Chapter 9 75

Nonidealities in Switched Capacitor Filters

• Finite amplifier gain

• Finite amplifier bandwidth and slew rate
• Thermal noise
– From SC resistor emulation
– From amplifiers
• Parasitic capacitance
– Use parasitic insensitive configurations
• Amplifier offset voltage and flicker noise
– Often not an issue
– If problematic use CDS
• Switch charge injection and clock feedthrough
– Use “bottom plate sampling”
• See EE315B

B. Murmann EE315A - Chapter 9 76

 SC Filter Nonidealities

Sufficient to understand Must look at errors in the

errors in the discrete time continuous time domain
signal samples

Much more complicated; signals

Focus mostly on this are sums of reconstruction pulses,
aspect in the following continuous time feedthrough
discussion signals, etc.

B. Murmann EE315A - Chapter 9 77

Finite Gain (1)

n-1 n n+1

2
a0
1

t/Ts n-3/2 n-1/2 n+1/2

t/Ts Qs QI
n-1/2 Cs·Vi(n-1/2) CI·Vo2(n-1)·[1+1/a0]
n Cs·Vo2(n)/a0 CI·Vo2(n)·[1+1/a0]
= CI·Vo2(n-1)·[1+1/a0] + Cs·Vi(n-1/2) - Cs·Vo2(n)/a0

B. Murmann EE315A - Chapter 9 78

 Finite Gain (2)
1
  1 1 Cs 
Vo 2 ( z )CI  1 +  1 − z −1  +
−
 = Vi ( z )Cs z 2
  a C 
  a0  0 I 

1
−
Vo 2 ( z ) Cs z 2 C 1
= ≅ s
Vi ( z ) CI  1 1 Cs CI  1 1 Cs
1 +  1 − z  +
−1
1 +  sTs +
 a0  a0 CI  a0  a0 CI

Cs 1
≅
CITs  1 1 Cs
1 +  s +
 a0  a0 CITs

Compare to active RC 1 Bottom line: approximately

A(s ) = −ω0
integrator with finite a0:  1 ω same gain requirements as
s 1 +  + 0 active RC
 a0  a0

B. Murmann EE315A - Chapter 9 79

Finite Bandwidth (1)

• First order result

– SC filters have much
smaller amplifier
bandwidth requirements
than active RC
counterparts

K. Martin and A. Sedra, "Effects of the op amp

finite gain and bandwidth on the performance of
switched-capacitor filters," IEEE Trans. Circuits and
Systems, vol. 28, no. 8, pp. 822-829, Aug. 1981.

B. Murmann EE315A - Chapter 9 80

 Finite Bandwidth (2)

• Unfortunately, this first order result relies on perfectly linear

behavior in the amplifiers
• Slewing changes the situation significantly
• As a result, it turns out that the bandwidth must be overdesigned
significantly to meet typical linearity requirements
• Everything considered, it turns out that the bandwidth
requirements in SC filters are comparable to those in active RC
realizations

B. Murmann EE315A - Chapter 9 81

Noise in A Passive SC Lowpass Filter

φ1

φ2

௢௨௧   ିଵ/ଶ

 =

=
௜௡ () 1 + ଶ 1 −  ିଵ
ଵ

• During φ1, the circuit simply samples kT/C1 on C1

– And this noise has a white discrete time spectrum, per our
previous analysis

B. Murmann EE315A - Chapter 9 82

 Equivalent Model for φ1 Noise

White input PSD Colored output PSD

௜௡,ଵ
ଶ
2  ௢௨௧,ଵ
ଶ ௜௡,ଵ
ଶ
⋅
௝ఠ்ೞ ଶ
= =
Δ ௦ ଵ Δ Δ

௜௡,ଵ
ଶ
= ௢௨௧,ଵ
ଶ
ଵ
=?
Noiseless
H(z)

• The output noise PSD follows from passing the input noise
through the (known) transfer function (magnitude squared)
• What is the variance of the output samples?
– Can be calculated by integrating output PSD from 0Kfs/2

B. Murmann EE315A - Chapter 9 83

φ1 Noise Integral
ଵ/ଶ
ଶ
1 1 1
=
1+ 1− 2 1 + 2
Useful integral: ି௝ଶగ௙
଴

ଶ
௙ೞ /ଶ ௝గ௙
2  2  ௦
ି ௙
1
௢௨௧,ଵ
ೞ
ଶ
௦ ଵ 2 1 + 2 ଶ
= ⋅ = ⋅
௦ ଵ ଶ ௝ଶగ௙
ଵ
ି ௙
ଵ
଴ 1+ 1− ೞ

 1 1  ଶ
௢௨௧,ଵ
ଶ
ଵ 1 + 2 ଶ 2 ଶ  + ଵ
= = Slightly less than ½ kT/C2
ଵ ଶ 2

B. Murmann EE315A - Chapter 9 84

 Model for φ2 Noise Analysis

4kTR∆f 4kTR∆f
R R Vout
ଵ ଶ
Vout
ଶ
= 
C1 C2 C1 C2
ଶ
ଵ + ଶ

• We can easily compute the noise charge on C2 that is

introduced during φ2
• Since this charge is introduced in every cycle, it can be referred
to the input, just like the φ1 noise
• To find the proper conversion factor, let’s remind ourselves how
charge is transferred between the phases

B. Murmann EE315A - Chapter 9 85

Charge Transfer

ଵ
௢௨௧ = ௜௡
Vin Vout
ଵ + ଶ
ଵ ଶ
C1 C1 C2
= ௜௡
ଶ
ଵ + ଶ

ଵ + ଶ
௜௡ = ଶ
ଵ ଶ

This is the input voltage needed to induce charge q2 on the

plates of C2 during φ2

B. Murmann EE315A - Chapter 9 86

 Putting it All Together

ଵ + ଶ ଵ ଶ ଵ + ଶ  ଵ + ଶ
ଶ ଶ
௜௡,ଶ
ଶ
= ଶ
=  =
ଶ
ଵ ଶ ଵ + ଶ ଵ ଶ ଵ ଶ

 ଵ + ଶ 1 1  ଶ + ଵ
௢௨௧,ଶ
ଶ
ଵ ଶ 1 + 2 ଶ 2 ଶ  + ଵ
= = Slightly more than ½ kT/C2

ଵ ଶ 2

1  ଶ 1  ଵ + ଶ 
௢௨௧,ଵ
ଶ
+ ௢௨௧,ଶ
ଶ
2 ଶ  + ଵ 2 ଶ  + ଵ
= + =
ଶ
ଶ 2 ଶ 2

• We could have guessed this from the equipartition theoremK

B. Murmann EE315A - Chapter 9 87

Simulation Circuit
300K

300K
R1

R2

C1 = 68.83 fF
C2 = 1 pF
fs = 1 MHz
f-3dB = 10 kHz

B. Murmann EE315A - Chapter 9 88

 Simulation Result

Noise PSD Noise Integral

φ2 noise

φ1 noise

B. Murmann EE315A - Chapter 9 89

Experiment: Reset Output During φ1

300K

300K
R1

R2

ideal

sres p1!

noiseless

• Expecting to see
– White noise spectrum
– Total integrated noise equal to

2 2
kT  C1  C1C2  1 
v 2
out =   + kT   = 21.7µVrms
C1  C1 + C2  C1 + C2  C2 
1442443 144 42444 3
φ1 noise referred to output φ 2 noise

B. Murmann EE315A - Chapter 9 90

 Simulation Result

Noise PSD Noise Integral

Good match!

B. Murmann EE315A - Chapter 9 91

Noise in an SC Integrator

B. Murmann EE315A - Chapter 9 92

 Old School Approach (1)
Phase 1: Sampled noise charge is
dumped into virtual ground:
q 2 kTC
i12 = = 2
Ts2 Ts
Phase 2: Virtual ground switch induces
independent noise charge packet

q 2 kTC
i 22 = =
Ts2 Ts2

2 2 2 2 i2 2 1
i = i + i = 2kTCf
1 2 s = 2kTCfs2 = 4kTCfs = 4kT
∆f fs Ravg
Same noise as a resistor!

J. H. Fischer, "Noise sources and calculation techniques for switched capacitor

filters," IEEE J. Solid-State Circuits, vol. 17, no. 4, pp. 742-752, Aug. 1982

B. Murmann EE315A - Chapter 9 93

Old School Approach (2)

“Equivalent”

Good luck!

B. Murmann EE315A - Chapter 9 94

 Proper Integrator Noise Analysis

• Think discrete time!

• Analyze integrator circuits in the same way first order filter example
– Process input referred noise using z-domain transfer function
• Caveat: Noise splits into an input referred and output referred
component, and these two noise components are correlated
• Luckily, only the input referred component is typically relevant

[Schreier, TCAS1, 2005]

B. Murmann EE315A - Chapter 9 95

Integrator’s Input Referred Noise

2 kT kT 1 kT 1
v in,tot = + + αγ x = gm ⋅ 2Ron
Cs Cs 1 + 1 Cs 1 + x
{
φ1 1444 x424444 3 [Schreier, TCAS1, 2005]

φ2

Analysis of phi2 noise:

Calculate noise charge left behind
at Y after switch has turned off.
Charges at X and Y are equal and
opposite, so calculating charge on
Cs accomplishes the task.

Output noise
β
input noise

B. Murmann EE315A - Chapter 9 96

 Noise Analysis of a Martin-Sedra Biquad

B. Murmann EE315A - Chapter 9 97

Noise Analysis of a Martin-Sedra Biquad

• After some algebra, considering switch noise only (see

supplementary handout):

ଶ
ଶ ହ  1  1  ଴

௢௨௧  ଵ  ଶ    ଺
ଶଶ ଵ ଶ ହ ହ ଶ ௦

• Can “easily” incorporate OTA noise

B. Murmann EE315A - Chapter 9 98

 SC Filter Summary
• Pole and zero frequencies are proportional to sampling
frequency and capacitor ratios
– High accuracy and stability in response
– Large time constants realizable without large R, C
• Compatible with operational transconductance amplifiers; no
need to drive resistive loads
• Amplifier gain and BW requirements comparable to active RC
• Noise
– SC resistor emulation has same noise as an actual resistor
– Arguing about amplifier noise requires detailed analysis
• Special issue in SC circuits: noise aliasing
• SC filters typically require continuous time anti-aliasing and
reconstruction filters
– Sometimes first order RC will suffice, particularly for large fs

B. Murmann EE315A - Chapter 9 99

References (1)

• R. Gregorian, K.W. Martin, and G.C. Temes, “Switched-Capacitor Circuit

Design,” Proceedings of the IEEE, vol. 71, no. 8, pp. 941-966, Aug. 1983
• D.L. Fried, "Analog sample-data filters," IEEE J. Solid-State Circuits, vol. 7, no.
4, pp. 302-304, Aug. 1972
• D. Senderowicz et al., “A Family of Differential NMOS Analog Circuits for PCM
Codec Filter Chip,” IEEE J. Solid-State Circuits, pp.1014-1023, Dec. 1982
• T.C. Choi, "High-Frequency CMOS Switched-Capacitor Filters," UC Berkeley,
Ph.D. Thesis, May 1983 (ERL Memorandum No. UCB/ERL M83/31)
• B.-S. Song and P.R. Gray "Switched-Capacitor High-Q Bandpass Filters for IF
Applications," IEEE J. Solid-State Circuits, pp. 924-933, Dec. 1986
• K. Martin and A. Sedra, "Effects of the op amp finite gain and bandwidth on the
performance of switched-capacitor filters," IEEE Trans. Circuits and Systems,
vol. 28, no. 8, pp. 822-829, Aug. 1981
• K.L. Lee, “Low Distortion Switched-Capacitor Filters," UC Berkeley, Ph.D.
Thesis, Feb. 1986 (ERL Memorandum No. UCB/ERL M86/12)

B. Murmann EE315A - Chapter 9 100

 References (2)
• K. Martin and A.S. Sedra, “Stray-insensitive switched-capacitor filters based on
the bilinear z transform,” Electronics Letters, vol. 19, pp. 365-366, June 1979
• R. Castello, and P.R. Gray, "A high-performance micropower switched-capacitor
filter," IEEE J. Solid-State Circuits, vol. 20, no. 6, pp. 1122-1132, Dec. 1985
• J. H. Fischer, "Noise sources and calculation techniques for switched capacitor
filters," IEEE J. Solid-State Circuits, vol. 17, no. 4, pp. 742-752, Aug. 1982
• C.-A. Gobet and A. Knob, "Noise analysis of switched capacitor networks," IEEE
Trans. Circuits and Systems, vol. 30, no. 1, pp. 37-43, Jan 1983
• J. Goette and C.-A. Gobet, "Exact noise analysis of SC circuits and an
approximate computer implementation," IEEE Trans. Circuits and Systems, vol.
36, no. 4, pp.508-521, Apr. 1989.
• R. Schreier, et al., "Design-oriented estimation of thermal noise in switched-
capacitor circuits," IEEE Trans. Circuits and Systems I, vol. 52, no. 11, pp. 2358-
2368, Nov. 2005
• K. Kundert, “Simulating Switched-Capacitor Filters with SpectreRF,”
http://www.designers-guide.org/Analysis/sc-filters.pdf

B. Murmann EE315A - Chapter 9 101

 Physical Layout

David Su & Boris Murmann

Stanford University
Copyright © 2014

D.Su & B. Murmann EE315A - Chapter 10 1

Part I – Physical Layout Basics

• Floorplanning
– blocks, power/ground
– metal density rule
• Passives: resistors, capacitors,
• Transistors

D.Su & B. Murmann EE315A - Chapter 10 2

 Basics

Tapeout
Schematics Layout Mask Silicon

• DRC: Design Rule Check

• LVS: Layout Vs Schematics
• LPE: Layout Parasitic Extraction

D.Su & B. Murmann EE315A - Chapter 10 3

Tapeout

• Layout database is
stored in gds format
• Transfer to foundry
was done on
magnetic tape
(Tapeout)
• Tape is not used
today.

Photo from wikimedia.org

D.Su & B. Murmann EE315A - Chapter 10 4

 Chip micrograph

D.Su & B. Murmann EE315A - Chapter 10 5

Design Rules
• Design rules defines geometry in x-y dimension
– Width, spacing, overlap
• z dimension is pre-determined by the
foundry/process
• Understand design rules
– Design rules: must
– Recommended rules: want
– Guidelines: nice to have
• Following design rules ensures functionality and
yield

D.Su & B. Murmann EE315A - Chapter 10 6

 Floorplanning
• Do planning before layout of cells
– Estimate area and package pins
– Organize block placement
– Package choice:
• Size of package vs die
• Length of bond wire and package trace (esp. for power/gnd)
• Coupling between adjacent bond wire and package pins
• Avoid a large output signal coupling back to weak input
signal
• Iterative process

D.Su & B. Murmann EE315A - Chapter 10 7

Block Level Layout

• For each block:
– Determine pin location of each block including power/gnd
• Where are the signals coming and going
– Place the transistors
– Plan power routing (current path)
• A “ground” or “vdd” label on a metal line does not change parasitic
resistance or inductance
• “vdd” needs decoupling capacitors to “ground”
– Routing of sensitive nodes
• Separate noisy (digital, clock, !) and quiet (input, bias, !) signals
• Shield signal signals using ground, vdd, digital control signals that
are not toggling
• Decouple (add capacitors) sensitive dc signals (bias, supply)
• Iterative process

D.Su & B. Murmann EE315A - Chapter 10 8

 Reminders
• Resistance (including metal / poly)
V=IR
• Inductance (long metal traces, bond wire)
V = L di/dt
• Capacitance (charging current)
I = C dv/dt

D.Su & B. Murmann EE315A - Chapter 10 9

Metal Routing
• Width of metal:
– Electro-migration: ~1mA/um
– IR drop: ~50-100mohms/square/layer
– Wide metal rule < ~10um (process dependent) but
use multiple layers or parallel lines

• Establish metal routing ground rules to ease

layout
– Example: M1, M3 horizontal; M2, M4 vertical

D.Su & B. Murmann EE315A - Chapter 10 10

 Routing Signals
• Use low impedance node
– Example: route current instead of high impedance
voltage nodes
• Watch for IR drop in current
– Voltage headroom
• Shield sensitive signals
– Use return path shields
– Choose vdd or gnd
• Shielding adds capacitance
– Consider spacing to reduce coupling

D.Su & B. Murmann EE315A - Chapter 10 11

CMP Effect
• Chemical-Mechanical Polishing (CMP) process
planarizes wafer surface after each metal layer;
Otherwise, unevenness of one layer that may
affect the next layer
• Relative hardness of metal and oxide affects the
polishing
• Solution:
– Metal coverage rule: Keep relatively uniform density
of metal/oxide over ~100um diameter
– Metal density rule to avoid large area without metal

dummy metal fill
– Limit the width of metal to avoid large area with only
metal

metal slot rules
D.Su & B. Murmann EE315A - Chapter 10 12
 Dummy Metal Fill

• Automatic generation of small rectangles

in “empty” space to provide more uniform
density
• Dummy metal can impact parasitic
capacitance.
• Can block the automatic generation of
dummy metal (with a dummy block layer)
for critical circuits
D.Su & B. Murmann EE315A - Chapter 10 13

Wide Metal
• Metal width can not be too wide
– Copper is softer than oxide.
– CMP can over polish the copper, reducing its
thickness (increasing resistance) and making
the overall surface less planar (more difficult
for higher layer metal)
• Add slots to metal width to increase the
density of oxide
– Or, avoid using very wide metal, use several
narrower metal lines in parallel
D.Su & B. Murmann EE315A - Chapter 10 14
 Matching
• A major advantage of VLSI design is device
matching:
– Fully differential circuits
CMRR, offset
– Current mirrors
– Ratioed devices: capacitors, resistors, transistors
• Random mismatch:
– Process: geometry, implant dose, =
• Systematic:
– Mask gradient
– Thermal gradient

D.Su & B. Murmann EE315A - Chapter 10 15

Systematic vs Random Mismatch

µ
Distribution of Parameter

Systematic

Random
σ

−3σ −2σ −σ σ 2σ 3σ

• Systematic mismatch changes the average

• Random mismatch leads to fluctuation/spread

D.Su & B. Murmann EE315A - Chapter 10 16

 Intrinsic Resistor
• Ohms/square, R
; voltage coefficient
• Types:
– Poly (salicided vs non-salicided)
– Diffusion (salicided vs non-salicided)
– Nwell for kohm/square

L
R intrinsic = # of Squares   × R

W
D.Su & B. Murmann EE315A - Chapter 10 17

Poly Resistor 1

Metal 1

L contact

W Poly

Salicide Block
• Types (consult design/electric rules)
– p or n doped
– salicided or non-salicided
– Recommended width > minimum poly width
– Choice: R
, voltage coefficient, matching

D.Su & B. Murmann EE315A - Chapter 10 18

 Poly Resistor 2

Metal 1

L contact

W Poly

Salicide Block

• Resistance = 2 X Rend + Rintrinsic

• Keep W large to reduce Rend
• Keep L large to reduce voltage dependency
D.Su & B. Murmann EE315A - Chapter 10 19

Resistor Matching
• Systematic Mismatch
– Use identical unit elements
– Keep same orientation, environment
• Use dummy resistors
• Minimize metal routing over resistors (keep all metal routing
identical) to reduce noise coupling
– Watch out for mask gradient, temperature gradient,
pressure gradient
• Keep devices in close proximity
• Use interdigitated layout
• Random Mismatch
– Keep W and L large to reduce random mismatch
– Reduce the contribution of Rend

D.Su & B. Murmann EE315A - Chapter 10 20

 Interdigitated Resistor Layout
0 +∆ +2∆ +3∆ +4∆ +5∆

Dummy
Dummy
RA RB RA RA RB RA

Top View
• Interdigitated: ABAABA
• Remove linear gradient in temperature, mask CD,
pressure
D.Su & B. Murmann EE315A - Chapter 10 21

Capacitor
• Metal sandwich capacitor
– Small fF/um^2
• MiM: Metal-insulator-Metal (process option)
– 1-2 fF/um^2
– Best matching
• Interdigitated metal capacitor
– Standard process
– Almost as high density as standard MiM
– Matching is not as good as MiM
• MOS capacitors
– High density
– Poor voltage coefficient
D.Su & B. Murmann EE315A - Chapter 10 22
 Intrinsic Capacitor
Top

Bottom
Cross Section

• Assume no fringing effect

ε
CINT = Area
tox

D.Su & B. Murmann EE315A - Chapter 10 23

Sandwich Capacitor

M6
Top CINT
Bottom Top
M5

M4
CBOT CTOP
M3

M2
Bottom Capacitor Model

Cross Section

D.Su & B. Murmann EE315A - Chapter 10 24

 Interdigitated Capacitor
M6 + - + - + • Alternating fingers of
capacitors
M5 - + - + - • Vertical separation is
larger than horizontal
M4 + - + - + separation; most
capacitance from lateral
M3 - + - + - flux
• Other permutations are
M2 + - + - + possible (see references)
Cross-section

H. Samavati, et al, “Fractal Capacitors,” JSSC, Dec 1998.

R. Aparicio, A. Hajimir, “Capacity limits & matching properties of integrated capacitors, JSSC, March 2002.

D.Su & B. Murmann EE315A - Chapter 10 25

Capacitor Matching
• Systematic Mismatch
– Use identical unit elements in an array
– Keep same environment
• Use dummy capacitors
– Watch out for mask, temperature, pressure gradient
• Keep devices in close proximity
• Use common centroid layout
– Keep routing parasitics small and matched
• Random Mismatch
– Use large area to reduce random mismatch

D.Su & B. Murmann EE315A - Chapter 10 26

 Common Centroid Capacitor

C1 C2

C2 C1

Top View
D.Su & B. Murmann EE315A - Chapter 10 27

MOS Transistors
• Layout
• Random Mismatch
– Process tolerance
Large W and L
– Vt, beta
keep Vgs-Vt large
• Systematic Mismatch
– Gradient: Common centroid layout
– Implant angle: Step symmetry vs mirror
symmetry
– Neighbor effect: add dummies

D.Su & B. Murmann EE315A - Chapter 10 28

NMOS Transistor Cross-Section

Metal 1

drain source
gate

n+ n+
STI p STI

D.Su & B. Murmann EE315A - Chapter 10 29

NMOS Transistor Top View

gate

drain source
contact

Metal 1
W
N-diff

Poly

L
D.Su & B. Murmann EE315A - Chapter 10 30
 PMOS Transistor Top View
gate

drain source
contact

Metal 1
W
P-diff

Poly

L Nwell

D.Su & B. Murmann EE315A - Chapter 10 31

Gate Resistance
• Gate resistance:
– Keep W short
– Connect on one end: Rg = 1/3 x (W/L) x R

– Connect on both ends: Rg = 1/12 x (W/L) x R

Rg

Ref: Razavi et al, “Impact of distributed gate resistance on the performance of MOS devices,”
IEEE Trans circuits & systems I, Nov 1994.

D.Su & B. Murmann EE315A - Chapter 10 32

 Random Transistor Mismatch
1 W
ID = µCox (VGS − VT ) 2
2 L
β
ID = (VGS − VT ) 2
2
Random Mismatch in: VT and β

4σ ∆2Vt
σ ∆2I D / I D = + σ ∆2β / β
(VGS − VT ) 2

Ref: Pelgrom et al, “Matching Properties of MOS Transistors,” JSSC, Oct. 1989.
D.Su & B. Murmann EE315A - Chapter 10 33

Random Threshold Mismatch

Distribution of VT

Random
σ

−3σ −2σ −σ σ 2σ 3σ
AVT
σ ∆Vt ≈
W ×L AVT = 3 – 10 mV µm
Ignoring distance effect Process Dependent

Ref: Pelgrom et al, “Matching Properties of MOS Transistors,” JSSC, Oct. 1989.
D.Su & B. Murmann EE315A - Chapter 10 34
 Example: Threshold Mismatch

V1 v2
50 / 1 50 / 1

If AVT = 5mVµm

AVT 5mVµm
σ ∆ (V 1−V 2 ) ≈ = = 0.71mV
W ×L 50 µm × 1µm
Ignoring distance effect

Ref: Pelgrom et al, “Matching Properties of MOS Transistors,” JSSC, Oct. 1989.
D.Su & B. Murmann EE315A - Chapter 10 35

β Mismatch

Aβ
σ∆ ∆β / β ≈
W ×L
Ignoring distance effect

Aβ ≈ 0.5 - 3 %

D.Su & B. Murmann EE315A - Chapter 10 36

 Vt Matching Data

90nm data
[Chang,
AVT~tox Trans.
Electron
Devices,
7/2005]

[Pelgrom, IEDM 1998]

D.Su & B. Murmann EE315A - Chapter 10 37

Mirror Inaccuracy Due to Mismatch

∆β
∆I = I1 − I 2 ≅ − g m ∆Vt + I1
β
∆I g ∆β
≅ − m ∆Vt +
I1 I1 β

gm 2
σ ∆2I ≅ σ ∆Vt + σ ∆2β
I1 I1 β

• Example: W=10µm, L=0.35µm, gm/ID=10S/A, AVT = 7mV/um, Aβ=1%

2
 S 
σ ∆I =  10 ⋅ 3.7 mV  + (0.53% )2 = (3.7% )2 + (0.53% )2 = 3.74%
I
 A 
1

• Threshold mismatch usually dominates

D.Su & B. Murmann EE315A - Chapter 10 38
 Systematic Mismatch
• Gradient: Thermal, Mask, Pressure
– Common centroid layout

• Implant angle: Step symmetry vs mirror

symmetry

• Neighbor effect: add dummies

D.Su & B. Murmann EE315A - Chapter 10 39

Gradient Cancellation
• Gradient: Thermal, Mask, Pressure
• Linear gradient is easy to cancel
– Common centroid layout
• Other techniques exist for higher order
gradient cancellation
– Ref: G. Van der Plas, et al, JSSC, Dec 1999

D.Su & B. Murmann EE315A - Chapter 10 40

 Implant Angle

n+ n+
STI p STI

• A small angle of 7 deg in implant results in slight different

in implant; modern processes will compensate for this
but ...
• Keep same orientation/direction of current for matched
devices
– Step symmetry vs mirror symmetry

D.Su & B. Murmann EE315A - Chapter 10 41

Step vs Mirror Symmetry

M1 M2

Step Symmetry

S D S D

Mirror Symmetry

Not preferred
S D D S
M1 M2

D.Su & B. Murmann EE315A - Chapter 10 42

Common Centroid Transistors 1
M1 M2

S D D S

S D D S

M2 M1

Cancellation of offset due to current flow direction

D.Su & B. Murmann EE315A - Chapter 10 43

Common Centroid Transistors 2

D D
M1 M2
S S

D D
M2 M1

S S

Same current flow direction

D.Su & B. Murmann EE315A - Chapter 10 44
 Differential Pair

Dummy Dummy
SS SS
D1 D2 M1 M2
D1 D2
M1 M2 M1 M2
SS SS
SS M2 M1
D2 D1
M2 M1
SS SS
Dummy Dummy

D.Su & B. Murmann EE315A - Chapter 10 45

Neighbor Effects
• Keep the “neighborhood” of matched
transistors identical
• Add dummy transistors for the “edged”
devices
• Watch out for z-direction as well
– Metal layers must also match
– Avoid Metal-1 overlap

D.Su & B. Murmann EE315A - Chapter 10 46

 Second order effects
• Second order effects of MOS transistors
– Antenna rule
– Strained silicon
– Well proximity

D.Su & B. Murmann EE315A - Chapter 10 47

Antenna Rule
• Implant/deposition process can induce charge on metal
and create voltage stress on gate capacitance
• Q=CV; If C is small, V is large
Damage! Large VT shift
– Q depends on area (Copper) and perimeter (Aluminum) of metal
– C depends on the W x L (area) of the transistor gate

Area/Perimeter of Metal
V ∝ Metal - Gate Ratio =
Gate area of transistor
• “Antenna rule” violation when induced voltage V exceeds
safe limits.
• Solution: Add “antenna” (reverse-biased) diodes to shunt
charge
D.Su & B. Murmann EE315A - Chapter 10 48
Length of Diffusion (LOD) Effect
SD
SA SB
Shallow
Trench
Isolation
Edge

Source: Sally Liu, ISSCC 2006 SET

• STI (shallow trench isolation) induces mechanical stress effect on
transistor
strained device
• Starting with 130nm/90nm and modulated by the distance between
poly and OD/STI edge (SA, SB)
• Applies to both NMOS and PMOS (see DRC)
• Effect can be extracted in Layout Parasitic Extraction (LPE)
simulations.
D.Su & B. Murmann EE315A - Chapter 10 49

Minimizing LOD Effect

Different SB

• Use unit devices for best matching

• Avoid using irregular diffusion shape
• Use dummy transistors on both ends of a multi-finger
device to keep the same SA and SB for matching

D.Su & B. Murmann EE315A - Chapter 10 50

 Well Edge Proximity Effect 1

• Well proximity ions scatter at

well photo resist edge,
bounce into the active region
and thus increase the device
threshold voltage
• Affects device matching
Shallow • Important for Well to gate
Trench spacing: SC of 1um or less
Isolation
(STI) • Should be modeled by LPE
extraction
• Well proximity effect reduced
Y-M Sheu et al, CICC 2005 by guard ring
D.Su & B. Murmann EE315A - Chapter 10 51

Well Edge Proximity Effect 2

• P. G. Drennan et al., "Implications of Proximity Effects for Analog Design," Proc. CICC, pp.169-
176, Sep. 2006.
D.Su & B. Murmann EE315A - Chapter 10 52
 Minimizing WPE Effect
Matched

Keep SC large

NWELL

• Keep distance between gate to well as large as

possible (>> 1um; see DRC)
• For matching, keep SC equal and large
D.Su & B. Murmann EE315A - Chapter 10 53

Transistor Matching
• Keep transistor area large
• Use same size, shape, orientation, and in
close proximity
• Keep same voltage, current, temperature
• Minimize gradient effect: common centroid
• Keep neighbors (up to >10um) identical in
x, y, and z directions
– Use dummy devices
– Avoid edge of chip
D.Su & B. Murmann EE315A - Chapter 10 54
 Part II: Design Related Issues

• Noise coupling effects

• Latchup
• ESD

D.Su & B. Murmann EE315A - Chapter 10 55

Noise Interference

Noise
Noise Coupling
Source

Sensitive
Circuits
D.Su & B. Murmann EE315A - Chapter 10 56
 Noise Coupling Mechanisms
• Capacitive
– E.g. through on-chip wire crosstalk
• Inductive
– E.g. through bond wires
• Supply coupling
– Modulation of supplies due to IR or Ldi/dt drop
• Substrate coupling

D.Su & B. Murmann EE315A - Chapter 10 57

Capacitive Coupling -- Bias

Vx Low cap:
fast recovery
big bounce

t
Vx

t
High cap:
Noise Coupling slow recovery
small bounce

• Can use decoupling capacitors to reduce the amplitude of noise coupling

into bias nodes
• If noise is "deterministic" and occurs at a “don’t care” point in time, you
might be better off not decoupling, but making the bias node "fast" (small
mirror ratio, no decoupling cap) so it can recover quickly
• Must go for either extreme case: no decoupling or large decoupling

D.Su & B. Murmann EE315A - Chapter 10 58

 Capacitive Coupling -- SC

Charge conservation node

• Must minimize coupling into charge conservation node

– Proper placement of “bottom plate” parasitics
– Substrate shielding

D.Su & B. Murmann EE315A - Chapter 10 59

Capacitor Parasitics
C
Ideal Capacitor

C
n1 n2
n1 n2
Typical Integrated C
C
Circuit Capacitor

E.g. α~1%, β~10%

for a MIM capacitor

[Ng, Trans. Electron Dev., 7/2005]

D.Su & B. Murmann EE315A - Chapter 10 60

 Proper Configuration

Keep wiring as short as possible and do not cross with any other signal
May want to place a “clean” shield between wires and substrate

D.Su & B. Murmann EE315A - Chapter 10 61

Layout
Gregorian & Temes, pp. 518, 524

Can use metal shield in a modern

process to protect coupling to
output. Such a shield is usually not
needed when the signals are
differential

D.Su & B. Murmann EE315A - Chapter 10 62

 Floorplanning
• A common mistake is to do a great job of laying out lots of little cells
but then make a big mess when pulling the design together
• A good floorplan is essential to being able to quickly make a good
layout with few iterations
• A floorplan is an evolving document that helps the designer organize
the chip into pieces that fit together well
– Don’t be afraid to change it as you go along and discover new
issues, just start out with one so you don’t miss the obvious
things that can be very painful later
• Know when to stop! You can easily get so carried away with these
issues that your layout takes a very long time to complete
• The key is to do what is right for the application
– An RF mixer should minimize capacitance
– A 14-bit A/D converter needs well a very balanced layout
– G

D.Su & B. Murmann EE315A - Chapter 10 63

Inductive Coupling through Bondwires

Package Bond Wire Silicon Bondwire Leadframe PCB
Silicon
Leadframe

Source: Lawrence Larson, ISSCC 2009 SET

• The leadframe/wirebond interface may require careful modeling

• Ground pin is not “ground” (~1 nH/mm)
• Significant mutual coupling between two adjacent traces (K ~ 0.4)
• Parallel ground bonds is not very effective (reduction to ~0.7L)
• Sometimes better off keeping sensitive signals on chip
• E.g. VCO control voltage

D.Su & B. Murmann EE315A - Chapter 10 64

 Test/Application Board
• Planning begins with chip pin-out
– Uhps, my analog pin is right next to a digital output...
• Not "black magic", but weeks of design time and "thinking"
• Key aspects
– Supply/ground routing
– Bypass capacitors
– Coupling between signals
• Good idea to look at vendor datasheets for example
layouts/schematics/application notes
• For good practices on how to avoid issues see e.g.
– Analog Devices Application Note 345: "Grounding for Low-and-High-Frequency Circuits“
– A Practical Guide to High-Speed Printed-Circuit-Board Layout,
http://www.analog.com/library/analogDialogue/archives/39-09/layout.html
– http://www.hottconsultants.com/techtips/split-gnd-plane.html

D.Su & B. Murmann EE315A - Chapter 10 65

Vendor Eval Bord Layout

[Analog Devices AD9235 Data Sheet]

D.Su & B. Murmann EE315A - Chapter 10 66

 Supply Noise
• Typical culprits
– Digital logic
– Clocks
– IO pads
• Preventive measures
– Reduce noise by turning off unused digital logic
• Clock gating, etc.
– Avoid oversized digital buffers (large current spikes, high
frequency content)
– Stagger digital switching in time; try to minimize activity at certain
instants (e.g. when sampling switch opens)
• Avoid large number of digital pads switching simultaneously
– Work with “current mode” outputs where possible

D.Su & B. Murmann EE315A - Chapter 10 67

LVDS Outputs

Helps minimize
dynamic currents
due to I/O

Cost: additional pin

Analog Devices Application Note 586: "LVDS Data Outputs for High Speed ADCs"

D.Su & B. Murmann EE315A - Chapter 10 68

 Basic View of Supply Noise

BAD

BETTER

Gregorian & Temes, p. 515

D.Su & B. Murmann EE315A - Chapter 10 69

Proper GND Separation

M. Ingels and M.S.J. Steyaert, "Design strategies and decoupling techniques for reducing the effects
of electrical interference in mixed-mode IC's," IEEE J. Solid-State Circuits, pp.1136-1141, July 1997.

D.Su & B. Murmann EE315A - Chapter 10 70

 On-Chip Decoupling

Cornell et al, ISSCC 2002

D.Su & B. Murmann EE315A - Chapter 10 71

IR Drop Issues – Mirror Example

V1 V2=V1
I1 I2
∆I = I1 − I 2 ≅ g mVwire
M1 M2
∆I g m
- Vwire + ≅ Vwire
I1 I1
Rwire

• Want small gm/ID ("large gate voltage overdrive") to

mitigate errors due to wire IR drop
– Unfortunately this means large Vmin

D.Su & B. Murmann EE315A

EE 214 -Lecture
Chapter1310 72
 Current Distribution (1)
• Typically, we'll only have one single reference current generator
on a chip
• Can generate/distribute currents across chip in two different ways
– Distribute gate voltage
• Can cause big problems due to IR drop and process
gradients
• Usually limited to local distribution
– Distribute currents
• Have one global bias cell close to reference that sends
currents into local biasing sub-circuits
• Disadvantage: consumes additional current

D.Su & B. Murmann EE315A

EE 214 -Lecture
Chapter1310 73

Current Distribution (2)

Iref

D.Su & B. Murmann EE315A

EE 214 -Lecture
Chapter1310 74
 Substrate Noise

http://www-tcad.stanford.edu/tcad/pubs/theses/iorga.pdf
D.Su & B. Murmann EE315A - Chapter 10 75

Substrate Types

"Epi Substrate"

D.Su & B. Murmann EE315A - Chapter 10 76

 Epitaxial Substrate

D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, "Experimental results and modeling techniques for substrate
noise in mixed-signal integrated circuits," IEEE Journal of Solid-State Circuits, vol. 28, pp. 420 - 430, April 1993.

D.Su & B. Murmann EE315A - Chapter 10 77

Observed Waveforms

• Current disturbance roughly ± 1%

D.Su & B. Murmann EE315A - Chapter 10 78

 Coupling vs. Distance

• Essentially independent of distance!

– Why?

D.Su & B. Murmann EE315A - Chapter 10 79

Current Flow in Epi-Substrate

(Setup as in slide 77)

• Majority of current
flows in low-
resistivity wafer

• Coupling is very
weak function of
distance

D.Su & B. Murmann EE315A - Chapter 10 80

 Guard Ring

D.Su & B. Murmann EE315A - Chapter 10 81

Effect of Guard Ring

Large guard
rings increase
w/o coupling!
w

Epi substrate
D.Su & B. Murmann EE315A - Chapter 10 82
 Backside Contact

D.Su & B. Murmann EE315A - Chapter 10 83

Noise vs. L4

D.Su & B. Murmann EE315A - Chapter 10 84

 Summary (Epi-Substrate)
• Closely modeled by a "single node"
• The most effective way to reduce coupling in Epi-substrates to is to
provide a good, low inductance backside contact
• Unfortunately distance and guard rings don't help much in reducing
coupling
• If you decide to use guard rings, make sure to use dedicated guard
ring potentials
– Otherwise guard rings may increase coupling!

D.Su & B. Murmann EE315A - Chapter 10 85

Current in High Resistivity Substrate

Current trough p+ channel stop

D.Su & B. Murmann EE315A - Chapter 10 86

 Coupling vs. Distance

(Epi)

D.Su & B. Murmann EE315A - Chapter 10 87

Effect of Guard Rings

Breaks p+
channel
stop implant

(Epi)

D.Su & B. Murmann EE315A - Chapter 10 88

 Example

http://www.commsdesign.com/showArticle.jhtml?articleID=192200561

D.Su & B. Murmann EE315A - Chapter 10 89

Deep N-Well

http://www.commsdesign.com/showArticle.jhtml?articleID=192200561

D.Su & B. Murmann EE315A - Chapter 10 90

 Summary (Lightly doped substrate)

• Distance and guard rings can help reduce coupling significantly

• Must connect guard rings to quiet, dedicated potentials
– Otherwise they may inject noise!
• Isolation and coupling effects are highly layout dependent
– If substrate coupling is critical, the designer should invest a
good amount of time to think about potential issues and
solutions
• CAD tools?
– Still being developed/finding commercial use

D.Su & B. Murmann EE315A - Chapter 10 91

Selected References
• R. Gharpurey and R. G. Meyer, "Modeling and analysis of substrate coupling in
integrated circuits," IEEE Journal of Solid-State Circuits, vol. 31, pp. 344 - 353, March
1996.
• Balsha R. Stanisic, Nishath Verghese, Rob A. Rutenbar, L. Richard Carley, David J.
Allstot,"Addressing substrate coupling in mixed-mode ICs: Simulation and power
distribution synthesis," IEEE Journal of Solid-State Circuits, vol. 29, pp. 226 - 238,
March 1994.
• Kuntal Joardar, "A simple approach to modeling cross-talk in integrated circuits,"
IEEE Journal of Solid-State Circuits, vol. 29, pp. 1212 - 1219, October 1994.
• Nishath Verghese and David J. Allstot, "Computer-aided design considerations for
mixed-signal coupling in RF integrated circuits," IEEE Journal of Solid-State Circuits,
vol. 33, pp. 314 - 323, March 1998.
• A. Samavedam, A. Sadate, K. Mayaram, and T. S. Fiez, "A scalable substrate noise
coupling model for design of mixed-signal ICs," IEEE Journal of Solid-State Circuits,
vol. 35, pp. 895 - 904, June 2000.
• Tallis Blalack et al., “On-Chip RF-Isolation Techniques,”
http://www.commsdesign.com/showArticle.jhtml?articleID=192200561

D.Su & B. Murmann EE315A - Chapter 10 92

 Latchup

Minimize RS and RW
using proper guard
rings!

http://www.analog.com/library/analogDialogue/archives/35-05/latchup/

D.Su & B. Murmann EE315A - Chapter 10 93

What is ESD?
• Electrostatic discharge
• Example: Charge built up on human body
while walking on carpet...
• Charged objects near or touching IC pins
can discharge through on-chip devices
• Without dedicated protection circuitry, ESD
events are destructive

D.Su & B. Murmann EE315A - Chapter 10 94

 Models
2000V 150V

500V

http://www-tcad.stanford.edu/tcad/pubs/theses/chun.pdf

D.Su & B. Murmann EE315A - Chapter 10 95

Basic Protection Circuit

[http://www.ce-mag.com/archive/03/ARG/dunnihoo.html]

D.Su & B. Murmann EE315A - Chapter 10 96

 General Architecture

http://www-tcad.stanford.edu/tcad/pubs/theses/chun.pdf

D.Su & B. Murmann EE315A - Chapter 10 97

Rail Clamp Approach

D.Su & B. Murmann EE315A - Chapter 10 98

 Testability
• How to test an SoC?
• Test circuits
– Probe pads
– Post fabrication: cut and short?

D.Su & B. Murmann EE315A - Chapter 10 99