Majority)Gate)with)Temporary)

Signals
The$following$version$of$the$majority$gate$uses$some$
temporary$“wires”

// Majority Logic Circuit

module maj_circ(Y, A, B, C);
input A, B, C;
output Y;
wire x1, x2, x3; //Optional
assign x1 = A&B;
assign x2 = A&C;
assign x3 = B&C;
assign Y = x1|x2|x3;
endmodule 1

Concurrent$Assignment$with$Ternary$
Select
assign mux_out = (select==1’b0) ? q0 : q1;

if statement$is$procedural$(sequential)$

Used$inside$begin – end Block

Similar$to$if Statement$but$Concurrent$Version

2
 Majority$Gate$with$conditional$statement
The$following$version$of$the$majority$gate$uses$a$conditional$
concurrent$statement:

// Majority Logic Circuit

module maj_circ(Y, A, B, C);
input A, B, C;
output Y;
assign Y = ((A&&B)||(A&&C)||(B&&C))
? 1’b1 : 1’b0;
endmodule

You$will$find$that$there$are$many$different$ways$to$
accomplish$the$same$result$in$Verilog. There$is$usually$no$
best$wayK$just$use$one$that$you$feel$most$comfortable$with.3

Concurrent$Versus$Sequential$
Statements
• The$statements$we$have$looked$at$so$far$are$
called$concurrent statements.
– Each$concurrent$statement$will$synthesize$to$a$block$of$
logic.
• Another$class$of$Verilog$statements$are$called$
procedural$(sequential) statements.
– Sequential$statements$can$ONLY$appear$inside$of$a$
always or$an initial block.$
– An$always block$is$considered$to$be$a$single$
concurrent$statement
– Can$have$multiple$always blocks$in$a$module
– Usually$use$always blocks$to$describe$complex$
combinational$or$sequential$logic
4
 Comments$on$always$block$model
• always$statement$executes$at$every$simulator$time$cycle
always CLK = ~CLK; //Will Loop indefinitely

• General$Form:
always [timing_control] procedural statement(s)

• always$statement$with$delay$control
always #5 CLK = ~CLK; //Waveform CLK is 10 time units

• always$statement$with$event$control
CL always @(A or B or C) //Event on A, B, or C
CL always @(CLK) //Event on rising-falling edge of CLK
Sto always @(posedge CLK) //Event on rising edge of CLK
Sto always @(negedge CLK) //Event on falling edge of CLK
5

Verilog$Always$Block

6
 Precedence$in$Always$Block

Majority$Gate$using$always&block$and$if
statement
// Majority Logic Circuit
module maj_circ(Y, A, B, C);
input A, B, C;
output Y;
reg Y;
always @(A or B or C)
begin
if((A==1’b1)&&(B==1’b1))
Y = 1’b1;
else if ((A==1’b1)&&(C==1’b1))
Y = 1’b1;
else if ((B==1’b1)&&(C==1’b1))
Y = 1’b1;
else
Y = 1’b0;
end
endmodule 8
 Use$of$if)else
Comments:
Module$name$is$maj_circ
// Majority Logic Circuit
module maj_circ(Y, A, B, C);
input A, B, C; Used$an$'else'$clause$to$
output Y; specify$what$the$output$
reg Y; should$be$if$the$if$condition$
always @(A or B or C)
test$was$not$true.
if((A&&B)||
(A&&C)||
(B&&C)) CAREFUL!$Instead$of$
Y = 1’b1; Remembering$Boolean
else Operator$Precedence,$Just
Y = 1’b0;
Use$Parentheses$to$Make$
endmodule
Sure
9

Unassigned$outputs$in$Always$blocks
A$common$mistake$in$writing$a$combinational$module$is$to$
leave$an$output$unassigned. If$there$is$a$path$through$the$
block$in$which$an$output$is$NOT$assigned$a$value,$then$that$
value$is$unassigned.
// Majority Logic Circuit
module bad_maj_circ(Y, A, B, C);
input A, B, C;
output Y;
reg Y;
always @(A or B or C)
if((A&&B)||
(A&&C)||
(B&&C))
Y = 1’b1;
endmodule

What$is$missing$here? 10
 Unassigned$outputs$in$Always$blocks
A$common$mistake$in$writing$a$combinational$module$is$to$
leave$an$output$unassigned. If$there$is$a$path$through$the$
block$in$which$an$output$is$NOT$assigned$a$value,$then$that$
value$is$unassigned.
// Majority Logic Circuit
module bad_maj_circ(Y, A, B, C);
input A, B, C;
output Y;
reg Y;
always @(A or B or C)
if((A&&B)||
(A&&C)||
(B&&C))
Y = 1’b1;
endmodule

What$if ((A&B)|(A&C)|(B&C))equals 1’b0 ?11

Comments$on$Previous$Example
• In$the$previous$always block,$the$ELSE$clause$was$left$out. If$
the$'if'$statement$condition$is$false,$then$the$output$Y is$not$
assigned$a$value.
– In$synthesis$terms,$this$means$the$output$Y should$have$a$
LATCH placed$on$it!$(INFERRED&LATCH)
– The$synthesized$logic$will$have$a$latch$placed$on$the$Y
outputK$once$Y goes$to$a$1’b1,$it$can$NEVER$return$to$a$
1’b0!!!!!
• This$is$probably$the$#1$student$mistake in$writing$always
blocks. To$avoid$this$problem$do$one$of$the$following$things:
– ALL$signal$outputs$of$the$always block$should$have$
DEFAULT$assignments.
– OR, all$'if'$statements$that$affect$a$signal$must$have$
ELSE$clauses$that$assign$the$signal$a$value$if$the$'if'$test$
is$false. 12
 Inferred$Latch
2:1$Multiplexer$Example

13

Priority)circuit)example
module pri_dec(dout,y7,y6,y5,y4,y3,y2,y1);
This$priority$circuit$has$7$
input y7,y6,y5,y4,y3,y2,y1; inputsK$
output [2:0] dout;
reg [2:0] dout;
Y7$is$highest$priority,$Y1$
always @(y7 or y6 or y5 or y4 or y3 is$lowest$priority.$
or y2 or y1)
begin
if (y7==1’b1) dout = 3’b111; Three$bit$output$should$
else if (y6 == 1’b1) dout = 3’b110;
else if (y5 == 1’b1) dout = 3’b101;
indicate$
else if (y4 == 1’b1) dout = 3’b100; the$highest$priority$input$
else if (y3 == 1’b1) dout = 3’b011;
else if (y2 == 1’b1) dout = 3’b010;
that$is$
else if (y1 == 1’b1) dout = 3’b001; a$'1'$(ie.$if Y6$='1'$,$Y4$=$
else dout = 3’b000;
end
'1',$then$output$should$be$
endmodule "110"). If$no$
input$is$asserted,$output$
should$be$"000".
14
 Comments$on$Priority$Example
• The$dout signal$is$a$3$bit$output$bus.
– reg [2:0] dout describes$a$3$bit$bus$where$dout[2] is$most$
significant$bit, dout[0] is$least$significant$bit.
– reg [0:2] dout is$also$a$3$bit$bus,$but$dout[0] is$MSB,$
dout[2] is$LSB.$NOT$RECOMMENDED!
• A$bus$assignment$can$be$done$in$many$ways:
– dout = 3’b110; assigns$all$three$bits
– dout[2] = 1’b1; assigns$only$bit$#2
– dout[1:0] = 2’b10; assigns$two$bits$of$the$bus.
• This$module$used$the$else if form$of$the$if statement
– This$is$called$an$else if chain.$

15

Priority$Circuit$with$just$IF$statements

module pri_dec(dout,y7,y6,y5,y4,y3,y2,y1);
input y7,y6,y5,y4,y3,y2,y1;
output [2:0] dout;
reg [2:0] dout; By$reversing$the$order$of$
always @(y7 or y6 or y5 or y4 or y3
or y2 or y1)
the$assignments,$we$can$
begin accomplish$the$same$as$
dout = 3’b000;
if (y1==1’b1) dout = 3’b001;
the$else if priority$
if (y2==1’b1) dout = 3’b010; chain.
if (y3==1’b1) dout = 3’b011;
if (y4==1’b1) dout = 3’b100;
if (y5==1’b1) dout = 3’b101; In$an$always$block,$the$
if (y6==1’b1) dout = 3’b110;
if (y7==1’b1) dout = 3’b111;
LAST$assignment$to$the$
end output$is$what$counts.
endmodule
16
 An$attempt at$a$Priority$Circuit

module pri_dec (dout,y7,y6,y5,y4,y3,y2,y1);

input y7,y6,y5,y4,y3,y2,y1;
output [2:0] dout;
assign dout = (y1==1’b1) ? 3’b001 : 3’b000;
assign dout = (y2==1’b1) ? 3’b010 : 3’b000;
assign dout = (y3==1’b1) ? 3’b011 : 3’b000;
assign dout = (y4==1’b1) ? 3’b100 : 3’b000;
assign dout = (y5==1’b1) ? 3’b101 : 3’b000;
assign dout = (y6==1’b1) ? 3’b110 : 3’b000;
assign dout = (y7==1’b1) ? 3’b111 : 3’b000;
endmodule

Is$anything$wrong$here?
17

Another$attempt$at$a$Priority$Circuit
(same$as$beforejdiff.$syntax)
module pri_dec (dout,y7,y6,y5,y4,y3,y2,y1);
input y7,y6,y5,y4,y3,y2,y1;
output [2:0] dout;
assign dout = (y1==1’b1) ? 3’b001 : 3’b000,
dout = (y2==1’b1) ? 3’b010 : 3’b000,
dout = (y3==1’b1) ? 3’b011 : 3’b000,
dout = (y4==1’b1) ? 3’b100 : 3’b000,
dout = (y5==1’b1) ? 3’b101 : 3’b000,
dout = (y6==1’b1) ? 3’b110 : 3’b000,
dout = (y7==1’b1) ? 3’b111 : 3’b000;
endmodule

Is$anything$wrong$here?
18
 Comments$on$“bad”$Priority$Circuits
• Bad$Attempts$for$Priority$Circuit
• Problems$in$this$Description
– Multiple$Concurrent$Statements$Driving$dout Signal
– Causes$Multiple$Gate$Outputs$to$be$Tied$Together
– Creates$Unknown$Logic$Condition$on$Bus
• Writer$seems$to$think$that$the$order$of$the$
concurrent$statements$makes$a$difference
– The$order$in$which$you$arrange$concurrent$statements$
MAKES$NO$DIFFERENCE.$ The$synthesized$logic$will$
be$the$same.
– Ordering$of$statements$only$makes$a$difference$within$
an$always(initial)$ block.$This$is$why$statements$
within$such$blocks$are$called$'sequential'$statementsK$
the$logic$synthesized$reflects$the$statement$ordering$
(only$for$assignments$to$the$same$output).
19

Priority$Circuit$with$Concurrent$
Statement
No$procedural$(sequential)$blockK$just$one$
concurrent$statement.

module pri_dec (dout,y7,y6,y5,y4,y3,y2,y1);

input y7,y6,y5,y4,y3,y2,y1;
output [2:0] dout;
assign dout = (y1==1’b1) ? 3’b001 :
((y2==1’b1) ? 3’b010 :
((y3==1’b1) ? 3’b011 :
((y4==1’b1) ? 3’b100 :
((y5==1’b1) ? 3’b101 :
((y6==1’b1) ? 3’b110 :
((y7==1’b1) ? 3’b111 : 3’b000))))));
endmodule
20
 4jtoj1$mux$with$8$bit$Datapaths

module mux8 (dout,A,B,C,D,SEL);

input [7:0] A,B,C,D;
input [1:0] SEL;
output [7:0] dout;
assign dout = (SEL==2’b00) ? A :
((SEL==2’b01) ? B :
((SEL==2’b10) ? C :
((SEL==2’b11) ? D : 8’hxx)));
endmodule

21

Comments$on$MUX$example
• This$is$one$way$to$write$a$mux,$but$it$is$not$the$best$
way.$The$nested$ternary$assignment$statement$is$
actually$a$priority structure.
– A$mux$has$no$priority$between$inputs,$just$a$
simple$selection.
– The$synthesis$tool$has$to$work$harder$than$
necessary$to$understand$that$all$possible$choices$
for$SEL are$specified$and$that$no$priority$is$
necessary.
• Just$want$a$simple$selection$mechanism.

22
 Multiplexers$in$Verilog

Priority$Structure NonjPriority$Structure
23

Another$4jtoj1$Mux$using$always Block
module mux8 (dout,A,B,C,D,SEL);
input [7:0] A, B, C, D;
input [1:0] SEL;
output [7:0] dout;
reg [7:0]dout;
always @(SEL or A or B or C or D)
begin
case (SEL)
2'b00: dout=A;
2'b01: dout=B;
2'b10: dout=C;
2'b11: dout=D;
default: dout=8'hxx;
endcase
end
endmodule

This$is$a$concurrent$always$blockK$the$sequential statement$within$the$
always$block$is$the$case&statement. 24
Full$and$Ripple$Adders

25

Adders$in$Verilog

26
Verilog$Synthesis$Results

27

FixedjPoint$Multipliers

28
 Array$Multiplier$Structure

29

Bit$Shifting$in$Verilog
Concatenation$Operation

30
 Bit$Shifting$with$Multiplexers

{ }
{ }

31

Multiplexerjbased$Barrel$Shifter

32
Trijstate$Buffers

33

Bus$Multiplexing

34
 Delay$ModelingjSimulation
• Timescale$Directive
– `timescale 1ns/100ps
– First$number$is$unit$of$measurement$for$delays
– Second$number$is$precision$(roundjoff$
increments)
• We$will$use$Default$Increments
– # Directive$for$Delay$Modeling
– Timing$Allows$for$More$Accurate$Modeling
– Concept$of$Back$Annotation
• Used$ONLY$FOR$SIMULATION
– Not$Used$for$Synthesis
– Backjannotation
35

Verilog$Example$with$Delay
// Description of circuit with delay
module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
not #(10) g2(y,C);
or #(20) g3(x,e,y);
endmodule

Where does this

come from?

36
Verilog$Example$with$Delay
// Description of circuit with delay
module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
not #(10) g2(y,C);
or #(20) g3(x,e,y);
endmodule

t=0:
events: A:0/1 B:0/1 C:0/1

simulations: g1(AND) A=1,B=1,t=30(30)

g2(NOT) C=1,t=10(10)

Simulation Scheduled at 10 Simulation Scheduled 37

at 30

Verilog$Example$(Waveform)
// Description of circuit with delay
module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
not #(10) g2(y,C);
or #(20) g3(x,e,y);
endmodule

A
B
C
y
e
x
10 20 30 40 50 60 38
Verilog$Example$with$Delay
// Description of circuit with delay
module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
not #(10) g2(y,C);
or #(20) g3(x,e,y);
endmodule

t=10:
events: y:1/0

simulations: g3(OR) e=0,y=0,t=20(30)

Another Simulation Scheduled at 30 39

Verilog$Example$(Waveform)
// Description of circuit with delay
module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
not #(10) g2(y,C);
or #(20) g3(x,e,y);
endmodule

A
B
C
y
e
x
10 20 30 40 50 60 40
Verilog$Example$with$Delay
// Description of circuit with delay
module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
not #(10) g2(y,C);
or #(20) g3(x,e,y);
endmodule

t=30:
events: e:0/1 x:1/0

simulations: g3(OR) e=1,y=0,t=20(50)

41

Verilog$Example$(Waveform)
// Description of circuit with delay
module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
not #(10) g2(y,C);
or #(20) g3(x,e,y);
endmodule

A
B
C
y
e
x
10 20 30 40 50 60 42
Verilog$Example$with$Delay
// Description of circuit with delay
module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
not #(10) g2(y,C);
or #(20) g3(x,e,y);
endmodule

t=50:
events: x:0/1

simulations: NONE

43

Verilog$Test$Benches
• Only$Used$FOR$SIMULATION
• Another$Verilog$Module$that:
– Provides$Input
– Allows$Various$Modules$to$be$Interconnected
– Contains$Simulation$Specific$Commands
• Separation$into$Different$Modules$Important:
– Can$Synthesize$Modules$Directly
– Can$Change$Abstraction$of$Modules
• “TopjLevel”$Design
– Allows$Large$Design$Teams$to$Work$Concurrently

44
 Verilog$Example$with$Testbench
// Stimulus for simple circuit
module stimcrct;
reg A, B, C;
wire x, y;
circuit_with_delay cwd(A, B, C, x, y);
initial
begin
A=1’b0; B=1’b0; C=1’b0;
#100
A=1’b1; B=1’b1; C=1’b1;
#100 $finish;
end
endmodule

// Description of circuit with delay

module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
not #(10) g2(y,C);
or #(20) g3(x,e,y);
45
endmodule

always and$initial blocks

• Both$Types$of$Blocks$Contain$Procedural$
(Sequential)$Statements
• If$More$than$One$Procedural$Statement$
use$begin – end
• Always Block$is$Scheduled$to$
Simulate/Execute$at$EVERY$Simulation$
Time$Cycle
• Initial Block$is$Scheduled$to$Simulate$
Only$at$the$First$Time$Epoch 46
 Verilog$Simulation$with$Testbench
• Most$Simulators$Allow$for$Graphic$Timing$Diagrams$to$be$Used
– SynaptiCAD$(software$packaged$with$M.$Mano$textbook)
– ModelTech$(commercial$simulator$– free$at$www.model.com)
– Cadence$Verilog$XL$(commercial$tool)
– QuartusII$(builtjin$timing$simulator$with$Altera$toolset)

47

Model$Abstractions$in$Verilog
• Netlist$Level$Models
– Contain$enough$information$to$construct$in$lab
– structural$modeling
– Commonly$“Lowest”$level$of$abstraction$
– Useful$for$Transfer$Among$CAD$tools
• RTL$(register$transfer$language)$Level
– Composed$of$Boolean$Expressions$and$Registers
– Can$be$Automatically$Synthesized$to$a$netlist
– We$will$work$mostly$at$this$level
• Behavioral$Level
– Highjlevel$Constructs$that$only$Describe$
Functionality
– Automatic$Behavioral$Synthesis$Tools$do$Exist
48