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DTE Imp Questions

This document contains 30 important questions for an MSBTE exam covering 5 units: Unit 1 covers number systems, binary operations, and characteristics of logic families such as noise margin, power dissipation, and speed of operation. Unit 2 covers full and half adders, basic gates using NAND gates only, and De Morgan's theorem. Unit 3 covers designing full adders using K-maps, binary to gray code converters, expression minimization using K-maps, and multiplexer/demultiplexer trees. Unit 4 covers flip flop circuits like JK and RS flip flops, shift registers, counters, and ring counters. Unit 5 covers memory classification and comparisons of RAM and ROM, R

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Pushkar rane 1oth,B,ROLL NO.47
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5K views2 pages

DTE Imp Questions

This document contains 30 important questions for an MSBTE exam covering 5 units: Unit 1 covers number systems, binary operations, and characteristics of logic families such as noise margin, power dissipation, and speed of operation. Unit 2 covers full and half adders, basic gates using NAND gates only, and De Morgan's theorem. Unit 3 covers designing full adders using K-maps, binary to gray code converters, expression minimization using K-maps, and multiplexer/demultiplexer trees. Unit 4 covers flip flop circuits like JK and RS flip flops, shift registers, counters, and ring counters. Unit 5 covers memory classification and comparisons of RAM and ROM, R

Uploaded by

Pushkar rane 1oth,B,ROLL NO.47
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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GURU GOBIND SINGH POLYTECHNIC NASHIK

AY:2023-24

Course Name & Code – DTE(22320) Class: SYCO-A

IMP Questions for MSBTE Exam

Unit-1

1) Number system conversion. (Solve Practice Examples from notes)


2) Binary subtraction & addition (Solve Practice Examples from notes)
3) Perform BCD Addition (Solve Practice examples from notes)
4) Explain following characteristics w.r.t logic families.
i) Noise Margin
ii) Power dissipation
iii) Figure of merit
iv) Speed of operation
5) Compare TTL & CMOS logic families based on following
i) Propagation delay
ii) Power dissipation
iii) Fan-out
iv) Basic gate

Unit-2

6) Explain Full adder


7) Draw logic diagram of half adder circuit.
8) Draw basic gates AND, OR, NOT using NAND gate only
9) State and prove De-Morgan’s theorem

Unit-3

10) Design full adder using truth table and K-Map.


11) Design binary to gray code converter and write its truth table.
12) Expression minimization using K-map (Solve Practice Examples from notes)
13) Draw MUX tree / DEMUX tree (Solve Practice examples from notes)

Unit-4
14) Explain working of JK Flip Flop.
15) Describe the working of RS flip flop using NAND gates only.
16) Explain working of 4 bit Universal Shift Register.
17) Design Mod-6 asynchronous counter with truth table and logic.
18) Describe the working of 4 bit SISO shift register with diagram and waveform if input
is 01101.
19) Design 4 bit ripple counter using JK flip flop with truth table and waveforms.
20) Describe the working of Ring counter using D Flip Flop with diagram and waveforms
21) Design 3 bit synchronous counter using JK Flip Flop.
22) State the applications of Shift register.

Unit-5

23) Give classification of Memory and compare RAM & ROM.


24) Draw the circuit diagram of 4 bit R-2R ladder DAC and obtain its output voltage
expression.
25) Draw block diagram of programmable logic array
26) Draw & explain successive approximation ADC
27) Explain any 4 specifications of DAC / ADC
28) Calculate analog output voltage for 4 bit weighted register type DAC for inputs –
i)1011 ii)1001
Assume VFS (full scale voltage) is 5V.
29) State any 4 specifications of ADC.
VVIMP QUESTIONS
30) Compare – a) combinational logic circuit and sequential logic circuit
b) SRAM & DRAM
c) PROM, EPROM & EEPROM
d) Encoder & Decoder
e) Multiplexer & Demultiplexer
f) Volatile and Non Volatile
g) EPROM and EEPROM
h) Synchronous and Asynchronous counter

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