PCI-1753/1753E

96/192-bit Digital I/O Card

User's manual
Copyright
This documentation and the software included with this product are
copyrighted 1999 by Advantech Co., Ltd. All rights are reserved.
Advantech Co., Ltd. reserves the right to make improvements in the
products described in this manual at any time without notice.
No part of this manual may be reproduced, copied, translated or
transmitted in any form or by any means without the prior written
permission of Advantech Co., Ltd. Information provided in this
manual is intended to be accurate and reliable. However, Advantech
Co., Ltd. assumes no responsibility for its use, nor for any infringe-
ments of the rights of third parties which may result from its use.

Acknowledgments
PC-LabCard is a trademark of Advantech Co., Ltd. IBM and PC are
trademarks of International Business Machines Corporation. MS-
DOS and Windows are trademarks of Microsoft Corporation. Intel and
Pentium are trademarks of Intel Corporation.

CE Notification
The PCI-1753/1753E, developed by ADVANTECH CO., LTD., has
passed the CE test for environmental specifications when shielded
cables are used for external wiring. We recommend the use of
shielded cables. This kind of cable is available from Advantech.
Please contact your local supplier for ordering information.

On-line Technical Support

For technical support and service please visit our support website at
http://support.advantech.com

Part No. 2003175300 1st Edition

Printed in Taiwan May 1999
 Contents
CHAPTER 1 General Information ......................... 1
1.1 Introduction ........................................................... 2
1.2 Features .................................................................. 4
1.3 Applications ........................................................... 4
1.4 Specifications ....................................................... 5
1.5 Pin Assignments ..................................................... 6
1.6 Block Diagram ....................................................... 7

CHAPTER 2 Installation ......................................... 9

2.1 Initial Inspection ................................................... 10
2.2 Unpacking ............................................................ 10
2.3 Jumper Settings ..................................................... 11
2.4 Installation Instructions ........................................ 14

CHAPTER 3 Operation ......................................... 17

3.1 Overview .............................................................. 18
3.2 Digital I/O Ports ................................................... 18
3.2.1 Introduction ........................................................................................... 18
3.2.2 8255 Mode 0 .......................................................................................... 18
3.2.3 Input/Output Control ............................................................................ 19
3.2.4 Initial Configuration ............................................................................... 19
3.2.5 Dry Contact Support for Digital Input ................................................. 20
3.3 Interrupt Functions............................................... 21
3.3.1 Introduction ........................................................................................... 21
3.3.2 IRQ Level ............................................................................................... 21
 3.3.3 Interrupt Control Registers .................................................................... 21
3.3.4 Interrupt Source Control ........................................................................ 24
3.3.5 Interrupt Triggering Edge Control .......................................................... 25
3.3.6 Interrupt Flag Bit ................................................................................... 25
3.3.7 Pattern Match Interrupt Function ......................................................... 26
3.3.8 Change of State Interrupt Function ....................................................... 27

APPENDIX A Register Format of PCI-1753/

1753E ................................................................... 29
A.1 PCI-1753 Register Format ....................................................................... 30
A.2 PCI-1753E Register Format ..................................................................... 31

APPENDIX B Pin Assignments of Cable PCL-

10268 ................................................................... 33
 1

CHAPTER
General Information
1.1 Introduction
The PCI-1753 is a 96-bit digital I/O card for the PCI bus, which can
be extended to 192 digital I/O channels by connecting with its
extension board, PCI-1753E. The card emulates mode 0 of the 8255
PPI chip, but the buffered circuits offer a higher driving capability
than the 8255. The 96 I/O lines are divided into twelve 8-bit I/O
ports: A0, B0, C0, A1, B1, C1, A2, B2, C2, A3, B3 and C3. Users can
configure each port as input or output via software.

Easy to Install: Plug and Play

The PCI-1753 uses a PCI controller to interface the card to the PCI
bus. The controller fully implements the PCI bus specification Rev
2.1. All bus relative configurations, such as base address and inter-
rupt assignment, are automatically controlled by software.

Dry Contact Support for Digital Input

Each digital input channel at the PCI-1753/1753E accepts either 0 ~
5 VDC wet contact or dry contact inputs. This dry contact capability
allows the channel to respond to changes in external circuitry (e.g.,
the closing of a switch in the external circuitry) when no voltage is
present in the external circuit.

Reset Protection Fulfills the True Require-

ment of Industrial Applications
When the system is hot reset (the power is not turned off), the PCI-
1753/1753E can either retain the last I/O port settings and outputs
value, or return to its default configuration, depending on the jumper
setting. This function protects the system from wrong operations
during unexpected system resets.

Interrupt Functions Ensure Faster System

Response
Two lines of each port C (i.e., ports C0, C1, C2 and C3) are connected
to an interrupt circuit. The “Interrupt Control Register” of the PCI-

2 PCI-1753 User's Manual

1753/PCI-1753E controls how these signals generate an interrupt.
More than one interrupt request signals can be generated at the same
time, and then the software can process these request signals by ISR.
The multiple interrupt sources provide the card with more capability
and flexibility.
The PCI-1753/1753E also provides “Pattern Match” interrupt
function for port A0. The card monitors the states of port A0 and
compares them with a pre-set pattern. When the received state
matches the pre-set pattern, the PCI-1753/1753E generates an
interrupt signal to the system.
“Change of State” interrupt function is provided at port B0. When
any signal line of port B0 changes its state, the card generates an
interrupt to the system to handle this event.
These interrupt functions release the CPU from the burden of pulling
all I/O points, enabling a PC to handle more I/O points with higher
performance.

Cost Savings for Increasing the Number of

Input/Output Lines
Industrial users are needing more and more digital I/O lines to
transmit data or to monitor/control outside devices. To meet this
trend and to satisfy user’s budget considerations, Advantech has
developed an extension board for the PCI-1753 called the PCI-
1753E. The PCI-1753E has almost the same structure as the PCI-
1753, without the interface controller. It shares PCI-1753’s interface
controller through a 10-cm flat cable connecting, so users can spend
less money while doubling the number of input/output lines.

Accessories for PCI-1753/1753E

The PCI-1753/1753E uses a 100-pin SCSI female connector. For easy
signal wiring, a PCI-1753 can be connected to two ADAM-3968s by a
100-pin to 2x68-pin SCSI cable (part number PCL-10268). The
ADAM-3968 allows easy access for wiring the individual pins of a 68-
pin SCSI connector. An ADAM-3968/50 adapter board converts the
68-pin connector to two opto-22 compatible 50-pin box headers for
connecting the PCI-1753/1753E to daughterboards, such as PCLD-
782B and PCLD-785B.

Chapter 1 Gerneral Information 3

1.2 Features
• 96/192 TTL digital I/O lines
• Emulates mode 0 of 8255 PPI
• Buffered circuits for higher driving capacity than 8255
• Multiple-source interrupt handling
• Interrupt output pin for simultaneously triggering external devices
with the interrupt
• Output status read-back
• “Pattern match” and “Change of state” interrupt functions for
critical I/O monitoring
• Keeps I/O setting and digital output values when hot system reset
• Supports dry contact and wet contact
• High-density 100-pin SCSI connector

1.3 Applications
• Industrial AC/DC I/O devices monitoring and controlling
• Relay and switch monitoring and controlling
• Parallel data transfer
• TTL, DTL and CMOS logic signal sensing
• Indicator LED driving

4 PCI-1753 User's Manual

1.4 Specifications

96 digital I/O lines (PCI-1753 only)

I/O Channels
192 digital I/O lines (using PCI-1753E extension)
Programming Mode 8255 PPI mode 0
Logic level 0: 0.8 V max.
Input Signal
Logic level 1: 2.0 V min.
Logic level 0: 0.44 V max. @ 24 mA (sink)
Output Signal
Logic level 1: 3.76 V min. @ 24 mA (source)
1.6 Mbytes/sec (tested under DOS, K6 300MHz
Transfer Rate
CPU)
+5 V @ 400 mA (typical)
Power Consumption
+5 V @ 2.7 A (max.)
Operating Temperature 0 ~ +60°C (32 ~ 140°F) (refer to IEC 68-2-1, 2)

Storage Temperature -20 ~ +70°C (-4 ~ 158°F)

Operating Humidity 5 ~ 95%RH non-condensing (refer to IEC 68-2-3)

Connector One 100-pin SCSI female connector

PCI-1753: 175 x 100 mm (6.9" x 3.9")
Dimensions
PCI-1753E: 175 x 100 mm (6.9" x 3.9")

MTBF over 75,013 hrs @ 25°C, ground fix environment

Chapter 1 Gerneral Information 5

1.5 Pin Assignments

PA 00 1 51 PA 20
PA 01 2 52 PA 21 PA 00 ~ PA 07 : I/O pins of P o rt A 0
PA 02 3 53 PA 22
PA 03 4 54 PA 23 PA 10 ~ PA 17 : I/O pins of P o rt A 1
PA 04 5 55 PA 24
PA 05 6 56 PA 25 PA 20 ~ PA 27 : I/O pins of P o rt A 2
PA 06 7 57 PA 26
PA 07 8 58 PA 27 PA 30 ~ PA 37 : I/O pins of P o rt A 3
P B 00 9 59 P B 20
P B 01 10 60 P B 20 P B 00 ~ P B 07 : I/O pins of P ort B 0
P B 02 11 61 P B 22
P B 03 12 62 P B 23 P B 10 ~ P B 17 : I/O pins of P ort B 1
P B 04 13 63 P B 24
P B 05 14 64 P B 25 P B 20 ~ P B 27 : I/O pins of P ort B 2
P B 06 15 65 P B 26
P B 07 16 66 P B 27 P B 30 ~ P B 37 : I/O pins of P ort B 3
P C 00 17 67 P C 20
P C 01 18 68 P C 21 P C 00 ~ P C 07 : I/O pins o f P ort C 0
P C 02 19 69 P C 22
P C 03 20 70 P C 23 P C 10 ~ P C 17 : I/O pins o f P ort C 1
P C 04 21 71 P C 24
P C 05 22 72 P C 25 P C 20 ~ P C 27 : I/O pins o f P ort C 2
P C 06 23 73 P C 26
P C 07 24 74 P C 27 P C 30 ~ P C 37 : I/O pins o f P ort C 3
GND 25 75 GND
PA 10 26 76 PA 30 G N D : G round
PA 11 27 77 PA 31
PA 12 28 78 PA 32 V C C : + 5V voltage outp ut (1A m ax.)
PA 13 29 79 PA 33
PA 14 30 80 PA 34
PA 15 31 81 PA 35
PA 16 32 82 PA 36
PA 17 33 83 PA 37
P B 10 34 84 P B 30
P B 11 35 85 P B 31
P B 12 36 86 P B 32
P B 13 37 87 P B 33
P B 14 38 88 P B 34
P B 15 39 89 P B 35
P B 16 40 90 P B 36
P B 17 41 91 P B 37
P C 10 42 92 P C 30
P C 11 43 93 P C 31
P C 12 44 94 P C 32
P C 13 45 95 P C 33
P C 14 46 96 P C 34
P C 15 47 97 P C 35
P C 16 48 98 P C 36
P C 17 49 99 P C 37
VCC 50 100 VCC

6 PCI-1753 User's Manual

1.6 Block Diagram

Figure 1-1: PCI-1753/1753E Block Diagram

Chapter 1 Gerneral Information 7

8 PCI-1753 User's Manual
 2

CHAPTER
Installation

Chapter 2 Installation 9
2.1 Initial Inspection
Before starting to install the PCI-1753/1753E, make sure there is no
visible damage on the card. We carefully inspected the card both
mechanically and electrically before shipment. It should be free of
marks and in perfect order on receipt.
As you unpack the PCI-1753/1753E, check it for signs of shipping
damage (damaged box, scratches, dents, etc.). If it is damaged or fails
to meet its specifications, notify our service department or your local
sales representative immediately. Also, call the carrier immediately
and retain the shipping carton and packing materials for inspection
by the carrier. We will then make arrangements to repair or replace
the unit.

2.2 Unpacking
The PCI-1753/1753E contains components that are sensitive and
vulnerable to static electricity. Discharge any static electricity on
your body to ground by touching the back of the system unit
(grounded metal) before you touch the board.
Remove the PCI-1753/1753E card from its protective packaging by
grasping the card's rear panel. Handle the card only by its edges to
avoid static discharge which could damage its integrated circuits.
Keep the antistatic package. Whenever you remove the card from the
PC, please store the card in this package for its protection.
You should also avoid contact with materials that hold static electrici-
ty such as plastic, vinyl and styrofoam.
Check the product contents inside the packing. In PCI-1753's
package, there should be one card, one CD-ROM, and this manual; in
PCI-1753E's package, there should be one card and a 10-cm 20-pin
flat cable. Please make sure nothing is missing.

10 PCI-1753 User's Manual

2.3 Jumper Settings
We designed the PCI-1753/1753E with ease-of-use in mind. It is a
"plug and play" card, i.e. the system BIOS assigns the system resourc-
es such as base address and interrupt automatically. There are only
two functions with 17 jumpers on the PCI-1753, and one function
with 16 jumpers on the PCI-1753E. The following section describes
how to configure the card. You may want to refer to the figure below
for help in identifying card components.
CN2

CN1

JP 1 JP C 0 L
JP B0
JP C 0 H
JPA 0
JP C 1 L
JP B1
JP C 1 H
JPA 1
JP C 2 L
JP B2
JP C 2 H
JPA 2
JP C 3 L
JP B3
JP C 3 H
JPA 3

Figure 2-1: Location of connectors and jumpers

Jumper Settings to Set Ports as Input or

Output by Software
When the two pins of jumpers JPA0, JPB0, JPC0L, JPC0H, JPA1, JPB1,
JPC1L, JPC1H, JPA2, JPB2, JPC2L, JPC2H, JPA3, JPB3, JPC3L or
JPC3H are not shorted (i.e., by setting a jumper), the corresponding
ports are set to be configurable as input or output ports by software.
(JPA0 means jumper for port A0, JPB0 means jumper for port B0, etc.
See Table 2-1) If jumper JP1 is not enabled (i.e., by shorting the
upper two pins of JP1), all ports configured by software are automa-
tially set as input ports during system startup a reset, with a default
signal level of logic 1(high). (But see Jumper JP1 discussion below.)

Chapter 2 Installation 11
 Using Jumpers to Set Ports as Output Ports
By shorting the two pins of the jumpers JPA0, JPB0, JPC0L, JPC0H,
JPA1, JPB1, JPC1L, JPC1H, JPA2, JPB2, JPC2L, JPC2H, JPA3, JPB3,
JPC3L or JPC3H, a user sets the corresponding ports to be output
ports. (JPA0 means jumper for port A0, JPB0 means jumper for port
B0, etc.) Shorting the two pins of a port's jumper disables the port
from being software configurable as an input port. The initial state of
each of these ports after system power on or reset will be logic 0
(voltage low), unless jumper JP1 determines otherwise. (See Jumper
JP1 below.)

Jumper JP1 Restores Ports to Their Condi-

tion Prior to Reset
Jumper JP1 gives the PCI-1753/1753E a new and valuable capability.
With JP1 enabled (i.e., by shorting the lower two pins of JP1), the PCI-
1753/1753E "memorizes" all port I/O settings and output values, and,
in the event of a "hot" reset, the settings and output values present at
the port just prior to reset are restored to each port following reset.
This feature applies to both ports set by software, and to ports
configured as output ports via jumper. Depending on the application,
this capability may allow a card to be reset without requiring a
complete shutdown of processes controlled by the card (since port
values are left unchanged and are interrupted only momentarily).
Complete loss of power to the chip clears chip memory. Thus, even if
JP1 is enabled, if the power to the card is disconnected, the card's
initial power-on state will be the state of an input port with voltage
high input (for software-set ports) or the state of an output port with
voltage low output (for jumper-set ports).
When jumper JP1 is not enabled (i.e., by shorting the upper two pins
of JP1), both power-off and reset results in ports returning to the state
of an input port with voltage high input (for software-set ports) or
returning to the state of output port with voltage low output (for
jumper-set ports).

12 PCI-1753 User's Manual

 Table 2-1: Summary of jumper settings

Names of Jumpers Function description

JPA0, JPA1, JPA2 and JPA3: Jumpers for
ports A0, A1, A2 and A3

JPB0, JPB1, JPB2 and JPB3: Jumpers for Sets port as an output port
ports B0, B1, B2 and B3

JPC0L, JPC1L, JPC2L and JPC3L: Jumpers

for low nibble of ports C0, C1, C2 and C3
Sets port to be software
JPC0H, JPC1H, JPC2H and JPC3H: configurable as input or
Jumpers for high nibble of ports C0, C1, C2 output (default)
and C3

Enables the reset

1 protection function.
All ports return to the state
held just prior to reset

JP1
Disables the reset
1 protection function.
All ports return to the default
state (for software-set) or to
output port, output low (for
jumper-set ports) (default)

Chapter 2 Installation 13
2.4 Installation Instructions
The PCI-1753/1753E can be installed in any PCI slot in the computer.
However, refer to the computer user's manual to avoid any mistakes
and danger before you follow the installation procedure below:
1. Turn off your computer and any accessories connected to the
computer.

Warning!: TURN OFF your computer power supply whenever

you install or remove any card, or connect and
disconnect cables.

2. Disconnect the power cord and any other cables from the back of
the computer.
3. Remove the cover of the computer.
4. Select an empty 5 V PCI slot. (If you also need to intall the
extension board, the PCI-1753E, to control more than 96 I/O points,
please find two adjacent 5V PCI slots.) Remove the screw that
secures the expansion slot cover to the system unit. Save the screw
to secure the interface card retaining bracket.
5. Carefully grasp the upper edge of the PCI-1753. Align the hole in
the retaining bracket with the hole on the expansion slot and align
the gold striped edge connector with the expansion slot socket.
Press the card into the socket gently but firmly. Make sure the card
fits the slot tightly.
5.1. Repeat Step 5 for the PCI-1753E.
5.2. Connect the PCI-1753 and PCI-1753E with the 10-cm 20-pin flat
cable, which is shipped with the PCI-1753E.

Caution!: Please note that the first pin* of the cable connector
should match the first pin* of the connector CN2 on
the PCI-1753/1753E. (* first pin as marked by the
arrow on each connector

14 PCI-1753 User's Manual

6. Secure the PCI-1753/1753E card by screwing the mounting bracket
to the back panel of computer.
7. Attach any accessories (100-pin cable, wiring terminal board, etc.)
to the card.
8. Replace the cover of your computer. Connect the cables you
removed in step 2.
9. Turn the computer power on.

Chapter 2 Installation 15
16 PCI-1753 User's Manual
 3

CHAPTER
Operation

Chapter 3 Function Description 17

3.1 Overview

This chapter describes the operating characteristics of the PCI-1753/

1753E. The driver software bundled with this card allows a user to
access all of the card's functions without register level programming.
Please see the User's Manual included on the driver CD-ROM for
more information. For users who prefer to implement their own bit-
level programming to drive the card's functions, information useful
for making such a program is included in this chapter.

3.2 Digital I/O Ports

3.2.1 Introduction
The PCI-1753 and 1753E each emulate four 8255 programmable
peripheral interface (PPI) chips in mode 0, but with higher driving
capability than a standard 8255 chip. Each of these 8255 chip
emulators has 24 programmable I/O pins that are divided into three 8-
bit ports. The total 96 digital I/O pins on either the PCI-1753 or the
PCI-1753E are divided into 12 ports, designated PA0, PB0, PC0, PA1,
PB1, PC1, PA2, PB2, PC2, PA3, PB3 and PC3. Each port can be
programmed as an input or an output port. The I/O pins in port A0 are
designated PA00, PA01,..., PA07; the pins in port B0 are designated
PB00, PB01,..., PB07, etc. These port names are used both in this
manual and in the software library. Please refer to Section 1.5, Pin
Assignments.

3.2.2 8255 Mode 0

The basic 8255 mode 0 features included on the PCI-1753/1753E
cards are:
• 8-bit I/O ports - port A (PA) and port B (PB)
• Port C is divided into two nibble-wide (4-bit) I/O ports - PC upper
and PC lower
• Any port can be used for either input or output.
• Output status can be read back.

18 PCI-1753 User's Manual

3.2.3 Input/Output Control
A control word can be written to a port's configuration register
(Base+3, 7, 11 and 15 respectively for ports 0, 1, 2 and 3 on the PCI-
1753, and Base+35, 39, 43 and 47 respectively for ports 0, 1, 2 and 3
on the PCI-1753E) to set the port as an input or an output port, unless
the ports are set as output ports via jumpers (refer to Section 2.3,
Jumper Settings). Table 3-1 shows the format of a control word.
Table 3-1: Bit map of port configuration register

D7 D6 D5 D4 D3 D2 D1 D0

Not Not Not Port A Port C Not Port B Port C

read read read 0: output upper bits read 0: output lower bits
1: input 0: output 1: input 0: output
1: input 1: input

Note!: A control word has no effect if the corresponding port is

set as an output port by a jumper.

Warning! Before setting any port as an output port via soft-

ware, make sure that a safe output value has also
been set. An output voltage will appear at the pins
immediately following the control word taking effect.
If no output value was specified, the value will be
indeterminate (either 0 or 1), which may cause a
dangerous condition.

3.2.4 Initial Configuration

The initial configuration of each port depends on the input/output
jumper setting of each port, on the setting of the jumper JP1, and on
whether the power was actually disconnected or whether the system
was hot reset.
If jumper JP1 is not enabled, all ports configured by software are
automatically set as input ports during system start up or reset, with a
default signal level of logic 1 (high). All ports set via jumpers as
output ports are set as output ports during system start up or reset,
signal level logic 0 (0 V).

Chapter 3 Function Description 19

 If the jumper JP1 is enabled and the initial configuration is caused by
a reset, all ports will return to the states they had just prior to the reset.
The reset must be a "hot" reset (power not disconnected) for enabled
JP1 to return ports to their prior values. Otherwise, the card behaves
as though JP1 were not enabled. Please refer to "Jumper settings" in
Chapter 2 for more information.

3.2.5 Dry Contact Support for Digital Input

Each digital input channel accepts either dry contact or 0 ~ 5 VDC wet
contact inputs. Dry contact capability allows the channel to respond
to changes in external circuitry (e.g., the closing of a switch in the
external circuitry) when no voltage is present in the external circuit.
Figure 3-1 shows external circuitry with both wet and dry contact
components, connected as an input source to one of the card's digital
input channels.

External Internal
PC 5V

10 K Ω

1.5 K Ω Buffer
0.5 W
Dry Contact: Open High
Close Low
Resistor
in Wet Contact: 2.0~5.25 V D C High
Parallel 0~0.8 V D C Low

Figure 3-1: Wet and dry contact inputs

Note!: For wet contact configurations, a malfunction may occur

if the internal resistance of the voltage source is signifi-
cant (> 1.5 kΩ). It is advisable to connect a 1.5 kΩ
resistor in parallel with such a voltage source to avoid a
voltage rise inside the voltage source.

20 PCI-1753 User's Manual

3.3 Interrupt Functions

3.3.1 Introduction
Two lines of each I/O port C, plus ports A0 and B0, are connected to
the interrupt circuitry. The “Interrupt Control Register” of the PCI-
1753/1753E controls how the combination of these signals generates
an interrupt. Six interrupt request signals can be generated at the
same time, and then the software can service these six request signals
by IRQ. The multiple interrupt sources provide the card with more
capability and flexibility.

3.3.2 IRQ Level

The IRQ level is set automatically by the PCI plug-and-play BIOS
and is saved in the PCI controller. There is no need for users to set the
IRQ level. Only one IRQ level is used by this card, although it has six
interrupt sources.

3.3.3 Interrupt Control Registers

The “Interrupt Control Registers” (Base + 16, 17, 18 and 19 for the
PCI-1753, and Base + 48, 49, 50 and 51 for the PCI-1753E) control
the interrupt signal sources, edges and flags. The following table
shows the bit map of each interrupt control register. These registers
are readable/writable. When writing to one of them, it is used as a
control register, and when reading from it, it is used as a status
register.

Chapter 3 Function Description 21

 Table 3-2: Interrupt control register bit map
Base+16/48 Port 0
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Abbreviation F0 E0 M01 M00 F02 M2 F01 M1
Base+17/49 Port 1
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Abbreviation F1 E1 M11 M10 - - - -
Base+18/50 Port 2
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Abbreviation F2 E2 M21 M20 - - - -
Base+19/51 Port 3
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Abbreviation F3 E3 M31 M30 - - - -

Mn0 and Mn1: “mode bits” of port Cn (n = 0 ~ 3)

M1: pattern match port enable control bit of port A0
M2: change of state port enable control bit of port B0
En: triggering edge control bit (n = 0 ~ 3)
Fn: interrupt flag bit of port Cn (n = 0 ~ 3)
F01: pattern patch interrupt flag bit of port A0
F02: change of state interrupt flag bit of port B0

22 PCI-1753 User's Manual

 M 0 1 :M 0 0
0 0

PC00 0 1

1 0
PC04
1 1

M 11 :M 1 0
0 0

PC10 0 1

1 0
PC14
1 1 VCC

M 2 1 :M 2 0
0 0 D Q
PC20 0 1

1 0 CLK
PC24
1 1

M 3 1 :M 3 0 IN T # A
0 0

PC30 0 1

1 0
PC34
1 1

M1
0

P attern m atch (PA 0 ) 1

M2
0

S tate ch an g e (P B 0) 1

Figure 3-2: Interrupt sources

Chapter 3 Function Description 23

 3.3.4 Interrupt Source Control
The “mode bits” in the interrupt control registers determine the
allowable sources of signals generating an interrupt. For the PCI-
1753, bit 4 and bit 5 of Base+16 determines the interrupt source of
port C0, bit 4 and bit 5 of Base+17 determines the interrupt source for
port C1, and so forth. Because of sharing the same PCI controller
with the PCI-1753, the PCI-1753E’s interrupt sources are also con-
trolled by the PCI-1753’s interrupt control register. Bit 4 and bit 5 of
Base+48 determines the interrupt source of port C0 on the PCI-
1753E, bit 4 and bit 5 of Base+49 determines the interrupt source of
port C1, and so forth. Please refer the table in Appendix A to find the
corresponding address for the interrupt source control of each port C.

The following table shows the relationship between an interrupt

source and the values in the mode bits.

Table 3-3: Interrupt mode bit values

Base+16/48 Port 0 Base+17/49 Port 1

M01 M00 Description M11 M10 Description
0 0 Disable interrupt 0 0 Disable interrupt
0 1 Source = PC00 0 1 Source = PC10
Source = PC00 and Source = PC10 and
1 0 1 0
PC04 PC14
1 1 Disable interrupt 1 1 Disable interrupt
Base+18/50 Port 2 Base+19/51 Port 3
M21 M20 Description M31 M30 Description
0 0 Disable interrupt 0 0 Disable interrupt
0 1 Source = PC20 0 1 Source = PC30
Source = PC20 and Source = PC30 and
1 0 1 0
PC24 PC34
1 1 Disable interrupt 1 1 Disable interrupt

24 PCI-1753 User's Manual

3.3.5 Interrupt Triggering Edge Control
The interrupt can be triggered by a rising edge or a falling edge of the
interrupt signal, selectable by the value written in the “triggering
edge control” bit in the interrupt control register, as shown in follow-
ing table.

Table 3-4: Triggering edge control bit values

En (n = 0 ~ 3) Triggering edge of interrupt signal

1 Rising edge trigger

0 Falling edge trigger

3.3.6 Interrupt Flag Bit

The “interrupt flag” bit is a flag indicating the status of an interrupt.
It is a readable and writable bit. Read the bit’s value to find the status
of the interrupt; write “1” to this bit to clear the interrupt. This bit
must be cleared in the ISR to service the next incoming interrupt.

Table 3-5: Interrupt flag bit values

F01, F02 and Fn (n = 0 ~ 3) Interrupt Status

Read 1 Interrupt exists
0 No interrupt
Write 1 Clear interrupt
0 Don’t care

F01: pattern patch interrupt flag bit of port A0

F02: change of state interrupt flag bit of port B0
Fn: interrupt flag bit of port Cn (n = 0 ~ 3)

Chapter 3 Function Description 25

 3.3.7 Pattern Match Interrupt Function
The PCI-1753/1753E provides the pattern match interrupt function
for port A0. It monitors the status of the enabled input channels,
which are chosen in Base+24 (or Base+56 for the PCI-1753E), and
compares the received state values with the pre-set state values
written in Base+20 (Base+52 for the PCI-1753E). When the actual
state values match the pre-set state values, the PCI-1753 will deliver
an interrupt signal to the system. This function releases the CPU from
the burden of polling all of the I/O points, enabling a PC to handle
more I/O points with higher performance. The following is an
example.

Example 3.1 Assume that the pattern match function for the I/O
channels PA01, PA02, PA06 and PA07 of the PCI-1753 is enabled (i.e.
PA00, PA03, PA04 and PA05 on the PCI-1753 and port A0 on the PCI-
1753E are ignored during the pattern match monitoring process). The
user can set the pattern match values for the enabled input channels,
and these will be compared to the actual channel states of the enabled
channels. The following is an example.

a) First, enable the pattern match interrupt function for channels

PA01, PA02, PA06 and PA07

Bit # 7 6 5 4 3 2 1 0

Base+24 1 1 0 0 0 1 1 0

b) Write the pre-set pattern-match state of the enabled channels

Bit # 7 6 5 4 3 2 1 0

Base+20 1 0 X X X 1 1 X

26 PCI-1753 User's Manual

c) Finally, enable the pattern match function for port A0 of the PCI-
1753 by writing a “1” in bit 0 of Base+16.

M1 Description
1 Enable the pattern match interrupt function for port A0
0 Disable the pattern match interrupt function for port A0

d) When the input signals at channels PA01, PA02 and PA07 are high
and PA06 is low, an interrupt signal will be generated. This result is
not affected by the states of channels PA00, PA03, PA04 and PA05.

3.3.8 Change of State Interrupt Function

The PCI-1753/1753E also provides the change of state interrupt
function for port B0. It monitors the status of the enabled channels of
port B0, which are chosen in Base+28 (or Base+60 for the PCI-
1753E). When one of the enabled channels changes its state, the PCI-
1753 delivers an interrupt signal to the system to handle this event.
The following is an example.

Example 4.2 Assume that the change of state interrupt function for
the I/O channels PB01, PB02, PB06 and PB07 on the PCI-1753E are
enabled (i.e. the signals in PB00, PB03, PB04 and PB05 on the PCI-
1753E and port B0 of the PCI-1753 are ignored during the change of
state process). When a change of state occurs in either PB01 or PB02
or PB06 or PB07, an interrupt signal will be delivered to the system.
a) First, enable the change of state interrupt function for PB01, PB02,
PB06 and PB07 of the PCI-1753E.

Bit # 7 6 5 4 3 2 1 0

Base+60 1 1 0 0 0 1 1 0

Chapter 3 Function Description 27

 b) Then, enable the change of state interrupt function for port B0 of
the PCI-1753E by writing a “1” in bit 2 of Base+48.

M2 Description
1 Enable the change of state interrupt function for port A0
0 Disable the change of state interrupt function for port A0

c) When a change of state occurs in PB01 or PB02 or PB06 or PB07

on the PCI-1753E, an interrupt signal is generated.

28 PCI-1753 User's Manual

 A

APPENDIX
Register Format of
PCI-1753/1753E

Appendix A Calibration 29
A.1 PCI-1753 Register Format

Base Function
Address
+ (Decimal) Read Write

0 Port A0 Port A0

1 Port B0 Port B0

2 Port C0 Port C0

3 Port 0 Configuration Register

4 Port A1 Port A1

5 Port B1 Port B1

6 Port C1 Port C1

7 Port 1 Configuration Register

8 Port A2 Port A2

9 Port B2 Port B2

10 Port C2 Port C2

11 Port 2 Configuration Register

12 Port A3 Port A3

13 Port B3 Port B3

14 Port C3 Port C3

15 Port 3 Configuration Register

16 Interrupt Control Register for Port 0 Interrupt Control Register for Port 0

17 Interrupt Control Register for Port 1 Interrupt Control Register for Port 1

18 Interrupt Control Register for Port 2 Interrupt Control Register for Port 2

19 Interrupt Control Register for Port 3 Interrupt Control Register for Port 3

20 Pattern Match Value Register for Port A0

24 Pattern Match Enable Register for Port A0

28 Change of State Enable Register for Port B0

30 PCI-1753 User's Manual

A.2 PCI-1753E Register Format

Base Function
Address
+ (Decimal) Read Write

32 Port A0 Port A0

33 Port B0 Port B0

34 Port C0 Port C0

35 Port 0 Configuration Register

36 Port A1 Port A1

37 Port B1 Port B1

38 Port C1 Port C1

39 Port 1 Configuration Register

40 Port A2 Port A2

41 Port B2 Port B2

42 Port C2 Port C2

43 Port 2 Configuration Register

44 Port A3 Port A3

45 Port B3 Port B3

46 Port C3 Port C3

47 Port 3 Configuration Register

48 Interrupt Control Register for Port 0 Interrupt Control Register for Port 0

49 Interrupt Control Register for Port 1 Interrupt Control Register for Port 1

50 Interrupt Control Register for Port 2 Interrupt Control Register for Port 2

51 Interrupt Control Register for Port 3 Interrupt Control Register for Port 3

52 Pattern Match Value Register for Port A0

56 Pattern Match Enable Register for Port A0

60 Change of State Enable Register for Port B0

Appendix A Calibration 31
32 PCI-1753 User's Manual
 B

APPENDIX
Pin Assignments of Cable
PCL-10268

Appendix A Calibration 33
 CON1
CON0
PIN 01 1 35 PIN 26
PIN 02 2 36 PIN 27
PIN 03 3 37 PIN 28
Port A0 PIN 04 4 38 PIN 29 Port A1
PIN 01 1 51 PIN 51 PIN 05 5 39 PIN 30
PIN 02 2 52 PIN 52 PIN 06 6 40 PIN 31
PIN 07 7 41 PIN 32
PIN 03 3 53 PIN 53 PIN 08 8 42 PIN 33
PIN 04 4 54 PIN 54 9 43
PIN 09 10 44 PIN 34
PIN 05 5 55 PIN 55 PIN 10 11 45 PIN 35
PIN 06 6 56 PIN 56 PIN 11 12 46 PIN 36
PIN 07 7 57 PIN 57 PIN 12 13 47 PIN 37 Port B1
Port B0 PIN 13 14 48 PIN 38
PIN 08 8 58 PIN 58 PIN 14 15 49 PIN 39
PIN 09 9 59 PIN 59 PIN 15 16 50 PIN 40
PIN 10 10 60 PIN 60 PIN 16 17 51 PIN 41
18 52
PIN 11 11 61 PIN 61 PIN 17 19 53 PIN 42
PIN 12 12 62 PIN 62 PIN 18 20 54 PIN 43
PIN 19 21 55 PIN 44
PIN 13 13 63 PIN 63 PIN 20 22 56 PIN 45
PIN 21 Port C1
PIN 14 14 64 PIN 64 Port C0 23 57 PIN 46
PIN 15 15 65 PIN 65 PIN 22 24 58 PIN 47
PIN 23 25 59 PIN 48
PIN 16 16 66 PIN 66 PIN 24 26 60 PIN 49
PIN 17 17 67 PIN 67 PIN 25 27 61
28 62
PIN 18 18 68 PIN 68 29 63
PIN 19 19 69 PIN 69 30 64
20 70 PIN 70 31 65
PIN 20 32 66
PIN 21 21 71 PIN 71 33 67
V CC PIN 50 34 68
PIN 22 22 72 PIN 72
PIN 23 23 73 PIN 73
PIN 24 24 74 PIN 74
PIN 25 25 75 PIN 75
PIN 26 26 76 PIN 76 CON2
PIN 27 27 77 PIN 77
PIN 28 28 78 PIN 78
PIN 51 1 35 PIN 76
PIN 29 29 79 PIN 79 PIN 52 2 36 PIN 77
PIN 30 30 80 PIN 80 PIN 53 3 37 PIN 78
31 81 PIN 81 PIN 54 4 38 PIN 79 Port A3
PIN 31 Port A2 PIN 55 5 39 PIN 80
PIN 32 32 82 PIN 82 PIN 56 6 40 PIN 81
PIN 33 33 83 PIN 83 PIN 57 7 41 PIN 82
PIN 58 8 42 PIN 83
PIN 34 34 84 PIN 84 9 43
PIN 35 35 85 PIN 85 PIN 59 10 44 PIN 84
PIN 60 11 45 PIN 85
PIN 36 36 86 PIN 86 PIN 61 12 46 PIN 86
PIN 37 37 87 PIN 87 Port B2 PIN 62 13 47 PIN 87 Port B3
PIN 63 14 48 PIN 88
PIN 38 38 88 PIN 88 PIN 64 15 49 PIN 89
PIN 39 39 89 PIN 89 PIN 65 16 50 PIN 90
PIN 40 40 90 PIN 90 PIN 66 17 51 PIN 91
18 52
PIN 41 41 91 PIN 91 PIN 67 19 53 PIN 92
PIN 42 42 92 PIN 92 PIN 68 20 54 PIN 93
PIN 69 21 55 PIN 94
PIN 43 43 93 PIN 93 PIN 70 22 56 PIN 95 Port C3
PIN 44 44 94 PIN 94 Port C2 PIN 71 23 57 PIN 96
PIN 72 24 58 PIN 97
PIN 45 45 95 PIN 95 PIN 73 25 59 PIN 98
PIN 46 46 96 PIN 96 PIN 74 26 60 PIN 99
PIN 47 47 97 PIN 97 PIN 75 27 61
28 62
PIN 48 48 98 PIN 98 29 63
PIN 49 49 99 PIN 99 30 64
31 65
PIN 50 50 100 PIN 100 32 66
33 67
V CC PIN 100 34 68

* CON0, CON1 and CON2 are female Connectors

34 PCI-1753 User's Manual