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Performance comparison review of 8–3 compressor on FPGA

Conference Paper · November 2017

DOI: 10.1109/TENCON.2017.8228275

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 Proc. of the 2017 IEEE Region 10 Conference (TENCON), Malaysia, November 5-8, 2017

PERFORMANCE COMPARISON REVIEW OF 8-3 COMPRESSOR

ON FPGA
Yuhao Leong, HaiHiung Lo, Micheal Drieberg, Abu Bakar Sayuti, and Patrick Sebastian ∗
[email protected], (lo haihiung, mdrieberg, sayutis, patrick sebastian)@utp.edu.my

Abstract— Compressors are commonly utilized in multipliers to have high latencies [10], [11]. Adders that are generally
for reducing partial products in a parallel manner. In this used to shorten the critical path can cause uneven signal
paper 7-3, 7-4, 8-3, 8-4, 9-3, and 9-4 compressors designed transition and glitches. Furthermore, a higher number of
with adder circuits or multiplexer circuits were implemented
in Altera EP2C70F896 FPGA and their performance compared adder stages is required to reduce the partial product [1],
in terms of number of logic gates used, cell area and power [8], [12]. To overcome these issues, compressors are used
delay product (PDP) for an optimum recommendation for the in multiplier design as it provides a regular structure in the
implementation of 8-3 compressor design in FPGA. stage of partial product reduction [5]. A compressor is a
Keywords: Compressor, Full and Half Adder, Multiplexer circuit that consist of a combinatorial device that reduces
I. INTRODUCTION a large number of inputs to a smaller number of outputs
by utilizing accumulation method in a parallel manner [10],
Advancement of computer system performance has flat- [11], [12], [13] while simultaneously decreasing the stage
tened out as fabrication technology is reaching its physical operations [3], [7], [8]. In general, a compressor consists of
limit. Therefore there is a need to review circuit designs in half adders and full adders [1], [2], [3], [5].
search of possible improvement in order to meet the demand In this paper, high order compressors (7-3, 7-4, 8-3, 8-
of the future for faster computing. One potential area for 4, 9-3, and 9-4) design were performed and implemented
improvement is in the multiplier unit design. Typically, com- in Altera EP2C70F896 FPGA to verify and compare their
pressors are used in high speed addition and multiplication performances in terms of Power Delay Product (PDP),
unit design in microprocessor. Thus, a faster compressor Energy Delay Product (EDP), Cell Area, and Critical Path
unit would result in an improvement in the latter for future Propagation delay. From the performance comparison, an
computer architecture systems design. optimum design would be recommended for implementation
Multiplication can be considered as a complicated and in FPGA.
time-consuming arithmetic operation. Nevertheless, it is the
key operation in most of the signal processing algorithm [1], II. R ELATED W ORKS
[2], [3], [4]. Generally, the process of multiplication can be A. 9-4 COMPRESSORS
split into three stages: generating partial product, reducing
R.Marimuthu, et al. [1] proposed an 9-4 compressor using
partial product, and computing final product [2], [3], [5], [6].
5 Full Adders and 2 half adder as shown in Figure 2. Its
The partial product generation and final product computation
implementation results are shown in TABLE I, where it was
concept is shown in Figure 1.
compared to a 8-4 compressor. From the table, it shows
that the higher order compressors consume more power,
have longer critical path propagation delay and larger cell
area of compressor. This is because the 9-4 compressor
contains more logic gates than the 8-4 compressor which
are 2 AND gates and 1 XOR gate. By increasing the number
of logic gates in higher order compressors, the critical path
propagation delay of the compressors is increased by 5.66%
contributing to higher power consumed and larger area of
cell.
B. 8-4 COMPRESSORS
Fig. 1. Partial Product Generation and Final Product Computation R.Marimuthu, et al. [1] proposed an 8-4 compressor using
10 multiplexers and 1 half adder as shown in Figure 3. Its
In VLSI circuit, the stage of reducing partial product can implementation results are shown in TABLE II, where it
greatly reduce the performance of multiplier from the aspect was compared to a conventional compressor. From the table,
of power consumption and speed [5], [7], [8], [9]. A long it shows that the compressors using multiplexers are more
critical path during addition causes partial product reduction energy and power efficient. However, the critical path prop-
∗ Department of Electrical and Electronics Engineering, Universiti agation delay and cell area of compressor using multiplexer
Teknologi PETRONAS, 32610 Seri Iskandar, Perak, Malaysia is larger than compressor using half and full adder. It shows

978-1-5090-1134-6/17/$31.00 ©2017 IEEE 2462

 Proc. of the 2017 IEEE Region 10 Conference (TENCON), Malaysia, November 5-8, 2017

TABLE II
P ERFORMANCE C OMPARISON OF 8-4 C OMPRESSOR [1]

C. 7-3 COMPRESSORS
Nirlakalla et al. [2] proposed a (7:3) compressor which
consisted of 4 full adders. He proved that 16-T full adder
showed lowest PDP and EDP at gate level proving that it is
the most energy efficient if compared to the other 4 types of
adders mentioned in his paper. However, The research done
Fig. 2. Implementation of 9-4 Compressor using Half and Full Adder [1]
by Nirlakalla did not take into account the aspect of fan-in
and area and these 2 aspects are vital since the fan-in of logic
TABLE I
gates or area of compressors increase, the cost increases.
P ERFORMANCE C OMPARISON OF 8-4 C OMPRESSOR AND 9-4
C OMPRESSOR [1] D. 8-3 COMPRESSORS
Dandapat et al. [3] proposed an 8:3 compressor design
that is illustrated in Figure 4, which is a general structure
of m:3 compressors. The implementation results with a final
ripple adder is listed in TABLE III which indicates lower
data arrival time, lower power consumption, lower PDP and
fewer connections compared to 8:2 compressor. A hybrid 8:3
wide compressor is shown in Figure 5 has larger total cell
area which will limit the deployment of m:3 compressors
within a limited area.
that the critical path of a compressor using multiplexer is
4.18% longer than compressor using half and full adder.

Fig. 4. The Overall Proposed Structure of m:3 Compressor[3]

E. 7-2 Compressor
Rouholamini et. al. [13] proposed a 7:2 compressor that
consist of 5 units of 3:2 compressors compared to a conven-
tional 7:2 compressors that has 4 units of 3:2 compressors
and a final adder is shown in Figure 6. Referring to TABLE
IV, the proposed 7:2 compressor has shown improvements
in terms of power consumption from 0.07% (at 3.5V) to
maximum of 11% (at 1.2V) and speed from 19% (at 3.5V) to
23% (at 1.2V) with respect to conventional 7:2 compressor
Fig. 3. Implementation of 8-4 Compressor using Multiplexer[1] on low voltage. Therefore, in terms of PDP, the proposed
7:2 compressor has lower value than the conventional 7:2
compressor.

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 Proc. of the 2017 IEEE Region 10 Conference (TENCON), Malaysia, November 5-8, 2017

Fig. 5. 8:3 Hybrid Wide Compressor[14]

TABLE III
I MPLEMENTATION R ESULTS WITH F INAL R IPPLE A DDER [3]

Fig. 6. The Overall Proposed Structure of 7:2 Compressor[13]

compressor is better than 7-3 MUX-XOR compressor as it

has 1 fewer number of logic gates used, 0.50% smaller cell
area, 9.03% lower power consumption, and 32.63% lower
power delay product. The same observation is also made for
the 8-4 compressors, where the performance of 8-4 adders
TABLE IV compressor is better than 8-4 MUX-XOR compressor as it
E VALUATION OF P ROPOSED 7:2 C OMPRESSOR WITH RESPECT TO has 30 fewer number of logic gates used, 15.92% smaller
C ONVENTIONAL 7:2 C OMPRESSOR [13] cell area, 5.13% lower power consumption, and 1.00% lower
power delay product.
TABLE V also shows that the 9-4 compressors imple-
mented with adders has 32 fewer logic gates used, 6.80%
lower critical path propagation delay, 8.91% smaller cell
area, 10.68% lower power consumption, and 16.75% lower
power delay product than the 9-4 compressors implemented
with MUX and XOR.
IV. CONCLUSIONS
From our results, it seems to be preferable to use adders
III. R ESULTS AND D ISCUSSIONS for compressor circuits design instead of the combination of
multiplexers and XOR gates with the trade off of a minor
TABLE V shows the overall compressor types and its
increases in propagation delay but provided significantly less
performance. In this table, the 7-3, 8-3, 8-4, 9-3, and 9-
logic gates, lower compressors power consumption, smaller
4 compressors implemented with Full and Half Adders are
compressor cell area, and lower power delay product.
compared with its corresponding MUX-XOR implementa-
tion for their total number of logic gates used, critical
path propagation delay, power delay product, cell area, and
power consumption . To have better understanding of the
comparison table, the 7-3, 8-4, and 9-4 compressors will be
discussed as below.
Our result shows that the performance of 7-3 Adder

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 Proc. of the 2017 IEEE Region 10 Conference (TENCON), Malaysia, November 5-8, 2017

TABLE V
S UMMARY OF C OMPRESSOR T YPES AND T HEIR P ERFORMANCE

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