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Experiment 1

The document describes the design and simulation of various logic gates like AND, OR, XOR, XNOR, NAND and NOR gates using dataflow, behavioral and structural modeling styles in Xilinx Vivado HLS. Code examples and output waveforms are provided for each logic gate modeled using the different styles.

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chinusood08
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19 views42 pages

Experiment 1

The document describes the design and simulation of various logic gates like AND, OR, XOR, XNOR, NAND and NOR gates using dataflow, behavioral and structural modeling styles in Xilinx Vivado HLS. Code examples and output waveforms are provided for each logic gate modeled using the different styles.

Uploaded by

chinusood08
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Experiment-1

Name-Saiyamsood
Roll no-21104091

AIM : Design of different logic gates such as: AND gate,


OR gate, EX-OR gate, EX-NOR gate, NOR gate and
NAND gate using “Dataflow”, “Behavioural” and
“Structural modelling” styles.
Software: Xilinx(Vivardo HLS)
Program Code:
(I) And Gate
AND Gate using Data Flow :
module andGate_Saiyam_21104091(a,b,c);
Input a,b;
output c;
assign c = a&b;
endmodule
AND Gate simulation using data flow :
module andGate_;
reg a;
reg b;
// Outputs
wire c;
andGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule
Structure::
WaveForm:

AND Gate using behavioural modelling:


module andGate_Saiyam_21104091(a , b , c);
Input a , b;
output c;
reg c;
always@(a or b)
begin
case({a,b})
2'b00: begin
c=1'b0;
End
2'b01: begin
c=1'b0;
End
2'b10:begin
c=1'b0;
end
2'b11: begin
c=1'b1;
End
default:begin
c=1'b0;
end
endcase
End
Endmodule

AND Gate simulation using behavioural modelling:


module andGate_;
reg a;
reg b;
// Outputs
wire c;
andGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:
Waveform:

AND Gate Using Structural modelling:


module andGate_Saiyam_21104091(a,b,c);
Input a,b;
output c;
and(c,a,b);
Endmodule
AND Gate Simulation Using Structural modelling:
module andGate_;
reg a;
reg b;
// Outputs
wire c;
andGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:

WaveForm:
(II) OR Gate
OR gate using data flow:
module orGate_Saiyam_21104091(a,b,c);
Input a,b;
output c;
assign c = a | b;
Endmodule

OR Gate simulation using data flow:


module orGate_;
reg a;
reg b;
// Outputs
wire c;
orGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:

Waveform:
OR Gate using behavioral modelling:
module orGate_Saiyam_21104091(a , b , c);
Input a , b;
output c;
reg c;
always@(a or b)
begin
case({a,b})
2'b00: begin
c=1'b0;
End
2'b01: begin
c=1'b1;
End
2'b10:begin
c=1'b1;
end
2'b11: begin
c=1'b1;
End
default:begin
c=1'b0;
end
endcase
End
Endmodule

OR Gate simulation using behavioral modelling:


module orGate_;
reg a;
reg b;
// Outputs
wire c;
orGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:

Waveform:
OR Gate using structural modelling:
module orGate_Saiyam_21104091(a,b,c);
Input a,b;
output c;
assign c = a | b;
Endmodule
OR Gate simulation using structural modelling:
module orGate_;
reg a;
reg b;
// Outputs
wire c;
orGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:

Waveform:
(III) EX-or gate
EX-or gate using data flow:
module exorGate_Saiyam_21104091(a,b,c);
Input a,b;
output c;
assign c = a ^ b;
Endmodule

EX-or gate simulation using data flow:


module exorGate_;
reg a;
reg b;
// Outputs
wire c;
exorGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:

Waveform:
EX-or gate using behavioral modelling:
module exorGate_Saiyam_21104091(a , b , c);
Input a , b;
output c;
reg c;
always@(a or b)
begin
case({a,b})
2'b00: begin
c=1'b0;
End
2'b01: begin
c=1'b1;
End
2'b10:begin
c=1'b1;
end
2'b11: begin
c=1'b1;
End
default:begin
c=1'b0;
end
endcase
End
Endmodule
EX-or gate simulation using behavioral modelling:
module exorGate_;
reg a;
reg b;
// Outputs
wire c;
exorGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:

Waveform:
EX-or gate using Structural modelling:
module exorGate_Saiyam_21104091(a,b,c);
Input a,b;
output c;
assign c = a ^ b;
Endmodule

EX-or gate simulation using Structural modelling:


module exorGate_;
reg a;
reg b;
// Outputs
wire c;
exorGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:

Waveform:
(IV) NAND GATE:
NAND gate using data flow:
module nandGate_Saiyam_21104091(a,b,c);
Input a,b;
output c;
assign c = ~(a&b);
Endmodule
NAND gate simulation using data flow:
module nandGate_;
reg a;
reg b;
// Outputs
wire c;
nandGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:

Waveform:

NAND gate using Behavioral modelling:


module nandGate_Saiyam_21104091(a , b , c);
Input a , b;
output c;
reg c;
always@(a or b)
begin
case({a,b})
2'b00: begin
c=1'b0;
End
2'b01: begin
c=1'b1;
End
2'b10:begin
c=1'b1;
end
2'b11: begin
c=1'b1;
End
default:begin
c=1'b0;
end
endcase
End
Endmodule

NAND gate simulation using behavioral modelling:


module nandGate_;
reg a;
reg b;
// Outputs
wire c;
nandGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:
Waveform:

NAND GATE using structure modelling:


module nandGate_Saiyam_21104091(a,b,c);
Input a,b;
output c;
assign c = ~(a&b);
Endmodule
NAND Gate simulation using structure modelling:
module nandGate_;
reg a;
reg b;
// Outputs
wire c;
nandGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:
Waveform:

(V) NOR Gate:


NOR gate using data flow:
module norGate_Saiyam_21104091(a,b,c);
Input a,b;
output c;
assign c = ~(a|b);
Endmodule

NOR gate simulation using data flow:


module norGate_;
reg a;
reg b;
// Outputs
wire c;
norGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:
Waveform:

NOR GATE using behavioral modelling:


module norGate_Saiyam_21104091(a , b , c);
Input a , b;
output c;
reg c;
always@(a or b)
begin
case({a,b})
2'b00: begin
c=1'b0;
End
2'b01: begin
c=1'b1;
End
2'b10:begin
c=1'b1;
end
2'b11: begin
c=1'b1;
End
default:begin
c=1'b0;
end
endcase
End
Endmodule

NOR GATE simulation using behavioral modelling:


module norGate_;
reg a;
reg b;
// Outputs
wire c;
norGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:

Waveform:
NOR GATE using structural modelling:
module norGate_Saiyam_21104091(a,b,c);
Input a,b;
output c;
assign c = ~(a|b);
Endmodule

Nor gate simulation using structural modelling:


module norGate_;
reg a;
reg b;
// Outputs
wire c;
norGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:

Waveform:

(VI) EX-NOR Gate:


EX-NOR gate using data flow:
module exnorGate_Saiyam_21104091(a,b,c);
Input a,b;
output c;
assign c = ~(a ^ b);
Endmodule
EX-nor gate simulation using data flow:
module exnorGate_;
reg a;
reg b;
// Outputs
wire c;
exnorGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule
Structure:

Waveform:

EX-NOR gate using behavioral modelling:


module exnorGate_Saiyam_21104091(a , b , c);
Input a , b;
output c;
reg c;
always@(a or b)
begin
case({a,b})
2'b00: begin
c=1'b0;
End
2'b01: begin
c=1'b1;
End
2'b10:begin
c=1'b1;
end
2'b11: begin
c=1'b1;
End
default:begin
c=1'b0;
end
endcase
End
Endmodule

EX-NOR GATE simulation using behavioral modelling:


module exnorGate_;
reg a;
reg b;
// Outputs
wire c;
exnorGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:
Waveform:

EXNOR GATE using structural modelling:


module exnorGate_Saiyam_21104091(a,b,c);
Input a,b;
output c;
assign c = ~(a ^ b);
Endmodule

EXNOR gate simulation using structural modelling:

module exnorGate_;
reg a;
reg b;
// Outputs
wire c;
exnorGate_Saiyam_21104091uut (
.a(a),
.b(b),
.c(c) );
Initial
begin
#0 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
Endmodule

Structure:

Waveform:

RESULT: All basic gates are implemented in data flow, behavioral and
structural modelling and their corresponding logic circuits and simulations are
successfully obtained.

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