Noida Institute of Engineering and Technology, Greater Noida

(An Autonomous Institute)

School of Computer Science & Engineering in Emerging Technologies

Memory Unit

Unit: 4

Computer Organization & AMIT AYADV

Architecture (ACSE-0305)
Assistant Professor
B Tech 3rd Sem

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 Evaluation scheme

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 Subject Syllabus
Course Contents / Syllabus
UNIT-I Introduction 8 Hours
Computer Organization and Architecture, Functional units of digital system and their
interconnections, buses, bus architecture, types of buses and bus arbitration and it’s types.
Register, bus and memory transfer. Process or organization, general registers organization,
stack organization and addressing modes.
UNIT-II ALU Unit 8 Hours
Arithmetic and logic unit: Lookahead carries adders. Multiplication: Signed operand
multiplication, Booth’s algorithm and array multiplier. Division and logic operations.
Floating point arithmetic operation, Arithmetic & logic unit design. IEEE Standard for
Floating Point Numbers.
UNIT-III Control Unit 8 hours
Control Unit: Instruction types, formats, instruction cycles and sub cycles (fetch and execute
etc.), microoperations,
execution of a complete instruction. Program Control, Reduced Instruction Set Computer,
Complex Instruction Set Computer, Pipelining. Hardwire and microprogrammed control,
Concept of horizontal and vertical microprogramming, Flynn's classification.
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 Subject Syllabus
Course Contents / Syllabus

UNIT-IV Memory Unit 8 hours

Memory: Basic concept and hierarchy, semiconductor RAM memories, 2D & 2 1/2D
memory organization. ROM memories. Cache memories: concept and design issues &
performance, address mapping and replacement Auxiliary memories: magnetic disk,
magnetic tape and optical disks Virtual memory: concept implementation, Memory
Latency, Memory Bandwidth, Memory Seek Time.
UNIT-V Input/Output 8 hours
Peripheral devices, I/O interface, I/O ports, Interrupts: interrupt hardware, types of
interrupts and exceptions. Modes of Data Transfer: Programmed I/O, interrupt initiated
I/O and Direct Memory Access. ,I/O channels and processors. Serial Communication:
Synchronous & asynchronous communication.

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 Branch wise Applications
Computer Science:

Understanding of Computer Organization and Architecture is required

for:
• Performance analysis of practical software
• Parallel Software and its execution
• High performance databases
• Modern Compilers and Code optimization
• High performance game programming

Other applications

• Bio-informatics, Data science using python, Web programming

For high performance computing, we require COA background.

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 Course Objective

• Discuss the basic concepts and structure of computers.

• Understand concepts of register transfer logic and arithmetic
operations.
• Explain different types of addressing modes and memory
organization.
• Understand the concepts of memory system and Learn the different
types of memories to store data.
• Explain the various types of interrupts and modes of data transfer.

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 Course Outcomes

Course outcomes : After completion of this course students will be able to

CO 1 Understand the basic structure and operation of a digital K1, K2

computer system
CO 2 Analyze the design of arithmetic & logic unit and understand the K1, K4

fixed point and floating-point arithmetic operations.

CO 3 Implement control unit techniques and the concept of Pipelining K3

CO 4 Understand the hierarchical memory system, cache memories K2

and virtual memory.

CO 5 Understand different ways of communicating with I/O devices K2

and standard I/O interfaces.

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 Program Outcomes
• Program Outcomes are narrow statements that describe what the students
are expected to know and would be able to do upon the graduation.

• These relate to the skills, knowledge, and behavior that students acquire
through the programmed.

1. Engineering knowledge 9. Individual and team work

2. Problem analysis 10. Communication
3. Design/development of solutions 11. Project management and
4. Conduct investigations of complex finance
problems 12. Life-long learning
5. Modern tool usage
6. The engineer and society
7. Environment and sustainability
8. Ethics

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 CO-PO Mapping

COMPUTER ORGANIZATION AND ARCHITECTURE

(ACSE-0305)

PO PO PO
CO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 10 11 12
CO1 3 2 1 1 1 1 1 - 1 1 1 2
CO2 2 2 2 2 1 1 - 1 1 1 1 2
CO3 3 2 2 1 2 2 1 1 2 2 1 2
CO4 3 2 2 2 2 1 1 - 1 1 1 2
CO5 2 2 2 1 2 - 1 - 1 2 2 2

Average 2.6 2 1.8 1.4 1.6 1 0.8 0.4 1.2 1.4 1.2 2

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 End Semester Question Paper Template
B.Tech (Semester III Theory Examination 2020-21) Total Marks : 100
Note: Attempt all sections. If require any missing data, then choose suitably. Time: 3 hours
Section A
1. Attempt all questions in brief. 2 X 10 = 20
Q. No. Question Marks CO
a. to j 2
Section B
2. Attempt any three of the following 3 X 10 = 30
Q. No. Question Marks CO
a to e 10
Section C
Question no. 3,4,5,6,7. Attempt any one of the following 1 X 10 = 10
a 10
b 10

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 Content

Memory:
➢Basic concept and hierarchy
➢semiconductor RAM memories
➢2D & 2 1/2D memory organization
➢ ROM memories
➢Cache memories: concept and design issues & performance
address mapping and replacement
➢Auxiliary memories: magnetic disk, magnetic tape and
optical disks
➢Virtual memory: concept implementation
.

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 Course Objective

➢ Study the various memory used by computer like hierarchical

memory system, RAM, ROM, 2D & 2 1/2D memory organization.

➢ Study of Cache memories and virtual memory , Auxiliary memories:

magnetic disk, magnetic tape and optical disks .

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 Course Outcome

Understanding the hierarchical memory system, cache memories and

virtual memory

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 CO-PO Mapping

COMPUTER ORGANIZATION AND ARCHITECTURE

(ACSE-0305)

CO.K PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12

KCS-
302.4 3 2 2 2 2 1 1 1 1 1 1 2

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 CO- PSO Mapping

COMPUTER ORGANIZATION AND ARCHITECTURE

(ACSE-0305)
CO.K PSO1 PSO2 PSO3 PSO4
KCS-302.2 2 3 3 2

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 Memory

• A Memory Unit is a collection of storage cells together with

associated circuits needed to transfer information in and out of
storage.

• The memory stores binary information(1's and 0's) in groups

of bits called words. A storage element is called a Cell.

• A group of eight bits is called a byte. Most computer memories use

words whose number of bits is a multiple of 8.

• The capacity of memories in commercial computers is usually stated

as the total number of bytes that can be stored.

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 Prerequisite and Recap

• Basics of Computer Organization & architecture

• Functional unit and their interconnection

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 Memory

• A memory unit consists of data lines, address selection lines, and

control lines that specify the direction of transfer. The block diagram
of a memory unit is shown below:

•Data lines provide the information to be stored in memory. The

control inputs specify the direction transfer.

•The k-address lines specify the word chosen. When there are k
address lines, 2k memory word can be accessed.

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 Classification of Memory

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 Memory Hierarchy

•The memory hierarchy system consists of all storage devices contained in

a computer system from the slow Auxiliary Memory to fast and to smaller
Cache memory and Register.

•Auxiliary memory access time is generally 1000 times that of the

main memory, hence it is at the bottom of the hierarchy.

•The Memory Hierarchy was developed based on a program behavior

known as locality of references.

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 Memory Hierarchy

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 Memory Hierarchy

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 Semiconductor RAM

•RAM (Random Access Memory) is a part of computer’s Main

Memory which is directly accessible by CPU.

•RAM is used to Read and Write data into it which is accessed by CPU
randomly. RAM is volatile in nature.

• RAM is used to store the data that is currently processed by the CPU.

Integrated RAM chips are available in two form:

SRAM(Static RAM)
DRAM(Dynamic RAM)

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 Semiconductor RAM

The block diagram of RAM chip is given below.

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 SRAM

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 DRAM

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AMIT YADAV Computer Organization and Architecture
 DRAM

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 SRAM Vs. DRAM

The block diagram of RAM chip is given below.

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 Organization of Memory Chips

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 2D and 2.5D Memory organization
2D Memory organization
In 2D organization memory is divides in the form of rows and
columns. Each row contains a word now in this memory organization
there is a decoder.

A decoder is a combinational circuit which contains n input lines and

2n output lines.

One of the output line will select the row which address is contained
in the MAR.

The word which is represented by the row that will get selected and
either read or write through the data lines.

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 2D and 2.5D Memory organization
2D Memory organization

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 2D and 2.5D Memory organization
2.5 D Memory organization
In 2.5D Organization the scenario is the same but we have two
different decoders one is column decoder and another is row
decoder.

Column decoder used to select the column and row decoder is used
to select the row. Address from the MAR will go in decoders’ input.

Decoders will select the respective cell. Through the bit outline, the
data from that location will be read or through the bit in line data
will be written at that memory location.

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 2D and 2.5D Memory organization
2.5D Memory organization

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 2D and 2.5D Memory organization
Read and Write Operations

•If the select line is in Read mode then the Word/bit which is
represented by the MAR that will be coming out to the data lines
and get read.

•If the select line is in write mode then the data from memory data
register (MDR) will go to the respective cell which is addressed by
the memory address register (MAR).

•With the help of the select line the data will get selected where the
read and write operations will take place.
•

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 2D and 2.5D Memory organization
Comparison between 2D & 2.5D Organizations

•In 2D organization hardware is fixed but in 2.5D hardware changes.

•2D Organization requires more no. of Gates while 2.5D requires less
no. of Gates.

•2D is more complex in comparison to the 2.5D Organization.

•Error correction is not possible in the 2D organization but In 2.5D

error correction is easy.

•2D is more difficult to fabricate in comparison to the 2.5D

organization.

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 ROM Memory

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AMIT YADAV Computer Organization and Architecture
 ROM Memory
•Internal Structure of ROM:
•The internal structure comprises two basic components: decoder
and OR gates.

•A decoder is a circuit that decodes an encoded form (such as

binary coded decimal, BCD) to a decimal form. So, the input is in
binary form, and the output is its decimal equivalent.

•All the OR gates present in the ROM will have outputs of the
decoder as their output.

•Let us take an example of 64 x 4 ROM. The structure is shown in

the following image.

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 ROM Memory

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 RAM Vs.ROM

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 Cache Memory
•Cache Memory is a special very high-speed and small memory. It is used
to speed up and synchronizing with high-speed CPU.

•Cache memory is costlier than main memory or disk memory but

economical than CPU registers.

•Cache memory acts as a buffer between RAM and the CPU. It holds
frequently requested data and instructions so that they are immediately
available to the CPU when needed.

•Cache memory is used to reduce the average time to access data from the
Main memory.

•The cache stores copies of the data from frequently used main memory
locations.
•There are various different independent caches in a CPU, which store
instructions and data.
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 Cache Memory

Position of cache memory

Cache Performance: When the processor needs to read or write a
location in main memory, it first checks for a corresponding entry in
the cache.
•If available in the cache, a cache hit otherwise cache miss

•For a cache miss, the cache allocates a new entry and copies in data
from main memory, then the request is fulfilled from the contents of
the cache.
Hit ratio = hit / (hit + miss)
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 Cache Memory

Types of Cache
There are two types of cache memory-

•Primary Cache
A primary cache is always located on the processor chip. This cache is
small and its access time is comparable to that of processor registers.
It is referred to as the level 1 (L1) cache.

•Secondary Cache
Secondary cache is placed between the primary cache and the rest of
the memory. It is referred to as the level 2 (L2) cache. Often, the Level
2 cache is also housed on the processor chip.

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 Cache Memory

Locality of reference
Since size of cache memory is less as compared to main
memory. So to check which part of main memory should be given
priority and loaded in cache is decided based on locality of reference.

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 Cache Memory Mapping

Cache Mapping:
There are three different types of mapping used for the purpose
of cache memory which are as follows:
Associative mapping
Direct mapping
Set-Associative mapping.

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 Cache Memory Mapping

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 Cache Memory Mapping

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 Cache Memory Mapping

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 Virtual Memory

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 Virtual Memory

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 Virtual Memory

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 Virtual Memory

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 Virtual Memory

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 Page Replacement Algorithm

Page replacement is a process of swapping out an existing page from

the frame of a main memory and replacing it with the required page.
Page Replacement Algorithms-

Page replacement algorithms help to decide which page must be

swapped out from the main memory to create a room for the
incoming page.

FIFO Page Replacement Algorithm

LIFO Page Replacement Algorithm
LRU Page Replacement Algorithm
Optimal Page Replacement Algorithm

A good page replacement algorithm is one that minimizes the number

of page faults.
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 Page Replacement Algorithm

FIFO Page Replacement Algorithm-

As the name suggests, this algorithm works on the principle of “First in
First out“.
It replaces the oldest page that has been present in the main memory for
the longest time. It is implemented by keeping track of all the pages in a
queue.

Example
A system uses 3 page frames for storing process pages in main memory. It
uses the FIFO page replacement policy. Assume that all the page frames
are initially empty. What is the total number of page faults, hit ratio and
miss ratio and page reference string given below-
4 , 7, 6, 1, 7, 6, 1, 2, 7, 2

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 FIFO Replacement Algorithm

Solution-
Total number of references = 10

Total number of page faults occurred = 6

Total number of page hits
= Total number of references – Total number of page misses or page faults
= 10 – 6 = 4
Thus, Hit ratio = 4 / 10 = 0.4 or 40%, Miss ratio = 6 / 10 = 0.6 or 60%

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 LIFO Page Replacement Algorithm

LIFO Page Replacement Algorithm-

This algorithm works on the principle of “Last in First out“.

It replaces the newest page that arrived at last in the main memory.

It is implemented by keeping track of all the pages in a stack.

Example
A system uses 3 page frames for storing process pages in main memory. It
uses the LIFO page replacement policy. Assume that all the page frames
are initially empty. What is the total number of page faults, hit ratio and
miss ratio and page reference string given below-
4 , 7, 6, 1, 7, 6, 1, 2, 7, 2

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 LIFO Page Replacement Algorithm

Solution-
Total number of references = 10

Total number of page faults occurred = 6

Total number of page hits
= Total number of references – Total number of page misses or page faults
= 10 – 6 = 4
Thus, Hit ratio = 4 / 10 = 0.4 or 40%, Miss ratio = 6 / 10 = 0.6 or 60%

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 Optimal Replacement Algorithm

Optimal Page Replacement Algorithm-

This algorithm replaces the page that will not be referred by the CPU in
future for the longest time.
It is practically impossible to implement this algorithm.
However, it is the best known algorithm and gives the least number of
page faults.
Hence, it is used as a performance measure criterion for other algorithms.

Example
A system uses 3 page frames for storing process pages in main memory. It
uses the Optimal page replacement policy. Assume that all the page
frames are initially empty. What is the total number of page faults, hit
ratio and miss ratio and page reference string given below-
4 , 7, 6, 1, 7, 6, 1, 2, 7, 2

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 Optimal Page Replacement Algorithm

Solution-
Total number of references = 10

Total number of page faults occurred = 5

Total number of page hits
= Total number of references – Total number of page misses or page faults
= 10 – 5 = 5
Thus, Hit ratio = 5 / 10 = 0.5 or 50%, Miss ratio = 5 / 10 = 0.5 or 50%

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 Auxiliary Memories
Auxiliary memory (also referred to as secondary storage) is the non-
volatile memory lowest-cost, highest-capacity, and slowest-access
storage in a computer system.
It is where programs and data kept for long-term storage or when not in
immediate use. It is not directly accessible by the CPU. For example:
Magnetic disks and tapes, Optical Disk.

Secondary Storage Media

There are the following main types of storage media:

1. Magnetic storage media:

Magnetic media is coated with a magnetic layer which is magnetized in
clockwise or anticlockwise directions. When the disk moves, the head
interprets the data stored at a specific location in binary 1s and 0s at
reading.
Examples: hard disks, floppy disks and magnetic tapes.
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 Auxiliary Memories
Floppy Disk: A floppy disk is a flexible disk with a magnetic coating on it. It
is packaged inside a protective plastic envelope.

Hard disk: A hard disk consists of one or more circular disks called platters
which are mounted on a common spindle. Each surface of a platter is coated
with a magnetic material.

2. Optical storage media

In optical storage media information is stored and read using a laser beam.
The data is stored as a spiral pattern of pits and ridges denoting binary 0 and
binary 1.
Examples: CDs and DVDs
Compact Disk: A Compact Disc drive(CDD) is a device that a computer uses
to read data that is encoded digitally on a compact disc(CD). A compact disk
or CD can store approximately 650 to 700 megabytes of data.

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 Auxiliary Memories
DVD:
It stands for Digital Versatile Disk or Digital Video Disk. It looks just like a CD
and use a similar technology as that of the CDs but allows tracks to be
spaced closely enough to store data that is more than six times the CD’s
capacity.

It is a significant advancement in portable storage technology. A DVD holds

4.7 GB to 17 GB of data.

Blue Ray Disk:

This is the latest optical storage media to store high definition audio and
video. It is similar to a CD or DVD but can store up to 27 GB of data on a
single layer disk and up to 54 GB of data on a dual layer disk.

While CDs or DVDs use red laser beam, the blue ray disk uses a blue laser to
read/write data on a disk.
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 Auxiliary Memories

Example of Auxiliary Memories

DVD CD
Hard Disk

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 Faculty Video Links, You tube Courses Details

You tube/other Video Links

• https://www.youtube.com/watch?v=NVUWlO5zsk0
• https://www.youtube.com/watch?v=zwovvWfkuSg
• https://www.youtube.com/watch?v=m1dA7D6c3C0
• https://www.youtube.com/watch?v=o2_iCzS9-ZQ
• https://www.youtube.com/watch?v=pJ6qrCB8pDw&list=PLIY8eNd
w5tW-BxRY0yK3fYTYVqytw8qhp

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 Daily Quiz

• Sketch memory hierarchy .

• Sketch 2.5D RAM organization.
• Write some differences between SRAM and DRAM.
• What do mean by virtual memory in COA.
• Which page replacement algorithm is good & why ?

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 Weekly Assignment

➢ Explain memory hierarchy with suitable diagram.

➢ Analysis different mapping scheme of cache memory.

➢ Discuss 2 D RAM and 2+1/2D RAM with suitable diagram.

➢ Write short notes on-

a) Cache Memory b) Associative Memory c) Auxiliary Memory

➢ Explain the method to improve the performance of cache memory.

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 MCQ
1 Which of the following is the fastest means of memory access for CPU?
a) Registers b) Cache c) Main memory d) Virtual Memory
2. Size of the ____memory mainly depends on the size of the address bus.
a) Main b) Virtual c) Secondary d) Cache
3. What is the location of the internal registers of CPU?
a) Internal b) On-chip c) External d) Motherboard
4. MAR stands for ___________
5. Which of the following is non-volatile storage?
a) Backup b) Secondary c) Primary d) Cache
6. Which of the following is used in main memory?
a) SRAM b) DRAM c) PRAM d) DDR
7. RAID stands for __________
Solution 1 b. 2a. 3 b. 4 Memory address register. 5 b 6 b
7 Redundant array of independent disks

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 Old Question Papers

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 Old Question Papers

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 Expected Questions for University Exam

➢Describe CAM in memory unit with major characteristics

with suitable diagram.
➢A computer uses RAM chips of 1024*1 capacity.
i) How many chips are needed & how should their address lines be
connected to provide a memory capacity of 1024*8 ?
ii) How many chips are needed to provide a memory capacity of
16KB ?
➢Calculate the page fault for a given string with the help of LRU & FIFO
page replacement algorithm, Size of frames = 4 and
string 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
➢Explain Memory hierarchy with suitable diagram.

➢Define Direct and Set associative mapping in a cache memory.

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 Summary

In previous slides we discuss in details

Memory Unit:
➢Basic concept and hierarchy
➢semiconductor RAM memories
➢2D & 2 1/2D memory organization
➢ ROM memories
➢Cache memories: concept and design issues & performance
address mapping and replacement
➢Auxiliary memories: magnetic disk, magnetic tape and
optical disks
➢Virtual memory: concept implementation

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