SN75ALS172A

QUADRUPLE DIFFERENTIAL LINE DRIVER

SLLS121D – AUGUST 1990 – REVISED APRIL 1998

D Meets or Exceeds ANSI Standards N PACKAGE

EIA/TIA-422-B and RS-485 and ITU (TOP VIEW)
Recommendation V.11
D High-Speed Advanced Low-Power Schottky
1A
1Y
1
2
16
15
VCC
4A
Circuitry
1Z 3 14 4Y
D Designed for 20-MBaud Operation in Both G 4 13 4Z
Serial and Parallel Applications 2Z 5 12 G
D Designed for Multipoint Transmission on 2Y 6 11 3Z
Long Bus Lines in Noisy Environments 2A 7 10 3Y
D Low Supply-Current Requirements: GND 8 9 3A
55 mA Max
D Wide Positive and Negative Input/Output DW PACKAGE
Bus-Voltage Ranges (TOP VIEW)
D Driver Output Capacity . . . ±60 mA
D Thermal Shutdown Protection 1A 1 20 VCC

D Driver Positive and Negative Current

1Y
NC
2
3
19
18
4A
4Y
Limiting
1Z NC
D
4 17
Logically Interchangeable With SN75172 G 5 16 4Z
2Z 6 15 G
description
NC 7 14 3Z
The SN75ALS172A comprises four line drivers 2Y 8 13 NC
with 3-state differential outputs. They are 2A 9 12 3Y
designed to meet the requirements of ANSI GND 10 11 3A
Standards EIA/TIA-422-B and RS-485 and ITU
Recommendation V.11. This device is optimized NC – No internal connection
for balanced multipoint bus transmission at rates
of up to 20 Mbaud. Each driver features wide
positive and negative common-mode output
voltage ranges, making it suitable for party-line
applications in noisy environments.
The SN75ALS172A provides positive- and negative-current limiting and thermal shutdown for protection from
line-fault conditions on the transmission bus line. Shutdown occurs at a junction temperature of
approximately 150°C.
The SN75ALS172A is characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  1998, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN75ALS172A
QUADRUPLE DIFFERENTIAL LINE DRIVER
SLLS121D – AUGUST 1990 – REVISED APRIL 1998

FUNCTION TABLE
(each driver)
INPUT ENABLES OUTPUTS
A G G Y Z
H H X H L
L H X L H
H X L H L
L X L L H
X L H Z Z
H = high level, L = low level, X = irrelevant,
Z = high impedance (off)

logic symbol†
4
G ≥1
12 EN
G
2
1 1Y
1A 3
1Z
6
7 2Y
2A 5
2Z
10
9 3Y
3A 11
3Z
14
15 4Y
4A 13
4Z

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the N package.

logic diagram (positive logic)

4
G
12
G

2
1 1Y
1A 3
1Z

6
7 2Y
2A 5
2Z

10
9 3Y
3A 11
3Z

14
15 4Y
4A 13
4Z
Pin numbers shown are for the N package.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN75ALS172A
QUADRUPLE DIFFERENTIAL LINE DRIVER
SLLS121D – AUGUST 1990 – REVISED APRIL 1998

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

VCC VCC
35 kΩ NOM

Input
Output

GND

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –9 V to 14 V
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.

DISSIPATION RATING TABLE

TA ≤ 25°C DERATING TA = 70°C TA = 85°C
PACKAGE
POWER RATING FACTOR POWER RATING POWER RATING
DW 1125 mW 9 mW/°C 720 mW 585 mW
N 1150 mW 9.2 mW/°C 736 mW 598 mW

recommended operating conditions

MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
High-level input voltage, VIH 2 V
Low-level input voltage, VIL 0.8 V
12
Common-mode output voltage, VOC V
–7
High-level output current, IOH –60 mA
Low-level output current, IOL 60 mA
Operating free-air temperature, TA 0 70 °C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN75ALS172A
QUADRUPLE DIFFERENTIAL LINE DRIVER
SLLS121D – AUGUST 1990 – REVISED APRIL 1998

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIK Input clamp voltage II = –18 mA –1.5 V
VO Output voltage IO = 0 0 6 V
|VOD1| Differential output voltage IO = 0 1.5 6 V
VCC = 5 V, RL = 100 Ω, See Figure 1 1/2 VOD1 or 2‡
|VOD2| Differential output voltage V
RL = 54 Ω, See Figure 1 1.5 2.5 5
|VOD3| Differential output voltage See Note 2 1.5 5 V
Change in magnitude of
∆|VOD| RL = 54 Ω or 100 Ω, See Figure 1 ±0.2 V
differential output voltage§
3
VOC Common-mode output voltage¶ RL = 54 Ω or 100 Ω, See Figure 1 V
–1
Change in magnitude of
∆|VOC| RL = 54 Ω or 100 Ω, See Figure 1 ±0.2 V
common-mode output voltage§
IO Output current with power off VCC = 0, VO = –7 V to 12 V ±100 µA
High-impedance-state
IOZ VO = –7 V to 12 V ±100 µA
output current
IIH High-level input current VI = 2.7 V 20 µA
IIL Low-level input current VI = 0.4 V –100 µA
IOS Short-circuit output current VO = –7 V to 12 V ±250 mA
Outputs enabled 36 55
ICC Supply current (all drivers) No load mA
Outputs disabled 15 30
† All typical values are at VCC = 5 V and TA = 25°C.
‡ The minimum VOD2 with a 100-Ω load is either 1/2 VOD1 or 2 V, whichever is greater.
§ ∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low
level.
¶ In ANSI Standard EIA/TIA-422-B, VOC, which is the average of the two output voltages with respect to ground, is called output offset voltage,
VOS.
NOTE 2: See EIA Standard RS-485, Figure 3-5, Test Termination Measurement 2.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
td(OD) Differential-output delay time RL = 54 Ω, See Figure 2 9 15 22 ns
tPZH Output enable time to high level RL = 110 Ω, See Figure 3 30 45 70 ns
tPZL Output enable time to low level RL = 110 Ω, See Figure 4 25 40 65 ns
tPHZ Output disable time from high level RL = 110 Ω, See Figure 3 10 20 35 ns
tPLZ Output disable time from low level RL = 110 Ω, See Figure 4 10 30 45 ns
† All typical values are at VCC = 5 V and TA = 25°C.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN75ALS172A
QUADRUPLE DIFFERENTIAL LINE DRIVER
SLLS121D – AUGUST 1990 – REVISED APRIL 1998

PARAMETER MEASUREMENT INFORMATION

RL
2
VOD2
RL
VOC
2

Figure 1. Differential and Common-Mode Output Voltages

Y
3V
CL RL = Input 1.5 V 1.5 V
Generator 54 Ω 0V
50 Ω td(ODL)
(see Note A) 3V Z td(ODH)
CL = 50 pF Output Z
(see Note B)
Output Y
TEST CIRCUIT VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, ZO = 50 Ω, duty cycle = 50%, tf ≤ 5 ns,
tr ≤ 5 ns.
B. CL includes probe and stray capacitance.

Figure 2. Differential Output Test Circuit and Voltage Waveforms

Output 3V
Input 1.5 V 1.5 V
0 V or 3 V S1
0V

CL = 50 pF tPZH 0.5 V
Generator 50 Ω (see Note B) RL = 110 Ω
(see Note A) VOH
Output
3V 2.3 V
Voff ≈ 0
(see Note C) tPHZ

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, ZO = 50 Ω, duty cycle = 50%, tf ≤ 5 ns,
tr ≤ 5 ns.
B. CL includes probe and stray capacitance.
C. To test the active-low enable G, ground G and apply an inverted input waveform to G.

Figure 3. Test Circuit and Voltage Waveforms, tPZH and tPHZ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN75ALS172A
QUADRUPLE DIFFERENTIAL LINE DRIVER
SLLS121D – AUGUST 1990 – REVISED APRIL 1998

PARAMETER MEASUREMENT INFORMATION

5V

RL = 110 Ω
3V
S1 Output Input 1.5 V 1.5 V
0 V or 3 V
0V
tPZL tPLZ
CL = 50 pF
Generator 50 Ω
(see Note B) 5V
(see Note A) 2.3 V
Output
3V VOL
(see Note C)
0.5 V
TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, ZO = 50 Ω, duty cycle = 50%, tf ≤ 5 ns,
tr ≤ 5 ns.
B. CL includes probe and stray capacitance.
C. To test the active-low enable G, ground G and apply an inverted input waveform to G.

Figure 4. Test Circuit and Voltage Waveforms, tPZL and tPLZ

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 18-Nov-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN75ALS172ADW LIFEBUY SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS172A

SN75ALS172ADWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS172A Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Nov-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN75ALS172ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Nov-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75ALS172ADWR SOIC DW 20 2000 367.0 367.0 45.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Nov-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN75ALS172ADW DW SOIC 20 25 506.98 12.7 4826 6.6
SN75ALS172ADW DW SOIC 20 25 507 12.83 5080 6.6

Pack Materials-Page 3
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated