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From performance and power dissipation perspective, data transfer on-chip can be significantly
faster than off chip and requires less power. At power back-off, some amplifiers are turned off, the
matching network need be reconfigured to maintain reasonable efficiency. These cookies do not
store any personal information. Because of these reasons, the PA transmits much lower than peak
output power under typical operating conditions. 1.3 Overview of the work and its contribution To
date, there has been relatively little research on the design of a CMOS PA targeting good average
efficiency. Because actual substrate thickness (after thinning) is thicker than this value, its effect on
magnetic field and eddy current induced loss should be considered. Page 67. Even when it is
possible to design a single bigger PA, using a number of smaller PAs offers several advantages, such
as better phase linearity, lower Page 125. In this chapter, LC resonant matching networks are
compared to transformer matching, which explains why transformer matching is desired when
impedance transformation ratio is high. Again, this can be overcome through careful design. Figure
4.1: The cascode configuration with two NMOS transistors Page 93. The availability of low-cost
digital circuits paved the way to adopting advanced digital modulation schemes. Because automatic
power control circuit was not implemented with the prototype, the improvement on average
efficiency cannot be tested with modulated signals. Page 185. The loss due to the finite conductivity
of the conductors is probably the only source of loss in a GaAs technology. At last, some design
guidelines will be given. 5.1 Impedance Transformation The importance of impedance
transformation needs no more introduction. For bipolar power amplifiers, emitter ballasting resistors
are used to equalize current flow in unit devices. It was noted that AM-PM becomes more important
in modern modulation schemes which employ multi-carrier for spectral efficiency and robustness.
The output swing increases linearly with input until reaching the clipping point. To overcome those
two hurdles, highly efficient power combining can be used to generate enough power with good
overall efficiency. None minimum channel length thin-oxide devices were employed to ensure
reliable operations. Figure 6.15 shows the micrograph of the prototype. However if the capacitor is
used as a part of a tuned tank, the stray capacitance could be absorbed into the tank. Through-wafer
vias are also available in this technology. These approaches allow fabricating very fast transistors
with “relatively” cheap GaAs substrate. An overall linear transfer characteristic can thus be 15
Actually, the inventor, H.S. Black, filed patent of feedforward 9 years earlier than the patent of
feedback. Page 49. At microwave frequencies, the skin effect becomes dominant, further increasing
series resistance. The operation of the Doherty amplifier can be explained by dividing it into low-
power, medium power and high power region, assuming lossless matching networks. Decreasing of
this distance is of course the advantage from integration density perspective. Vout Figure 5.20: A
power combining transformer with oval-like high-Q inductors Page 152. Class-S, however, may be
used for amplitude modulation with excellent efficiency. At the beginning of the 21st century, third
generation mobile phone systems such as Universal Mobile Telecommunication System (UMTS),
CDMA 1xEV and Time Division-Synchronous Code Division Multiple Access (TD-SCDMA) have
now begun to be available. A less frequently used measure is called 8 Drain efficiency gets its name
from FET devices, though it probably should be called collector efficiency when BJT devices are
used. Page 34. If the gain is high, it is safe to ignore the effect of input power. As shown in chapter 2,
the importance of large voltage swing at the output needs no introduction.
In fact, the second- order term gm,2 peaks at the biasing point corresponding to minimum gm,3. In
RF circuit design, power amplifier efficiency is calculated in three Page 33. It turned out that it is
also possible to grow such heterostructure from materials with different natural lattice constants
provided the thickness of the grown layer does not exceed a critical value. You also have the option
to opt-out of these cookies. The input is driven by a commercial driver amplifier through an off-chip
balun. A simple transformer layout is shown in Figure 5.18. In this approach, the adjacent windings
have current flowing in opposite direction, and thus do not contribute as much flux and coupling to
the secondary. CMOS has proven itself a suitable vehicle to meet such stringent requirements. With
series capacitor approach, it will block DC current flowing into the load. The CMOS prototype was
implemented and tested to verify the concept. Both amplifiers contribute output power when the
input signal amplitude is high. Figure 4.6: A possible configuration of Doherty Amplifier 26 Just like
many others, the Doherty amplifier was invented in Bell Labs. Page 100. Therefore, the active
devices typically operate as a transconductor (or a current source) as those in transconductance
amplifiers. The quality factor of an inductor will definitely change due to current redistribution.
There are some preliminary research results on this issue. To maintain optimum output impedance
seen by the amplifiers remaining on, the corresponding primary sides of the transformer also need to
be reconfigured to obtain optimum performance53. In some developing countries, where there is
little existing fixed-line infrastructure, the mobile phone has become widespread. Vgs Class-AB
Class-A Figure 2.9 Conceptual AM-PM for different bias conditions 2.3.3 Adjacent Channel Power
Ratio (ACPR) ACPR is an important linearity metric. At the beginning of the 21st century, third
generation mobile phone systems such as Universal Mobile Telecommunication System (UMTS),
CDMA 1xEV and Time Division-Synchronous Code Division Multiple Access (TD-SCDMA) have
now begun to be available. For digital circuits, active power consumption of a chip has quadratic
relationship with the supply voltage: fCVPactive2. Each pad was bonded to the test board with only
one bond-wire, although multi bond-wires can be employed to minimized lead inductance. Supply
voltage of CMOS is scaled down 20 International Electronics Manufacturing Initiative, an industry-
led consortium of approximately 70 electronics manufacturers, suppliers and related organizations,
including Intel, IBM, TI. Page 79. In a chain of cascaded amplifiers, if each amplifier has the same
PAE, then the PAE of the entire chain will be exactly the same as the PAE of an individual amplifier.
Very little signal will take this path which effectively eliminates this loss. Consequently, the envelope
of such an OFDM signal can be considered as Rayleigh distributed. It is defined as the ratio of the
total power with a certain bandwidth in the channel adjacent to the transmission channel to the total
power in the transmission channel. To overcome some limitations and further improve amplifier
performance, several hybrid classes were proposed. A desirable layout should be compact and delay-
equalized as shown in Figure 6.10. If the delay of the input signal is made equal to the delay of the
output signal, then a delay-equalized structure is obtained. Substrate and n-well are heavily doped to
reduce the resistance of Rwell and Rsub. Nonetheless, quantization noise from switching actions
needs to be carefully investigated. Other advantages, such as noise reduction or linearity
improvement, could also be obtained, benefiting from parallelism. 3. It demonstrates that linearity
required by advanced modulation schemes can be achieved with deeply scaled CMOS technologies.
A typical in-band spectrum is shown in Figure 2.7. The IM side-bands appear on both sides of each
tone, at frequency spacing equal to the difference between the two input tones.
In this region, the auxiliary amplifier also sees load-pulling effect that the effective load also
decreases with the increase in the input signal amplitude. The relative high cost of substrate
materials, the slow pace to large diameter manufacturing have made GaAs an expensive choice. 0 5
10 15 20 2510 1 102 103 Breakdown Voltage (V) f T (GH z) SiGe HBT (BiCMOS)GaAs
HBTNMOS (CMOS)LDMOS Figure 3.13: Comparison of breakdown voltages of different
technologies. Through-wafer vias are also available in this technology. Class-H amplifiers are similar
to class-G, which takes the class-G design one step further. Funded by: Commonwealth Environment
Research Facilities Programme Grant Pre-2014 from (2007 to 2010) Digital Elevation Models
(DEMs) Research Project. This measure can be used to evaluate the effectiveness of an amplifier and
estimate heat removal requirements. That effort, however, lost to CMOS, primarily because of its
high static power consumption. Page 62. The dimensions of the inductors are designed to make them
have roughly equal inductance. She patented an idea (Figure 1.1) about radio control with the
concept of “frequency hopping”, with her friend George Antheil, a composer. As the output power is
backed off from that single point, the efficiency typically drops rapidly. CMOS was first invented
purely for digital integrated circuits. You also have the option to opt-out of these cookies. Moreover,
since spectrum is a scarce commodity, modern transmitters for wireless communications employ
spectrally efficient digital modulations with high peak-to-average ratio. As the conduction angle
shrinks, the amplifier is biased from class- AB, to class-B and eventually class-C. He has the
background of mechanical engineering and engineering education. Capacitors are large enough to be
treated as AC short at the frequency of operation. For digital circuits, active power consumption of a
chip has quadratic relationship with the supply voltage: fCVPactive2. For example, orthogonal
frequency division multiplexing (OFDM) employs multiple carriers with the same amplitude
modulation, separated in frequency and codes so that the modulation products from one carrier are
zero at the Page 35. Recently, silicon-on-insulator (SOI) wafers have become more than a niche
technology, although the total number of SOI wafers shipped is still small compared to non-epi and
epi wafers. Lumped components can be synthesized to implement a Wilkinson power combiner
(Figure 4.9(b)). (a) Page 104. And the metal strip could be laid out with wider width comparing to a
spiral inductor, because of less layout constraints. Because actual substrate thickness (after thinning)
is thicker than this value, its effect on magnetic field and eddy current induced loss should be
considered. Page 67. Sometime, it is referred as “kahn” technique or “envelope following”
technique. 2.1.6 Class-S power amplifiers Class-S PAs looks like Class-D PAs, with one difference.
An advantage that the cascode configuration has over single transistor topology is it can sustain
higher voltage before breakdown happens. MOSFETs as Power Transistors For Nanometer CMOS
and Post-CMOS Integrated Nanosystems.. An important result of the vertical. A SiGe BiCMOS
process usually features SiGe HBT devices, CMOS transistors, and passives including capacitors and
resistors. Rethinking pedagogical assumptions in Canadian French immersion programs. A different
approach, referred as “tree” layout, guarantees equal delay55. In the case of RF power amplifiers, the
cascode offers an important additional benefit. Each amplifier acts as a current source with
transconductance gm.
When ITR is equal to 36, corresponding to turn ratio of 6, the primary side inductance should be
around 52-pH in order to achieve the optimum power efficiency. 0 10 20 30 40 500 0.2 0.4 0.6 0.8 1
1.2 1.4 1.6 1.8 2 ITR Indu ctan ce (n H) Figure 5.10: The required primary inductance for maximum
efficiency vs. While this work demonstrated average efficiency enhancement technique at power
back-off, the automatic power control circuitry was not designed due to time constraints at the time
of tape-out. Therefore, in power amplifiers design, the output is rarely conjugate matched. Page 129.
Over the years, the complexity of the analog signal separator implementation has prevented the
outphasing approach from being widely accepted. For now, an overlay structure is adopted for
comparison, where primary and secondary are implemented with the top two “analog” metal layers.
The simulation is performed when output power per tone is 18dBm (around 9dBv with 50 ohm
reference). In this chapter, the design process will be highlighted, with some discussion of practical
issues. It is well known that a PA can only achieve maximum efficiency at peak output power. In the
meantime, reverse hole injection from the base to the emitter should be minimized. The first issue is
how to implement low impedance inductor for the primary of the transformer. The analysis of such
an amplifier is very straightforward due to the simple drain voltage waveform. In high frequency
applications, the fmax is the most relevant figure-of-merit. Or in other words, power amplifiers need
to maintain high efficiency over a wide dynamic range. Optics and Lasers in Engineering, 2015, 66:
92-97. Cjs and Cjd are junction capacitance of source and drain respectively. In Chapter 4, after
presenting various power combining approaches, a simple yet elegant power combining transformer
was proposed as a means to enable CMOS integration and improve average efficiency
simultaneously. Funded by: Melbourne Water Research Project from (2005 to 2006) An investigation
of future global navigation satellite systems in support of research and development of positioning
technology in Australia. However, the need to conserve battery power and to mitigate interference to
Page 190. A comparison of the BVCBO of bipolar transistors and the recommended operating
voltage for MOSFETs as a function of fT is shown in Fig 3.13. Benefited from wide band gap as
well as high carrier mobility, GaAs HBT is clearly the star in this arena. As the output power is
backed off from peak, the efficiency drops sharply. The size of the cascode transistor is determined
after considering several trade-offs. In the low-power region (Figure 4.7(a)), the instantaneous
amplitude of the input signal is not sufficient to turn on the auxiliary power amplifier, so it will
remain off and appear as an open-circuit without any interaction with the main amplifier. It was
based on cellular networks with multiple base stations located close to each other, and protocols for
the automated handover between two cells when phones moved from one cell to another. 1 In 1942,
at the height of her Hollywood career, Hedy Lamarr patented a frequency-switching system for
torpedo guidance that was two decades ahead of its time. Page 12. The developments of circuits to
consume low power at lower supply voltages are consistent with the general trends of CMOS
scaling. And because of that, GaAs wafers have only recently become 19 From communications with
engineers in foundries, supply voltage can be boosted with non-minimum channel length transistors.
A new transformer combining architecture, which is suitable in designing highly efficient PAs in
CMOS processes, is proposed to address this issue. Therefore, switched capacitor arrays work at low
frequency. Since 2G systems were “THE” system at that time, the majority of published CMOS PAs
are nonlinear power amplifiers. From the integration perspective, it is ill-suited for full integration
since it increases the possibility of coupling with other components on-chip. This is in contrast to
wide-band system, which is usually limited by EVM requirements. Page 186.
Even worse, the disturbance might be dependent on the input signal level at the receiver input, which
further complicates the system design. It is a measure of how well a device converts one energy
source to another. Therefore, an 8-way transformer power combining amplifier is needed for the peak
output power49. 6.1.4 Pseudo-Differential Pair The differential topology prevails in integrated
circuits design for good reasons. Based on those considerations, only thin-oxide core transistors were
employed to implement the prototype. The resistors ladder will bias the circuit up and ensure a
predictable division of drain-to-source voltage. This structure can provide good magnetic coupling
without excessive capacitive coupling. For digital circuits, active power consumption of a chip has
quadratic relationship with the supply voltage: fCVPactive2. When in-phase outputs are combined,
there is no power dissipated in the isolation resistor. However, it should be noted that there are many
ways to layout one structure. Because there is no negative magnetic coupling from the opposite side
of the spiral, the total metal length will be shorter than a spiral inductor to obtain the same
inductance. We'll assume you're ok with this, but you can opt-out if you wish. In the following
setions of this chapter, those two metrics will be studied in detail. 2.2 Efficiency of Power Amplifiers
One of the most important metrics for a power amplifier is its power efficiency. The processing is
similar to CMOS with the addition of thick interconnect metallization. The opportunity for SOI
wafers to be used in mainstream high-volume application is being driven by improved high
frequency logic performance and reduced power consumption, as well as enhanced device
performance via unique device configurations such as multiple-gate transistor structure. Besides, this
parasitic resistance consumes signal power. The trend in supply voltage as technologies advance is
touched upon. The buffer layer also transforms the lattice constant Page 58. The other one is to use
several bondwires in parallel to reduce the parasitic inductance. It should be quite obvious to see the
relations between distortion products and spectrum regrowth. Figure 2.7: The spectrum of two-tone
IM products Page 43. The VLSI capabilities of CMOS make itself a well-suited vehicle for high
integration, since more and more functionalities are realized in digital domain. Please upgrade your
browser to improve your experience. In a number of applications, it is more convenient and robust to
use a large number of carriers with low data rates than a single carrier with a high data rate. Chapter
6 presents a detailed description of design process of the prototype that proves the concept of the
power control and average efficiency enhancement technique. Careful design and layout is required
to suppress this potential oscillation. Figure 6.4: (a) A simplified cascode configuration, where m1 is
the transconductor device and m2 is the cascode device; (b) An equivalent model for stability
analysis. Page 167. Since then, the growth of digital technologies such as the microprocessor has
provided the motivation to advance silicon16 MOSFET technology faster than any other
semiconductor technology. Due to the semi- insulating substrate used, as well as thick top metal
layer, high Q passive elements could be realized on-chip. The 12.9 dielectric constant and semi-
insulating substrate make it an excellent media for micro-strip and CPW (coplanar wave) design. If
the combiner at the output only performs simple mathematical summing function, it will be true. The
second component of the coupling is magnetic coupling. Funded by: Melbourne Water Research
Project from (2005 to 2006) An investigation of future global navigation satellite systems in support
of research and development of positioning technology in Australia. Various average efficiency
enhancement techniques have been proposed to solve this problem as reviewed in Chapter 2.
The loss due to the finite conductivity of the conductors is probably the only source of loss in a
GaAs technology. In silicon technology, LDMOS technologies are also not easy to get access
compared to as other silicon technologies. HBTs only require a single supply voltage for normal
operation, and have very good high-frequency power performance. It should be noted this loss could
be significantly reduced in a single-turn or multi-turn inductor using a patterned metal shield as
ground plane. Wireless electronics requires a power source which is generally rechargeable. Very little
signal will take this path which effectively eliminates this loss. He has the background of mechanical
engineering and engineering education. Considering an N-way power combining PA with N identical
amplifiers, an equivalent model (Figure 4.13) is used to study signal and noise relationship between
input and output. Figure 4.13: An equivalent model for an N-way power combining PA with additive
noise30 Noise in the combining PA can be divided into the following categories: 30 Signals are
represented in voltage domain in the context of integrated circuit design Page 110. For a multi-turn
spiral inductor47, as number of turns increases, the spacing between opposite sides shrinks, causing a
drop of inductance because of increasing negative magnetic coupling. This device consists of a
barrier junction at the Page 55. The fact is that it is not practical at all to implement, considering even
a few hundreds of micron metal interconnects might Page 140. And the current ratio of current in
the secondary sides to that of one of the primaries is obviously 129. d. The impedance seen by each
port at the primary sides is N times smaller than the load at the secondary. In this chapter, LC
resonant matching networks are compared to transformer matching, which explains why transformer
matching is desired when impedance transformation ratio is high. Solid-State Circuits, vol. 34, no. 7,
pp. 962-970, July 1999. Page 23. Therefore, the efficiency of each amplifier as well as that of the
power combined amplifier drop rapidly. Hence, changing bias conditions as a function of input
power can also be used. The voltage ratio between the swing at the load and the swing at one of the
primaries is N. c. Contrarily, the current on both sides of the transformer equal to each other. The
efficiency of the on-chip transformer is approximately 80%, simulated with ADS Momentum and
HFSS. The simple and elegant average efficiency enhancement technique was successfully
demonstrated. The inductance is primarily limited by back plane mirror current. In this section,
several practical considerations are presented. Using injection locking technique to reduce the input
drive requirements, the power amplifier could transmit 1-W power at 2GHz with 41% combined
power added efficiency using 2-V supply. Vertical PNP transistors are formed by a p-substrate, an
n-well, and a p-source or drain and lateral NPN transistors are formed by an n-source or n-drain, a
p-substrate and an n-well. At the end, fundamental limitation of CMOS technologies and the impact
of scaling for RF power amplifiers are studied. GaAs wafers are very brittle and fragile; often require
modification to equipment to prevent wafer breakage. Regardless of conduction angle, active devices
are used as current sources. If the differential topology is employed, a balun is required to convert a
differential signal to a single-ended signal. A fully rigorous distortion analysis of a power amplifier is
lengthy and highly mathematical. Even if the substrate thickness is slightly thinner than the skin
depth, the loss would be nearly the same. Extra leads necessary for connecting transistors with the
transformer, bypass network, and M1 patterned ground are included in the simulation.