Applications of Logic Gates –

NAND Gates are used in Burglar alarms and buzzers.

 They are basically used in circuits involving computation and processing.

 They are also used in push button switches. E.g. Door Bell.
 They are used in the functioning of street lights.
 AND Gates are used to enable/inhibit the data transfer function.
 They are also used in TTL (Transistor Transistor Logic) and CMOS
circuitry.

Advantages of Logic Gates

 Logical Operations are performed using Boolean Algebra which makes the
circuit design more economical and simpler.
 Logic ‘1’ and Logic ‘0’ can be easily distinguished.

Disadvantages of Logic Gates

 Operating Voltage is limited.

 Time delay occurs between input and output.

Multiplexer -The multiplexer is a combinational logic circuit designed to switch one of several
input lines to a single common output line. Multiplexing is the generic term used to describe the

operation of sending one or more analogue or digital signals over a common transmission line at

different times or speeds and as such, the device we use to do just that is called the multiplexer.

A multiplexer is a combinational circuit that has 2 n input lines and a single output line. Simply,
the multiplexer is a multi-input and single-output combinational circuit. The binary information
is received from the input lines and directed to the output line. On the basis of the values of the
selection lines, one of these data inputs will be connected to the output.

Multiplexer Symbol

2×1 Multiplexer:
In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection line, i.e., S and single
outputs, i.e., Y. On the basis of the combination of inputs which are present at the selection line
S, one of these 2 inputs will be connected to the output. The block diagram and the truth table
of the 2×1 multiplexer are given below.
Truth Table:

The logical expression of the term Y is as follows:

Y=S'.A0+S.A1

Logical circuit of the above expression is given below:

4×1 Multiplexer:
In the 4×1 multiplexer, there is a total of four inputs, i.e., A 0, A1, A2, and A3, 2 selection lines, i.e.,
S0 and S1 and single output, i.e., Y. On the basis of the combination of inputs that are present at
the selection lines S0 and S1, one of these 4 inputs are connected to the output. The block
diagram and the truth table of the 4×1 multiplexer are given below.
Truth Table:

The logical expression of the term Y is as follows:

Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

Logical circuit of the above expression is given below:

8 to 1 Multiplexer
In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4, A5, A6, and A7,
3 selection lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the combination
of inputs that are present at the selection lines S 0, S1, and S2, one of these 8 inputs are
connected to the output. The block diagram and the truth table of the 8×1 multiplexer
are given below.
Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2 .A6

+S0.S1.S3.A7

Logical circuit of the above expression is given below:

Decoder
The combinational circuit that change the binary information into 2N output lines is known
as Decoders. The binary information is passed in the form of N input lines. The output
lines define the 2N-bit code for the binary information. In simple words,
the Decoder performs the reverse operation of the Encoder. At a time, only one input
line is activated for simplicity. The produced 2N-bit output code is equivalent to the binary
information.

2 to 4 line decoder:
In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and A1 and E and four
outputs, i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is set
to 1, one of these four outputs will be 1. The block diagram and the truth table of the 2
to 4 line decoder are given below.

Block Diagram:
Truth Table:

The logical expression of the term Y0, Y1, Y2, and Y3 is as follows:

Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

Logical circuit of the above expressions is given below:

3 to 8 line decoder:
The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line decoder,
there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three inputs, i.e., A0,
A1, and A2. This circuit has an enable input 'E'. Just like 2 to 4 line decoder, when enable
'E' is set to 1, one of these four outputs will be 1. The block diagram and the truth table
of the 3 to 8 line encoder are given below.

Block Diagram:

Truth Table:

The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:
Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

Logical circuit of the above expressions is given below:

Computer organization and architecture –

A computer organization describes the functions and design of the various units of a
digital system. A general-purpose computer system is the best-known example of a digital
system. Computer architecture deals with the specification of the instruction set and the
hardware units that implement the instructions. Computer hardware consists of electronic
circuits, displays, magnetic and optic storage media and also the communication facilities.
Computer organization is concerned with the way the hardware components operate and
the way they are connected together to form the computer system. The various components
are assumed to be in place and the task is to investigate the organizational structure to verify
that the computer parts operate as intended. Software is also the part of Computer
Organization.

Functional Units (Block Diagram) of Computer System-

Functional units of a computer system are parts of the CPU (Central Processing Unit) that
performs the operations and calculations called for by the computer program. A computer
consists of following five main components.

Input unit

Input units are used by the computer to read the data. The most commonly used input
devices are keyboards, mouse, joysticks, trackballs, microphones, etc. However, the most well-
known input device is a keyboard. Whenever a key is pressed, the corresponding letter or digit is
automatically translated into its corresponding binary code and transmitted over a cable to either
the memory or the processor.

Central processing unit -

Central processing unit commonly known as CPU can be referred as an electronic circuitry
within a computer that carries out the instructions given by a computer program by performing
the basic arithmetic, logical, control and input/output (I/O) operations specified by the
instructions.

Arithmetic & logical unit (ALU)-

Most of all the arithmetic and logical operations of a computer are executed in the ALU
(Arithmetic and Logical Unit) of the processor. It performs arithmetic operations like addition,
subtraction, multiplication, division and also the logical operations like AND, OR, NOT operations.
Control unit (CU)

The control unit is a component of a computer's central processing unit that coordinates
the operation of the processor. It tells the computer's memory, arithmetic/logic unit and input
and output devices how to respond to a program's instructions. The control unit is also known as
the nerve center of a computer system. Let's us consider an example of addition of two operands
by the instruction given as Add LOCA, RO. This instruction adds the memory location LOCA to the
operand in the register RO and places the sum in the register RO. This instruction internally
performs several steps.

Memory unit-

The Memory unit can be referred to as the storage area in which programs are kept which are
running, and that contains data needed by the running programs. The Memory unit can be
categorized in two ways namely, primary memory and secondary memory. It enables a processor
to access running execution applications and services that are temporarily stored in a specific
memory location. Primary storage is the fastest memory that operates at electronic speeds. It is
also known as the volatile form of memory, means when the computer is shut down, anything
contained in RAM is lost. Cache memory is also a kind of memory which is used to fetch the data
very soon. They are highly coupled with the processor. The most common examples of primary
memory are RAM and ROM. Secondary memory is used when a large amount of data and
programs have to be stored for a long-term basis. It is also known as the Non-volatile memory
form of memory, means the data is stored permanently irrespective of shut down. The most
common examples of secondary memory are magnetic disks, magnetic tapes, and optical disks.

Output Unit-

The primary function of the output unit is to send the processed results to the user.
Output devices display information in a way that the user can understand. Output devices are
pieces of equipment that are used to generate information or any other response processed by
the computer. These devices display information that has been held or generated within a
computer. The most common example of an output device is a monitor.

Registers
A Register is a collection of flip flops. A flip flop is used to store single bit digital data. For
storing a large number of bits, the storage capacity is increased by grouping more than
one flip flops. If we want to store an n-bit word, we have to use an n-bit register containing
n number of flip flops.
The register is used to perform different types of operations. For performing the
operations, the CPU use these registers. The faded inputs to the system will store into the
registers. The result returned by the system will store in the registers.

Types of Registers (Registers in Computer Architecture)-

Register is a very fast computer memory, used to store data/instruction in-execution.
A Register is a group of flip-flops with each flip-flop capable of storing one bit of information.
An n-bit register has a group of n flip-flops and is capable of storing binary information of n-bits.
Loading the Registers: The transfer of new information into a register is referred to as loading the
register. If all the bits of register are loaded simultaneously with a common clock pulse than the
loading is said to be done in parallel.
Following are some commonly used registers:
a) Accumulator: This is the most common register, used to store data taken out from the
memory.
b) General Purpose Registers: This is used to store data intermediate results during program
execution. It can be accessed via assembly programming.
c) Special Purpose Registers: Users do not access these registers. These registers are for
Computer system,
o MAR: Memory Address Register is that register that holds the address for memory unit.
o MBR: Memory Buffer Register stores instruction and data received from the memory and
sent from the memory.
o PC: Program Counter points to the next instruction to be executed.
o IR: Instruction Register holds the instruction to be executed.

(d) MDR or Memory Data Register

Memory Data Register is a part of the computer's control unit. It contains the data that
we want to store in the computer storage or the data fetched from the computer storage.
The MDR works as a buffer that contains anything for which the processor is ready to use
it. The MDR contains the copied data of the memory for the processor. Firstly the MDR
holds the information, and then it goes to the decoder.

The data which is to be read out or written into the address location is contained in
the Memory Data Register.

The data is written in one direction when it is fetched from memory and placed into the
MDR. In write instruction, the data place into the MDR from another CPU register. This
CPU register writes the data into the memory. Half of the minimal interface between the
computer storage and the microprogram is the memory data address register, and the
other half is the memory data register.
(e) Index Register
The Index Register is the hardware element that holds the number. The number adds to
the computer instruction's address to create an effective address. In CPU, the index
register is a processor register used to modify the operand address during the running
program.

(f)Data Register

The data register is used to temporarily store the data. This data transmits to or from a
peripheral device.

(g)Shift Register

A group of flip flops which is used to store multiple bits of data and the data is moved
from one flip flop to another is known as Shift Register. The bits stored in registers
shifted when the clock pulse is applied within and inside or outside the registers. To form
an n-bit shift register, we have to connect n number of flip flops. So, the number of bits
of the binary number is directly proportional to the number of flip flops. The flip flops are
connected in such a way that the first flip flop's output becomes the input of the other
flip flop.

A Shift Register can shift the bits either to the left or to the right. A Shift Register, which
shifts the bit to the left, is known as "Shift left register", and it shifts the bit to the right,
known as "Right left register".

Register Transfer: Information transferred from one register to another is designated in symbolic
form by means of replacement operator.

R2 ← R1 (It denotes the transfer of the data from register R1 into R2.)
Normally we want the transfer to occur only in predetermined control condition. This can be
shown by following if-then statement: if (P=1) then (R2 ← R1), Here P is a control signal
generated in the control section.

There are the following operations which are performed by the registers:

Fetch:
It is used
 o To take the instructions given by the users.
o To fetch the instruction stored into the main memory.

Decode:
The decode operation is used to interpret the instructions. In decode, the operation
performed on the instructions is identified by the CPU. In simple words, the decode operation
is used to decode the instructions.

Execute:
The execution operation is used to store the result produced by the CPU

into the memory. After storing this result, it is displayed on the user screen.

Bus

Bus is a subsystem that is used to transfer data and other information between devices. Means
various devices in computer like (Memory, CPU, I/O and Other) are communicate with each other
through buses. In general, a bus is said to be as the communication pathway connecting two or
more devices. A key characteristic of a bus is that it is a shared transmission medium, as multiple
devices are attached to a bus. A bus consists of multiple communication Pathways or lines which
are either in the form of wires or metal lines etched in a card or board (Printed Circuit Board).
Each line is capable of transmitting binary 1 and binary 0.

Bus Architecture

There are three types of buses in computer architecture:

Data Lines:
Data Lines provide a path for moving data between system modules. It is bidirectional
which means data lines are used to transfer data in both directions. As an example, CPU can read
data on these lines DROM memory as well as send data out of these lines to a memory location
or to a port. And in any bus the no. of lines in data lines are either 8, 16, 32 or more depending
on size of bus. These lines collectively are called as data bus.

Address Lines:
Address Lines are collectively called as address bus. In any bus, the no. of lines in address is
usually 16, 20, 24, or more depending on type and architecture of bus. On these lines, CPU sends
out the address of memory location on I/O Port that is to be written on or read from. In short, it
is an internal channel from CPU to Memory across which the address of data (not data) is
transmitted. Here the communication is one way that is, the address is send from CPU to Memory
and I/O Port but not Memory and I/O port send address to CPU on that line and hence these lines
are unidirectional.

Control Lines:
Control Lines are collectively called as Control Bus. Control Lines are gateway used to
transmit and receives control signals between the microprocessor and various devices attached
to it. In other words, Control Lines are used by CPUs for Communicating with other devices within
the computer. As an example-CPU sends signals on the Control bus to enable the outputs of
address memory devices and port devices. Typical Control Lines signals are: Memory Read,
Memory Write, I/O Read, I/O Write, Bus Request, Bus Grant, etc.

Types of Bus

There is variety of Buses, but here I will describe only those that are widely used.

System Bus:
A Bus that connects major computer components (Processor, Memory, I/O) is called a
System Bus. It is a single computer bus among all Buses that connects all these components of a
computer system. And it is the only Bus, in which data lines, address, control lines all are present.
It is also known as "front side” Bus. It is faster than peripheral Bus (PCI, ISA, etc) but slower than
backside bus.

Bus (I/O Bus /External Bus):

Peripheral Bus also known as "I/O Bus”. It is data pathway that connects peripheral devices
to the CPU. In other words, in computing, a peripheral bus is a computer bus designed to support
computer peripheral like printers, hard drives. The PCI and USB buses are commonly used
Peripheral Buses, and are today used in commonly many PCs. Now we will discuss both of them
in brief:

PCI (Peripheral Component Interconnect): PCI Bus connects the CPU and expansion
boards such as modem cards, network cards and sound cards. These expansion boards are
normally plugged into expansion slots on the motherboard. That’s why PCI bus is also known as
expansion bus or external Bus.

USB (Universal Serial Bus): Universal Serial Bus is used to attach USB devices like Pen
Drive, etc to CPU.

Local Bus:
Local Bus are the traditional I/O (Peripheral) buses such as ISA, MCA, or EISA Buses. Now
we will discuss about each in brief one by one.

ISA (Industry Standard Architecture Bus): The ISA Bus permits bus mastering i.e., it
enabled peripheral connected directly to the bus to communicate directly with other peripherals
without going through the processor. One of the consequences of bus mastering is Direct
Memory Access. Up to end of 1990s almost all PCs computers were equipped with ISA Bus, but
it was progressively replaced by the PCI Bus, which offer a better performance.

MCA (Micro Channel Architecture): It is an improved proprietary bus designed by IBM in

1987 to be used in their PS/2 lines of computers.

EISA (Extended Industry Standard Architecture): The EISA Bus use connectors that were
same size as the ISA connectors but with 4 rows of contacts instead of 2 for 32 bit addressing.

High Speed Bus:

High Speed Bus is specifically designed to support high capacity I/O devices. High Speed Bus
brings high demand devices into closer integration with the processor. This Bus supports
connection to high speed LANs, such as Fast Ethernet at 100 Mbps, video and graphic
workstation, fire wire etc.

Bus Arbitration-

Bus Arbitration refers to the process by which the current bus master accesses and then leaves
the control of the bus and passes it to the another bus requesting processor unit. The controller
that has access to a bus at an instance is known as Bus master.
A conflict may arise if the number of DMA controllers or other controllers or processors try to
access the common bus at the same time, but access can be given to only one of those. Only one
processor or controller can be Bus master at the same point of time. To resolve these conflicts,
Bus Arbitration procedure is implemented to coordinate the activities of all devices requesting
memory transfers. The selection of the bus master must take into account the needs of various
devices by establishing a priority system for gaining access to the bus. The Bus Arbiter decides
who would become current bus master.
There are two approaches to bus arbitration:
1. Centralized Arbitration

In centralized bus arbitration, a single bus arbiter performs the required arbitration. The bus
arbiter may be the processor or a separate controller connected to the bus.
There are three different arbitration schemes that use the centralized bus arbitration approach.
There schemes are:
a) Daisy chaining
b) Polling method
c) Independent request
a) Daisy chaining

The system connections for Daisy chaining method are shown in fig below.

It is simple and cheaper method. All masters make use of the same line for bus request. In
response to the bus request the controller sends a bus grant if the bus is free. The bus grant signal
serially propagates through each master until it encounters the first one that is requesting access
to the bus. This master blocks the propagation of the bus grant signal, activities the busy line and
gains control of the bus. Therefore any other requesting module will not receive the grant signal
and hence cannot get the bus access.

b) Polling method
The system connections for polling method are shown in figure above.

In this the controller is used to generate the addresses for the master. Number of address line
required depends on the number of master connected in the system. For example, if there are 8
masters connected in the system, at least three address lines are required. In response to the bus
request controller generates a sequence of master address. When the requesting master
recognizes its address, it activated the busy line ad begins to use the bus.

c) Independent request

The figure below shows the system connections for the independent request scheme. In this
scheme each master has a separate pair of bus request and bus grant lines and each pair has a
priority assigned to it. The built in priority decoder within the controller selects the highest
priority request and asserts the corresponding bus grant signal.
2. Distributed Arbitration
No single processor or controller controls the network as an authority. Since all arbiters
participate actively to decide who will be the bus master, so this method is known as Distributed
Arbitration.
Sometimes it is also known as Democratic Arbitration because every arbiter follows the set of
rules and cooperates during the arbitration process of the bus.
The network decides a network master among all arbiters who calculates all the requests on the
basis of set of rules decided by the network. The result of the calculation decides the priority of
all arbiters and highest priority request becomes the bus master.

Bus and Memory Transfers

A digital system composed of many registers, and paths must be provided to transfer information
from one register to another. The number of wires connecting all of the registers will be excessive
if separate lines are used between each register and all other registers in the system.
A bus structure, on the other hand, is more efficient for transferring information between
registers in a multi-register configuration system.
A bus consists of a set of common lines, one for each bit of register, through which binary
information is transferred one at a time. Control signals determine which register is selected by
the bus during a particular register transfer.
The following block diagram shows a Bus system for four registers. It is constructed with the help
of four 4 * 1 Multiplexers each having four data inputs (0 through 3) and two selection inputs (S1
and S2).
We have used labels to make it more convenient for you to understand the input-output
configuration of a Bus system for four registers. For instance, output 1 of register A is connected
to input 0 of MUX1.
The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers.
The selection lines choose the four bits of one register and transfer them into the four-line
common bus.
When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four
multiplexers are selected and applied to the outputs that forms the bus. This, in turn, causes the
bus lines to receive the content of register A since the outputs of this register are connected to
the 0 data inputs of the multiplexers.
Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content
provided by register B.
The following function table shows the register that is selected by the bus for each of the four
possible binary values of the Selection lines.

A bus system can also be constructed using three-state gates instead of multiplexers.
The three state gates can be considered as a digital circuit that has three gates, two of which are
signals equivalent to logic 1 and 0 as in a conventional gate. However, the third gate exhibits a
high-impedance state.
The most commonly used three state gates in case of the bus system is a buffer gate.
The following diagram demonstrates the construction of a bus system with three-state buffers.

The outputs generated by the four buffers are connected to form a single bus line. Only one
buffer can be in active state at a given point of time. The control inputs to the buffers determine
which of the four normal inputs will communicate with the bus line. A 2 * 4 decoder ensures that
no more than one control input is active at any given point of time.

Memory Transfer –

Read Operation-

The transfer of data from the Address Register into the Memory Buffer Register is known as the
Read Operation.
The read operation is represented by MBR ← [AR] M. It states that the Memory Unit M is
transferred from [AR] representing Address register to Memory Buffer Register (MBR).
Write Operation-
Write Operation is the transfer of new data into the memory.
The write operation is denoted by [AR] M ← R1. It states that the Memory M from Register R1
is transferred to Address Register([AR]).

Figure showing Read and Write operation on the memory unit.

Register Transfer Language (RTL)-

It is a kind of intermediate representation (IR) that is very close to assembly language, such as
that which is used in a compiler. The term “Register Transfer” can perform micro-operations
and transfer the result of operation to the same or other register.

Micro-operations:
The operation executed on the data store in registers are called micro-operations.

For RTL –

1) General way of representing a register is by the name of the register

enclosed in a rectangular box.

2) Register has numbered in a sequence of 0 to (n-1).

3) The numbering of bits in a register can be marked on the top of the box.
 4) A 16-bit register PC is divided into 2 parts- Bits (0 to 7) are assigned with
lower byte of 16-bit address and bits (8 to 15) are assigned with higher bytes of
16-bit address.

Basic symbols of RTL:-

Symbol Description Example

() Denotes a part of register R1(8-bit)
R1(0-7)

<- Denotes a transfer of information R2 <- R1

, Specify two micro-operations of Register R1 <- R2, R2 <- R3
Transfer
:
Denotes conditional operations P : R2 <- R1
if P=1
Naming Denotes another name for an already existing Ra := R1
Operator register
:=

Register Transfer Operations:

The operation performed on the data stored in the registers are referred to as register transfer
operations.
There are different types of register transfer operations:
1. Simple Transfer – R2 <- R1
The content of R1 are copied into R2 without affecting the content of R1. It is an
unconditional type of transfer operation.
2. Conditional Transfer –
It indicates that if P=1, then the content of R1 is transferred to R2. It is a
unidirectional operation.
3. Simultaneous Operations –
If 2 or more operations are to occur simultaneously then they are separated
with comma (,).

If the control function P=1, then load the content of R1 into R2 and at the same
clock load the content of R2 into R1.

Computer architecture –
THE VON NEUMANN ARCHITECTURE –

Mathematician John von Neumann and his colleagues proposed the von Neumann architecture in
1945, which stated that a computer consists of: a processor with an arithmetic and logic unit (ALU)
and a control unit; a memory unit that can communicate directly with the processor using
connections called buses; connections for input/output devices; and a secondary storage for saving
and backing up data.
The central computation concept of this architecture is that instructions and data are both loaded
into the same memory unit, which is the main memory of the computer and consists of a set of
addressable locations. The processor can then access the instructions and data required for the
execution of a computer program using dedicated connections called buses – an address bus which
is used to identify the addressed location and a data bus which is used to transfer the contents to
and from a location.

There are a number of reasons why the von Neumann architecture has proven to be so successful.
It is relatively easy to implement in hardware, and von Neumann machines are deterministic and
introspectable. They can be described mathematically and every step of their computing process
is understood. The biggest challenge with von Neumann machines is that they can be difficult to
code. This has led to the growth of computer programming, which takes real-world problems and
explains them to von Neumann machines.

HARVARD ARCHITECTURE-
Another popular computer architecture, though less so than the von Neumann architecture, is
Harvard architecture. The Harvard architecture keeps instructions and data in separate memories,
and the processor accesses these memories using separate buses. The processor is connected to the
‘instructions memory’ using a dedicated set of address and data buses, and is connected to the
‘data memory’ using a different set of address and data buses. This architecture is used extensively
in embedded computing systems such as digital signal processing (DSP) systems, and many
microcontroller devices use a Harvard-like architecture.

Difference between Von Neumann and Harvard Architecture:

VON NEUMANN ARCHITECTURE HARVARD ARCHITECTURE

It is ancient computer architecture based on It is modern computer architecture based on

stored program computer concept. Harvard Mark relay based model.

Same physical memory address is used for Separate physical memory address is used
instructions and data. for instructions and data.

There is common bus for data and instruction Separate buses are used for transferring data
transfer. and instruction.

Two clock cycles are required to execute

single instruction. An instruction is executed in a single cycle.

It is cheaper in cost. It is costly than Von Neumann Architecture.

CPU cannot access instructions and CPU can access instructions and read/write
read/write at the same time. at the same time.

It is used in personal computers and small It is used in micro controllers and signal
computers. processing.
 Stack Organization

Stack - A stack is a memory unit with an address register. This register influences the address
for the stack, which is known as Stack Pointer (SP). The stack pointer continually influences the
address of the element that is located at the top of the stack.

The main difference between stack pointer and program counter is that the stack pointer is a
register that stores the address of the last program request in a stack while the program counter is
a register that stores the address of the next instruction to be executed from the memory.

Inserting new items to the stack is called push whereas removing items from the stack is called
pop. For example, assume that there are three elements as A, B and C. The first items pushed to
the stack is A. Then B and C are added. B is on top of A while C is on top of A. Now the
topmost element is C. When removing the items, C pops out first, then B and finally A. The last
inserted items are popped out first. Therefore, a stack operates according to the last in-first out
manner. This is the basic operation of a stack.
A stack pointer, or a stack register, is a small register that helps to handle the stack. It stores the
address of the last program request. Here, the recently entered request resides at the top of the
stack. When inserting a program request to the stack, the stack pointer first increments by one.
Then, the request is pushed to the stack. When removing a program request from the stack, the
requests first pops out of the stack. Then, the stack pointer decrements by one. Likewise, the stack
pointer keeps track of the operations of the stack.

Stack pointer is also called a stack register while program counter is also called an instruction
pointer, instruction address register, and instruction counter.

Register Stack
The stack can be arranged as a set of memory words or registers. Consider a 64-word register
stack arranged as displayed in the figure. The stack pointer register includes a binary number,
which is the address of the element present at the top of the stack. The three-element A, B, and C
are located in the stack.
The element C is at the top of the stack and the stack pointer holds the address of C that is 3. The
top element is popped from the stack through reading memory word at address 3 and decrementing
the stack pointer by 1. Then, B is at the top of the stack and the SP holds the address of B that is
2. It can insert a new word; the stack is pushed by incrementing the stack pointer by 1 and inserting
a word in that incremented location.
The stack pointer includes 6 bits, because 26 = 64, and the SP cannot exceed 63 (111111
in binary). After all, if 63 is incremented by 1, therefore the result is 0(111111 + 1 =
1000000). SP holds only the six least significant bits. If 000000 is decremented by 1 thus
the result is 111111.
Therefore, when the stack is full, the one-bit register ‘FULL’ is set to 1. If the stack is null,
then the one-bit register ‘EMTY’ is set to 1. The data register DR holds the binary
information which is composed into or readout of the stack.
First, the SP is set to 0, EMTY is set to 1, and FULL is set to 0. Now, as the stack is not
full (FULL = 0), a new element is inserted using the push operation.
The push operation is executed as follows –

SP←SP + 1 It can increment stack pointer

K[SP] ← DR It can write element on top of the stack

If (SP = 0) then (FULL ← 1) Check if stack is full

EMTY ← 0 Mark the stack not empty

The stack pointer is incremented by 1 and the address of the next higher word is saved
in the SP. The word from DR is inserted into the stack using the memory write operation.
The first element is saved at address 1 and the final element is saved at address 0. If the
stack pointer is at 0, then the stack is full and ‘FULL’ is set to 1. This is the condition
when the SP was in location 63 and after incrementing SP, the final element is saved at
address 0. During an element is saved at address 0, there are no more empty registers
in the stack. The stack is full and the ‘EMTY’ is set to 0.
A new element is deleted from the stack if the stack is not empty (if EMTY = 0). The pop
operation includes the following sequence of micro-operations −

DR←K[SP] It can read an element from the top of the stack

SP ← SP – 1 It can decrement the stack pointer

If (SP = 0) then (EMTY ← 1) Check if stack is empty

FULL ← 0 Mark the stack not full

The top element from the stack is read and transfer to DR and thus the stack pointer is
decremented. If the stack pointer reaches 0, then the stack is empty and ‘EMTY’ is set
to 1. This is the condition when the element in location 1 is read out and the SP is
decremented by 1.

Computer Instructions (Instruction Formats)–

Computer instructions are a set of machine language instructions that a particular processor
understands and executes. A computer performs tasks on the basis of the instruction provided.

An instruction comprises of groups called fields. These fields include:

o The Operation code (Opcode) field which specifies the operation to be performed.
o The Address field which contains the location of the operand, i.e., register or
memory location.
o The Mode field which specifies how the operand will be located.

Addressing Modes-

The operation field of an instruction specifies the operation to be performed. And this operation
must be performed on some data. So, each instruction needs to specify data on which the
operation is to be performed. But the operand (data) may be in accumulator, general purpose
register or at some specified memory location. So, appropriate location (address) of data is
needed to be specified, and in computer, there are various ways of specifying the address of data.
These various ways of specifying the address of data are known as “Addressing Modes.”
So, Addressing Modes can be defined as “The technique for specifying the address of the
operands.” And in computer the address of operand i.e., the address where operand is actually
found is known as “Effective Address”.
Now, in addition to this, the two most prominent reason of why addressing modes are so
important, are:
1. First, the way the operand data are chosen during program execution is
dependent on the addressing mode of the instruction.
2. Second, the address field (or fields) in a typical instruction format are relatively
small and sometimes we would like to be able to reference a large range of locations, so
here to achieve this objective i.e., to fit this large range of location in address field, a
variety of addressing techniques has been employed. As they reduce the number of fields
in the addressing field of the instruction.
Thus, Addressing Modes are very vital in Instruction Set Architecture (ISA).
Now, before discussing various addressing modes, I should know some notations that will be
used in throughout of this section. These are:
A= Contents of an address field in the instruction
R= Contents of an address field in the instruction that refers to a register
EA= Effective Address (Actual address) of location containing the referenced operand.
(X)= Contents of memory location x or register X.

Types of Addressing Modes:

Various types of addressing modes are:

1. Implied and Immediate Addressing Modes
2. Direct or Indirect Addressing Modes
3. Register Addressing Modes
4. Register Indirect Addressing Mode
5. Auto-Increment and Auto-Decrement Addressing Modes
6. Displacement Based Addressing Modes
Now, we will explore to each one by one.
(1) Implied and Immediate Addressing Modes-
Although most Addressing modes need the address field of the instruction, but implied and
immediate addressing modes are the only addressing modes that need no address field at all.
(a) Implied Addressing Mode-

Implied Addressing Mode also known as "Implicit" or "Inherent" addressing mode is the
addressing mode in which, no operand (register or memory location or data) is specified in the
instruction. As in this mode the operand is specified implicit in the definition of instruction. For
Example: “Complement Accumulator” is an Implied Mode instruction because the operand in the
accumulator register is implied in the definition of instruction. In assembly language it is written
as:

CMA: Take complement of content of AC

RLC: Rotate the content of Accumulator is an implied mode instruction.

In addition to this, all Register-Reference instruction that use an accumulator and Zero-Address
instruction in a Stack Organized Computer are implied mode instructions, because in Register
reference operand implied in accumulator and in Zero-Address instruction, the operand implied
on the Top of Stack.

(b)Immediate Addressing Mode:

In Immediate Addressing Mode operand is specified in the instruction itself. In other words, an
immediate mode instruction has an operand field rather than an address field, which contain
actual operand to be used in conjunction with the operand specified in the instruction. That is, in
this mode, the format of instruction is as follows:

For example
MVI 06 Move 06 to the accumulator
ADD 05 ADD 05 to the content of accumulator
In addition to this, this mode is very useful for initializing the register to a constant value.

(2) Direct and Indirect Addressing Modes:

The instruction format for direct and indirect addressing mode is shown below:

It consists of 3-bit opcode, 12-bit address and a mode bit designated as (I). The mode bit (I) is
zero for Direct Address and 1 for Indirect Address.
a) Direct Addressing Mode-
Direct Addressing Mode is also known as “Absolute Addressing Mode”. In this mode the address
of data (operand) is specified in the instruction itself. That is, in this type of mode, the operand
resides in memory and its address is given directly by the address field of the instruction.
Means, in other words, in this mode, the address field contain the Effective Address of
operand i.e., EA=A
For Example
ADD A means add contents of cell A to accumulator
It would look like as shown below:

Here, we see that in its Memory Address=Operand.

b) Indirect Addressing Mode -

In this mode, the address field of instruction gives the memory address where on, the operand is
stored in memory. That is, in this mode, the address field of the instruction gives the address
where the “Effective Address” is stored in memory i.e., EA= (A)
Means, here, Control fetches the instruction from memory and then uses its address part to
access memory again to read Effective Address.

For Example
ADD (A) Means adds the content of cell pointed to contents of A to Accumulator.
It looks like as shown in figure below:
 Thus in it, AC <-- M [M (A)] [M=Memory]
i.e., (A) =1350=EA

3. Register Addressing Mode –

In Register Addressing Mode, the operands are in registers that reside within the CPU. That is,
in this mode, instruction specifies a register in CPU, which contains the operand. It is like Direct
Addressing Mode; the only difference is that the address field refers to a register instead of
memory location. i.e., EA=R
It looks like as:

For Example
MOV AX, BX Move contents of Register BX to AX
ADD AX, BX Add the contents of register BX to AX
Here, AX, BX are used as register names which is of 16-bit register.
Thus, for a Register Addressing Mode, there is no need to compute the actual address as the
operand is in a register and to get operand there is no memory access involved.
 4. Register Indirect Addressing Mode:-
In Register Indirect Addressing Mode, the instruction specifies a register in CPU whose contents
give the operand in memory. In other words, the selected register contains the address of
operand rather than the operand itself. That is, i.e., EA=(R)
Means, control fetches instruction from memory and then uses its address to access Register and
looks in Register(R) for effective address of operand in memory. It looks like as:

For Example
MOV AL, [BX]
Code example in Register:
MOV BX, 1000H
MOV 1000H, operand
From above example, it is clear that, the instruction (MOV AL, [BX]) specifies a register [BX], and
in coding of register, we see that, when we move register [BX], the register contain the address
of operand(1000H) rather than address itself.

5. Auto-increment and Auto-decrement Addressing Modes: -

These are similar to Register indirect Addressing Mode except that the register is incremented or
decremented after (or before) its value is used to access memory.
These modes are required because when the address stored in register refers to a table of data
in memory, then it is necessary to increment or decrement the register after every access to table
so that next value is accessed from memory. Thus, these addressing modes are common
requirements in computer.
Now, we will discuss each separately in detail.
(a)Auto-increment Addressing Mode:
Auto-increment Addressing Mode is similar to Register Indirect Addressing Mode except that the
register is incremented after its value is loaded (or accessed) at another location like accumulator
(AC). That is the Effective Address is equal to EA=(R) But, after accessing operand, register is
incremented by 1.
For Example, it looks like as shown below:
Here, we see that effective address is (R) =400 and operand in AC is 7. And after loading, R1 is
incremented by 1. It becomes 401. Means, here we see that, in the Auto-increment mode, the
R1 register is increment to 401 after execution of instruction.

(b) Auto-decrement Addressing Mode:

Auto-decrement Addressing Mode is reverse of auto-increment, as in it the register is decrement
before the execution of the instruction. That is, in this case, effective address is equal to EA=(R)
-1
For Example

Here, we see that, in the Auto-decrement mode, the register R1 is decremented to 399 prior to
execution of the instruction, means the operand is loaded to accumulator, is of address 1099H in
memory, instead of 1088H.Thus, in this case effective address is 1099H and contents loaded into
accumulator is 700.
 6. Displacement Based Addressing Modes:
Displacement Based Addressing Modes is a powerful addressing mode as it is a combination of
direct addressing and register indirect addressing mode i.e., EA=A+(R)

Means, Displacement Addressing Modes requires that the instruction have two address fields, at
least one of which is explicit means, one is address field indicate direct address and other
indicate indirect address. That is, value contained in one addressing field is A, which is used
directly and the value in other address field is R, which refers to a register whose contents are to
be added to produce effective address.
It looks like as shown in figure below:

There are three areas where Displacement Addressing modes are used. In other words,
Displacement Based Addressing Modes are of three types. These are:

a) Relative Addressing Mode

b) Base Register Addressing Mode
c) Indexing Addressing Mode
Now we will explore to each one by one.

a) Relative Addressing Mode

In Relative Addressing Mode, the contents of program counter are added to the address part of
instruction to obtain the Effective Address. That is, in Relative Addressing Mode, the address
field of the instruction is added to implicitly reference register Program Counter to obtain
effective address. i.e., EA=A+PC
For Example
Assume that PC contains the no.- 825 and the address part of instruction contain the no.- 24,
then the instruction at location 825 is read from memory during fetch phase and the Program
Counter is then incremented by one to 826.
The effective address computation for relative address mode is 826+24=850
 Thus, Effective Address is displacement relative to the address of instruction. Relative
Addressing is often used with branch type instruction.

b) Index Register Addressing Mode

In indexed addressing mode, the content of Index Register is added to direct address part (or
field) of instruction to obtain the effective address. Means, in it, the register indirect addressing
field of instruction point to Index Register, which is a special CPU register that contain an Indexed
value, and direct addressing field contain base address.
As, indexed type instruction make sense that data array is in memory and each operand in the
array is stored in memory relative to base address. And the distance between the beginning
address and the address of operand is the indexed value stored in indexed register.
Any operand in the array can be accessed with the same instruction, which provided that the
index register contains the correct index value i.e., the index register can be incremented to
facilitate access to consecutive operands.
Thus, in index addressing mode, EA=A + Index
It looks like as shown in fig. below:

c) Base Register Addressing Mode

In this mode, the content of the Base Register is added to the direct address part of the
instruction to obtain the effective address. Means, in it the register indirect address field point
to the Base Register and to obtain EA, the contents of Instruction Register, is added to direct
address part of the instruction. This is similar to indexed addressing mode except that the register
is now called as Base Register instead of Index Register. That is, the EA=A + Base. It looks like as
shown in fig. below:

Thus, the difference between Base and Index mode is in the way they are used rather than the
way they are computed. An Index Register is assumed to hold an index number that is relative
to the address part of the instruction. And a Base Register is assumed to hold a base address
and the direct address field of instruction gives a displacement relative to this base address.
Thus, the Base register addressing mode is used in computer to facilitate the relocation of
programs in memory. Means, when programs and data are moved from one segment of memory
to another, then Base address is changed, the displacement value of instruction do not change.
So, only the value of Base Register requires updating to reflect the beginning of new memory
segment.