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Microprocessors And Microcontrollers

Assignment 9- Week 9
TYPE OF QUESTION: MCQ
Number of questions: 15 Total mark: 15 X 1 = 15
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QUESTION 1:
ARM9TDMI is a

A. 3-stage pipeline processor

B. 5-stage pipeline processor
C. 6-stage pipeline processor
D. 8-stage pipeline processor

Correct Answer: b

Detailed Solution:

Following shows pipeline stages used in different versions of ARM

3-stage pipeline – ARM7TDMI and earlier

5-stage pipeline – ARMS, ARM9TDMI

6-stage pipeline – ARM10TDMI

8-stage pipeline – ARM11

option b is correct

QUESTION 2:

In ARM10 core, which of the following is true?

A. Both instruction and data buses are 32-bit
B. Instruction buses are 32 bits, but data buses are 64 bit
C. Instruction buses are 64 bits, but data buses are 32 bit
D. Both instruction and data buses are 64-bit

Correct Answer: D

Detailed Solution:
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ARM10 core is a 6-stage Pipeline, which has 64 bit instruction bus and data bus

Option D is correct

QUESTION 3:
When a procedure call is made, the return address is automatically placed into

A. Program Counter (R15)

B. Link Register (R14)
C. Stack Pointer (R15)
D. Stack Pointer (R13)

Correct Answer: B

Detailed Solution:

R14 is called as link register. When a procedure call is made, the return address is automatically
placed into this register. A return from the procedure can be implemented by copying R14 to
R15

Option B is correct

QUESTION 4:
When the processor encounters a software interrupt instruction, ARM processor enters in
A. Fast interrupt processing mode (FIQ)
B. Normal interrupt processing mode (IRQ)
C. Supervisor mode (SVC)
D. Abort mode

Correct Answer: C

Detailed Solution:

ARM enters supervisor mode when it experience a RESET or software interrupt instruction

Option C is correct

QUESTION 5:
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Which of the following ARM instructions is the same as multiplying the contents of r0 by nine
and storing the product in r7?
A. ADD r0, r7, r7, LSL #3
B. ADD r0, r7, r0, LSL #3
C. ADD r7, r7, r0, LSL #3
D. ADD r7, r0, r0, LSL #3
Correct Answer: D

Detailed Solution:
ADD r7, r0, r0, LSL #3 ;

r0,LSL #3 means logical left shift r0 by three positions, which is equivalent to r0*8.

r7 = r0+r0*8 , this instruction multiplies the content of r0 by 9 and stores the result in r7

QUESTION 6:
Which register is not allowed in ARM multiplication instructions?
A. R0
B. R1
C. R14
D. R15
Correct Answer: D

Detailed Solution:

PC (R15) cannot be used for multiplication. Option d is correct

QUESTION 7:
In which of the following modes of an ARM processor, The CPSR cannot be modified?

A. Fast Interrupt Processing (FIQ) mode

B. Normal Interrupt Processing (IRQ) mode
C. User mode
D. Supervisor (SVC) mode

Correct Answer: C

Detailed Solution:
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QUESTION 8:
Which of the following operations is performed by the below ARM instruction?
EQADD R0, R1, R2;
A. Performs R0 = R1+R2 if zero flag is set
B. Performs R0 = R1+R2 if zero flag is reset
C. Performs R0 = R1+R2 if carry flag is set
D. Performs R0 = R1+R2 if parity flag is set

Correct Answer: A

Detailed Solution:
QUESTION 9:
A little-endian processor stores _______________________.

A. the most significant byte is stored at the lowest memory address

B. the least significant byte is stored at the lowest memory address
C. the least significant byte is stored at the highest memory address
D. the most significant byte is stored in stack memory

Correct Answer: B

Detailed Solution:
In a little-endian processor, the least significant byte of a word is stored in the memory location
with the lowest address, while the most significant byte is stored in the memory location with the
highest address.

QUESTION 10:
Which of the following registers acts as a program counter (PC)?
A. R0
B. R1
C. R14
D. R15

Correct Answer: D

Detailed Solution:
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QUESTION 11:
Which of the following statements is TRUE?
A. ARM instructions are 16 bit wide
B. ARM instructions are 32 bit wide
C. THUMB instructions are 8 bit wide
D. THUMB instructions are 64 bit wide
Correct Answer: B

Detailed Solution:

ARM instructions are 32 bits wide. Thumb instructions are 16 or 32-bits wide.

QUESTION 12:
Which ARM operating mode is used for handling software interrupts (SWIs)?
A. SVC
B. FIQ
C. IRQ
D. Abort

Correct Answer: A

Detailed Solution:

Supervisor mode (SVC)

– entered when the processor encounters a software interrupt instruction
– used for OS services
– on reset, ARM enters into this mode
QUESTION 13:
Which ARM operating mode is entered when an undefined instruction is encountered?
A. Supervisor mode
B. User mode
C. Undefined instruction mode
D. Abort mode
Correct Answer: C

Detailed Solution:
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ARM enters undefined mode when fetched instruction is not an ARM instruction or a

coprocessor instruction

QUESTION 14:
What is the purpose of the N flag in the CPSR register?
A. Indicates if the result of the previous operation was negative
B. Indicates if the processor is in privileged mode
C. Indicates if the result of the previous operation resulted in a carry
D. Indicates if the result of the previous operation result is zero
Correct Answer: A

Detailed Solution:

QUESTION 15:
What is the purpose of the T flag in the CPSR register?

A. Indicates if the processor is in ARM instruction mode

B. Indicates if the processor is in THUMB instruction mode
C. Indicates if the result of the previous operation resulted in a carry
D. Indicates if the result of the previous operation was negative
Correct Answer: B

Detailed Solution:

Flag T in CPSR register specifies the ARM processor operates in THUMB instruction set

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