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Ece113 Lec18 Oscillators

This document summarizes a lecture on oscillators, phase-locked loops (PLLs), frequency synthesizers, and mixers. It discusses key considerations for oscillators like tuning range and phase noise. It also explains how PLLs use a phase detector and voltage-controlled oscillator in a feedback loop to generate a stable output frequency based on a reference signal. Finally, it compares different techniques for frequency synthesis including direct, indirect, and direct digital synthesis and their properties like switching speed and phase continuity.

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97 views29 pages

Ece113 Lec18 Oscillators

This document summarizes a lecture on oscillators, phase-locked loops (PLLs), frequency synthesizers, and mixers. It discusses key considerations for oscillators like tuning range and phase noise. It also explains how PLLs use a phase detector and voltage-controlled oscillator in a feedback loop to generate a stable output frequency based on a reference signal. Finally, it compares different techniques for frequency synthesis including direct, indirect, and direct digital synthesis and their properties like switching speed and phase continuity.

Uploaded by

許耕立
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ECE 113 Lecture 18:

Oscillators
Ch. 13, Pozar 4th ed; Ch. 11-12 Hagen

1s1819 Revision October 2018


Oscillators
• Important considerations
• Tuning Range (MHz/V for VCOs)
• Frequency Stability (ppm/°C)
• Phase Noise (dBc/Hz below carrier, offset from
carrier)
• Harmonics (dBc below carrier)

• Can be transistor or diode sources (e.g. tunnel,


Gunn, or IMPATT)
• Transistors allow more control and compatibility
• Diodes are capable of higher frequency and power
outputs
Recall: Oscillator Operation
• Oscillator – nonlinear circuit that converts DC
power to an AC waveform, usually sinusoidal.

• Nyquist or Barkhausen criterion for instability

• In contrast to amplifier design where at least


conditional stability is achieved
Negative Resistance

• Using negative resistance diodes or transistors

𝑍𝐿 = 𝑅𝐿 + 𝑗𝑋𝐿

𝑍𝑖𝑛 I, jω = 𝑅𝑖𝑛 𝐼, 𝑗𝜔 + 𝑗𝑋𝑖𝑛 (𝐼, 𝑗𝜔)


Negative Resistance
• By KVL, 𝑍𝐿 + 𝑍𝑖𝑛 𝐼 = 0
• If there is oscillation, then 𝐼 ≠ 0 thus

• But load is passive, 𝑅𝐿 > 0, thus 𝑅𝑖𝑛 < 0


• Positive resistance – energy dissipation
• Negative resistance – energy source

• 𝑋𝐿 + 𝑋𝑖𝑛 = 0 controls the frequency of


oscillation
Stable Oscillation
• Previous requirement not enough to guarantee
stable operating point
• Kurokawa’s condition:

• High-Q circuit results in maximum oscillator


stability (e.g. cavity and dielectric resonators)
• Reserved topics for advanced electronics
Transistor Oscillator
• Terminating network drives a potentially unstable
transistor creating the negative resistance towards
unstable region
• RF output port can be either on the load network or
terminating network
Transistor Oscillator
• For an oscillator, we require a device with a
high degree of instability
• Positive feedback for CE or CB configurations
• Steady-state oscillation requires:

• Can again use stability circles – but we’ve had


enough! At least for ECE 113. ☺
Phase Noise
• Refers to short-term random noise fluctuation
in the frequency (or phase) of an OSC signal
• May severely degrade the performance of
communications or radar receiver system
• Adds to the noise level of the receiver
• Introduces uncertainty during the detection of
digitally modulated signals
• Unwanted generation of signals during mixing
• Limits selectivity and sensitivity of the receiver
• Produces interferences during transmission
Phase Noise
• Ideal OSC → single delta function in frequency
• Practical OSC:
Phase Noise
• Quantified in dBc/Hz (decibels relative to
carrier power per Hertz of bandwidth)
• Example: GSM radio specs: -110 dBc/Hz at 25
kHz offset
• Representation:

Can be well-controlled Can be discrete or random in nature


• Recall: instantaneous phase variation is
indistinguishable from a variation in frequency
Phase Noise
• How it can degrade selectivity of a receiver
Phase Noise Requirement
• To achieve a certain adjacent channel rejection
(or selectivity) of 𝑆 𝑑𝐵 ≥ 0

Where:
𝐶 𝑑𝐵𝑚 - desired signal level
𝐼 𝑑𝐵𝑚 - unwanted/interference signal level
𝐵 𝐻𝑧 - IF filter bandwidth
Example: GSM Receiver
• The GSM cellular telephone requires a
minimum of 9dB rejection of interfering signal
levels of -23 dBm at 3 MHz from the carrier, -33
dBm at 1.6 MHz from the carrier, and -43 dBm
at 0.6 MHz from the carrier, for a carrier level of
-99 dBm. Determine the required local
oscillator phase noise at these offsets. GSM
channel bandwidth is 200 kHz.
Example: GSM Receiver
• Plugging in the values into the previous
equation…

• These phase noise levels are too low


• Can be achieved using phase-locked loops
(PLLs)
ECE 113
Phase-Locked Loops (PLLs) and
Frequency Synthesizers
Phase-locking

• PLL circuit forces the phase of a VCO to follow the


phase of a reference signal

• Consider mechanical clocks: Clock B is consistently


behind Clock A
• Adjust to agree with each other, OR
• Make Clock B run faster and then reset frequency
control when it catches up Clock A
Phase-locking
• PLL is used to generate a stable signal whose
frequency is determined by an unstable/noisy
reference signal

• In effect, PLL acts as a narrowband filter that


passes a carrier while rejecting its noise
sidebands

• Recall: carrier recovery


Phase-Lock Loop

• Phase difference between VCO and reference


signal produces an “error” voltage that will
adjust the frequency of the VCO

• VCO phase (𝜃𝑜𝑢𝑡 ) depends on the loop filter or


“compensation network”
Loop filter
• Uses op-amp to produce a weighted sum of
the phase detector output plus the integral of
the phase detector output
Loop filter
• Design consideration and trade-offs:
➢ Frequency range and stability
➢ Acquisition time
➢ High loop gain and tracking accuracy
Frequency Synthesizer
• A signal generator which can be switched to
put out any one of a discrete set of frequencies
and whose frequency stability is derived from a
standard oscillator

• Mostly sinusoidal

• Has high resolution ~1Hz step


Techniques
• Direct synthesizers
• Use frequency multipliers, frequency dividers, and
mixers
• Indirect synthesizers
• Use phase-lock loops
• Direct digital synthesizers
• Use a digital accumulator to produce a staircase
sawtooth, and then a staircase sinusoid, and finally
a DAC
Direct Synthesis
• Example: Producing 321 MHz from 1-MHz
reference

• Prime factor of 321 is 107 (difficult to create


this kind of multiplier). Thus, this design uses
triplers and mixers.
• Usually ad hoc designs depending on the ratio
of desired frequency and reference frequency
Mix and Divide Direct Synthesis
• Frequency division – done digitally thru flip-
flops and logic gates
• Frequency translation – thru mixers
Indirect Synthesis
• Used for digitally tuned radio and television
receivers (steps of 10 kHz)

• Due to limitations on fast switching and narrow


loop filter bandwidth, this is not desirable for
short-wave radio (steps of 10 Hz)
Direct Digital Synthesis (DDS)
• Uses adder and register (DQ flip-flops) for
accumulator, ROM for digital wave converter
(sawtooth to sine), and finally a DAC for digital-
to-analog conversion

• Example: 32-bit accumulator with 100-MHz


clock
𝑓𝑐𝑙𝑜𝑐𝑘 108
• Frequency resolution will be = = 0.023 𝐻𝑧
2𝑛 232
Comparison: Frequency Synthesizers
PARAMETER Direct Indirect Direct Digital
Switching speed Can switch almost Cannot change Can switch almost
instantly frequency faster instantly
than the time
needed for PLL to
capture and settle
Phase continuity Can be obtained if Takes some time No sudden phase
using only mixers to catch up jump
and multipliers
(no dividers)
Phase noise Depends on the filter bandwidth but in general:
Multipliers – noise power increases by 𝑛2
Dividers – noise power decreases by 𝑚2
ECE 113
Lecture 18: Oscillators, Phase-
Locked Loops (PLLs) and Frequency
Synthesizer, and Mixers

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