2396 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO.

8, AUGUST 2018

measured in [28], [29], and [34], all comparisons are based on

the previous results, including the analysis, the measurement,
and the performance of the chips qualitatively. Results are
consistent with the theoretical analysis in [28], [29], and [34].
The results in Fig. 18 indicate good noise resilience of the
proposed CLA chip under the interference of high noise
power. Compared with an MS CLA [28], the proposed CLA
is characterized by a 20% reduction in BER with 37.7% area
saving. Although a full MRF CLA [29] has the lowest BER
(28% lower than the proposed CLA), it consumes 64.4% more
transistor area. The MRF-Schmitt CLA [34] has 29% lower
BER than the proposed CLA, but it cost 35.1% more transistor
area. The observation that the BER of the MRF-Schmitt
Fig. 16. Eye pattern of the input signal of the proposed CLA chip CLA is close to that of the conventional MRF is consis-
under 6.02-dB SNR. tent with what is presented in [34]. Although the proposed
adder requires about three times the transistor number used
in a non-MRF traditional design, it achieves about 51% the
reduction of BER. For power savings, the proposed CLA
only consumes 125 nW/MHz, which saves 93% of the power
consumption of an MS CLA [28] at a supply voltage of
0.25 V. As indicated in [34], the MRF-Schmitt CLA consumes
more power than the MS CLA. Although it has a better
BER than the proposed method, it uses much more power
and requires more transistors. Therefore, the proposed MRF
circuit is a promising design, which can satisfy a great balance
between the demanding requirements of noise immunity,
power consumption, and hardware cost.

Fig. 17. Eye pattern of the output signal of the proposed CLA chip
V. C ONCLUSION
under 6.02 dB.
In this paper, we propose a low-power CPMRF method for
multi-logic operations in order to achieve a better tradeoff
between chip area and noise immunity at low power supply
voltage. First, we put forward an idea of partial clique energy
corresponding to the full clique energy used in the conven-
tional MRF design [24]. The partial clique energy is intended
to combine multiple logic operations within a shared MRF
network. Second, a coding unit is built based on the benefit
of asymmetric gates. We also propose general coding units
for complementary pairs and non-complementary pairs. Using
this CPMRF method, we fabricated an 8-bit CLA chip using
IBM 130-nm technology. In the chip validation, the proposed
CPMRF CLA achieves significant area saving and power
saving compared with the traditional MRF design [29] and
exhibits relatively high noise immunity. In comparison with
the MS design [28], the proposed CLA outperforms MS CLA
with 20% BER improvement, 37.7% area saving, and 93%
power saving at a supply voltage of 0.25 V. Considering the
Fig. 18. BER comparison under different SNRs. automation of the whole process, the CPMRF pairs proposed
in this paper can be generalized into corresponding standard
by the observed waveforms of the input and output signals, cells in cell-based designs by hardware description languages
which is shown in Figs. 16 and 17. Furthermore, we measured in the existing EDA flows. Macro blocks formed by a large
the BER of the proposed CLA under different levels of set of logic operations (standard cells) can also be trans-
noise power evaluated by SNR. Fig. 18 is the comparison of formed into the corresponding CPMRF designs by the same
BER measurements for a conventional CLA (constructed by approaches listed in this paper. Additionally, by following
normal logic gates), a full MRF CLA [29], an MS CLA [28], the mapping rules, designers can easily construct their own
an MRF-Schmitt CLA [34], and the proposed CPMRF CLA. CPMRF mapping cells to replace the old versions. The infor-
Since other designs have been implemented in silicon and mation can be included along with other parameters, such

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LI et al.: LOW-POWER NOISE-IMMUNE NANOSCALE CIRCUIT DESIGN USING CPMRF METHOD 2397

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vol. 16, no. 3, pp. 389–391, Mar. 2011. in communication engineering from the University
[15] A. Naderi, S. Mannor, M. Sawan, and W. J. Gross, “Delayed stochastic of Electronic Science and Technology of China,
decoding of LDPC codes,” IEEE Trans. Signal Process., vol. 59, no. 11, Chengdu, China, where she is currently pursuing the
pp. 5617–5626, Nov. 2011. Ph.D. degree in electrical engineering.
[16] Q. T. Dong, M. Arzel, C. Jego, and W. J. Gross, “Stochastic decoding She is currently a joint Ph.D. Student with
of turbo codes,” IEEE Trans. Signal Process., vol. 58, no. 12, the Department of Electrical and Computer Engi-
pp. 6421–6425, Dec. 2010. neering, University of Alberta, Edmonton, AB,
[17] J. Chen, J. Hu, and G. E. Sobelman, “Stochastic iterative MIMO Canada. Her current research interests include low-
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2398 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 8, AUGUST 2018

Yufeng Li (S’18) received the B.Eng. and M.Sc. Xuan Zeng (M’97) received the B.S. and Ph.D.
degrees in measuring and testing technologies and degrees in electrical engineering from Fudan Univer-
instruments inform the Wuhan University of Tech- sity, Shanghai, China, in 1991 and 1997, respec-
nology, Wuhan, China. She is currently pursuing tively.
the Ph.D. degree with the Department of Electrical She was a Visiting Professor with the Department
and Computer Engineering, University of Alberta, of Electrical Engineering, Texas A&M University,
Edmonton, AB, Canada. College Station, TX, USA, and with the Department
Her research interests include low-power error- of Microelectronics, Technische Universiteit Delft,
tolerant digital-integrated circuits and systems. Delft, The Netherlands, in 2002 and 2003, respec-
tively. She is currently a Full Professor with the
Department of Microelectronics, Fudan University,
where she was the Director of the State Key Laboratory of ASIC and
System from 2008 to 2012. Her current research interests include design for
I-Chyn Wey received the Ph.D. degree in elec- manufacturability, high-speed interconnect analysis and optimization, analog
tronics engineering from National Taiwan Univer- behavioral modeling, circuit simulation, and ASIC design.
sity, Taipei, Taiwan, in 2008. Dr. Zeng was a recipient of the Chinese National Science Funds for
He is currently an Associate Professor with the Distinguished Young Scientists in 2011 and the First-Class of Natural Science
Green Technology Research Center, Center for Prize of Shanghai in 2012. She is the Changjiang Distinguished Professor with
Reliability Sciences and Technologies, Electrical the Ministry of Education Department of China in 2014.
Engineering Department, School of Electrical and
Computer Engineering, College of Engineering,
Graduate Institute of Electrical Engineering, Chang
Gung University, Taoyuan, Taiwan, and with the
Department of Neurology, Chang Gung Memorial Xiaoxue Jiang (S’16) received the B.Sc. and M.Sc.
Hospital, Taoyuan. His current research interests include VLSI CMOS circuit degrees in electrical engineering from Jilin Univer-
design, noise-tolerant CMOS circuits, near-threshold-voltage CMOS circuits, sity, Changchun, China, in 2012 and 2015, respec-
ultralow-power CMOS circuits design, and circuits and system designs for tively. She is currently pursuing the Ph.D. degree
biomedical and wearable health applications. in electrical engineering with the University of
Alberta, Edmonton, AB, Canada.
Her current research interests include low-power
analog/mixed-signal integrated circuits and systems
Jianhao Hu (M’10) received the B.E. and Ph.D.
for biomedical applications, including wearable low-
degrees in communication systems from the Univer-
intensity pulsed-ultrasound system and impedance-
sity of Electronic Science and Technology of
based point-of-care biosensors.
China (UESTC), Chengdu, China, in 1993 and 1999,
respectively.
He is currently a Professor and Vice-Dean with
the National Key Laboratory of Communication,
UESTC. From 1999 to 2000, he was a Post-Doctoral
Jie Chen (F’16) received the Ph.D. degree in elec-
Researcher with the City University of Hong Kong,
trical and computer engineering from the University
Hong Kong. He served as a Senior System Engineer
of Maryland at College Park, College Park, MA,
with the 3G Research Center, The University of
USA.
Hong Kong, Hong Kong, from 2000 to 2004. His current research interests
He is currently a Professor with the Electrical and
include high-speed and low-power digital signal processing technology, very
Computer Engineering Department and an Adjunct
large-scale integration, NoC, wireless communications, and software radio.
Professor with the Biomedical Engineering Depart-
ment, University of Alberta, Edmonton, AB, Canada.
He is also a Research Officer at the National
Fan Yang (M’08) received the B.S. degree from Research Council/National Institute for Nanotech-
Xi’an Jiaotong University, Xi’an, China, in 2003 and nology, Edmonton. He has co-authored two books,
the Ph.D. degree from Fudan University, Shanghai, 93 journals, and 88 conference proceeding papers. He holds seven patents
China, in 2008. awarded, several of which have been either used in production or licensed by
From 2008 to 2011, he was an Assistant Professor various companies. He has i10-index of 64 according to the Google search.
with Fudan University, where he is currently His current research interests include low-power fault-tolerant nanoscale
an Associate Professor with the Microelectronics circuit and device design, impedance-based microfluidic biosensors for
Department. His current research interests include disease diagnosis and environmental monitoring, and pulsed-wave device for
model order reduction, circuit simulation, high-level increasing renewable biofuel production and cell therapy.
synthesis, yield analysis, and design for manufac- Dr. Chen is a fellow of the Canadian Academy of Engineering and the
turability. Engineering Institute of Canada.

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