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Os Notes Mit

The document summarizes the architecture of x86 CPUs and PCs. It discusses: - The key components of a PC including the CPU, memory, disk, keyboard, display and other resources like BIOS. - Details of early x86 CPUs like the 8086 including its registers, memory addressing, instruction set, and I/O. - How later CPUs like the 80386 added support for 32-bit addressing and operations to overcome limitations of 16-bit models. - Conventions for calling functions and using the stack in x86 as dictated by GCC. Functions preserve registers and set up stack frames through the frame pointer register EBP.

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0% found this document useful (0 votes)
36 views9 pages

Os Notes Mit

The document summarizes the architecture of x86 CPUs and PCs. It discusses: - The key components of a PC including the CPU, memory, disk, keyboard, display and other resources like BIOS. - Details of early x86 CPUs like the 8086 including its registers, memory addressing, instruction set, and I/O. - How later CPUs like the 80386 added support for 32-bit addressing and operations to overcome limitations of 16-bit models. - Conventions for calling functions and using the stack in x86 as dictated by GCC. Functions preserve registers and set up stack frames through the frame pointer register EBP.

Uploaded by

Surjo
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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6.

828 Lecture Notes: x86 and PC


architecture
Outline
• PC architecture
• x86 instruction set
• gcc calling conventions
• PC emulation

PC architecture
• A full PC has:
o an x86 CPU with registers, execution unit, and memory management
o CPU chip pins include address and data signals
o memory
o disk
o keyboard
o display
o other resources: BIOS ROM, clock, ...
• We will start with the original 16-bit 8086 CPU (1978)
• CPU runs instructions:
• for(;;){
• run next instruction
• }
• Needs work space: registers
o four 16-bit data registers: AX, CX, DX, BX
o each in two 8-bit halves, e.g. AH and AL
o very fast, very few
• More work space: memory
o CPU sends out address on address lines (wires, one bit per wire)
o Data comes back on data lines
o or data is written to data lines
• Add address registers: pointers into memory
o SP - stack pointer
o BP - frame base pointer
o SI - source index
o DI - destination index
• Instructions are in memory too!
o IP - instruction pointer (PC on PDP-11, everything else)
o increment after running each instruction
o can be modified by CALL, RET, JMP, conditional jumps
• Want conditional jumps
o FLAGS - various condition codes
ƒ whether last arithmetic operation overflowed
ƒ ... was positive/negative
ƒ ... was [not] zero
ƒ ... carry/borrow on add/subtract
ƒ ... overflow
ƒ ... etc.
ƒ whether interrupts are enabled
ƒ direction of data copy instructions
o JP, JN, J[N]Z, J[N]C, J[N]O ...
• Still not interesting - need I/O to interact with outside world
o Original PC architecture: use dedicated I/O space
ƒ Works same as memory accesses but set I/O signal
ƒ Only 1024 I/O addresses
ƒ Example: write a byte to line printer:
ƒ #define DATA_PORT 0x378
ƒ #define STATUS_PORT 0x379
ƒ #define BUSY 0x80
ƒ #define CONTROL_PORT 0x37A
ƒ #define STROBE 0x01
ƒ void
ƒ lpt_putc(int c)
ƒ {
ƒ /* wait for printer to consume previous byte */
ƒ while((inb(STATUS_PORT) & BUSY) == 0)
ƒ ;
ƒ
ƒ /* put the byte on the parallel lines */
ƒ outb(DATA_PORT, c);
ƒ
ƒ /* tell the printer to look at the data */
ƒ outb(CONTROL_PORT, STROBE);
ƒ outb(CONTROL_PORT, 0);
ƒ }

o Memory-Mapped I/O
ƒ Use normal physical memory addresses
ƒ Gets around limited size of I/O address space
ƒ No need for special instructions
ƒ System controller routes to appropriate device
ƒ Works like ``magic'' memory:
ƒ Addressed and accessed like memory, but ...
ƒ ... does not behave like memory!
ƒ Reads and writes can have ``side effects''
ƒ Read results can change due to external events
• What if we want to use more than 2^16 bytes of memory?
o 8086 has 20-bit physical addresses, can have 1 Meg RAM
o each segment is a 2^16 byte window into physical memory
o virtual to physical translation: pa = va + seg*16
o the segment is usually implicit, from a segment register
o CS - code segment (for fetches via IP)
o SS - stack segment (for load/store via SP and BP)
o DS - data segment (for load/store via other registers)
o ES - another data segment (destination for string operations)
o tricky: can't use the 16-bit address of a stack variable as a pointer
o but a far pointer includes full segment:offset (16 + 16 bits)
• But 8086's 16-bit addresses and data were still painfully small
o 80386 added support for 32-bit data and addresses (1985)
o boots in 16-bit mode, boot.S switches to 32-bit mode
o registers are 32 bits wide, called EAX rather than AX
o operands and addresses are also 32 bits, e.g. ADD does 32-bit arithmetic
o prefix 0x66 gets you 16-bit mode: MOVW is really 0x66 MOVW
o the .code32 in boot.S tells assembler to generate 0x66 for e.g. MOVW
o 80386 also changed segments and added paged memory...

x86 Physical Memory Map


• The physical address space mostly looks like ordinary RAM
• Except some low-memory addresses actually refer to other things
• Writes to VGA memory appear on the screen
• Reset or power-on jumps to ROM at 0x000ffff0

+------------------+ <- 0xFFFFFFFF (4GB)


| 32-bit |
| memory mapped |
| devices |
| |
/\/\/\/\/\/\/\/\/\/\

/\/\/\/\/\/\/\/\/\/\
| |
| Unused |
| |
+------------------+ <- depends on amount of RAM
| |
| |
| Extended Memory |
| |
| |
+------------------+ <- 0x00100000 (1MB)
| BIOS ROM |
+------------------+ <- 0x000F0000 (960KB)
| 16-bit devices, |
| expansion ROMs |
+------------------+ <- 0x000C0000 (768KB)
| VGA Display |
+------------------+ <- 0x000A0000 (640KB)
| |
| Low Memory |
| |
+------------------+ <- 0x00000000

x86 Instruction Set


• Two-operand instruction set
o Intel syntax: op dst, src
o AT&T (gcc/gas) syntax: op src, dst
ƒ uses b, w, l suffix on instructions to specify size of operands
o Operands are registers, constant, memory via register, memory via
constant
o Examples:

AT&T syntax "C"-ish equivalent


movl %eax, %edx edx = eax; register mode
movl $0x123, %edx edx = 0x123; immediate
movl 0x123, %edx edx = *(int32_t*)0x123; direct
movl (%ebx), %edx edx = *(int32_t*)ebx; indirect
movl 4(%ebx), %edx edx = *(int32_t*)(ebx+4); displaced

• Instruction classes
o data movement: MOV, PUSH, POP, ...
o arithmetic: TEST, SHL, ADD, AND, ...
o i/o: IN, OUT, ...
o control: JMP, JZ, JNZ, CALL, RET
o string: REP MOVSB, ...
o system: IRET, INT
• Intel architecture manual Volume 2 is the reference

gcc x86 calling conventions


• x86 dictates that stack grows down:

Example instruction What it does


subl $4, %esp
pushl %eax
movl %eax, (%esp)
movl (%esp), %eax
popl %eax
addl $4, %esp
pushl %eip (*)
call $0x12345
movl $0x12345, %eip (*)
ret popl %eip (*)
• (*) Not real instructions
• GCC dictates how the stack is used. Contract between caller and callee on x86:
o after call instruction:
ƒ %eip points at first instruction of function
ƒ %esp+4 points at first argument
ƒ %esp points at return address
o after ret instruction:
ƒ %eip contains return address
ƒ %esp points at arguments pushed by caller
ƒ called function may have trashed arguments
ƒ %eax contains return value (or trash if function is void)
ƒ %ecx, %edx may be trashed
ƒ %ebp, %ebx, %esi, %edi must contain contents from time of call
o Terminology:
ƒ %eax, %ecx, %edx are "caller save" registers
ƒ %ebp, %ebx, %esi, %edi are "callee save" registers
• Functions can do anything that doesn't violate contract. By convention, GCC does
more:
o each function has a stack frame marked by %ebp, %esp
o +------------+ |
o | arg 2 | \
o +------------+ >- previous
function's stack frame
o | arg 1 | /
o +------------+ |
o | ret %eip | /
o +============+
o | saved %ebp | \
o %ebp-> +------------+ |
o | | |
o | local | \
o | variables, | >- current
function's stack frame
o | etc. | /
o | | |
o | | |
o %esp-> +------------+ /

o %esp can move to make stack frame bigger, smaller


o %ebp points at saved %ebp from previous function, chain to walk stack
o function prologue:
o pushl %ebp
o movl %esp, %ebp

o function epilogue:
o movl %ebp, %esp
o popl %ebp
or

leave

• Big example:
o C code
o int main(void) { return f(8)+1; }
o int f(int x) { return g(x); }
o int g(int x) { return x+3; }

o assembler
o _main:
o prologue
o pushl %ebp
o movl %esp, %ebp
o body
o pushl $8
o call _f
o addl $1, %eax
o epilogue
o movl %ebp, %esp
o popl %ebp
o ret
o _f:
o prologue
o pushl %ebp
o movl %esp, %ebp
o body
o pushl 8(%esp)
o call _g
o epilogue
o movl %ebp, %esp
o popl %ebp
o ret
o
o _g:
o prologue
o pushl %ebp
o movl %esp, %ebp
o save %ebx
o pushl %ebx
o body
o movl 8(%ebp), %ebx
o addl $3, %ebx
o movl %ebx, %eax
o restore %ebx
o popl %ebx
o epilogue
o movl %ebp, %esp
o popl %ebp
o ret
• Super-small _g:
• _g:
• movl 4(%esp), %eax
• addl $3, %eax
• ret

• Compiling, linking, loading:


o Compiler takes C source code (ASCII text), produces assembly language
(also ASCII text)
o Assembler takes assembly language (ASCII text), produces .o file (binary,
machine-readable!)
o Linker takse multiple '.o's, produces a single program image (binary)
o Loader loads the program image into memory at run-time and starts it
executing

PC emulation
• Emulator like Bochs works by
o doing exactly what a real PC would do,
o only implemented in software rather than hardware!
• Runs as a normal process in a "host" operating system (e.g., Linux)
• Uses normal process storage to hold emulated hardware state: e.g.,
o Hold emulated CPU registers in global variables
o int32_t regs[8];
o #define REG_EAX 1;
o #define REG_EBX 2;
o #define REG_ECX 3;
o ...
o int32_t eip;
o int16_t segregs[4];
o ...

o malloc a big chunk of (virtual) process memory to hold emulated PC's


(physical) memory
• Execute instructions by simulating them in a loop:
• for (;;) {
• read_instruction();
• switch (decode_instruction_opcode()) {
• case OPCODE_ADD:
• int src = decode_src_reg();
• int dst = decode_dst_reg();
• regs[dst] = regs[dst] + regs[src];
• break;
• case OPCODE_SUB:
• int src = decode_src_reg();
• int dst = decode_dst_reg();
• regs[dst] = regs[dst] - regs[src];
• break;
• ...
• }
• eip += instruction_length;
• }

• Simulate PC's physical memory map by decoding emulated "physical" addresses


just like a PC would:
• #define KB 1024
• #define MB 1024*1024

• #define LOW_MEMORY 640*KB
• #define EXT_MEMORY 10*MB

• uint8_t low_mem[LOW_MEMORY];
• uint8_t ext_mem[EXT_MEMORY];
• uint8_t bios_rom[64*KB];

• uint8_t read_byte(uint32_t phys_addr) {
• if (phys_addr < LOW_MEMORY)
• return low_mem[phys_addr];
• else if (phys_addr >= 960*KB && phys_addr < 1*MB)
• return rom_bios[phys_addr - 960*KB];
• else if (phys_addr >= 1*MB && phys_addr <
1*MB+EXT_MEMORY) {
• return ext_mem[phys_addr-1*MB];
• else ...
• }

• void write_byte(uint32_t phys_addr, uint8_t val) {
• if (phys_addr < LOW_MEMORY)
• low_mem[phys_addr] = val;
• else if (phys_addr >= 960*KB && phys_addr < 1*MB)
• ; /* ignore attempted write to ROM! */
• else if (phys_addr >= 1*MB && phys_addr <
1*MB+EXT_MEMORY) {
• ext_mem[phys_addr-1*MB] = val;
• else ...
• }

• Simulate I/O devices, etc., by detecting accesses to "special" memory and I/O
space and emulating the correct behavior: e.g.,
o Reads/writes to emulated hard disk transformed into reads/writes of a file
on the host system
o Writes to emulated VGA display hardware transformed into drawing into
an X window
o Reads from emulated PC keyboard transformed into reads from X input
event queue

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