UNIT 2

EMBEDDED NETWORKING
Networks for embedded computing span a broad range of requirements; many of those requirements
are very different from those for general-purpose networks. Some networks are used in safety-critical
applications, such as automotive control. Some networks, such as those used in consumer electronics
systems, must be very inexpensive. Other networks,such as industrial control networks,must be
extremely rugged and reliable. IO devices communicate with processor through an IO bus ,which is
separate from memory bus that the processor used to communicate with the memory system.
Embedded system communicate internally on the same IC or systems with very short and long
distances and can be networked by using following bus each functioning according to specific
protocols.

1. Using serial IO bus allows a computer or controller or embedded system to interface network with
a wide range of IO devices without having to implement a specific interface for each IO device.when
the IO devices in the distributed embedded system are networked at long distances of 25cm and
above all can communicate through a common serial bus.A serial bus has very few lines

2. Using parellel IO bus allows a computer or controller or embedded system to interface with a
number of internal systems at very short distances without having to implement a specific interface
for each IO device.

3. Using the internet or intranet a computer, controller or embedded system IO device can interface
globally and can network with othersystems or computers and a wide range of devices in the
distributed system.

4. Using wireless protocols allows a handheld computer ,controller or embedded system IO device to
interface and network with a number of handheld system IO devices at short devices upto 100 m using
a wireless personel area(WPAN) protocol without having to implement a specific wireless interface
for each IO device Embedded systems are distributed and networked using a serial or parallel bus or
wireless protocol software and appropriate hardware.Several interconnect networks have been
developed especially for distributed embedded computing:
Synchronous Serial Input :The sender along with the serial bits also sends the clock pulses SCLK (serial
clock) to the receiver port pin. The port synchronizes the serial datainput bits with clock bits. Each bit
in each byte as well as each byte in synchronization . Synchronization means separation by a constant
interval or phase difference. If clock period = T, then each byte at the port is received at input in period
= 8T. The bytes are received at constant rates. Each byte at input port separates by 8T and data
transfer rate for the serial line bits is (1/T) bps. [1bps = 1 bit per s]

Serial data and clock pulse-inputs :On same input line − when clock pulses either encode or modulate
serial data input bits suitably. Receiver detects the clock pulses and receives data bits after decoding
or demodulating. On separate input line − When a separate SCLK input is sent, the receiver detects at
the middle or + ve edge or –ve edge of the clock pulses that whether the data-input is 1 or 0 and saves
the bits in an 8-bit shift register. The processing element at the port (peripheral) saves the byte at a
port register from where the microprocessor reads the byte.

Master output slave input (MOSI) and Master input slave output (MISO) : MOSI when the SCLK is
sent from the sender to the receiver and slave is forced to synchronize sent inputs from the master as
per the inputs from master clock. MISO when the SCLK is sent to the sender (slave) from the receiver
(master) and slave is forced to synchronize for sending the inputs to master as per the master clock
outputs. Synchronous serial input is used for interprocessor transfers, audio inputs and streaming data
inputs.

Synchronous Serial Input Example : Inter-processor data transfer, reading from CD or hard disk, audio
input, video input, dial tone, network input, transceiver input, scanner input, remote controller input,
serial I/O bus input, writing to flash memory using SDIO (Secure Data Association IO based card)
Synchronous Serial Output : Each bit in each byte sent in synchronization with a clock. Bytes sent at
constant rates. If clock period = T, then data transfer rate is (1/T) bps. Sender either sends the clock
pulses at SCLK pin or sends the serial data output and clock pulse-input through same output line with
clock pulses either suitably modulate or encode the serial output bits.

Synchronous serial output using shift register : The processing element at the port (peripheral) sends
the byte through a shift register at the port to where the microprocessor writes the byte. Synchronous
serial output is used for interprocessor transfers, audio outputs and streaming data outputs.

Example Synchronous Serial Output: Inter-processor data transfer, multiprocessor communication,

writing to CD or hard disk, audio Input/output, video Input/output, dialer output, network device
output, remote TV Control, transceiver output, and serial I/O bus output or writing to flash memory
using SDIO.
Synchronous Serial Input/Output : Each bit in each byte is in synchronization at input and each bit in
each byte is in synchronization at output with the master clock output . The bytes are sent or received
at constant rates. The I/Os can also be on same I/O line when input/output clock pulses either suitably
modulate or encode the serial input/output, respectively. If clock period = T, then data transfer rate
is (1/T) bps. The processing element at the port (peripheral) sends and receives the byte at a port
register to or from where the microprocessor writes or reads the byte.

Serial Bus Communication Protocols:

The following describes most popular serial buses

1. The I2 C bus is used in microcontroller-based systems.

2. The Controller Area Network (CAN) bus was developed for automotive electronics. It provides
megabit rates and can handle large numbers of devices.

3. USB Bus

4. Fire wire-IEEE 1394 bus standard

5. Advanced high speed buses

6. Ethernet and variations of standard Ethernet are used for a variety of control applications. In
addition, many networks designed for general-purpose computing have been put to use in embedded
applications as well.

The I2C Bus:

• The I 2C bus is a well-known bus commonly used to link microcontrollers into systems. I 2C is
designed to be low cost,easy to implement, and of moderate speed (up to 100 KB/s for the standard
bus and up to 400 KB/s for the extended bus). As a result, it uses only two lines: the serial data line
(SDL) for data and the serial clock line (SCL), which indicates when valid data are on the data line.
Figure 8.7 shows the structure of a typical I2C bus system. Every node in the network is connected
to both SCL and SDL. Some nodes may be able to act as bus masters and the bus may have more than
one master. Other nodes may act as slaves that only respond to requests from masters..

• I2C signaling

o Sender pulls down bus for 0.

o Sender listens to bus---if it tried to send a 1 and heard a 0, someone else is
simultaneously transmitting.
o Transmissions occur in 8-bit bytes.
➢ I C data link layer
2

o Every device has an address (7 bits in standard, 10 bits in extension).

o Bit 8 of address signals read or write.
o General call address allows broadcast.
➢ I C bus arbitration
2

o Sender listens while sending address.

o When sender hears a conflict, if its address is higher, it stops signaling.
o Low-priority senders relinquish control early enough in clock cycle to allow bit to be
transmitted reliably.

TABLE

Field and its length Explanation

First field of 1-bit It is start bit similar to the one in a UART.

 Second field of 7-bits It is called the address field. It defines the slave address
being sent the data frame(of man bytes)by the master.

Third field of 1 control bit It defines whether a read or write cycle is in progress.

Fourth field of 1 control bit Next bit defines whether the present data is an
acknowledgement (from the slave).

Fifth field of 8 bits It is used for IC device data bits.

Sixth field of 1-bit It is negative acknowledgement bit(NACK) from the

master.If active,then acknowledgement after a transfer is
not needed from the slave,else acknowledgement is
expected from the slave.

Seventh field of 1-bit It is a stop bit like in a UART.

The disadvantage of this bus is the time taken by algorithm in the master hardware that analyses the
bits through I²C in case the slave hardware does not provide for the hardware that supports it.

The I2C bus is designed as a multimaster bus—any one of several different devices may act as the
master at various times. As a result, there is no global master to generate the clock signal on SCL.
Instead, a master drives both SCL and SDL .when it is sending data.When the bus is idle, both SCL and
SDL remain high.When two devices try to drive either SCL or SDL to different values, the open collector
open drain circuitry prevents errors, but each master device must listen to the bus while transmitting
to be sure that it is not interfering with another message—if the device receives a different value than
it is trying to transmit, then it knows that it interfering with another message. Every I2 C device has an
address. The addresses of the devices are determined by the system designer, usually as part of the
program for the I2 C driver. The addresses must of course be chosen so that no two devices in the
system have the same address. A device address is 7 bits in the standard I2 C definition (the extended
I2 C allows 10-bit addresses). A bus transaction is initiated by a start signal and completed with an end
signal as follows:

■ A start is signaled by leaving the SCL high and sending a 1 to 0 transition on SDL.

■ A stop is signaled by setting the SCL high and sending a 0 to 1 transition on SDL.
I2C Characteristics
Open Drain – Bidirectional Communication

Open drain means all devices are using a MOSFET with open drain (not connected to anywhere
else) to drive the bus voltage. This technique ensures easy bidirectional communication among
multiple devices without any conflicts which may cause short circuit/excess currents if we
connect in normal ways.
Thus the bus line may be pulled down to GROUND voltage if any of the MOSFET in a I2C
device is ON or release the bus line and let it be pulled up by the pull up resistor.
Open Drain – Pulling Low

When the device needs to transmit LOW, it can switch ON the MOSFET, the bus will be pulled down
(shorted to ground).

Open Drain – Releasing Bus

When a device needs to transmit HIGH, it can simply release the bus (MOSFET OFF). This leaves the
bus floating and it will be pulled HIGH by the pull up resistors.

Arbitration:
Several I2C multi-masters can be connected to the same I2C bus and operate concurrently. By
constantly monitoring SDA and SCL for start and stop conditions, they can determine whether
the bus is currently idle or not. If the bus is busy, masters delay pending I2C transfers until a
stop condition indicates that the bus is free again.
However, it may happen that two masters start a transfer at the same time. During the transfer,
the masters constantly monitor SDA and SCL. If one of them detects that SDA is low when it
should actually be high, it assumes that another master is active and immediately stops its
transfer. This process is called arbitration.

APPLICATION OF I2C IN MICROCONTROLLERS

There is a built in I2C in modern microcontrollers such as PIC microcontroller. The basic
working and functioning of this chip is same as explained above. The figure below shows that
different devices can be connected with it by using only two pins of the microcontroller:

In this figure, the first device is a thermometer, the second one is an alarm clock and the third
device is a LCD display. All of these are connected as slaves with the microcontroller. If there
is any difference in their voltage levels then it can be adjusted by adding pull up resistors. Only
one set of pull up resistors will be enough for the whole bus, we don’t have to connect the
resistors separately with each device.
The communication will start as the clock signal is initiated. Both the master and slaves will be
synchronized, after which the master will initiate the data exchange. First, it will send the start bit,
then the 7 bit address which will indicate the slave to be selected and finally the read/write bit is sent.
As soon as the first byte is sent the master waits for an acknowledgement signal and the data transfer
continues till the stop bit is finally sent by the master.

CAN BUS:

CAN stands for Controller Area Network protocol. It is a protocol that was developed by Robert
Bosch in around 1986. The CAN protocol is a standard designed to allow the microcontroller and other
devices to communicate with each other without any host computer. The feature that makes the CAN
protocol unique among other communication protocols is the broadcast type of bus. Here, broadcast
means that the information is transmitted to all the nodes. The node can be a sensor, microcontroller,
or a gateway that allows the computer to communicate over the network through the USB cable or
ethernet port. The CAN is a message-based protocol, which means that message carries the message
identifier, and based on the identifier, priority is decided. There is no need for node identification in
the CAN network, so it becomes very easy to insert or delete it from the network. It is a serial half-
duplex and asynchronous type of communication protocol. The CAN is a two-wired communication
protocol as the CAN network is connected through the two-wired bus. The wires are twisted pair
having 120Ω characteristics impedance connected at each end. Initially, it was mainly designed for
communication within the vehicles, but it is now used in many other contexts. Like UDS, and KWP
2000, CAN also be used for the on-board diagnostics.

A CAN network consists of multiple of CAN nodes. In the above case, we have considered three CAN
nodes, and named them as node A, node B, and node C. CAN node consists of three elements which
are given below:

Host
A host is a microcontroller or microprocessor which is running some application to do a specific job. A
host decides what the received message means and what message it should send next.

CANController
CAN controller deals with the communication functions described by the CAN protocol. It also triggers
the transmission, or the reception of the CAN messages.

CANTransceiver
CAN transceiver is responsible for the transmission or the reception of the data on the CAN bus. It
converts the data signal into the stream of data collected from the CAN bus that the CAN controller
can understand.
In the above diagram, unshielded twisted pair cable is used to transmit or receive the data. It is also
known as CAN bus, and CAN bus consists of two lines, i.e., CAN low line and CAN high line, which are
also known as CANH and CANL, respectively. The transmission occurs due to the differential voltage
applied to these lines. The CAN uses twisted pair cable and differential voltage because of its
environment. For example, in a car, motor, ignition system, and many other devices can cause data
loss and data corruption due to noise. The twisting of the two lines also reduces the magnetic field.
The bus is terminated with 120Ω resistance at each end.

CAN BUS PROTOCOL FRAME FORMAT:

o SOF: SOF stands for the start of frame, which indicates that the new frame is entered in a
network. It is of 1 bit.
o Identifier: A standard data format defined under the CAN 2.0 A specification uses an 11-bit
message identifier for arbitration. Basically, this message identifier sets the priority of the data
frame.
o RTR: RTR stands for Remote Transmission Request, which defines the frame type, whether it
is a data frame or a remote frame. It is of 1-bit.
o Control field: It has user-defined functions.
1. IDE: An IDE bit in a control field stands for identifier extension. A dominant IDE bit
defines the 11-bit standard identifier, whereas recessive IDE bit defines the 29-bit
extended identifier.
 2. DLC: DLC stands for Data Length Code, which defines the data length in a data field. It
is of 4 bits.
3. Data field: The data field can contain upto 8 bytes.
o CRC field: The data frame also contains a cyclic redundancy check field of 15 bit, which is used
to detect the corruption if it occurs during the transmission time. The sender will compute the
CRC before sending the data frame, and the receiver also computes the CRC and then
compares the computed CRC with the CRC received from the sender. If the CRC does not
match, then the receiver will generate the error.
o ACK field: This is the receiver's acknowledgment. In other protocols, a separate packet for an
acknowledgment is sent after receiving all the packets, but in case of CAN protocol, no
separate packet is sent for an acknowledgment.
o EOF: EOF stands for end of frame. It contains 7 consecutive recessive bits known End of frame.

CAN layered architecture

The OSI model partitions the communication system into 7 different layers. But the CAN
layered architecture consists of two layers, i.e., data-link layer and physical layer.

Data-link layer: This layer is responsible for node to node data transfer. It allows you to establish and
terminate the connection. It is also responsible for detecting and correcting the errors that may occur
at the physical layer. Data-link layer is subdivided into two sub-layers:
MAC: MAC stands for Media Access Control. It defines how devices in a network gain access to the
medium. It provides Encapsulation and Decapsulation of data, Error detection, and signaling.

LLC: LLC stands for Logical link control. It is responsible for frame acceptance filtering, overload
notification, and recovery management.

Physical layer: The physical layer is responsible for the transmission of raw data. It defines the
specifications for the parameters such as voltage level, timing, data rates, and connector.

CAN specifications define CAN protocol and CAN physical layer, which are defined in the
CAN standard ISO 11898. ISO 11898 has three parts:
ISO 11898-1: This part contains the specification of the Data-link layer and physical signal link.

ISO 11898-2: This part comes under CAN physical layer for high speed CAN. The high- speed CAN allows
data rate upto 1 Mbps used in the power train and the charges area of the vehicle.

ISO 11898-3: This part also comes under CAN physical layer for low-speed CAN. It allows data rate
upto 125 kbps, and the low speed CAN is used where the speed of communication is not a critical
factor.

CiA DS-102: The full form of CiA is CAN in Automation, which defines the specifications for
the CAN connector.
As far as the implementation is concerned, the CAN controller and CAN transceiver are implemented
in the software with the help of the application, operating system, and network management
functions.

The Controller Area Network (CAN bus) is the nervous system, enabling communication.
In turn, 'nodes' or 'electronic control units' (ECUs) are like parts of the body, interconnected
via the CAN bus. Information sensed by one part can be shared with another.
In an automotive CAN bus system, ECUs can e.g. be the engine control unit, airbags, audio
system etc. A modern car may have up to 70 ECUs - and each of them may have information
that needs to be shared with other parts of the network.
The CAN bus system enables each ECU to communicate with all other ECUs - without
complex dedicated wiring.
Specifically, an ECU can prepare and broadcast information (e.g. sensor data) via the CAN
bus (consisting of two wires, CAN low and CAN high). The broadcasted data is accepted by
all other ECUs on the CAN network - and each ECU can then check the data and decide
whether to receive or ignore it.
Communication over the CAN bus is done via CAN frames.
Below is a standard CAN frame with 11 bits identifier (CAN 2.0A), which is the type used in
most cars. The extended 29-bit identifier frame (CAN 2.0B) is identical except the longer ID.
It is e.g. used in the J1939 protocol for heavy-duty vehicles.

In serial communication data bits are transmitted one after the other in sequential manner using
single communication channel. Example of serial interface is RS-232 which is point to point
and asynchronous interface. It is used between devices (i.e. DTE and DCE).
Protocol uses start bit and stop bit for data communication. Serial interfaces may have multiple
lines but only one line is used for data communication.
There are two methods in serial communication viz. synchronous and asychronous. In
synchronous communication, block of data (or characters) are transferred at a time. In
asynchronous communication, single byte (or bit) is transferred at a time. There are special ICs
used for this communication such as UART and USART. The microcontroller IC such as 8051
consists of in-built UART chip. PISO and SIPO shift registers are used to convert serial data
into parallel data and vice versa.

Benefits or advantages of Serial Interface

Following are the benefits or advantages of Serial Interface:

➨It uses less number of conducting wires, hence reduces cost of the interface.
➨It supports long distance data communication.

➨It uses less number of wires often only one, this leads to simple interface between
transmitting and receiving devices or ICs. It is easy to implement.

Drawbacks or disadvantages of Serial Interface

Following are the disadvantages of Serial Interface:

➨It uses less number of lines for transmission between devices. Hence it supports slower speed
of transmission.
 ➨It occupies overhead of about 20% other than useful information. This leads to wastage of
bandwidth meant for data trasmission for useless stuff.
The parallel transmission defines a transmission structure that shares multiple data bits at a
similar time over separate media. In general, parallel transmission can be used with a wired
channel that uses multiple, separate wires.
The figure given below shows the concept and shows why engineers use the term parallel to
characterize the wiring.

The figure omits two important elements. First, in addition to the parallel wires that each hold
data, a parallel interface generally includes other wires that enable the sender and receiver to
coordinate. Second, to create installation and troubleshooting simply, the wires for a parallel
transmission system are located in a single physical cable. Thus, one expects to view a single,
large cable connecting a sender and receiver rather than a set of independent physical wires.
Advantages
The advantages of parallel transmission are as follows −
• High speed − It can transmit N bits at the same time. A parallel interface can work N times
quicker than an equivalent serial interface.
• Match to underlying hardware − Internally, computer and transmission hardware use parallel
circuits. Thus, a parallel interface matches the internal hardware well.
• Data is sent much faster as parallel transmission can increase the transfer speed by a factor of
n over the serial transmission.
• A huge amount of data is to be transmitted over connection lines.
• Parallel transmission can send information from computer to printer. The printer is linked to
the parallel port of the computer and a parallel cable that has multiple wires can link the printer
to the computer. It is a very fast data transmission mode.
Disadvantages
• Transmission of n communication lines is required to transmit the data stream and for this n
number of wires must be required.
This is expensive so it is usually limited to shorter distances.

USB BUS:

It connets flash memory cards, pen-like memory devices, digital camera, printer, mouse-device,
PocketPC, video games, Scanner etc USB allows Serial transmission and reception between host and
serial devices .

The data transfer is of four types: (a) Controlled data transfer, (b) Bulk data transfer, (c) Interrupt
driven data transfer, (d) Iso-synchronous transfer A bus between the host system and interconnected
number of peripheral devices .Maximum 127 devices can connect a host.

Three standards:

• USB 1.1 (a low speed 1.5 Mbps 3 meter channel along with a high speed 12 Mbps 25 meter channel)
• USB 2.0 (high speed 480 Mbps 25 meter channel)

• wireless USB (high speed 480 Mbps 3 m) Host connection to the devices or nodes is using USB port
driving software and host controller, Host computer or system has a hostcontroller, which connects
to a root hub. A hub is one that connects to other nodes or hubs. A tree- like topology is used.

The root hub connects to the hub (s) and node (s) at level 1. A hub at level 1 connects to the hub (s)
and node (s) at level 2 and so on. Root hub and each hub at a level have a star topology with the next
level. Only the nodes are present at the last level.
USB Device features :Device Can be hot plugged (attached), configured and used, reset, reconfigured
and used Bandwidth sharing with other devices: Host schedules the sharing of bandwidth among the
attached devices at an instance. Can be detached (while others are in operation) and reattached.
Attaching and detaching USB device or host without rebooting

USB device descriptor: Has data structure hierarchy as follows: It has device descriptor at the root,
which has number of configuration descriptors, which has number of interface descriptor and which
has number of end point descriptor. Powering

USB device : A device can be either bus-powered or self- powered. In addition, there is a power
management by software at the host for USB ports

USB protocol:

USB bus cable has four wires, one for +5V, two for twisted pairs and one for ground.Termination
impedances at each end as per the device-speed.

• Electromagnetic Interference (EMI)- shielded cable for the 15 Mbps USB devices.

• Serial signals NRZI (Non Return to Zero (NRZI) The synchronization clock encoded by inserting
synchronous code (SYNC) field before each USB packet Receiver synchronizes its bits recovery clock
continuously

• A polled bus

• Host controller regularly polls the presence of a device as scheduled by the software. It sends a token
packet. The token consists of fields for type, direction, USB device address and device end-point
number.

• The device does the handshaking through a handshake packet, indicating successful or unsuccessful
transmission. A CRC field in a data packet permits error detection

USB supported three types of pipes 1. 'Stream' with no USB- defined protocol. It is used when the
connection is already established and the data flow starts 2. 'Default Control' for providing access. •
3. 'Message' for the control functions for of the device. Host configures each pipe with the data
bandwidth to be used, transfer service type and buffer sizes. Wireless USB: Wireless extension of USB
2.0 and it operates at UWB (ultra wide band) 3.1 GHZ to 10.6 GHz frequencies. For short-range
personal area network (high speed 480 Mbps 3 meter or 110 Mbps 10 meter channel).

SPI Protocol

SPI stands for the Serial Peripheral Interface. It is a serial communication protocol that is used to
connect low-speed devices. It was developed by Motorola in the mid-1980 for inter-chip
communication. It is commonly used for communication with flash memory, sensors, real-time clock
(RTC), analog-to-digital converters, and more. It is a full-duplex synchronous serial communication,
which means that data can be simultaneously transmitted from both directions.

The main advantage of the SPI is to transfer the data without any interruption. Many bits can be sent
or received at a time in this protocol.

In this protocol, devices are communicated in the master-slave relationship. The master device
controls the slave device, and the slave device takes the instruction from the master device. The
simplest configuration of the Serial Peripheral Interface (SPI) is a combination of a single slave and a
single master. But, one master device can control multiple slave devices.

SPI Interface:
The SPI protocol uses the four wires for the communication. There are shown in the figure.

SPI Lines

MISO (Master in Slave out): The MISO line is configured as an input in a master device and
as an output in a slave device.
MOSI (Master out Slave in): The MOSI is a line configured as an output in a master device
and as an input in a slave device wherein it is used to synchronize the data movement.
SCK (serial clock): This signal is always driven by the master for synchronous data transfer
between the master and the slave. It is used to synchronize the data movement both in and out
through the MOSI and MISO lines.
SS (Slave Select) and CS (Chip Select): This signal is driven by the master to select individual
slaves/Peripheral devices. It is an input line used to select the slave devices.

Master Slave Communication with SPI Serial Bus

Single Master and Single Slave SPI Implementation

Here, the communication is always initiated by the master. The master device first configures
the clock frequency which is less than or equal to the maximum frequency that the slave device
supports. The master then selects the desired slave for communication by dragging the chip
select line (SS) of that particular slave device to go low state and active. The master generates
the information on to the MOSI line that carries the data from master to slave.
Single Master and Multiple Slave Implementations

This is a multiple slave configuration with one master and multiple slaves through the SPI
serial bus. The multiple slaves are connected in parallel to the master device with the SPI serial
bus. Here, all the clock lines and data lines are connected together, but the chip select pin from
each slave device must be connected to a separate slave select pin on the maser device.

In this process, the control of each slave device is performed by a chip select line (SS). The
chip select pin goes low to activate the slave device and goes high to disable the slave device.
The data transfer is organized by using the shift registers at both master and slave devices with
a given word size of about 8-bit and 16-bit, respectively. Both the devices are connected in a
ring form so that the maser shift register value is transmitted through the MOSI line, and then
the slave shifts data in its shift register. The data is usually shifted out with the MSB first and
shifting new LSB into the same register.
In telecommunication, the process of sending data sequentially over a computer bus is called as serial
communication, which means the data will be transmitted bit by bit. While in parallel communication
the data is transmitted in a byte (8 bit) or character on several data lines or buses at a time. Serial
communication is slower than parallel communication but used for long data transmission due to
lower cost and practical reasons.

RS232 is a standard protocol used for serial communication, it is used for connecting computer and
its peripheral devices to allow serial data exchange between them. As it obtains the voltage for the
path used for the data exchange between the devices. It is used in serial communication up to 50 feet
with the rate of 1.492kbps. As EIA defines, the RS232 is used for connecting Data Transmission
Equipment (DTE) and Data Communication Equipment (DCE).

RS232 works on the two-way communication that exchanges data to one another. There are two
devices connected to each other, (DTE) Data Transmission Equipment& (DCE) Data Communication
Equipment which has the pins like TXD, RXD, and RTS& CTS. Now, from DTE source,
the RTS generates the request to send the data. Then from the other side DCE, the CTS, clears the
path for receiving the data. After clearing a path, it will give a signal to RTS of the DTE source to send
the signal. Then the bits are transmitted from DTE to DCE. Now again from DCE source, the request
can be generated by RTS and CTS of DTE sources clears the path for receiving the data and gives a
signal to send the data. This is the whole process through which data transmission takes place.

RS232 works on the two-way communication that exchanges data to one another. There are two
devices connected to each other, (DTE) Data Transmission Equipment& (DCE) Data Communication
Equipment which has the pins like TXD, RXD, and RTS& CTS. Now, from DTE source,
the RTS generates the request to send the data. Then from the other side DCE, the CTS, clears the
path for receiving the data. After clearing a path, it will give a signal to RTS of the DTE source to send
the signal. Then the bits are transmitted from DTE to DCE. Now again from DCE source, the request
can be generated by RTS and CTS of DTE sources clears the path for receiving the data and gives a
signal to send the data. This is the whole process through which data transmission takes place.

Handshaking is the process which is used to transfer the signal from DTE to DCE to make the
connection before the actual transfer of data. The messaging between transmitter & receiver
can be done by handshaking.
There are 3 types of handshaking processes named as:-

No Handshaking:

If there is no handshaking, then DCE reads the already received data while DTE transmits the
next data. All the received data stored in a memory location known as receiver’s buffer. This
buffer can only store one bit so receiver must read the memory buffer before the next bit arrives.
If the receiver is not able to read the stored bit in the buffer and next bit arrives then the stored
bit will be lost.

As shown in below diagram, a receiver was unable to read the 4th bit till the 5th bit arrival and
this result overriding of 4th bit by 5th bit and 4th bit is lost.

Hardware Handshaking:

▪ It uses specific serial ports, i.e., RTS & CTS to control data flow.
▪ In this process, transmitter asks the receiver that it is ready to receive data then receiver checks
the buffer that it is empty, if it is empty then it will give signal to the transmitter that I am ready to
receive data.
▪ The receiver gives the signal to transmitter not to send any data while already received data cannot
be read.
▪ Its working process is same as above described in handshaking.
Software Handshaking:

▪ In this process, there are two forms, i.e., X-ON & X-OFF. Here, ‘X’ is the transmitter.
▪ X-ON is the part in which it resumes the data transmission.
▪ X-OFF is the part in which it pauses the data transmission.
▪ It is used to control the data flow and prevent loss during transmission.

UART: Universal Asynchronous Receiver Transmitter UART is a serial communication device that
performs parallel to serial data conversion at the transmitter and serial to parallel data conversion at
the receiver side. UART is being used in many applications GPS Receivers, Bluetooth Modules, GSM
and GPRS Modems, Wireless Communication systems and RFID based systems. Features • It is a simple
half-duplex, asynchronous, serial protocol • Simple communication between two equivalent nodes. •
Any node can initiate communication. • Since connection is half-duplex, the two lanes of
communication are completely independent. • It is universal since its parameters (format, speed ..)
are configurable. • It is ‘asynchronous’ since it doesn’t have a clock.

Baud Rate: It is the no: of bits transmitted/received per second

Working of UART: In UART serial communication, the data is transmitted asynchronously. instead of
clock signals, UART uses some special bits called start and stop bits. These bits are added to the actual
data packet at the beginning and end respectively. These additional bits allow the receiving UART to
identify the actual data.
Connections for UART.

The speed of communication (measured in bauds) is predetermined on both ends. • A general rule of
thumb is to use 9600 bauds for wired communication. • UART implements error-detection in the form
of parity bit.

Parity bit is HIGH when number of 1’s in the Data is odd. •Respectively, it is LOW when number of 1’s
in the Data is even.

HDLC (HIGH- LEVEL Data Link Control) : The OSI’s data link protocol  A bit-oriented protocol that
supports both half –duplex and full duplex communication over point to point & multipoint link.  On
transmitting side, HDLC receives data from an application, and delivers it to the receiver on the other
side of the link  On the receiving side, HDLC accepts the data and delivers it to the higher level
application layer  There are two formats Standard HDLC and Extended HDLC for and 2 8 and 216
destination devices or systems, respectively. For any HDLC communication session one station is
designated primary and the other secondary. A session can use one of the following connection
modes: 1. Normal unbalanced: The secondary station responds only to the primary station. 2.
Asynchronous: The secondary station can initiate a message 3. Asynchronous balanced : Both stations
send and receive over its part of a duplex line. HDLC Frame Structure
 Flag bits (both opening and closing flags):8 bits( 01111110 or 7E hex)  Address bits : 8 bits in
Standard HDLC format and 16 bits in extended format  Control field: The control field distinguishes
between the three different types of frames used in HDLC, namely information, control and
unnumbered frames. The first one or two bits of the field determine the type of frame.  Information
field: The information field does not have a length specified by HDLC. In practice, it normally has a
maximum length determined by a particular implementation. Information frames (also known as I-
frames) are the only frames that carry information bits which are normally in the form of a fixed-length
block of data of several kilobytes in length  Frame check sequence: The FCS field contains error-
checking bits, normally 16 bit with a provision for increasing this to 32. If the FCS fails, the frame is
discarded.

PCI (Peripheral Component Interconnect) • The Peripheral Component Interconnect is an

interconnect bus developed by Intel in 1992 which runs at 33 MHz and supports plug-and-play • It
allows high speed connection between peripherals(video adapters, drive adapters and network
adapters to the chipset, processor and memory), and from the peripherals to the processor. • PCI
allows the transfer of data amongst peripherals ,independently • Found on many desktops, but not
limited to them, the PCI bus is a 32 bit wide bus capable of transferring at data rates up to 132 M Bytes
per second • A 66 MHz, 64-bit version is capable of transfer rates of up to 524 Mbytes/second  The
most recent motherboards usually provide 4 or 5 PCI slots.  The PCI bus can be either 32 bits or 64
bits wide.  Information is transferred across the bus at 33 MHz.

PCI-X:
 • It is an expansion slot advanced to PCI.
• PCI-X is faster version of PCI running at twice the speed of PCI.
• Standard PCI supports up to 64 bit at 66 MHz.
• Peripheral Component Interconnect .
• Designed as a replacement for the ISA standard.
3 main goals:

To get better performance when transferring data between the computer and its peripherals.

To be as platform independent as possible.

To simplify adding and removing peripherals to the system.

To get better performance . uses a higher clock rate (25 or 33 MHz) than ISA.

To be as platform independent is used extensively on IA-32, Alpha, PowerPC, SPARC64, and IA-64
systems. To simplify adding and removing peripherals. supports for auto detection of interface boards.
PCI Addressing . Each PCI peripheral is identified by a bus number(16-bits), combined by bus (8),
device(5), and function(3). Using the lspci tool, we can get the information of each PCI peripheral. 
BB:DD.F as three values (bus, device, and function) The hardware circuitry of each peripheral board
will know memory locations, I/O ports, and configuration registers. Memory locations and I/O ports
are shared by all the devices on a PCI bus. When you access a memory location, all the devices see the
bus cycle at the same time. Configuration space exploits geographical addressing.Configuration
transactions address only one slot at a time.

RS-232 SERIAL INTERFACE

RS232 was first introduced in 1962, This is the most common type of serial interface, it was the
standard communication before the PS2 and USB become popular in the computer industry, you
connect a mouse, modem, and printer to RS-232 serial interface. RS232 only allows for one transmitter
and one receiver on each line. RS232 also use a Full-Duplex transmission method. RS232 can transmit
up to 1Mbps with maximum distance up to 50 ft.

RS485 SERIAL INTERFACE

RS485 is an improved version of RS422, it expands on the capabilities, the major change is to have
multi-drop Limitation of RS422, it allows up to 32 devices to communicate through the same data line.
Any of the slave devices on an RS-485 bus can communicate with all the slave within the data line
without going through the master device.

RS-232 RS- 485

Cabling Single ended Multi-drop

No. of Devices 1 transmitter 32 transmitters

1 receiver 32 receivers

Communication Mode Full duplex Full duplex,

Half duplex

Max Distance 50 feet at 4000 feet at

19.2 kbps 100 kbps

Max Data Rate 1 mbps for 10 mbps for 50

50 feet feet

RS-422

RS-422 (EIA RS-422-A Standard) is the serial connection historically used on Apple Macintosh
computers. RS-422 uses a differential electrical signal, as opposed to unbalanced signals referenced to
ground with the RS-232. Differential transmission uses two lines each for transmit and receive signals
which results in greater noise immunity and longer distances as compared to the RS-232. These
advantages make RS-422 a better fit for industrial applications.

RS-232, RS-422, and RS-485 Comparison

RS-232 is the most common serial interface and used to ship as a standard component on most
Windows-compatible desktop computers. Now it is more common to use RS-232 over USB using a
converter. RS-232 only allows for one transmitter and one receiver on each line. RS-232 also uses a
Full-Duplex transmission method. Some RS-232 boards sold by National Instruments support baud
rates up to 1 Mbit/s, but most devices are limited to 115.2 kbits/s.
RS-422 (EIA RS-422-A Standard) is the serial connection used on legacy Apple computers. It provides
a mechanism for transmitting data up to 10 Mbits/s. RS-422 sends each signal using two wires to
increase the maximum baud rate and cable length. RS-422 is also specified for multi-drop applications
where only one transmitter is connected to, and transmits on, a bus of up to 10 receivers.
RS-485 is a superset of RS-422 and expands on the capabilities. RS-485 was made to address the multi-
drop limitation of RS-422, allowing up to 32 devices to communicate through the same data line. Any
of the slave devices on a RS-485 bus can communicate with any other 32 slave devices without going
through a master device. Since RS-422 is a subset of RS-485, all RS-422 devices may be controlled by
RS-485.
Both RS-485 and RS-422 have multi-drop capability, but RS-485 allows up to 32 devices and RS-422
has a limit of 10. For both communication protocols, you should provide your own termination. All
National Instruments RS-485 boards will work with RS-422 standards.
The following table compares mode of operation, total number of drivers and receivers, maximum cable
length, and maximum data rate.

Specifications RS-232 RS-422 RS-485

Mode of Operation Single-Ended Differential Differential

Number of Drivers / 1 Driver 1 Driver 32 Drivers*

Receivers on One Line 1 Receiver 10 Receivers 32 Receivers

Maximum Cable Length 50 ft (2500 pF) 4000 ft 4000 ft

Maximum Data Rate (at max 160 kbits/s (can be 10 Mbit/s 10 Mbit/s
cable length) up to 1Mbit/s)

Table 3: Specifications of RS-232, RS-422, and RS-485

DEVICE DRIVER

Figure : Embedded Systems Model and Device Drivers.

Device driver is a piece of software that acts as a bridge between the operating system and hardware.
In an operating system based product architecture, the user application talk to the OS kernel for all
necessary information exchange including communication with the hardware peripherals. The
architecture of the OS kernel will not allow direct device access from the user application. All the device
related access should flow through the OS kernel and the OS kernel routes it to the concerned hardware
peripherals. Os provide interfaces in the form of application programming interfaces (API) for accessing
the hardware. The device driver abstracts the hardware from the user application. Topology of user
applications and hardware interaction in an RTOS based system.
Device drivers are responsible for initiating and managing the communication with the hardware
peripheral. They are responsible for establishing the connectivity initializing the hardware and
transferring data. An embedded product may contain different types of hardware components like Wi-
Fi module, file system, storage device interfaces etc. the initialization of these devices and the protocols
required for communicating with these devices may be different. All these requirements are
implemented in drivers and a single driver will not be able to satisfy all this. Hence each hardware
requires a unique driver component.
Certain drivers come as part of the OS kernel and certain drivers need to be installed on the fly. For
example, the program storage memory for an embedded product say NAND flash memory requires a
NAND flash driver to read and write data from/to. This driver should come as part of OS kernel image.
Certainly the OS will not contain the drivers for all devices and peripherals under the sun. it contains
only the necessary drivers to communicate with the on-board devices and for certain set of devices
supporting standard protocols and device class. If an external device whose driver software is not
available with Os kernel image is connected to the embedded device, the OS prompts the user to install
its driver manually. Device drivers which are the part of the OS image are known as built-in drivers or
on-board drivers. These drivers are loaded by the OS at the time of booting the device and always kept
in the RAM. Drivers need to be installed for accessing a device are known as installable drivers. These
drivers are loaded by the OS on a need basis. Whenever the device is connected OS loads the
corresponding driver to memory. When the device is removed the driver is unloaded from memory. The
OS maintains record of the drivers corresponding to each hardware.
The implementation of driver is OS dependent. There is no Universal implementation for a driver. How
the driver communicates with the kernel is dependent on the OS structure and implementation. Different
operating systems followed different implementations.
It is very essential to know the hardware interfacing details like the memory address assigned to the
device, the interrupt used, etc . Off on -board peripherals for writing a driver for that peripheral. It varies
on the hardware design of the product. Some real -time operating systems like 'windows CE' support a
layered architecture for the driver which separates out the lower level implementations from the OS
specific interface. The lower level implementation part is generally known as platform dependent device
layer (PDD). The way specific interface part is known as Model Device Driver (MDD) or logical device
driver (LDD).4 standard driver, for a specific operating system, the MDD / LDD always remain the
same and only the period e parts need to be modified according to the target hardware for a particular
class of devices.
Most of the time, the hardware developer provides the implementation for all onboard devices for a
specific OS along with the platform. The drivers are normally shipped in the form of board support
package. What package contains low level driver implementation for the on board peripherals and OEM
adaptation layer (OAL) for accessing the various Chip Level functionalities and a bootloader for loading
the operating system. The OAL facilities communication between the operating system (OS) and the
target device and includes code to handle interrupts power management, bas abstraction, generic IO
control codes, etc. The driver files are usually in the form of an all file. Drivers can run on the user
space and kernel space. Drivers which run in user space are known as user mode drivers and the drivers
which run in kernel space are known as kernel-mode drivers. User mod drivers are safer than kernel-
mode drivers. If an error exception occurs in a user mode driver, it won't affect the services of the kernel.
On the other hand, if an exception occurs in the kernel mode driver, it may lead to the kernel crash. The
way how a device driver is written and how the interpreter handled in it what is system and target
hardware specific. However regardless of the OS types, a device driver implements the following:
1. Device driver (hardware) installation and internet configuration
2. Interrupt handling and processing
3. Client interfacing( interfacing with user applications)

The device (hardware) initialisation part deals with configuring the IO port line of the processor as input
or output line and setting its associated register for building a general purpose I/O (GPIO) driver. The
interrupt configuration part deals with configuring the interrupts that needs to be associated with the
hardware. In the case of GPIO driver, if the intention is to generate an interrupt when the input line is
asserted yeah, we need to configure the interrupt associated with the IO Port by modifying its associated
registers. The basic Internet configuration involves the following,
1. Set the interrupt type (edge triggered (rising/ falling) or level triggered (low or high)) comma enable
interrupts and set the interrupt priorities.
2. Bind the interrupt with an interrupt request (IRQ). The processor identifies an interrupt through IRQ.
These IRQs are generated by the interrupt controller. In order to identify an interrupt the interrupt needs
to be bonded to an IRQ.
3. Register an interrupt service routine (ISR) with an interrupt request (IRQ) .ISR is the handler for an
interrupt. In order to service and interrupt, an ISR should be associated with an IRQ. Registering an
ISR with an IRQ take care of it.
With this internet configuration is complete. If an interrupt occurs, depending on its priority, it is
serviced and the corresponding ISR is invoked. The processing part of an interrupt is handled in an ISR.
The whole interrupt processing can be done by the ISR itself or by invoking an interrupt service thread
(IST). The IST performs interrupt processing on behalf of the ISR. To make the ISR compact and short,
it is always advice to use an IST for interrupt processing. The intention of an interrupt is to send or
receive command or data to and from the hardware device and make the received data available to user
programs for application specific processing. Since interrupt processing happens at kernel level,
applications may not have Direct Access to the drivers to pass and receive data. Hence it is the
responsibility of the interrupt processing routine or thread to inform the user applications that can
interrupt is occurred and data is available for further processing. The client interfacing part of the device
driver takes care of this. The client interfacing implementation makes use of the inter process
communication mechanism supported by the embedded OS for communicating and synchronising with
user applications and drivers. For example, to inform a user application that and interoffice occurred
and the data received from the device is placed in a shared buffer the client interfacing code can signal
(or set) an event. The user applications creates the event, register it and wait for the driver to signal it .
The driver can share the receive data through shared memory techniques. IOCTLs, shared buffers, etc.
can be used for data sharing. The story line is incomplete without performing an interrupt done (interrupt
processing completed) functionality in the driver. Whenever an interrupt is asserted, vectoring to its
corresponding ISR, equal and low priorities are disabled. They are re- enable only on executing the
interrupt done function by the driver. The interrupt done function can be invoked at the end of
corresponding ISR or IST.