S3CES02 Analog Electronic Circuits (Unit-3) III Semester

Unit – 3 MOS Differential Amplifier and Power Amplifier

Differential amplifier is the most important building block of analog integrated

circuit. The input stage of operation amplifier (OP-Amp) is a differential amplifier. The
differential amplifier shown in Fig. 3.1 is one which amplifies the difference of input signals.

𝑉1
Amplifier (A) 𝑉𝑂 = 𝐴(𝑉1 ~𝑉2 )
𝑉2

Fig. 3.1 Block diagram of differential amplifier

3.1 The MOS differential pair

Fig. 3.2 shows the basic MOS differential pair configuration. It consists of two
matched transistors Q1 and Q2, whose sources are connected together and biased by a constant
current source I. The drain of each MOSFET is connected to supply VDD through resistance
RD.
𝑉𝐷𝐷 𝑉𝐷𝐷
𝑖𝐷1 𝑖𝐷2

𝑅𝐷 𝑅𝐷
𝑣𝐷1 𝑉𝑂 𝑣𝐷2
𝑄1 𝑄2

𝑣𝐺1 𝑣𝐺2

−𝑉𝑆𝑆

Fig. 3.2 Basic MOS differential pair configuration

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 1

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

3.1.1 Operation with a common mode input voltage

Consider the MOS differential pair shown in Fig. 3.3 with the inputs shorted and a
common mode input VCM is applied that is VG1 = VG2 = VCM. Since Q1 and Q2 are identical it
follows from symmetry that the current I will divide equally between the two transistors.

𝑉𝐷𝐷 𝑉𝐷𝐷
𝐼 𝐼
2 2
𝑅𝐷 𝑅𝐷
𝐼 𝐼
𝑣𝐷1 = 𝑉𝐷𝐷 − 2 𝑅𝐷 𝑣𝐷2 = 𝑉𝐷𝐷 − 2 𝑅𝐷
𝑄1 𝑄2
+ +
𝑣𝐶𝑀 𝑉𝐺𝑆 𝑉𝐺𝑆
− −

−𝑉𝑆𝑆

Fig. 3.3 MOS differential pair with common mode input voltage VCM

𝑆𝑖𝑛𝑐𝑒 𝑄1 𝑎𝑛𝑑 𝑄2 𝑎𝑟𝑒 𝑚𝑎𝑡𝑐𝑕𝑒𝑑 𝑖𝐷1 = 𝑖𝐷2 = 𝐼 2

𝑡𝑕𝑒 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑎𝑡 𝑡𝑕𝑒 𝑠𝑜𝑢𝑟𝑐𝑒𝑠, 𝑣𝑆 = 𝑣𝐶𝑀 − 𝑉𝐺𝑆
𝐼 1 ′𝑊 2
𝑁𝑒𝑔𝑙𝑒𝑐𝑡𝑖𝑛𝑔 𝑐𝑕𝑎𝑛𝑛𝑒𝑙 𝑙𝑒𝑛𝑔𝑡𝑕 𝑚𝑜𝑑𝑢𝑙𝑎𝑡𝑖𝑜𝑛, = 𝐾 𝑉 − 𝑉𝑡
2 2 𝑛 𝐿 𝐺𝑆
𝑆𝑖𝑛𝑐𝑒 𝑉𝐺𝑆 − 𝑉𝑡 = 𝑉𝑂𝑉
𝐼 1 ′𝑊 2
= 𝐾 𝑉
2 2 𝑛 𝐿 𝑂𝑉
𝐼
𝑉𝑂𝑉 = 𝑊
𝐾𝑛 ′ 𝐿

𝐼
𝑡𝑕𝑒 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑎𝑡 𝑒𝑎𝑐𝑕 𝑑𝑟𝑎𝑖𝑛, 𝑣𝐷1 = 𝑣𝐷2 = 𝑉𝐷𝐷 − 𝑅𝐷
2
𝑇𝑕𝑢𝑠 𝑡𝑕𝑒 𝑜𝑢𝑡𝑝𝑢𝑡 𝑣𝑜𝑙𝑡𝑎𝑔𝑒, 𝑉𝑂 = 𝑉𝐷1 − 𝑉𝐷2 = 0
Now if the common mode voltage VCM is varied, the current I will divide equally
between Q1 and Q2 as long as the transistors remain in saturation region, hence the output
voltage will be zero. Thus the differential pair rejects the common mode input signal V CM.

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 2

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

Input common mode range

Input common mode range is the range of VCM over which the differential pair
operates properly.
The highest value of VCM is limited by the requirement that Q1 and Q2 remain in
saturation then
𝐼
𝑣𝐶𝑀 𝑚𝑎𝑥 = 𝑉𝑡 + 𝑉𝐷𝐷 − 𝑅𝐷
2
The lowest value of VCM is determined by the need to allow for a sufficient voltage
across current source I for it to operate properly. If a voltage VCS is needed across the current
source then
𝑣𝐶𝑀 𝑚𝑖𝑛 = −𝑉𝑆𝑆 + 𝑉𝐶𝑆 + 𝑉𝑡 + 𝑉𝑂𝑉

3.1.2 Operation with a differential input voltage

Consider the MOS differential pair shown in Fig. 3.4 with a differential input voltage
by grounding the gate of Q2 (VGS2 = 0) and applying a signal Vid to the gate of Q1

𝑉𝐷𝐷 𝑉𝐷𝐷
𝑖𝐷1 𝑖𝐷2
𝑅𝐷 𝑅𝐷
𝑣𝐷1 𝑣𝐷2
𝑄1 𝑄2
+ +

𝑣𝑖𝑑 𝑣𝐺𝑆1 𝑣𝐺𝑆2

− −

−𝑉𝑆𝑆

Fig. 3.4 MOS differential pair with differential input voltage V id

𝐹𝑟𝑜𝑚 𝑡𝑕𝑒 𝑐𝑖𝑟𝑐𝑢𝑖𝑡 𝑤𝑒 𝑐𝑎𝑛 𝑤𝑟𝑖𝑡𝑒, 𝑣𝐺𝑆1 = 𝑣𝑖𝑑 𝑎𝑛𝑑 𝑣𝐺𝑆2 = 0

𝑇𝑕𝑒 𝑑𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑡𝑖𝑎𝑙 𝑖𝑛𝑝𝑢𝑡, 𝑣𝑖𝑑 = 𝑣𝐺𝑆1 − 𝑣𝐺𝑆2
𝐼𝑓 𝑣𝑖𝑑 𝑖𝑠 𝑝𝑜𝑠𝑖𝑡𝑖𝑣𝑒, 𝑣𝐺𝑆1 > 𝑣𝐺𝑆2 𝑡𝑕𝑒𝑛 𝑖𝐷1 > 𝑖𝐷2
𝑉𝑂 = 𝑣𝐷2 − 𝑣𝐷1 𝑤𝑖𝑙𝑙 𝑏𝑒 𝑝𝑜𝑠𝑖𝑡𝑖𝑣𝑒

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 3

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

𝐼𝑓 𝑣𝑖𝑑 𝑖𝑠 𝑛𝑒𝑔𝑎𝑡𝑖𝑣𝑒, 𝑣𝐺𝑆2 > 𝑣𝐺𝑆1 𝑡𝑕𝑒𝑛 𝑖𝐷2 > 𝑖𝐷1

𝑉𝑂 = 𝑣𝐷2 − 𝑣𝐷1 𝑤𝑖𝑙𝑙 𝑏𝑒 𝑛𝑒𝑔𝑎𝑡𝑖𝑣𝑒
Assume that vGS1 is fixed such that the entire current I flows through Q1 and vGS2 = Vt then
1 ′𝑊 2
𝐼= 𝐾 𝑣 − 𝑉𝑡
2 𝑛 𝐿 𝐺𝑆1
2𝐼
𝑣𝐺𝑆1 − 𝑉𝑡 2 = ′ 𝑊
𝐾𝑛 𝐿

2𝐼
𝑣𝐺𝑆1 − 𝑉𝑡 = 𝑊
𝐾𝑛 ′ 𝐿

2𝐼
𝑣𝐺𝑆1 = 𝑉𝑡 + 𝑊
𝐾𝑛 ′ 𝐿

𝑣𝐺𝑆1 = 𝑉𝑡 + 2 𝑉𝑂𝑉 𝑉𝑂𝑉 → 𝑂𝑣𝑒𝑟𝑑𝑟𝑖𝑣𝑒 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑐𝑢𝑟𝑟𝑒𝑠𝑝𝑜𝑛𝑑𝑖𝑛𝑔 𝑡𝑜 𝐼 2

𝐴𝑝𝑝𝑙𝑦𝑖𝑛𝑔 𝐾𝑉𝐿 𝑡𝑜 𝑔𝑎𝑡𝑒 𝑙𝑜𝑜𝑝
𝑣𝑖𝑑 − 𝑣𝐺𝑆1 + 𝑣𝐺𝑆2 = 0
𝑣𝑖𝑑 = 𝑣𝐺𝑆1 − 𝑣𝐺𝑆2
𝑣𝑖𝑑 𝑚𝑎𝑥 = 𝑉𝑡 + 2 𝑉𝑂𝑉 − 𝑉𝑡 = 2 𝑉𝑂𝑉
𝑆𝑖𝑚𝑖𝑙𝑎𝑟𝑙𝑦, 𝑣𝑖𝑑 𝑚𝑖𝑛 = − 2 𝑉𝑂𝑉
Thus the current I can be steered from one transistor to other by varying V id in the
range
− 2 𝑉𝑂𝑉 ≤ 𝑣𝑖𝑑 ≤ 2 𝑉𝑂𝑉

Problems :
P1. In a MOS differential amplifier with a common mode voltage, V CM applied. Let VDD
𝑊
= VSS = 1.5 V, 𝐾𝑛 ′ = 4𝑚𝐴/𝑉 2 , Vt = 0.5V, I = 0.4mA, RD = 2.5 K,  = 0. Find
𝐿

(i) VOV and VGS

(ii) If vCM = 0, Find VS, iD1, iD2, vD1 and vD2
(iii) If vCM = +1V, repeat (ii)
(iv) If vCM = -0.2V, repeat (ii)
(v) vCM max
(vi) If VCS = 0.4V, VCM min, VS

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 4

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

Solution :

𝑉𝐷𝐷 𝑉𝐷𝐷
𝐼 𝐼
2 2
𝑅𝐷 𝑅𝐷
𝐼 𝐼
𝑣𝐷1 = 𝑉𝐷𝐷 − 2 𝑅𝐷 𝑣𝐷2 = 𝑉𝐷𝐷 − 2 𝑅𝐷
𝑄1 𝑄2
+ +
𝑣𝐶𝑀 𝑉𝐺𝑆 𝑉𝐺𝑆
− −

−𝑉𝑆𝑆
𝐼 0.4 𝑚
(i) 𝑉𝑂𝑉 = 𝑊 = = 0.316 𝑉
𝐾𝑛 ′ 4𝑚
𝐿

𝑉𝐺𝑆 = 𝑉𝑂𝑉 + 𝑉𝑡 = 0.316 + 0.5 = 0.816

(ii) 𝑣𝑆 = 𝑣𝐶𝑀 − 𝑉𝐺𝑆 = 0 − 0.816 = −0.816𝑉
0.4 𝑚
𝑖𝐷1 = 𝑖𝐷2 = 𝐼 2 = = 0.2 𝑚𝐴
2
𝐼
𝑣𝐷1 = 𝑣𝐷2 = 𝑉𝐷𝐷 − 𝑅𝐷 = 1.5 − 0.2𝑚 × 2.5𝐾 = 1𝑉
2
(iii) 𝑣𝑆 = 𝑣𝐶𝑀 − 𝑉𝐺𝑆 = 1 − 0.816 = 0.184 𝑉
0.4 𝑚
𝑖𝐷1 = 𝑖𝐷2 = 𝐼 2 = = 0.2 𝑚𝐴
2
𝐼
𝑣𝐷1 = 𝑣𝐷2 = 𝑉𝐷𝐷 − 𝑅𝐷 = 1.5 − 0.2𝑚 × 2.5𝐾 = 1𝑉
2
(iv) 𝑣𝑆 = 𝑣𝐶𝑀 − 𝑉𝐺𝑆 = −0.2 − 0.816 = −1.016 𝑉
0.4 𝑚
𝑖𝐷1 = 𝑖𝐷2 = 𝐼 2 = = 0.2 𝑚𝐴
2
𝐼
𝑣𝐷1 = 𝑣𝐷2 = 𝑉𝐷𝐷 − 𝑅𝐷 = 1.5 − 0.2𝑚 × 2.5𝐾 = 1𝑉
2
𝐼
(v) 𝑣𝐶𝑀 𝑚𝑎𝑥 = 𝑉𝑡 + 𝑉𝐷𝐷 − 2 𝑅𝐷 = 0.5 + 1.5 − 0.2𝑚 × 2.5𝐾 = 1.5𝑉

(vi) 𝑣𝐶𝑀 𝑚𝑖𝑛 = −𝑉𝑆𝑆 + 𝑉𝐶𝑆 + 𝑉𝑡 + 𝑉𝑂𝑉 = −1.5 + 0.4 + 0.5 + 0.316 = −0.284𝑉
𝑣𝑆 = 𝑣𝐶𝑀 − 𝑉𝐺𝑆 = −0.284 − 0.816 = −1.1𝑉

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 5

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

𝑊
P2. In a MOS differential amplifier if VDD = VSS = 1.5 V, 𝐾𝑛 ′ = 4𝑚𝐴/𝑉 2 , Vt = 0.5V, I
𝐿

= 0.4mA, RD = 2.5 K,  = 0. Find

(i) vid that cause Q1 to conduct I, vD1 and vD2
(ii) vid that cause Q2 to conduct I, vD1 and vD2
(iii) Range of the differential output voltage (vD2 – vD1)
Solution : 𝑉𝐷𝐷
𝑉𝐷𝐷

𝑖𝐷1 𝑖𝐷2
𝑅𝐷 𝑅𝐷
𝑣𝐷1 𝑣𝐷2
𝑄1 𝑄2
+ +

𝑣𝑖𝑑 𝑣𝐺𝑆1 𝑣𝐺𝑆2

− −

−𝑉𝑆𝑆

2𝐼 2×0.4𝑚
(i) 𝑣𝐺𝑆1 = 𝑉𝑡 + 𝑊 = = 0.447𝑉
𝐾𝑛 ′ 4𝑚
𝐿

𝑣𝐷1 = 𝑉𝐷𝐷 − 𝑖𝐷1 𝑅𝐷 = 1.5 − 0.4𝑚 × 2.5𝐾 = 0.5𝑉 𝑆𝑖𝑛𝑐𝑒 𝑖𝐷1 = 𝐼 𝑎𝑛𝑑 𝑖𝐷2 = 0
𝑣𝐷2 = 𝑉𝐷𝐷 − 𝑖𝐷2 𝑅𝐷 = 1.5 − 0 × 2.5𝐾 = 1.5𝑉 𝑆𝑖𝑛𝑐𝑒 𝑖𝐷1 = 𝐼 𝑎𝑛𝑑 𝑖𝐷2 = 0
(ii) 𝑣𝐺𝑆2 = −𝑣𝐺𝑆1 = −0.447𝑉
𝑣𝐷1 = 𝑉𝐷𝐷 − 𝑖𝐷1 𝑅𝐷 = 1.5 − 0 × 2.5𝐾 = 1.5𝑉 𝑆𝑖𝑛𝑐𝑒 𝑖𝐷1 = 0 𝑎𝑛𝑑 𝑖𝐷2 = 𝐼
𝑣𝐷2 = 𝑉𝐷𝐷 − 𝑖𝐷2 𝑅𝐷 = 1.5 − 0.4𝑚 × 2.5𝐾 = 0.5𝑉 𝑆𝑖𝑛𝑐𝑒 𝑖𝐷1 = 0 𝑎𝑛𝑑 𝑖𝐷2 = 𝐼
(iii) 𝑅𝑎𝑛𝑔𝑒 𝑜𝑓 𝑣𝐷2 − 𝑣𝐷1 = 1.5 − 0.5 𝑎𝑛𝑑 0.5 − 1.5 = 1.0𝑉 𝑡𝑜 − 1.0𝑉

3.2 Small signal operation of the MOS differential pair

In this section we will discuss the MOS differential pair as amplifier.

3.2.1 Differential gain

The MOS differential amplifier with a common mode voltage applied to set the DC
bias voltage at the gates and with vid applied in a complementary manner is shown in Fig. 3.5

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 6

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

𝑉𝐷𝐷 𝑉𝐷𝐷

𝑅𝐷 𝑅𝐷

𝑣𝑂1 𝑣𝑂2
𝐺1 𝐺2
𝑣𝑖𝑑 𝑣𝑖𝑑
𝑣𝐺1 = 𝑉𝐶𝑀 + 𝑣𝐺2 = 𝑉𝐶𝑀 − 2
2

Fig. 3.5 MOS differential amplifier with a common mode voltage applied to set the DC bias
voltage at the gates and with vid applied in a complementary manner

𝑉𝑖𝑑 𝑉𝑖𝑑
𝑉𝐺1 = 𝑉𝐶𝑀 + 2 and 𝑉𝐺2 = 𝑉𝐶𝑀 − 2

VCM denotes a common mode DC voltage within the input common mode range of
the differential amplifier. Typically VCM is at the middle value of power supplies, when two
complementary supplies are utilised VCM = 0.
Equivalent circuit for small signal analysis is shown in Fig. 3.6.

𝐼
𝑅𝐷 𝑅𝐷 𝐵𝑖𝑎𝑠𝑒𝑑 𝑎𝑡
2
𝑣𝑂1 𝑖𝐷1 𝑖𝐷2 𝑉𝑂2

𝑣𝑖𝑑 𝑣𝑖𝑑
𝑄1 𝑄2 −
2 2
𝑣𝑖𝑑 𝑣𝑖𝑑
𝑣𝑔𝑠1 = 𝑣𝑔𝑠2 = −
2 2
0𝑉

Fig. 3.6 Equivalent circuit for small signal analysis

𝑣𝑖𝑑 𝑣𝑖𝑑
𝑖𝑑1 = 𝑔𝑚 𝑎𝑛𝑑 𝑖𝑑2 = 𝑔𝑚
2 2
𝑣𝑖𝑑 𝑣𝑖𝑑
𝑣𝑂1 = −𝑖𝑑1 𝑅𝐷 = −𝑔𝑚 𝑅𝐷 𝑎𝑛𝑑 𝑣𝑂2 = 𝑖𝑑2 𝑅𝐷 = 𝑔𝑚 𝑅𝐷
2 2

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 7

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

𝑣𝑖𝑑
𝐴𝑠𝑠𝑢𝑚𝑖𝑛𝑔 ≪ 𝑉𝑂𝑉 𝑠𝑚𝑎𝑙𝑙 𝑠𝑖𝑔𝑛𝑎𝑙 𝑎𝑛𝑙𝑦𝑠𝑖𝑠
2
𝐼
2𝐼𝐷 2 𝐼
𝑔𝑚 = = 2=
𝑉𝑂𝑉 𝑉𝑂𝑉 𝑉𝑂𝑉
𝑣𝑂1 1 𝑣𝑂1 1
= − 𝑔𝑚 𝑅𝐷 𝑎𝑛𝑑 = 𝑔𝑚 𝑅𝐷
𝑣𝑖𝑑 2 𝑣𝑖𝑑 2
𝑣𝑂2 − 𝑣𝑂1
𝐴𝑑 = = 𝑔𝑚 𝑅𝐷
𝑣𝑖𝑑

Effect of the MOSFET's ro

The MOS differential amplifier with r O and RSS and the equivalent circuit is shown in
Fig. 3.7
𝐼
𝐵𝑖𝑎𝑠𝑒𝑑 𝑎𝑡 2

𝑅𝐷 𝑅𝐷 𝑅𝐷 𝑅𝐷
𝑣𝑂
𝑣𝑂1 𝑣𝑂 𝑣𝑂2
𝑟𝑂 𝑟𝑂
𝑣𝑖𝑑 𝑣𝑖𝑑
− 𝑟𝑂 𝑟𝑂
2 2 𝑣𝑖𝑑 𝑣𝑖𝑑
0𝑉 −
2 2
𝑅𝑆𝑆
𝑅𝑆𝑆 → 𝐹𝑖𝑛𝑖𝑡𝑒 𝑜𝑢𝑡𝑝𝑢𝑡 𝑟𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 𝑜𝑓 𝑐𝑢𝑟𝑟𝑟𝑒𝑛𝑡 𝑠𝑜𝑢𝑟𝑐𝑒

Fig. 3.7 MOS differential amplifier with rO and RSS and equivalent circuit

𝑣𝑖𝑑
𝑣𝑂1 = −𝑔𝑚 (𝑅𝐷 𝑟𝑂 ) 2
𝑣𝑖𝑑
𝑣𝑂2 = 𝑔𝑚 (𝑅𝐷 𝑟𝑂 ) 2
𝑣𝑖𝑑 𝑣𝑖𝑑
𝑣𝑂 = 𝑣𝑂2 − 𝑣𝑂1 = 𝑣𝑂1 = −𝑔𝑚 (𝑅𝐷 𝑟𝑂 ) — 𝑔𝑚 (𝑅𝐷 𝑟𝑂 )
2 2

𝑣𝑂 = 𝑔𝑚 (𝑅𝐷 𝑟𝑂 )𝑣𝑖𝑑
𝑣𝑂
𝐴𝑑 = = 𝑔𝑚 (𝑅𝐷 𝑟𝑂 )
𝑣𝑖𝑑

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 8

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

3.2.2 Common mode gain and common mode rejection ratio (CMRR)
The common mode
The MOS differential amplifier with common mode signal vicm applied and equivalent
circuit is shown in Fig. 3.8.
𝐼
𝐵𝑖𝑎𝑠𝑒𝑑 𝑎𝑡 2
𝑉𝐷𝐷 𝑉𝐷𝐷
𝑅𝐷 𝑅𝐷
𝑅𝐷 𝑅𝐷 𝑣𝑂1 𝑣𝑂 𝑣𝑂2
𝑣𝑂1 𝑣𝑂 𝑣𝑂2
𝑄1 𝑄2
𝑣𝑖𝑐𝑚 𝑣𝑖𝑐𝑚
𝑣𝑖𝑐𝑚 𝑄1 𝑄2 𝑣𝑖𝑐𝑚
2𝑅𝑆𝑆 2𝑅𝑆𝑆

𝑅𝑆𝑆 𝐼
2𝑅𝑆𝑆 → 𝑆𝑜𝑢𝑟𝑐𝑒 𝑑𝑒𝑔𝑒𝑛𝑒𝑟𝑎𝑡𝑖𝑜𝑛 𝑟𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒
−𝑉𝑆𝑆

Fig. 3.8 MOS differential amplifier with common mode signal vicm applied and equivalent
circuit

The symmetry of the circuit enables us to break it into two identical halves known as
CM half circuit.
Neglecting the effect of rO we can write the expression for gain as
𝑣𝑂1 𝑣𝑂2 𝑅𝐷 Common Source amplifier with RS,
𝐴𝑐𝑚 = = =− 1
𝑣𝑖𝑐𝑚 𝑣𝑖𝑐𝑚 + 2𝑅𝑆𝑆
𝑔𝑚 discussed in unit - I
1
𝑆𝑖𝑛𝑐𝑒 𝑅𝑆𝑆 ≫ 𝑔
𝑚

𝑣𝑂1 𝑣𝑂2 𝑅𝐷
= =−
𝑣𝑖𝑐𝑚 𝑣𝑖𝑐𝑚 2𝑅𝑆𝑆

i) When the output of the differential pair is taken single endedly

𝑅𝐷
𝐴𝑐𝑚 =
2𝑅𝑆𝑆
1
𝐴𝑑 = 𝑔𝑚 𝑅𝐷
2
𝑅𝐷
𝐴𝑑 2𝑅
𝐶𝑜𝑚𝑚𝑜𝑛 𝑚𝑜𝑑𝑒 𝑟𝑒𝑗𝑒𝑐𝑡𝑖𝑜𝑛 𝑟𝑎𝑡𝑖𝑜𝑛, 𝐶𝑀𝑅𝑅 = = 1 𝑆𝑆 = 𝑔𝑚 𝑅𝑆𝑆
𝐴𝑐𝑚 𝑔 𝑅
2 𝑚 𝐷

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 9

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

ii) When output is taken differentially

𝑣𝑂2 − 𝑣𝑂1
𝐴𝑐𝑚 = =0
𝑣𝑖𝑐𝑚
𝑣𝑂2 − 𝑣𝑂1
𝐴𝑑 = = 𝑔𝑚 𝑅𝐷
𝑣𝑖𝑑
𝐴𝑑 𝑔𝑚 𝑅𝐷
𝐶𝑜𝑚𝑚𝑜𝑛 𝑚𝑜𝑑𝑒 𝑟𝑒𝑗𝑒𝑐𝑡𝑖𝑜𝑛 𝑟𝑎𝑡𝑖𝑜𝑛, 𝐶𝑀𝑅𝑅 = = =∞
𝐴𝑐𝑚 0

Effect of RD mismatch on CMRR

Assume the two drain resistances exhibit a mismatch of RD, and then the common
mode rejection ratio will be finite even if the output is taken differentially. Let us assume the
drain resistance connected to transistor Q1 is RD and that of Q2 is RD + RD.
𝑅𝐷
𝑣𝑂1 = − 𝑣
2𝑅𝑆𝑆 𝑖𝑐𝑚
𝑅𝐷 + 𝑅𝐷
𝑣𝑂2 = − 𝑣𝑖𝑐𝑚
2𝑅𝑆𝑆
𝑅𝐷 + 𝑅𝐷 𝑅𝐷 𝑅𝐷
𝑣𝑂2 − 𝑣𝑂1 = − 𝑣𝑖𝑐𝑚 − − 𝑣𝑖𝑐𝑚 = − 𝑣
2𝑅𝑆𝑆 2𝑅𝑆𝑆 2𝑅𝑆𝑆 𝑖𝑐𝑚
𝑣𝑂2 − 𝑣𝑂1 𝑅𝐷
𝐴𝑐𝑚 = =−
𝑣𝑖𝑐𝑚 2𝑅𝑆𝑆
𝑅𝐷 𝑅𝐷
𝑂𝑟 𝐴𝑐𝑚 = −
2𝑅𝑆𝑆 𝑅𝐷
𝑆𝑖𝑛𝑐𝑒 𝑡𝑕𝑒 𝑚𝑖𝑠𝑚𝑎𝑡𝑐𝑕 𝑖𝑛 𝑅𝐷 𝑤𝑖𝑙𝑙 𝑕𝑎𝑣𝑒 𝑛𝑒𝑔𝑙𝑖𝑔𝑖𝑏𝑙𝑒 𝑒𝑓𝑓𝑒𝑐𝑡 𝑜𝑛 𝑑𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑡𝑖𝑎𝑙 𝑔𝑎𝑖𝑛
𝐴𝑑 = −𝑔𝑚 𝑅𝐷
𝐴𝑑 𝑔𝑚 𝑅𝐷 2𝑔𝑚 𝑅𝑆𝑆
𝐶𝑜𝑚𝑚𝑜𝑛 𝑚𝑜𝑑𝑒 𝑟𝑒𝑗𝑒𝑐𝑡𝑖𝑜𝑛 𝑟𝑎𝑡𝑖𝑜𝑛, 𝐶𝑀𝑅𝑅 = = 𝑅𝐷 =
𝐴𝑐𝑚 ∆𝑅𝐷
2𝑅𝑆𝑆 𝑅𝐷

Effect of gm mismatch on CMRR

𝐿𝑒𝑡 𝑖𝑑1 = 𝑔𝑚1 𝑣𝑔𝑠1 𝑎𝑛𝑑 𝑖𝑑2 = 𝑔𝑚2 𝑣𝑔𝑠2
𝑖𝑑1 𝑔𝑚1 𝑣𝑔𝑠1 𝑔𝑚1
= = 𝑆𝑖𝑛𝑐𝑒 𝑣𝑔𝑠1 = 𝑣𝑔𝑠2
𝑖𝑑2 𝑔𝑚2 𝑣𝑔𝑠2 𝑔𝑚2
𝑔𝑚2 𝑖𝑑1
𝑖𝑑2 =
𝑔𝑚1
𝑇𝑤𝑜 𝑑𝑟𝑎𝑖𝑛 𝑐𝑢𝑟𝑟𝑒𝑛𝑡𝑠 𝑠𝑢𝑚 𝑡𝑜𝑔𝑒𝑡𝑕𝑒𝑟 𝑖𝑛 𝑅𝑆𝑆
𝑣𝑆 = (𝑖𝑑1 + 𝑖𝑑2 )𝑅𝑆𝑆

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 10

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

𝑣𝑆
𝑖𝑑1 + 𝑖𝑑2 =
𝑅𝑆𝑆
1
𝑆𝑛𝑐𝑒 𝑄1 𝑎𝑛𝑑 𝑄2 𝑎𝑟𝑒 𝑜𝑝𝑒𝑟𝑎𝑡𝑖𝑛𝑔 𝑎𝑠 𝑠𝑜𝑢𝑟𝑐𝑒 𝑓𝑜𝑙𝑙𝑜𝑤𝑒𝑟 𝑎𝑛𝑑 𝑅𝑆𝑆 ≫ 𝑔
𝑚

𝑣𝑆 ≈ 𝑣𝑖𝑐𝑚
𝑣𝑖𝑐𝑚
𝑖𝑑1 + 𝑖𝑑2 =
𝑅𝑆𝑆
𝑔𝑚2 𝑖𝑑1 𝑣𝑖𝑐𝑚
𝑖𝑑1 + = 𝑆𝑢𝑏𝑠𝑡𝑖𝑡𝑢𝑡𝑖𝑛𝑔 𝑓𝑜𝑟 𝑖𝑑2
𝑔𝑚1 𝑅𝑆𝑆
𝑔𝑚2 𝑣𝑖𝑐𝑚
𝑖𝑑1 1+ =
𝑔𝑚1 𝑅𝑆𝑆
𝑣𝑖𝑐𝑚
𝑅𝑆𝑆
𝑖𝑑1 = 𝑔𝑚 2
1+𝑔
𝑚1

𝑣𝑖𝑐𝑚 𝑔𝑚1 𝑔𝑚1 𝑣𝑖𝑐𝑚

𝑖𝑑1 = × =
𝑅𝑆𝑆 𝑔𝑚1 + 𝑔𝑚2 𝑔𝑚1 + 𝑔𝑚2 𝑅𝑆𝑆
𝑆𝑖𝑛𝑐𝑒 ∆𝑔𝑚 𝑖𝑠 𝑣𝑒𝑟𝑦 𝑠𝑚𝑎𝑙𝑙, 𝑔𝑚1 + 𝑔𝑚2 = 2𝑔𝑚
𝑔𝑚1 𝑣𝑖𝑐𝑚 𝑔𝑚2 𝑣𝑖𝑐𝑚
𝑖𝑑1 = 𝑎𝑛𝑑 𝑖𝑑2 =
2𝑔𝑚 𝑅𝑆𝑆 2𝑔𝑚 𝑅𝑆𝑆
𝑣𝑂2 − 𝑣𝑂1 = −𝑖𝑑2 𝑅𝐷 + 𝑖𝑑1 𝑅𝐷 = 𝑅𝐷 (𝑖𝑑1 − 𝑖𝑑2 )
𝑔𝑚1 𝑣𝑖𝑐𝑚 𝑔𝑚2 𝑣𝑖𝑐𝑚
𝑣𝑂2 − 𝑣𝑂1 = 𝑅𝐷 −
2𝑔𝑚 𝑅𝑆𝑆 2𝑔𝑚 𝑅𝑆𝑆
∆𝑔𝑚 𝑅𝐷
𝑣𝑂2 − 𝑣𝑂1 = 𝑣 𝑊𝑕𝑒𝑟𝑒 ∆𝑔𝑚 = 𝑔𝑚1 − 𝑔𝑚2
2𝑔𝑚 𝑅𝑆𝑆 𝑖𝑐𝑚
𝑅𝐷 ∆𝑔𝑚
𝑇𝑕𝑒𝑟𝑒𝑓𝑜𝑟𝑒, 𝐴𝑐𝑚 =
2𝑅𝑆𝑆 𝑔𝑚
𝑆𝑖𝑛𝑐𝑒 𝑔𝑚 𝑚𝑖𝑠𝑚𝑎𝑡𝑐𝑕 𝑤𝑖𝑙𝑙 𝑕𝑎𝑣𝑒 𝑛𝑒𝑔𝑙𝑖𝑔𝑖𝑏𝑙𝑒 𝑒𝑓𝑓𝑒𝑐𝑡 𝑜𝑛 𝐴𝑑
𝐴𝑑 = −𝑔𝑚 𝑅𝐷
𝐴𝑑 𝑔𝑚 𝑅𝐷 2𝑔𝑚 𝑅𝑆𝑆
𝐶𝑜𝑚𝑚𝑜𝑛 𝑚𝑜𝑑𝑒 𝑟𝑒𝑗𝑒𝑐𝑡𝑖𝑜𝑛 𝑟𝑎𝑡𝑖𝑜𝑛, 𝐶𝑀𝑅𝑅 = = 𝑅𝐷 ∆𝑔𝑚 =
𝐴𝑐𝑚 ∆𝑔𝑚
2𝑅𝑆𝑆 𝑔𝑚 𝑔𝑚

Problems :
P1. A MOS differential pair is operated at a total bias current of 0.8mA, using transistors
𝑊
with a ratio of 100, 𝑛 𝐶𝑜𝑥 = 0.2 𝑚𝐴/𝑉 2 , VA = 20V and RD = 5K. Find VOV, gm,
𝐿

rO and Ad.
Solution :
𝐼 1 𝑊
= 2 𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑡 2
2 𝐿

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 11

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

1
0.4𝑚 = × 0.2𝑚 × 100 𝑉𝑂𝑉 2
2
2
0.4𝑚 × 2
𝑉𝑂𝑉 = = 0.04
0.2𝑚 × 100
𝑉𝑂𝑉 = 0.2
𝐼 0.8𝑚
𝑔𝑚 = = = 4𝑚𝐴/𝑉
𝑉𝑂𝑉 0.2
𝑉𝐴 𝑉𝐴 20
𝑟𝑂 = = 𝐼 = = 50𝐾
𝐼𝐷 0.4𝑚
2

𝐴𝑑 = 𝑔𝑚 (𝑅𝐷 𝑟𝑂 ) = 4𝑚 (50𝐾 5𝐾) = 18.18

P2. A MOS differential pair operated at a bias current of 0.8mA employs transistor with a
𝑊
= 100 and 𝑛 𝐶𝑜𝑥 = 0.2 𝑚𝐴/𝑉 2 , using RD = 5K and RSS = 25K.
𝐿

i) Find the differential gain, common mode gain and CMRR (in dB) if the output
is taken single endedly and the circuit is perfectly matched.
ii) Repeat (i) when the output is taken differentially
iii) Repeat (i) when the output is taken differentially when drain resistance have
1% mismatch
iv) Repeat (i) when the output is taken differentially when gm have 2% mismatch
Solution :
𝐼 1 𝑊
= 2 𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑡 2
2 𝐿
1
0.4𝑚 = × 0.2𝑚 × 100 𝑉𝑂𝑉 2
2
2
0.4𝑚 × 2
𝑉𝑂𝑉 = = 0.04
0.2𝑚 × 100
𝑉𝑂𝑉 = 0.2
𝐼 0.8𝑚
𝑔𝑚 = = = 4𝑚𝐴/𝑉
𝑉𝑂𝑉 0.2
𝑅 5𝐾
i) 𝐴𝑐𝑚 = 2𝑅𝐷 = 2×25𝐾 = 0.1
𝑆𝑆

1 1
𝐴𝑑 = 𝑔𝑚 𝑅𝐷 = × 4𝑚 × 5𝐾 = 10
2 2
𝐶𝑀𝑅𝑅 𝑖𝑛 𝑑𝐵 = 20𝐿𝑜𝑔 𝑔𝑚 𝑅𝑆𝑆 = 20𝐿𝑜𝑔 4𝑚 25𝐾 = 40𝑑𝐵
ii) 𝐴𝑐𝑚 = 0 𝑆𝑖𝑛𝑐𝑒 𝑐𝑖𝑟𝑐𝑢𝑖𝑡 𝑖𝑠 𝑝𝑒𝑟𝑓𝑒𝑐𝑡𝑙𝑦 𝑚𝑎𝑡𝑐𝑕𝑒𝑑
𝐴𝑑 = 𝑔𝑚 𝑅𝐷 = 4𝑚 5𝐾 = 20

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 12

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

𝐴𝑑 𝑔𝑚 𝑅𝐷
𝐶𝑀𝑅𝑅 𝑖𝑛 𝑑𝐵 = 20 𝐿𝑜𝑔 = =∞
𝐴𝑐𝑚 0
𝑅 50
iii) 𝐴𝑐𝑚 = − 2𝑅 𝐷 = − 2×25𝐾 = 0.001
𝑆𝑆

𝐴𝑑 = 𝑔𝑚 𝑅𝐷 = 4𝑚 5𝐾 = 20
𝐴𝑑 20
𝐶𝑀𝑅𝑅 𝑖𝑛 𝑑𝐵 = 20 𝐿𝑜𝑔 = 20 𝐿𝑜𝑔 = 86𝑑𝐵
𝐴𝑐𝑚 0.001
𝑅 ∆𝑔𝑚 5𝐾 80𝜇
iv) 𝐴𝑐𝑚 = 2𝑅𝐷 = 2×25𝑘 = 2𝑚
𝑆𝑆 𝑔𝑚 4𝑚

𝐴𝑑 = 𝑔𝑚 𝑅𝐷 = 4𝑚 5𝐾 = 20
𝐴𝑑 20
𝐶𝑀𝑅𝑅 𝑖𝑛 𝑑𝐵 = 20 𝐿𝑜𝑔 = 20 𝐿𝑜𝑔 = 80𝑑𝐵
𝐴𝑐𝑚 0.002

3.3 The differential amplifier with active load

To increase the gain of the amplifier R D should be increased, but it has impact on the
operating point, hence replacing RD by constant current source results in much higher gain
and saving in chip area.

3.3.1 Differential to single ended conversion

Fig. 3.9 illustrates the simplest differential to single ended conversion. It consists of
simply ignoring the drain current signal of Q1 and eliminating its drain resistor and taking the
output between the drain of Q2 and ground.
𝑉𝐷𝐷

𝑅𝐷

𝑣𝑂
𝑄1 𝑄2
𝑣𝑖𝑑 −𝑣𝑖𝑑
2 2

−𝑉𝑆𝑆

Fig. 3.9 Differential to single ended conversion of MOS differential amplifier

If output is taken between two drains the differential gain will be double and much
reduced common mode gain of output taken at one of the drain with respect to ground.

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 13

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

3.3.2 The active loaded MOS differential pair

The active loaded MOS differential pair is shown in Fig. 3.10. The differential pair is
formed by transistor Q1 and Q2 and in place of RD current mirror formed by Q3 and Q4 (active
load) is connected.
𝑉𝐷𝐷

𝑄3 𝑄4

𝑣𝑂

𝑄1 𝑄2
𝑣𝐺2 𝑣𝐺1

−𝑉𝑆𝑆

Fig. 3.10 Active loaded MOS differential pair

Assume the two input terminals are connected to a DC voltage equal to the common
mode equilibrium value, in this case 0V as shown in Fig. 3.11.
𝑉𝐷𝐷
+
𝑉𝑆𝐺3
−
𝑄3 𝑄4
𝐼
2

𝐼
2 𝑉𝑂 = 𝑉𝐷𝐷 − 𝑉𝑆𝐺3
𝐼
2 0
𝑄1 𝑄2
𝐼 𝐼
2 2

−𝑉𝑆𝑆

Fig. 3.11 The circuit at equilibrium assuming perfect matching

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 14

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

Assuming perfect matching the bias current I divide equally between Q1 and Q2. The
𝐼
drain current of Q1 is fed to the input transistor of the mirror, Q 3. Thus a replica of this
2

current is provided by the output transistor of the mirror Q 4. Observe at the output node the
𝐼
two currents 2 balance each other out, leaving a zero current to flow out to the next stage or

load. If Q4 is perfectly matched with Q3, the drain voltages of both the MOS will be same.
Hence the output voltage at equilibrium is 𝑉𝐷𝐷 − 𝑉𝑆𝐺3 . But in practical case there will always
be mismatches which cause a large deviation in output voltage from the ideal value.
Consider the circuit with a differential input voltage 𝑣𝑖𝑑 applied as shown in Fig. 3.12

𝑄3 𝑄4

𝑖 2𝑖

𝑖 𝑣𝑂
𝑖
𝑄1 𝑄2
𝑉𝑖𝑑 −𝑉𝑖𝑑
2 2

0𝑉

Fig. 3.12 The circuit with a differential input signal applied

Since we are doing small signal analysis DC sources are removed and the output
resistance rO of all transistors is ignored. Transistor Q1 will conduct a drain signal current
𝑣𝑖𝑑
𝑖 = 𝑔𝑚1 and transistor Q2 will conduct equal and opposite current i. The drain signal
2

current i of transistor Q1 is fed to the input of the Q3 - Q4 mirror, which responds by

providing a replica in the drain of Q4. At the output node there are two currents each equal to
i which sum together to form 2i hence there is no loss of gain even though the output is single
ended. If load is connected the current 2i will flow through it and determines vO.

3.3.3 Differential gain of the active loaded MOS differential pair

The output resistance rO of the transistor plays a significant role in the operation of
active loaded amplifiers. Since the circuit is not symmetrical, let us find the short circuit
transconductance Gm and the output resistance RO, then the gain will be determined by GmRO.

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 15

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

Determining the transconductance Gm

Fig. 3.13 is the circuit for determining Gm. Note that the output is short circuited to the
ground to find Gm as iO / vid.

1/𝑔𝑚3 1
𝑟𝑂3 𝑔𝑚4 𝑣𝑔3 𝑟𝑂4
𝑔𝑚 3 𝑣𝑔3
𝑟𝑂3 𝑄3 𝑄4 𝑟𝑂4 0
𝑣𝑔3 𝑖𝑂
𝑣𝑖𝑑
𝑖𝑂 𝑔𝑚1
𝑣𝑖𝑑
0 𝑔𝑚2
2 2
𝑄1 𝑟𝑂1 𝑄2
𝑣𝑖𝑑 𝑟𝑂2 −𝑣𝑖𝑑

𝑄1 𝑟𝑂2 𝑄2 2 2
𝑣𝑖𝑑 𝑟𝑂1 −𝑣𝑖𝑑
2 2

0𝑉

Fig. 3.13 Circuit for determining Gm

Even though the circuit is not symmetrical, when the output is shorted to ground, the
circuit becomes almost symmetrical. This is because the voltage between the drain of Q 1 and
ground is very small because the low resistance between the node and ground which is equal
to 1 / gm3. Hence we can assume a virtual ground at source of Q 1 and Q2, in this way the
equivalent circuit is written.
The voltage vg3 that develops at the common gate line of the mirror can be found as
𝑣𝑖𝑑 1
𝑣𝑔3 = −𝑔𝑚1 𝑟 𝑟
2 𝑔𝑚3 𝑂3 𝑂1
1
𝑆𝑖𝑛𝑐𝑒 𝑟𝑂1 𝑎𝑛𝑑 𝑟𝑂3 ≫
𝑔𝑚3
𝑔𝑚1 𝑣𝑖𝑑
𝑣𝑔3 = −
𝑔𝑚3 2
This voltage controls the drain current of Q4 resulting in a current of 𝑔𝑚4 𝑣𝑔3 . Note
that the ground at the output note causes the currents in rO2 and rO4 to be zero.
Hence the output current iO will be
𝑣𝑖𝑑
𝑖𝑂 = −𝑔𝑚4 𝑣𝑔3 + 𝑔𝑚2
2
Substituting for vgs

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 16

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

𝑔𝑚4 𝑣𝑖𝑑 𝑣𝑖𝑑

𝑖𝑂 = 𝑔𝑚1 + 𝑔𝑚2
𝑔𝑚3 2 2
𝑆𝑖𝑛𝑐𝑒 𝑔𝑚1 = 𝑔𝑚2 = 𝑔𝑚3 = 𝑔𝑚4 = 𝑔𝑚
𝑖𝑂 = 𝑔𝑚 𝑣𝑖𝑑
𝐻𝑒𝑛𝑐𝑒, 𝐺𝑚 = 𝑔𝑚

Determining the output resistance RO

Fig. 3.14 shows the circuit for determining RO.

1/𝑔𝑚3
𝑟𝑂3 𝑄3 𝑄4 𝑟𝑂4
𝑖 𝑖
𝑖𝑥
𝑖 𝑅𝑂2
𝑖
𝑣𝑥
𝑄1 𝑟𝑂2 𝑄2
𝑟𝑂1
𝑖
𝑅𝑂

Fig. 3.14 Circuit for determining RO

The current i that enters Q2 must exist at its source. It then enters Q 1 existing at the
drain to feed the feed the Q3 - Q4 mirror. Since 1/𝑔𝑚3 of transistor Q3 is much smaller than
rO3, most of the current i will flow in to the drain of Q4 which determines the relation
between i and vx
𝑣𝑥
𝑖= 𝑅𝑂2 → 𝑂𝑢𝑡𝑝𝑢𝑡 𝑟𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 𝑜𝑓 𝑄2
𝑅𝑂2
Now Q2 is a common gate (CG) transistor has in its source the input resistance of Q 1
which is connected in the CG configuration (Q1) with a small resistance in the drain
(approximately 1/𝑔𝑚3 ) thus its input resistance is approximately 1/𝑔𝑚1
1
𝐻𝑒𝑛𝑐𝑒 𝑅𝑂2 = 𝑟𝑂2 + (1 + 𝑔𝑚2 𝑟𝑂2 )
𝑔𝑚1
𝑖𝑓 𝑔𝑚1 = 𝑔𝑚2 = 𝑔𝑚 𝑎𝑛𝑑 𝑔𝑚2 𝑟𝑂2 ≫ 1
𝑅𝑂2 = 2𝑟𝑂2

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 17

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

From the circuit shown in Fig. 3.14, we can write at the output node
𝑣𝑥 𝑣𝑥 𝑣𝑥 𝑣𝑥
𝑖𝑥 = 𝑖 + 𝑖 + = 2𝑖 + =2 +
𝑟𝑂4 𝑟𝑂4 𝑅𝑂2 𝑟𝑂4
Substituting for RO2
𝑣𝑥 𝑣𝑥 1 1 1
𝑖𝑥 = + = 𝑣𝑥 + = 𝑣𝑥
𝑟𝑂2 𝑟𝑂4 𝑟𝑂2 𝑟𝑂4 (𝑟𝑂2 𝑟𝑂4 )
𝑣𝑥
𝑇𝑕𝑢𝑠 𝑅𝑂 = = (𝑟𝑂2 𝑟𝑂4 )
𝑖𝑥

Determining the differential gain

𝑣𝑂
𝑇𝑕𝑒 𝑑𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑡𝑖𝑎𝑙 𝑔𝑎𝑖𝑛, 𝐴𝑑 = = 𝐺𝑚 𝑅𝑂 = 𝑔𝑚 (𝑟𝑂2 𝑟𝑂4 )
𝑣𝑖𝑑
𝐼𝑓 𝑟𝑂2 = 𝑟𝑂4 = 𝑟𝑂
1 𝐴𝑂
𝐴𝑑 = 𝑔𝑚 𝑟𝑂 = 𝐴𝑂 → 𝐼𝑛𝑡𝑟𝑖𝑛𝑠𝑖𝑐 𝑔𝑎𝑖𝑛 𝑜𝑓 𝑡𝑕𝑒 𝑀𝑂𝑆 𝑡𝑟𝑎𝑛𝑠𝑖𝑠𝑡𝑜𝑟
2 2

3.3.4 Common mode gain and CMRR

Fig. 3.15 shows the circuit for determining common mode gain applied with common
mode signal vicm and with the power supplies eliminated except of course the output
resistance RSS of the bias current source I.

1/𝑔𝑚3 𝑣𝑔3
𝑟𝑂3 𝑄3 𝑄4 𝑟𝑂4
𝑟𝑂3 𝑄3 𝑄4 𝑟𝑂4 𝑖4
𝑖2
𝑖1 𝑅𝑂1 𝑅𝑂2 𝑣𝑂
𝑣𝑂
𝑟𝑂1
𝑟𝑂1 𝑄1 𝑄2
𝑄1 𝑄2 𝑣𝑖𝑐𝑚 𝑟𝑂2 𝑣𝑖𝑐𝑚
𝑣𝑖𝑐𝑚 𝑟𝑂2 𝑣𝑖𝑐𝑚

2𝑅𝑆𝑆 2𝑅𝑆𝑆
𝑅𝑆𝑆

Fig. 3.15 Circuit to determine common mode gain

Even though the output is single ended, the active loaded MOS differential has low
common mode gain and correspondingly high CMRR. Even though the circuit is not

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 18

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

symmetrical and hence we cannot use the common mode half circuit, we can split RSS equally
between Q1 and Q2 as shown in Fig. 3.15. It can now be seen that each of Q1 and Q2 is a
common source transistor with a large source degeneration resistance 2RSS. Since 2RSS is
much larger than 1/𝑔𝑚 of each of Q1 and Q2, the signal at the source terminals will be
approximately equal to vicm.
𝑣𝑖𝑐𝑚
𝑇𝑕𝑢𝑠 𝑤𝑒 𝑐𝑎𝑛 𝑤𝑟𝑖𝑡𝑒 𝑖1 = 𝑖2 =
2𝑅𝑆𝑆
𝑇𝑕𝑒 𝑜𝑢𝑡𝑝𝑢𝑡 𝑟𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 𝑜𝑓 𝑒𝑎𝑐𝑕 𝑜𝑓 𝑄1 𝑎𝑛𝑑 𝑄2 𝑖𝑠 𝑔𝑖𝑣𝑒𝑛 𝑏𝑦
𝑅𝑂1 = 𝑅𝑂2 = 𝑟𝑂 + 2𝑅𝑆𝑆 + 2𝑔𝑚 𝑅𝑂 𝑅𝑆𝑆
𝑊𝑕𝑒𝑟𝑒, 𝑟𝑂1 = 𝑟𝑂2 = 𝑟𝑂 𝑎𝑛𝑑 𝑔𝑚1 = 𝑔𝑚2 = 𝑔𝑚
1
Note that RO1 will be much greater than the 𝑟𝑂3 parallel resistance introduced by
𝑔𝑚 3

Q3
Similarly RO2 will be much greater than rO4. Hence RO1and RO2 can be easily neglected
while finding the total resistance between each of the drain nodes and ground.
1
The current i1 is passed through 𝑟𝑂3 and as a result produces a voltage vg3.
𝑔𝑚 3

1
𝑣𝑔3 = −𝑖1 𝑟𝑂3
𝑔𝑚3
Transistor rO4 senses this voltage and hence provides a drain current i4
1
𝑖4 = −𝑔𝑚4 𝑣𝑔3 = 𝑖1 𝑔𝑚4 𝑟𝑂3
𝑔𝑚3
At the output node the current difference between i4 and i2 passes through rO4 (Since
RO2 >> rO4) to provide vO
1
𝑣𝑂 = 𝑖4 − 𝑖2 𝑟𝑂4 = 𝑖1 𝑔𝑚4 𝑟𝑂3 − 𝑖2 𝑟𝑂4
𝑔𝑚3
Substituting for i1 and i2 and setting gm3 = gm4 it can be simplified with manipulation
as
𝑣𝑂 1 𝑟 𝑂4
𝐴𝑐𝑚 = 𝑣 = − 2𝑅
𝑖𝑐𝑚 𝑆𝑆 1+𝑔𝑚 3 𝑟 𝑂3

𝑈𝑠𝑢𝑎𝑙𝑙𝑦 𝑔𝑚3 𝑟𝑂3 ≫ 1 𝑎𝑛𝑑 𝑟𝑂3 = 𝑟𝑂4

1
𝐴𝑐𝑚 = −
2𝑔𝑚3 𝑅𝑆𝑆
Since RSS is usually large Acm will be small
𝐴𝑑 𝑔𝑚 (𝑟𝑂2 𝑟𝑂4 )
𝐶𝑀𝑅𝑅 = = 1 = 𝑔𝑚 (𝑟𝑂2 𝑟𝑂4 )2𝑔𝑚3 𝑅𝑆𝑆
𝐴𝑐𝑚
2𝑔𝑚 3 𝑅𝑆𝑆

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 19

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

𝐼𝑓 𝑟𝑂2 = 𝑟𝑂4 = 𝑟𝑂 𝑎𝑛𝑑 𝑔𝑚3 = 𝑔𝑚

𝐶𝑀𝑅𝑅 = 𝑔𝑚 𝑟𝑂 𝑔𝑚 𝑅𝑆𝑆

Problem :
𝑊
P1. An active loaded MOS differential amplifier is specified as follows, = 100,
𝐿 𝑛

𝑊
= 200, 𝜇𝑛 𝐶𝑜𝑥 = 2𝜇𝑝 𝐶𝑜𝑥 = 0.2𝑚𝐴/𝑉 2 , 𝑉𝐴𝑛 = 𝑉𝐴𝑝 = 20𝑉, 𝐼 = 0.8𝑚𝐴, 𝑅𝑆𝑆 =
𝐿 𝑃

25𝐾. 𝐶𝑎𝑙𝑐𝑢𝑙𝑎𝑡𝑒 𝐺𝑚 , 𝑅𝑂 , 𝐴𝑑 , 𝐴𝑐𝑚 𝑎𝑛𝑑 𝐶𝑀𝑅𝑅.

𝑉𝐷𝐷

𝑄3 𝑄4

𝑣𝑂

𝑄1 𝑄2
𝑣𝐺2 𝑣𝐺1

Solution : 𝐼
𝐼 1 𝑊 −𝑉𝑆𝑆
= 2 𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑡 2
2 𝐿 𝑛

1
0.4𝑚 = × 0.2𝑚 × 100 𝑉𝑂𝑉 2
2
2
0.4𝑚 × 2
𝑉𝑂𝑉 = = 0.04
0.2𝑚 × 100
𝑉𝑂𝑉 = 0.2
𝐼 0.8𝑚
𝑔𝑚 = = = 4𝑚𝐴/𝑉
𝑉𝑂𝑉 0.2
𝐺𝑚 = 𝑔𝑚 = 4𝑚𝐴/𝑉
𝑉𝐴𝑛 𝑉𝐴𝑛 20
𝑟𝑂2 = = 𝐼 = = 50𝐾
𝐼𝐷 0.4𝑚
2
𝑉𝐴𝑝 𝑉𝐴𝑝 20
𝑟𝑂4 = = 𝐼 = = 50𝐾
𝐼𝐷 0.4𝑚
2

𝑅𝑂 = 𝑟𝑂2 𝑟𝑂4 = 50𝐾 50𝐾 = 25𝐾

1 1
𝐴𝑑 = 𝑔𝑚 𝑟𝑂 = × 4𝑚 × 50𝐾 = 100 𝑓𝑜𝑟 𝑟𝑂 = 𝑟𝑂2 = 𝑟𝑂4
2 2

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 20

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

1 1
𝐴𝑐𝑚 = = = 0.005 𝑓𝑜𝑟 𝑔𝑚3 = 𝑔𝑚
2𝑔𝑚3 𝑅𝑆𝑆 2 × 4𝑚 × 25𝐾
𝐶𝑀𝑅𝑅 = 𝑔𝑚 𝑟𝑂 𝑔𝑚 𝑅𝑆𝑆 = 4𝑚 × 50𝐾 × 4𝑚 × 25𝐾 = 20000
𝐶𝑀𝑅𝑅 𝑖𝑛 𝑑𝐵 = 20 𝐿𝑜𝑔 20000 = 86𝑑𝐵

3.4 Output Stages and Power Amplifiers

An important function of the output stage is to provide the amplifier with a low output
resistance so that it can deliver the output signal to the load without loss of gain. Since the
output stage is the final stage of the amplifier, it usually deals with relatively large signals
hence the small signal approximations and models are not applicable. The most challenging
requirement in the design of the output stage is that it delivers the required amount of power
to the load in an efficient manner. This implies the power dissipated in the output stage
transistors must be as low as possible. Also high power conversion efficiency also may be
required to prolong the life of batteries employed in battery powered circuits.

3.4.1 Classification of output stages

Output stages are classified according to the collector current waveform that results
when an input signal is applied.

Class - A Stage

𝑖𝐶 The Class - A stage is biased at a current

𝐼𝐶 IC greater than the amplitude of the
𝐼𝐶 signal current, 𝐼𝐶 . Thus the transistor in a
Class - A stage conducts for the entire
cycle of input signal 360 as shown in
Fig. 3.16. The output is distortion less in
0 𝜋 2𝜋 𝜔𝑡
Class - A mode but power efficiency is
Fig. 3.16 Collector current in Class - A
Stage more (30%)

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 21

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

Class - B Stage
The Class - B stage is biased at zero
𝑖𝐶 current, hence transistor conducts for
only 180 that is half the cycle of input
𝐼𝐶 sine wave as shown in Fig. 3.17. Since

0 𝜋 2𝜋 transistor conducts half the cycle of input

𝜔𝑡
Fig. 3.17 Collector current in Class - B power efficiency is good and the output
Stage will be distorted.
To overcome this problem one more transistor will be used in Class - B mode to obtain the
negative half cycle.

Class - AB Stage
An intermediate class between A and
𝑖𝐶
B appropriately named Class - AB
𝐼𝐶
involves biasing the transistor at a non
zero dc current much smaller than the
0 𝜋 2𝜋 𝜔𝑡 peak current of the sine wave signal.
Fig. 3.18 Collector current in Class - AB As a result transistor conducts for an
Stage
interval slightly greater than half a
cycle as shown in Fig. 3.18.
The resulting conduction angle is greater than 180 but much less than 360.

Class - C Stage
In Class - C stage the transistor
𝑖𝐶
conducts for an interval shorter than
that of a half cycle, that is the
𝐼𝐶 conduction angle is less than 180 as
0 𝜋 2𝜋 𝜔𝑡 shown in Fig. 3.19 hence the collector
Fig. 3.19 Collector current in Class - C current is periodically pulsating
Stage
waveform.
In class - C stage the power efficiency is very good but output is distorted. To overcome this
problem parallel LC circuit is used at output tuned to the frequency of the input signal.

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 22

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

3.5 Class - A Output stage

Consider the class - A output stage or emitter follower shown in Fig. 3.20.

+𝑉𝐶𝐶

𝑣𝑖 𝑄1
𝑉𝐵𝐸1
𝑖𝐸1
𝑣𝑂
𝑅 𝐼 𝑖𝐿
𝑄2
𝑅𝐿
𝑄3

−𝑉𝐶𝐶

Fig. 3.20 Class - A Output stage

The transistor Q1 is biased with a constant current I supplied by transistor Q 2. Since

the emitter current 𝐼𝐸1 = 𝐼 + 𝑖𝐿 , the bias current I must be greater than the largest negative
load current. Otherwise Q1 cuts off and Class - A operation will no longer be maintained. The
transfer characteristic of the emitter follower is shown in Fig. 3.21.
𝑣𝑂

𝑉𝐶𝐶 − 𝑉𝐶𝐸1𝑆𝑎𝑡

0
𝑉𝐵𝐸1 𝑣𝑖

−𝐼 𝑅𝐶
−𝑉𝐶𝐶 + 𝑉𝐶𝐸2𝑆𝑎𝑡

Fig. 3.21 Transfer characteristic of Class - A Output stage

From the circuit we can write that

𝑣𝑂 = 𝑣𝑖 − 𝑉𝐵𝐸1
The positive limit of the linear region is determined by the saturation of Q1
𝑣𝑂𝑚𝑎𝑥 = 𝑉𝐶𝐶 − 𝑉𝐶𝐸1𝑠𝑎𝑡

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 23

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

In the negative direction depending on the value of I and R L, the limit of the linear
region is determined either by Q1 turning off
𝑣𝑂𝑚𝑖𝑛 = −𝐼𝑅𝐿
or by Q2 saturating
𝑣𝑂𝑚𝑖𝑛 = −𝑉𝐶𝐶 + 𝑉𝐶𝐸2𝑆𝑎𝑡
this is achieved provided the bias current I is greater than the magnitude of the
corresponding load current
−𝑉𝐶𝐶 + 𝑉𝐶𝐸2𝑆𝑎𝑡
𝐼≥
𝑅𝐿
Signal waveform

𝑣𝐶𝐸1
2𝑉𝐶𝐶

𝑉𝐶𝐶

0
𝑡
𝑖𝐶1
2𝐼

𝑡
𝑣𝑂
𝑉𝐶𝐶

𝑡
−𝑉𝐶𝐶

𝑝𝐷1
𝑉𝐶𝐶 𝐼

Fig. 3.22 Maximum signal waveforms of Class - A output stage

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 24

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

Consider the operation of emitter follower circuit shown in Fig. 3.20 for sine wave
input. Neglecting VCESat, if the bias current I is properly selected, the output voltage can
swing from –VCC to +VCC with the quiescent value being zero and the corresponding
waveforms VCE1 = VCC –vO are shown in Fig. 3.22. Assuming that the bias current I is
𝑉𝐶𝐶
selected to allow a maximum negative load current of the collector current of Q1
𝑅𝐿

and instantaneous power dissipation in Q1, 𝑝𝐷1 = 𝑣𝐶𝐸1 𝑖𝐶1 is also shown in Fig. 3.22.

Power dissipation
When input is zero, the maximum power dissipation in Q 1 is VCC I hence the
transistor Q1 must be capable of withstanding this power. When R L = , 𝑖𝐶1 = 𝐼 is constant
and the instantaneous power dissipation in Q1 will depend on the instantaneous value of vO.
The maximum power dissipation will occur when vO = -VCC, for this case VCE1 = 2 VCC and
pD1 = 2 VCC I.
When RL = 0, the load current will be infinity, hence current through Q 1 is very large
resulting in large power dissipation, if this condition persist for long duration Q 1 may burn
up. The maximum power dissipation of Q2 is also 2 VCC I.

Power conversion efficiency

The power conversion efficiency of an output stage is defined as
𝐿𝑜𝑎𝑑 𝑃𝑜𝑤𝑒𝑟 (𝑃𝐿 )
 =
𝑆𝑢𝑝𝑝𝑙𝑦 𝑃𝑜𝑤𝑒𝑟 (𝑃𝑆 )
2
𝑉𝑂 2
2 𝑉𝑂
𝐴𝑣𝑒𝑟𝑎𝑔𝑒 𝑙𝑜𝑎𝑑 𝑝𝑜𝑤𝑒𝑟 = =
𝑅𝐿 2𝑅𝐿
𝑃𝑜𝑤𝑒𝑟 𝑑𝑟𝑎𝑤𝑛 𝑓𝑜𝑟𝑚 𝑛𝑒𝑔𝑎𝑡𝑖𝑣𝑒 𝑎𝑛𝑑 𝑝𝑜𝑠𝑖𝑡𝑖𝑣𝑒 𝑠𝑢𝑝𝑝𝑙𝑦, 𝑃𝑆 = 2 𝑉𝐶𝐶 𝐼
In a voltage follower assuming the output voltage will take up the maximum value
𝑣𝑂𝑚𝑎𝑥 = 𝑉𝐶𝐶 and minimum value 𝑣𝑂𝑚𝑖𝑛 = 𝐼 𝑅𝐿
𝑡𝑕𝑒 𝑚𝑎𝑥𝑖𝑚𝑢𝑚 𝑒𝑓𝑓𝑖𝑐𝑖𝑒𝑛𝑐𝑦,  = 25 %
Hence Class - A output stage is rarely used in high power applications

3.6 Transformer coupled power amplifier

The RC coupled Class - A amplifier discussed in previous section has ideal efficiency
of 25 %. To improve efficiency the transformer coupled class - A power amplifier is

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 25

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

preferred in which a transformer is used to couple ac power to the load. By adjusting the turn
ratio of the primary winding to the secondary winding the source and load impedances can be
matched for maximum power transfer. The transformed coupled power amplifier is shown in
Fig. 3.23 and the DC and AC load line is shown in Fig. 3.24.

𝑉𝐶𝐶

𝐼1 𝐼2

𝑅𝐵 𝑉1 𝑉2 𝑅𝐿

𝑁1 𝑁2
𝐶

𝑉𝑖

Fig. 3.23 Transformer coupled power amplifier

The impedance matching of the transistor is

𝑉1 𝑁1 𝐼1 𝑁2
= 𝑎𝑛𝑑 =
𝑉2 𝑁2 𝐼2 𝑁1

𝑁1
𝑉1 = 𝑉
𝑁2 2

𝑉1 𝑁1 𝑉2
=
𝐼1 𝑁2 𝐼1

𝑁2
𝑅𝑒𝑝𝑙𝑎𝑐𝑖𝑛𝑔 𝐼1 = 𝐼
𝑁1 2
2
𝑉1 𝑁1 𝑉2
=
𝐼1 𝑁2 𝐼2
2
′ 𝑁1
𝑅𝐿 = 𝑅𝐿
𝑁2

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 26

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

𝐼𝐶
𝐷𝐶 𝐿𝑜𝑎𝑑𝑙𝑖𝑛𝑒

𝑉𝐶𝐶
𝑅𝑎𝑐 𝑉𝑚

𝐼𝐶𝑄
𝑄
𝐴𝐶 𝐿𝑜𝑎𝑑𝑙𝑖𝑛𝑒
𝑉𝐶𝐸𝑄
0 𝑉𝐶𝐶 2𝑉𝐶𝐶 𝑉𝐶𝐸

Fig. 3.24 DC and AC load line of transformer coupled amplifier

DC load line is drawn assuming DC resistance of primary winding of transformer as

1
zero, hence slope is infinity. AC load line is drawn with slope − where 𝑅𝑎𝑐 is ac
𝑅𝑎𝑐

resistance of the primary winding.

𝑃𝑜𝑤𝑒𝑟 𝑑𝑟𝑎𝑤 𝑓𝑟𝑜𝑚 𝑑𝑐 𝑠𝑜𝑢𝑟𝑐𝑒, 𝑃𝑑𝑐 = 𝑉𝐶𝐶 𝐼𝐶𝑄
𝑉𝑚 𝐼𝑚
𝑃𝑜𝑤𝑒𝑟 𝑑𝑒𝑙𝑖𝑣𝑒𝑟𝑒𝑑 𝑡𝑜 𝑙𝑎𝑜𝑑, 𝑃𝑎𝑐 = ; 𝑀𝑎𝑥𝑖𝑚𝑢𝑚 𝑝𝑒𝑎𝑘 𝑉𝑚 = 𝑉𝐶𝐶 𝑎𝑛𝑑 𝐼𝑚 = 𝐼𝐶𝐶
2 2
𝑃
𝑇𝑕𝑒 𝑒𝑓𝑓𝑖𝑐𝑖𝑒𝑛𝑐𝑦 𝑜𝑓 𝑡𝑟𝑎𝑛𝑠𝑓𝑜𝑟𝑚𝑒𝑟 𝑐𝑜𝑢𝑝𝑙𝑒𝑑 𝑎𝑚𝑝𝑙𝑖𝑓𝑖𝑒𝑟,  = 𝑃𝑎𝑐 = 50 %.
𝑑𝑐

3.7 Class - B Transformer coupled amplifier

In the class - B amplifier, the operating point is located in the cutoff region therefore
the transistor conducts only for 180 or half of the input signal, hence efficiency is more.
However to get the output signal for the complete cycle of the input signal, two transistors are
connected in push pull configuration as shown in Fig. 3.25.
The transistors are biased such that in the absence of the input signal both transistors
remain in cut off region hence efficiency is more.
The current flowing through each transistor in Class - B amplifier is shown in Fig.
3.26.

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 27

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

𝑄1 𝐼1
𝐼𝐿

𝑉𝑖
𝑉𝐶𝐶

𝑄2 𝐼2

Fig. 3.25 Class - B Transformer coupled amplifier

𝐼1

0 𝑡
𝐼2

𝑡
𝐼𝐿

𝐼𝑑𝑐
𝐼𝑚

2𝐼𝑚
𝜋
𝑡

Fig. 3.26 Current flowing through each transistor in Class - B amplifier

The efficiency of transformer coupled amplifier,

𝑃𝑎𝑐 𝑉𝑟𝑚𝑠 𝐼𝑟𝑚𝑠
= =
𝑃𝑑𝑐 𝑉𝐷𝐶 𝐼𝐷𝐶
𝑉𝑚 𝐼𝑚 𝑉𝑚 𝐼𝑚
2 2 2
 = 2𝐼𝑚 = 2𝐼𝑚 𝑉𝑚 𝑏𝑒𝑐𝑎𝑢𝑠𝑒 𝑉𝐶𝐶 = 𝑉𝑚
𝑉𝐶𝐶
𝜋 𝜋
𝜋
= = 78.5 %
4

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 28

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

3.8 Class - B output stage

The class - B output stage is shown in Fig. 3.27 which consists of complementary pair
of transistors (an NPN and PNP transistors) connected in such a way that both cannot conduct
simultaneously.
𝑉𝐶𝐶

𝑄𝑁
𝑉𝑂
𝑉𝑖
𝐼𝐿
𝑄𝑃 𝑅𝐿

−𝑉𝐶𝐶

Fig. 3.27 Class - B Output stage

Circuit operation
When Vi = 0, both transistors are in cut off and the output voltage, V O = 0. As input
increases in positive direction and exceeds 0.5 V (V ) QN conducts and operates as emitter
follower, that is VO = Vi – VbeN and QN supplies load current. When input increases in
negative direction by more than 0.5 V, QP turns on and acts as emitter follower and supplies
load current, the output voltage, VO = Vi + VEBP or VO = Vi - VBEP

Transfer characteristics
The transfer characteristics of Class - B output stage is shown in Fig. 3.28. From the
figure it is clear that near origin both transistors will be cutoff and V O = 0. This dead band
results with cross over distortion is shown in Fig. 3.29.

𝑉𝑂

𝑉𝑐𝑐 − 𝑉𝐶𝐸𝑁𝑆𝑎𝑡
𝑆𝑙𝑜𝑝𝑒 = 1
−𝑉𝑐𝑐 + 𝑉𝐶𝐸𝑃𝑆𝑎𝑡 + 𝑉𝐸𝐵𝑃 −0.5𝑉 𝑉𝑖
0.5𝑉 𝑉𝑐𝑐 − 𝑉𝐶𝐸𝑁𝑆𝑎𝑡 + 𝑉𝐵𝐸𝑁
𝑆𝑙𝑜𝑝𝑒 = 1
−(𝑉𝑐𝑐 − 𝑉𝐶𝐸𝑃𝑆𝑎𝑡 )

Fig. 3.28 Transfer characteristics of Class - B output stage

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 29

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

𝑉𝑂 𝑉𝑂

𝐶𝑟𝑜𝑠𝑠 𝑜𝑣𝑒𝑟
𝑑𝑖𝑠𝑡𝑜𝑟𝑡𝑖𝑜𝑛

𝑉𝑖 𝑡

𝑉𝑖

Fig. 3.29 Cross over distortion (dead zone) in class - B output stage

Power conversion efficiency

𝑉 2
Neglecting cross over distortion, the average load power, 𝑃𝐿 = 2 𝑂𝑅
𝐿
2
1 𝑉𝑂
Average power drawn from each power supply, 𝑃𝑆+ = 𝑃𝑆− = 𝜋 𝑉𝐶𝐶
𝑅𝐿

Maximum conversion efficiency of class - B output stage is 78.5 %.

Power dissipation
The maximum power dissipation in NPN transistor and PNP transistor is,
𝑉𝐶𝐶 2
𝑃𝐷𝑁𝑚𝑎𝑥 = 𝑃𝐷𝑃𝑚𝑎𝑥 =
𝜋 2 𝑅𝐿

3.9 Class - AB output stage

The crossover distortion of class - B output stage can be eliminated by biasing the
complementary output transistor at a small non zero current. The result is class - AB output
stage which is shown in Fig. 3.30.
𝑉𝐶𝐶

𝑄𝑁
𝑉𝐵𝐵
2

𝑉𝑖
𝑉𝐵𝐵
2 𝑅𝐿
𝑄𝑃

−𝑉𝐶𝐶
Fig. 3.30 Class - AB output stage

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 30

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

A bias voltage VBB is applied between the base of QN and QP. When input, Vi = 0 the
𝑉𝐵𝐵
output VO = 0 and voltage appears across base to emitter junction of each of QN and QP.
2

Circuit operation
When Vi goes positive, the voltage at the base of Q N increases by the same amount
and the output becomes positive
𝑉𝐵𝐵
𝑉𝑂 = 𝑉𝑖 + − 𝑉𝐵𝐸𝑁
2
The positive VO causes a current IL to flow through RL and thus IN must increase that
is 𝑖𝑁 = 𝑖𝑃 + 𝑖𝐿 ………………… ①
The increase in iN will increase VBEN, since the voltage between the two bases remain
constant at VBB, the increase in VBEN results in decrease in VEBP and hence iP hence
𝑉𝐵𝐸𝑁 + 𝑉𝐸𝐵𝑃 = 𝑉𝐵𝐵
𝑖𝑁 𝑖𝑝 𝑖𝑄
𝑉𝑇 𝑙𝑛 + 𝑉𝑇 𝑙𝑛 = 2𝑉𝑇 ln
𝑖𝑆 𝑖𝑆 𝑖𝑆
𝑖𝑁 𝑖𝑃 = 𝐼𝑄 2 …………………②
Thus as iN increases, iP decreases by the same ratio while the product remains constant
combining equation ① and ② yields
𝑖𝑁 2 − 𝑖𝐿 𝑖𝑁 − 𝑖𝑄 2 = 0
From the equation discussed above, it can be seen that for positive output voltages the
load current is supplied by QN and mean while QP conducts a current that decreases as V O
increases which can be neglected for large VO. For negative input voltage the opposite
occurs.
The transfer characteristics of Class - AB output stage is shown in Fig. 3.31.

𝑉𝑂
𝑉𝑐𝑐 − 𝑉𝐶𝐸𝑁𝑆𝑎𝑡
𝑆𝑙𝑜𝑝𝑒 = 1

𝑉𝑖

−(𝑉𝑐𝑐 − 𝑉𝐶𝐸𝑃𝑆𝑎𝑡 )

Fig. 3.31 Transfer characteristics of Class - AB output stage

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 31

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

The class - AB output stage operates almost in the same manner as class - B with an
exception that for small Vi both transistors conduct and as Vi increases or decreases one of
the two transistors take over the operation. Since the transition is smooth cross over distortion
will be eliminated.
The power relationship in the class - AB output stage is almost identical to those
discussed for class - B output stage. The only difference is under quiescent conditions class -
AB circuit dissipates a power of VCC IQ per transistor and since IQ is usually much smaller
than the peak current the quiescent power is negligible.

Output resistance
The equivalent circuit of class - AB output stage to determine output resistance is
shown in Fig. 3.32.

𝑄𝑁

𝑅𝑂𝑢𝑡

𝑄𝑃

Fig. 3.32 Equivalent circuit to determine output resistance

𝑅𝑂𝑢𝑡 = 𝑟𝑒𝑁 𝑟𝑒𝑃

𝑟𝑒𝑁 𝑎𝑛𝑑 𝑟𝑒𝑃 𝑎𝑟𝑒 𝑠𝑚𝑎𝑙𝑙 𝑠𝑖𝑔𝑛𝑎𝑙 𝑒𝑚𝑖𝑡𝑡𝑒𝑟 𝑟𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 𝑜𝑓 𝑄𝑁 𝑎𝑛𝑑 𝑄𝑃 𝑟𝑒𝑠𝑝𝑒𝑐𝑡𝑖𝑣𝑒𝑙𝑦
𝑉𝑇 𝑉𝑇
𝑟𝑒𝑁 = 𝑎𝑛𝑑 𝑟𝑒𝑃 =
𝑖𝑁 𝑖𝑃
𝑉𝑇 𝑉𝑇 𝑉𝑇
𝑡𝑕𝑢𝑠, 𝑅𝑂𝑢𝑡 = =
𝑖𝑁 𝑖𝑃 𝑖𝑃 + 𝑖𝑁

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 32

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

Biasing Class-AB circuit using diodes

The class-AB circuit biased using diodes is shown in Fig. 3.33. The bias voltage VBB
is generated by passing a constant current IBIAS through a pair of diodes, D1 and D2. In
circuits that supply large amounts of power, the output transistors are large-geometry devices.
The biasing diodes, however, need not be large devices, and thus the quiescent current I Q
established in QN and QP will be IQ = nIBIAS, where n is the ratio of the emitter–junction area
of the output devices to the junction area of the biasing diodes. In other words, the saturation
(or scale) current IS of the output transistors is n times that of the biasing diodes.

+
VBB Vo
_

Fig. 3.33 Class-AB circuit biased using diodes

The diode biasing arrangement has an important advantage: It can provide thermal
stabilization of the quiescent current in the output stage. To appreciate this point, recall that
the class AB output stage dissipates power under quiescent conditions. Power dissipation
raises the internal temperature of the BJTs. A rise in transistor temperature results in a
decrease in its VBE (approximately –2 mV/°C) if the collector current is held constant.
Alternatively, if VBE is held constant and the temperature increases, the collector current
increases. The increase in collector current increases the power dissipation, which in turn
increases the junction temperature and hence, the collector current. Thus a positive-feedback
mechanism exists that can result in a phenomenon called thermal runaway. Unless checked,
thermal runaway can lead to the ultimate destruction of the BJT. Diode biasing can be
arranged to provide a compensating effect that can protect the output transistors against
thermal runaway under quiescent conditions. Specifically, if the diodes are in close thermal
contact with the output transistors, their temperature will increase by the same amount as that
of QN and QP. Thus VBB will decrease at the same rate as VBEN + VEBP, with the result that IQ

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 33

S3CES02 Analog Electronic Circuits (Unit-3) III Semester

remains constant. Close thermal contact is easily achieved in IC fabrication. It is obtained in

discrete circuits by mounting the bias diodes on the metal case of Q N or QP.

Problems :
P1. A transformer coupled class - A power amplifier supplies power to an 80  load
connected across the secondary of a step down transformer having a turn ration 5:1.
Determine the maximum power output for a zero signal collector of 120 mA.
Solution :
𝑁
𝑇𝑢𝑟𝑛 𝑟𝑎𝑡𝑖𝑜, 𝛼 = 𝑁1 = 5
2

2
𝑁1
𝑅𝐿 ′ = 𝑅𝐿 = 52 × 80 = 2000
𝑁2
𝐼𝑚𝑎𝑥 = 2𝐼𝐶 , 𝐼𝑚𝑖𝑛 = 0
1 𝐼𝑚𝑎𝑥 − 𝐼𝑚𝑖𝑛 𝐼𝐶
𝐼𝑟𝑚𝑠 = =
2 2 2

2 ′𝐼𝐶 2 ′ 120 𝑚2
𝑃𝑂𝑢𝑡 (𝑎𝑐 ) = 𝐼 𝑟𝑚𝑠 𝑅𝐿 = 𝑅 = × 2𝐾 = 14.4 𝑊
2 𝐿 2

P2. A Class - B push pull amplifier is supplied with VCC = 50 V, the signal brings the
collector voltage down to Vmin = 5 V. The total dissipation from both transistors is 40
W. Find the total power and conversion efficiency.
Solution :
𝑃𝑑 = 𝑃𝑑𝑐 − 𝑃𝑎𝑐
2 𝐼𝑚
40 = 𝑉𝐶𝐶 𝐼𝑚 − 𝑉 − 𝑉min 𝑏𝑒𝑐𝑎𝑢𝑠𝑒 𝑉𝑚 = 𝑉𝐶𝐶
𝜋 2 𝐶𝐶
𝐼𝑚 = 4.287 𝐴
2
𝑃𝑑𝑐 = 𝑉 𝐼 = 136.45 𝑊
𝜋 𝐶𝐶 𝑚
𝐼𝑚
𝑃𝑎𝑐 = 𝑉 − 𝑉𝑚𝑖𝑛 = 96.45 𝑊
2 𝐶𝐶
𝑃𝑎𝑐
= = 73.03 %
𝑃𝑑𝑐

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 34