ASE2207: DIGITAL ELECTRONIC

INSTRUMENTATION SYSTEMS

Lecture 3: Computer Structure

Jan 2024
Lecture 3 Overview
• Basic logic circuits, Truth-table, Boolean equation, timing diagrams
• Combinatorial circuits: Adder, multiplexer, shifter, decoder/encoder, comparator
• Transistor-level implementation of logic circuit, digital circuit design using HDL
• Sequential circuits: SR latch, D and JK flip-flops, register, counters
• Computer Architecture and Communication
• Data buses and protocol
• OSI, transmission medium, networking and network topology

Important notes
• Please go thru the lecture materials and raise questions if you have any queries. Some relevant
videos are listed below, you are expected to search for the remaining topics (independent
learning)
• Video on Boolean algebra: https://www.youtube.com/watch?v=WW-NPtIzHwk
• Video on Sum of Product (SOP): https://www.youtube.com/watch?v=xnLBbOYYnHM&t=69s

2
Introduction
• Logic allows the reasoning on whether a
proposition (declarative statement) is true
if certain conditions are true.
• Propositions can be classified as true (1) or
false (0).
• In 1850s, the English Mathematician,
Philosopher and Logician George Boole
developed a mathematical system for
formulating logic statements.
• Logic statements can be realized using George Boole (/ˈbuːl/; 2 November 1815 – 8
December 1864) was an English
mathematician, philosopher and logician. He
electronic Logic Circuits. worked in the fields of differential equations
and algebraic logic, and is now best known as
• Logic circuits are classified into two types: the author of The Laws of Thought. As the
inventor of the prototype of what is now called
Boolean logic, which became the basis of the
̶ Combinatorial modern digital computer, Boole is regarded in
hindsight as a founder of the field of digital
̶ Sequential electronics.
3
Basic logic operations

Combinatorial Sequential Basic Logic

Circuit Circuit Operations
• Output depends not • AND
• Outputs depends only on its current
only on current • OR
inputs, but also the
inputs. past sequence of • NOT
inputs.

Z = A = A' =~ A = ¬A

AND OR NOT (Inverter)

4
 Basic logic operations: AND & NAND
1. Logic symbol and circuit

Z AND = A.B = A ∧ B
2. Logic/Boolean equation
4. Timing diagram
3. Truth table
AND NAND
A
Input A B output output
ZAND ZNAND B
010: 0 0 0 1
110: 0 1 0 1
ZAND
210: 1 0 0 1 ZNAND
310: 1 1 1 0 5
Basic logic operations: OR & NOR
1. Logic symbol and circuit

ZOR = A + B = A ∨ B
2. Logic/Boolean equation

4. Timing diagram
3. Truth table
OR NOR
Input A B output output A
ZOR ZNOR
B
010: 0 0 0 1
110: 0 1 1 0 ZOR
210: 1 0 1 0 ZNOR
310: 1 1 1 0
6
 Electronic logic gates
f (a, b) = a.b f ( a , b) = a + b f(a)Z = A = A' =~ A = ¬A
a a
a
b b

& ≥1 1
AND gate OR gate NOT gate / Inverter

a
f (a, b) = a.b = a + b NAND gate
b

a
f (a, b) = a + b = a.b NOR gate
b
7
 Electronic logic gates

a Input XOR output

b
f ( a, b) = a ⊕ b A B ZXOR
0 0 0
= a.b + a.b
0 1 1
=1 1 0 1
1 1 0
Exclusive-OR (XOR) gate

a Input XNOR output

b f ( a, b) = a ⊕ b A B ZXNOR
0 0 1
0 1 0
=1 = a.b + a.b
1 0 0
1 1 1
Exclusive-NOR (XNOR) gate
8
Combinatorial Circuits

• In combinational circuits, the current values of binary outputs {y1,…, ym}

depend only on the current binary inputs {x1,…, xn}.
• In actual implementations of combinational circuits, there are propagation
delays and the output changes are taking place some time (∆t) after the
inputs have changed.
• Typical propagation delays are ranging from several nanosecond to several
hundred nanoseconds.

9
Combinatorial Circuits

• Any Boolean function that is expressed as a sum of minterms

or as a product of max terms is said to be in its “canonical
form”.
• A minterm is a Boolean expression resulting in 1 for the
output of a single cell expressed in a product term. The
minterm is denoted as mi.
• A maxterm is a Boolean expression resulting in a 0 for the
output of a single cell expressed in a sum term. The max term
is denoted as Mi.
• Sum-of-Product (SOP) or Disjunctive Normal Form (DNF) is
the sum (OR) of all the product (AND) minterms.
• Product-of-Sum (POS) or Conjunctive Normal form (CNF) is
the product (AND) of all sum (OR) maxterms.
10
Sum-of-Product (SOP) & Product-of-Sum (POS) form

Sum-of-Product (SOP) or Disjunctive Normal Form (DNF) Index A B C f

is the sum (OR) of all the product (AND) minterms. 0 0 0 0 1
1 0 0 1 1
• f(A,B,C) = ∑ 𝑚𝑚(0,1,2,3,6) =∏ 𝑀𝑀(4,5,7) 2 0 1 0 1
3 0 1 1 1
• 𝑓𝑓𝑆𝑆𝑆𝑆𝑆𝑆 = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐶𝐶 ̅ 𝐶𝐶̅ + 𝐴𝐴𝐵𝐵𝐵𝐵
� + 𝐴𝐴𝐵𝐵 ̅ + 𝐴𝐴𝐴𝐴 𝐶𝐶̅
4 1 0 0 0
5 1 0 1 0
• 𝑓𝑓𝑃𝑃𝑃𝑃𝑃𝑃 = (𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶)(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶)(
̅ 𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶)̅
6 1 1 0 1
7 1 1 1 0

Index A B C g
Product-of-Sum (POS) or Conjunctive Normal form (CNF)
0 0 0 0 1
is the product (AND) of all sum (OR) maxterms.
1 0 0 1 0

• g(A,B,C) = ∏ 𝑀𝑀(1,2) =∑ 𝑚𝑚(0,3,4,5,6,7) 2 0 1 0 0

3 0 1 1 1
• g POS= 𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ 𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶 4 1 0 0 1
5 1 0 1 1
• g 𝑆𝑆𝑆𝑆𝑆𝑆 = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴𝐵𝐵𝐵𝐵
̅ + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴𝐵𝐵𝐶𝐶
� + 𝐴𝐴𝐴𝐴 𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐴𝐴 6 1 1 0 1
7 1 1 1 1
11
Sum-of-Product (SOP) & Product-of-Sum (POS) form

• Incompletely specified functions (don’t care Index A B C f

condition) 0 0 0 0 0
1 0 0 1 1
- Input combinations that never occur
2 0 1 0 1
- Output condition required to be 1 or 0 only 3 0 1 1 0
for certain combination 4 1 0 0 x
- Usually denoted as × 5 1 0 1 x

- 𝑓𝑓 = ∑ 𝑚𝑚 1,2,7 + 𝑑𝑑(4,5,6) 6 1 1 0 x
7 1 1 1 1
- 𝑓𝑓 = ∏ 𝑀𝑀 0,3 . 𝐷𝐷(4,5,6)

12
Sum-of-Product (SOP) & Product-of-Sum (POS) form

• Sum of product example: • Product of sum example:

A B C Z A B C Z
0 0 0 0 0 0 0 0 (A + B + C )
0 0 1 1 A.B.C 0 0 1 1
0 1 0 1 A.B.C 0 1 0 1
0 1 1 0 0 1 1 0 (A + B + C )
1 0 0 1 A.B.C 1 0 0 1
1 0 1 0 1 0 1 0 (A + B + C )
1 1 0 0 1 1 0 0 (A + B + C )
1 1 1 1 A.B.C 1 1 1 1

Z 1= A.B.C + A.B.C + A.B.C + A.B.C Z2 = ( A + B + C ).( A + B + C ).

Z = A.B.C + A.B.C + A.B.C + A.B.C ( A + B + C ).( A + B + C )

13
SOP and POS logic implementation

Z1 = A.B.C + A.B.C + A.B.C + A.B.C Z 2 = ( A + B + C ).( A + B + C ).

( A + B + C ).( A + B + C )
A
A.B.C A
B A+ B +C
B

A.B.C
A+ B +C
Z1
Z2
A.B.C
C A+ B +C
C

A.B.C
A+ B +C

14
 Performance matrices for Logic Circuits

• Objectives of simplifying switching functions

- Easier to realize, minimizing cost of implementing
physical circuits
- Cost depends on the nature of circuit components
used, complexity of the circuit and reliability

• Performance consideration in realizing a circuit

- 1. Number of gates (g):
- minimize the number of product term f = (A+B).(A+(C+C.D))
- 2. Number of gate inputs literals (gi):
- minimize gate complexity by minimizing number of
literals in each product term.

- 3. Maximum path length (mpl):

- timing consideration important to determine final design
- E.g. 2-level design may be preferred over a 3-level or 4-
level design
f = A+BC
- 4. Maximum fan-in (mfi):
- The maximum number of inputs to a particular gate that
is used to determine the worst case delay calculation

15
 7-Segment display work example
7-segment decoder (display)
WXYZ A B C D E F G
S0 0000 1 1 1 1 1 1 0
W
S1 0001 0 1 1 0 0 0 0
S2 0010 1 1 0 1 1 0 1
X
S3 0011 1 1 1 1 0 0 1
S4 0100 0 1 1 0 0 1 1
Y
S5 0101 1 0 1 1 0 1 1
S6 0110 1 0 1 1 1 1 1
Z
S7 0111 1 1 1 0 0 0 0
S8 1000 1 1 1 1 1 1 1
S9 1001 1 1 1 1 0 1 1
S10 1010 × × × × × × ×
S11 1011 × × × × × × ×
S12 1100 × × × × × × ×
S13 1101 × × × × × × ×
S14 1110 × × × × × × ×
S15 1111 × × × × × × ×
16
Inputs Outputs
 7-Segment display work example
𝑆𝑆𝑆𝑆𝐺𝐺𝐴𝐴 = 𝑋𝑋. 𝑍𝑍 + 𝑌𝑌 + 𝑊𝑊 + 𝑋𝑋. 𝑍𝑍 W
A
X
𝑆𝑆𝑆𝑆𝐺𝐺𝐵𝐵 = 𝑌𝑌. 𝑍𝑍 + 𝑋𝑋 + 𝑌𝑌. 𝑍𝑍 Y
Z B
SEGC = Y + Z + X
C
SEGD = X .Z + W
+ Y .Z + X .Y .Z + X .Y D

SEGE = X .Z + Y .Z
E

SEGF = W + Y .Z
F
+ X .Z + X .Y

SEGG = W + X .Y G

+ X .Z + X .Y
17
Landing gear door warning example

𝐴𝐴11 = 𝐴𝐴7

𝐴𝐴7 = A1. A2. A3. A4. A5

18
 Arithmetic circuits: Ripple adder

• It is possible to create a logical circuit using multiple full adders to

add N-bit numbers.
• Each full adder inputs a Cin, which is the Cout of the previous adder.
• This kind of adder is a ripple carry adder, since each carry bit
"ripples" to the next full adder.
• Ripple carry adders are very slow for wide operands, since the longest
path stretches from the least significant bit to the most significant bit.
Hence, the maximum time is proportional to the number of bits.
• More advance adder using the carry-look-ahead method is much
faster and independent of the bit length, however it requires a lot more
logic gates.

19
 Arithmetic circuits: Ripple adder

• The basic logic circuit of a ripple adder is a half-adder. A7 A6 A5 A4 A3 A2 A1 A0

• Using 2 half-adders, a full adder can be constructed. + B7 B6 B5B4 B3B2B1B0
S 7 S6 S5 S4 S3 S2 S1 S0
How to add two binary numbers?
Half adder
Step 1: You start adding the 2 LSB A0 S0
1111 111 bits (A0 + B0) of A and B. This will
produce a 1 bit sum output (S0) B0 C0
0111 1111 and 1 carry-out bit (C0).

+ 0000 0001 Step 2: You start adding the next Full adder
three bits (you notice is 3-bit as A1…7
1000 0000 you need to consider any carry- S1…7
in), two bits are (A1 and B1) as well
B1…7
as any carry in from the previous C1…7 C1…7
bit. This will produce another sum
output bit and a carry-out bit. You
also noted all subsequent bits are
added in the same manner. 20
 Arithmetic circuits: Ripple adder

• What are the steps involved to design a combinational circuit (e.g. adder)?
Step 1: Truth table Step 2: Optimised Step 3: Circuit implementations
Boolean equations
Half adder
Ai Bi Si Co Ai Si
0 0 0 0 Si = Ai ⊕ Bi
0 1 1 0
1 0 1 0 Co = Ai .Bi
Co
1 1 0 1 Bi
Full adder
Ai Bi Ci Si Ci+1
0 0 0 0 0
0 0 1 1 0 Si = Ai ⊕ Bi ⊕ Ci
0 1 0 1 0
0 1 1 0 1 Ci +1 = Ai .Bi + ( Ai ⊕ Bi )Ci
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1 21
Arithmetic circuits: Ripple adder
• Multiple full adders can be chained together to add N-bit numbers.
• Each full adder has its inputs Cin connected to the Cout of previous adder.
• This kind of adder is a ripple carry adder.
– Each carry bit "ripples" to the next full adder.
• Ripple carry adders are slow for adding input with many bits.
– Since the carry may need to be propagated along the longest path from the LSB to
the MSB, the delay is proportional to the bit length to be added.
1 0 0 1 1 0 0 1
A3 A2 A1 A0 A3 B3 A2 B2 A1 B1 A0 B0

+ B3B2B1B0
S3 S2 S1 S0 A B CI A B CI A B CI A B CI

1010 MSB LSB

+0101
1111
22
 Arithmetic circuits: 4-bit ripple adder

B3 A3 B2 A2 B1 A1 Cin=0 B0 A0

8 6 4 2

7 5 3

Cout S3 S2 S1 S0
• Longest path has 8 gates delay 23
 Multiplexer
• A multiplexer (or MUX) is a device
that selects one of several analog or
digital input signals and forwards the
selected input into a single output line.
• A demultiplexer (or DEMUX) is a
0
device taking a single input signal and
selecting one of many data-output- 1

lines, which is connected to the single

input.

A B sel Z
0 × 0 0
1 × 0 1 𝑍𝑍 = 𝐴𝐴. 𝑠𝑠𝑠𝑠𝑠𝑠 + 𝐵𝐵. 𝑠𝑠𝑠𝑠𝑠𝑠
× 0 1 0
× 1 1 1

24
 Multiplexer

• A 2n-to-1 multiplexer consists of 2n

inputs and n select (address) inputs and
1 output.
• The select inputs determine which
inputs (D0, D1, D2, D3) to be channeled to
the output (e.g. A1A0=00 selects D0)
• Higher-level multiplexer can be
constructed using lower level
multiplexers
̶ E.g. a 4-1 multiplexer can be constructed
using three 2-1 multiplexers.
• Multiplexer can also be used to
implement boolean functions.

25
 Decoder and Encoder

• A decoder is used to convert

information from one number
system to another, whereas an
encoder provide the reverse function.

26
 Decoder and Encoder
• Priority encoders can be used to reduce the number of wires needed in a
particular circuits or application that have multiple inputs
• Some applications include keyboard encoder and positional encoder.

27
 Buffer and Tri-state logics
• Buffer: Buffers do not affect the logical state of a digital signal (i.e. a logic 1 input results in
a logic 1 output, whereas a logic 0 input results in a logic 0 output). Buffers are normally
used to provide extra current drive at the output but can also be used to regularise the logic
levels present at an interface.

A Z
A Z 0 0
1 1

 Tri-state: Tri-state logic devices operate in a similar manner to conventional logic gates
but has a third, high impedance output state. This high-impedance state (Hi-Z) permits
the output of several tri-state devices to be connected directly together.
A EN Z

A Z 0 0 Hi-Z
1 0 Hi-Z
0 1 1
EN 1 1 0
28
 Logical shifter
• A logical shifter is a bitwise operation that shifts all the bits of its operand.
• The two base variants are the logical left shift and the logical right shift.
• This is further modulated by the number of bit positions a given value shall be
shifted, such as shift left by n-bit or shift right by n-bit.
̶ Shift left by 1-bit will multiply the number by 2 (binary numbers are base-2 numbers)
̶ Shift right by 1-bit will divide the number by 2.
• Unlike an arithmetic shift, a logical shift does not preserve a number's sign bit;
every bit in the operand is simply moved a given number of bit positions, and the
vacant bit-positions are filled, usually with zeros.

2310 Before Before 2310

23×2 23÷2
4610 After After 1110

Shift left by 1-bit Shift right by 1-bit

https://en.wikipedia.org/wiki/Logical_shift 29
 Logical shifter
• Consider an input A3-0 = 0110 and Sh=0,
the output is X3-0 still 0110, this implies no shift occurs.
• An N-bit shifter would require log2N number of levels
X3 to implement.
• The number of multiplexers required for an N-bit word
is Nlog2N
X2 • Given a 4-bit input A3-0 and a 1-stage output X3-0, the
control input Sh will determine if a 1-bit shift-left
happens.

X1 • Consider an input A3-0 = 0110 and Sh=0, the output is

X3-0 still 0110, this implies no shift occurs.
• Consider an input A3-0 = 0110 and Sh=1, the output is
X3-0 becomes 1100, this implies the input has been
X0 shifted 1-bit to the left. Do note shifting 1-bit to the
left is the same as multiplying the number by 2 (i.e.
binary)
• Thinkering: How to modify the circuit to shift right
instead? 30
 Comparator: 1-bit
• When you try to compare two 1-bit numbers (A and B), you
potentially can derive 3 outputs (A>B, A=B, A<B), this can be easily
tabulated in a truth table below:
Inputs Outputs
B A A>B A=B A<B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
Z = A.B Y = A ⊕ B X = A.B

A X = A.B A< B
Y = A⊕ B A= B

B Z = A.B A> B
31
 Electronic Realization of Logic Circuits

• To implement digital logic circuits, transistors are used.

• To date, Complementary Metal Oxide Semiconductor (CMOS) technology are the
most commonly used.
• The best current microfabrication technology is about 5nm (nanometer); this
refers to the width of the gate of the transistor.
• Transistors are used to construct universal logic gates (i.e. NAND, NOR, NOT)
upon which other boolean functions can be built on.
• CMOS logic employs both n-channel and p-channel enhancement MOSFETS.
̶ PMOS serves as pull-up circuit.
̶ NMOS serves as pull-down circuit.

PMOS, Vi=0 to switch NMOS, Vi=1 to switch

on, Vi=1 to switch off on, Vi=0 to switch off 32
Electronic Realization of Logic Circuits

• Inverter • NAND • NOR

̶ One N-Type & one ̶ Two N-Type & two ̶ Two N-Type & two
P-Type (2 transistors) P-Type (4 transistors) P-Type (4 transistors)

• To implement other logic gates, a combination of these basic gates are

used.
̶ Hence, E.g. AND gate can be implemented using a NAND gate with an inverter gate
(6 transistors required for AND compared to 4 transistors for NAND).
̶ Complement gates (NAND, NOR) are preferred.
33
 High-level design and implementation

• FPGA: Field Programmable Gate Array

̶ A field-programmable gate array (FPGA) is an
integrated circuit designed to be configured by the
customer or designer after manufacturing—hence
"field-programmable".
̶ Main manufacturers: Xilinx, Altera, Acatel
• ASIC: Application Specific Integrated Circuit
̶ An application-specific integrated circuit (ASIC) is
an integrated circuit (IC) customized for a particular
use, rather than intended for general-purpose use.
̶ Main suppliers:
 Integrated device manufacturer (IDM) ASIC
suppliers: TSMC, SMIC, Global Foundries, etc
 Fabless ASIC suppliers: Broadcom, Delta, Nvidia

34
 Hardware Description Languages (HDL)

• As designs grew larger and more

complex, designers began using gate-level
models described in a Hardware
Description Language to help with
verification before fabrication.

• When designers began working on

100,000 gate designs, these gate-level
models were too low level for the initial
functional specification and early high
level design exploration.

• Designers again turned to HDLs for help

– abstract behavioral models written in an
HDL (Verilog or VHDL) provided both a
precise specification and a framework for
design exploration.

• This is similar to the software concept of

reusability by building libraries or IP
(remember the ARM Core story)
35
 Why study digital system design?
• Majority of digital designs today target FPGA.
• Increasing costs of custom ASICs means economies of scale
come in at much higher volumes.
̶ Non-recurring engineering (NRE) costs at 22nm are close to
$100m, just the mask set cost over $1m. Silicon wafer
̶ FPGAs have a higher per-unit cost, but for medium to low
volume this is still more economical.
• FPGAs are programmable, hence can be ‘soft’ upgraded.
• FPGAs are often described as a ‘sea of gates’.
• Many programmable logic blocks, each with look-up-tables Altera FPGA
(LUT) and flip-flops.
• Programmable routing for connecting blocks together.
• I/O (input-output) blocks for board-level connections.
• Recent devices include other primitives such as embedded
hardware multiplier and memories.
Internal block level view
36
Sequential Circuits

• Combinational circuits produce output based on input

variables only
• Sequential circuits produces output based on current input as
well previous output (memory elements):
̶ previous output are stored and fed back into the circuit on the
next clock cycle.
• Key component to sequential circuit are storage (memory)
elements
̶ e.g. latch, flip-flop
4017 Decade Counter
• Electronic flip-flop was invented in 1918 by William Eccles and IC Chip
Frank Jordan

74LS279A Quad SR Flip-flop

74LS279A Dual D-Latch 37
Sequential circuit as memory device
• In the context of latch and flip-flop, think of them as 1-bit memory.
• This 1-bit memory can store only one bit: binary 0 or 1. The content of the
memory is indicated on its output 𝑄𝑄and 𝑄𝑄� (invert of 𝑄𝑄).
𝑄𝑄 0 𝑄𝑄 1
0 1
𝑄𝑄� 1 𝑄𝑄� 0
• This 1-bit memory must also allow the content to be changed, otherwise it is
useless. The content can only be changed by manipulating the inputs (can be one
or more inputs)
S 𝑄𝑄 S 𝑄𝑄

0 1
R 𝑄𝑄� R 𝑄𝑄�
0/1 0/1
• The technical terms when referring to memory
̶ Current/present state (existing content known as Q or Q0) or
̶ Next/future state (new content known as Q+ or Qn+1) 38
SR-latch
• The SR (Set-Reset) latch can be constructed from NOR gates or NAND gates.
• Using NOR gates, SR latch reacts to active-HIGH (‘1’) inputs.
̶ i.e. its content (output) does not change when both inputs are low
• Using NAND gates, SR latch reacts to active-LOW (‘0’) inputs.
̶ i.e. its content (output) does not change when both inputs are high

R S
Q Q
S 𝑄𝑄

R 𝑄𝑄�
Q Q
S R

NOR Active-HIGH Latch NAND Active-LOW Latch

39
SR-latch
S R Output Q Comments Current state Next state
0 0 Q0 No change 0 S 𝑄𝑄 0 S 𝑄𝑄
1 0 1 SET 0/1 0/1
0 1 0 RESET 0 R 𝑄𝑄� 0 R 𝑄𝑄�

1 1 Undeterministic Not allowed S=0, R=0: No change

• With two inputs (S & R), there will be four

0 S 𝑄𝑄 0 S 𝑄𝑄
permutations.
• For SR devices, only 3 combinations (00,
0/1 0
01, 10) are permitted. The last 1 R 𝑄𝑄� 0 R 𝑄𝑄�
combination is not allowed.
S=0, R=1: Reset
• No change: Configuring S=0 and R=0 will
hold the existing value (remain the same
as previous state) 1 S 𝑄𝑄 0 S 𝑄𝑄

• SET: To change the content (next/future 0/1 1

state) to 1, configure S=1 and R=0. 0 R 𝑄𝑄� 0 R 𝑄𝑄�
• RESET: To change the content (next/future
S=1, R=0: Set
state) to 0, configure S=0 and R=1.
40
D-latch
• The D latch is a variation of the SR latch
but combines the S and R inputs into a
single D input as shown below. Inputs Outputs
Comments
• A simple rule for the D latch is: D EN Q Q
̶ Q follows D when the Enable is 0 1 0 1 RESET
active (EN=1). 1 1 1 0 SET
• The truth table for the D latch × 0 Q0 Q 0 No Change
summarizes its operation. If EN is LOW,
then there is no change in the output as
the content remain the same.

D 𝑄𝑄

EN 𝑄𝑄�

41
D flip-flop
• A flip-flop differs from a latch in the manner it changes states, i.e. latch
is level-sensitive whereas a flip-flop is edge-sensitive.
• The flip-flop is a synchronous device (as it synchronise with the clock) unlike a latch which
is asynchronous.
• In the logic symbol, the flip-flop has a triangle at the C input to indicates it is edge
sensitive. Moreover, a circle with the triangle indicates it is falling edge sensitive, while
the triangle without circle indicates it is rising edge sensitive.
̶ A flip-flop is a clocked device, i.e. only the clock edge determines when a new bit is stored into the flip-flop.
̶ Positive-edge triggered (PGT) D flip-flop => output follows D input only on the rising edge of the clock.
̶ Negative-edge triggered (NGT) D flip-flop => output follows D input only on the falling edge of the clock.

Clock input
D 𝑄𝑄 indicator D 𝑄𝑄

PGT CLK 𝑄𝑄� NGT CLK 𝑄𝑄�

Positive edge triggered Negative edge triggered or

or rising edge triggered falling edge triggered
42
D flip-flop
• Internally, a D flip-flop is Inputs Outputs
Comments
constructed using two D D CLK Q Q
latches and an inverter. 1 ↑ 1 0 SET
• For D flip-flop, to change the 0 ↑ 0 1 RESET
content is simple:
Positive-edge triggered
̶ SET (make content to 1):
set input D=1 and assert Master Slave
a rising edge clock.
D Q D Q
̶ RESET (make content to
0): clear D=0 and assert a
rising edge. CLK EN Q EN Q
• An easy way to remember is a
Inside a D-FF consists of TWO D-latch
D flip-flop will simply follows
the state of D input.
D 𝑄𝑄

CLK 𝑄𝑄� 43
D latch versus D flip-flop
• With D latch, engineer discovered this type of memory device is
not optimal since any noise at the input of the latch will be coupled to the
output as it is sensitive to the input (DL) for the entire period with EN=1 (i.e.
level sensitive)
• However, for the D flip-flop, as the content of the f/f is updated by sampling
the input (DFF) only at the rising edge of the clock (i.e. edge sensitive), any
noise that occur at the input will be ignored.

DL 𝑄𝑄 L
DL/DFF
EN 𝑄𝑄𝐿𝐿
EN/CLK

DFF 𝑄𝑄FF QL

CLK 𝑄𝑄𝐹𝐹𝐹𝐹 QFF

44
JK flip-flop

• Positive going edge triggered JK FF

J K CLK Qn+1
0 0 ↑ 𝑄𝑄𝑛𝑛 , No change
1 0 ↑ 1
0 1 ↑ 0
1 1 ↑ 𝑄𝑄𝑛𝑛 , Toggle

• Most flip flops also come with asynchronous inputs. These

inputs operates independent of the clock (hence
asynchronous as they are not synchronized to the clock).
• CLR or clear input will clear the output Q to 0 when CLR = 0.
• PR or preset input will set the output Q to 1 when PR = 0.

45
 Monostable (one-shot)
 Monostable or one-shot devices provide a means of generating precise
time delays.
 Such delays become important in many sequential logic applications where
logic states are not constant but subject to change of time.
 The action of a monostable is the output is initially 0 until a change of state
occurs at its trigger input.

46
 Propagation delay

• tPLH = propagation delay time, low-to-high output

• tPHL = propagation delay time, high-to-low output
• tPD = average propagation delay time
a
b
a
c c
b
(i) Ideal (zero) delay

a a
b b
c c

tPD tPD tPLH tPHL

(ii) tPD = tPLH = tPHL (iii) tPLH < tPHL

47
 Flip-flop timing characteristics

• Propagation delay time is specified for the rising and

falling outputs. It is measured between the 50% level of
the clock to the 50% level of the output transition.
• The typical propagation delay time for the 74AHC family
(CMOS) is 4 ns. Even faster logic is available for specialized
applications.

50% point on triggering edge

CLK CLK 50% point

Q 50% point on LOW-to- Q 50% point on HIGH-to-

HIGH transition of Q LOW transition of Q

tPLH tPHL

48
 Flip-flop timing characteristics

• Setup time and hold time are times required before and after
the clock transition that data D must be present to be reliably
clocked into the flip-flop.

• Setup time is the

D
minimum time for the
data to be present before CLK

the clock.
Set-up time, ts

D
• Hold time is the minimum
time for the data to CLK

remain after the clock.

Hold time, tH
https://www.youtube.com/watch?v=g8lRqQ-IfYw 49
Flip-flop applications: 1. Memory

• Flip-flop is used in digital

system for temporary data
storage (registers), as
frequency dividers, and
counters
• For data storage (e.g.
registers in CPU)
applications, a group of flip-
flops are connected to
parallel data lines and
clocked together. Data is
stored until the next clock
pulse.
50
Flip-flop applications: 2. Frequency divider

• Flip-flop can also be used for frequency division by

chaining a series of JK flip flops in toggle mode
̶ Each flip-flop down the chain will produce output with half the clock
frequency (base 2 system, hence divide by 2).
̶ The ability to generate clocks with different frequencies is important as
various sub-system within a computer operate at different frequencies
(e.g. Bluetooth, Wifi, CPU, USB)
̶ Can also be used to implement Ripple Counter.

QA

51
Flip-flop applications: 3. Control Unit/FSM
• Flip-flop are also used with combinatorial circuits to build
control unit or finite state machine (FSM)
̶ FSM is the backbone of the control unit (CU) inside a CPU.
̶ Other examples of FSM include counters. Refer to chapter 1, what are the 3
components inside a CPU?
3-bit odd/even counter example

Block diagram
Even count: A=0

Odd count: A=1

Output
FSM: Combinatorial
State diagram/machine block with D-FFs 52
 Computer Architecture and Communication

• With basic knowledge of how a CPU is constructed using combinatorial and

sequential circuits, we will now focus on the computer architecture and
communication
̶ In Chapter 1, we cover about Von Neumann Architecture where the CPU consists of ALU,
Registers and Control Unit, and they are interconnected with Memory and I/O.
̶ In Chapter 2, we discuss about different computers can communicate with each other either
serially or in parallel.

53
 Computer Architecture and Communication

• Figure below depict a data communication model where a source system send data to the
destination system via the transmission network.
• An example below shows a historic network relying on modem over the public telephone
network (up to 56Kbps). Current broadband using fiber optics can achieve up to 1Gbps.

54
 Inter-computer system buses
• A bus refers to a system that permits interconnections and data exchange between the
computers in a complex system. System buses (data, address and control) were discussed
in chapter 1, however they are used internally within a computer for short range
communications.
• In a largest computer network over longer range, the interconnections involved more than
just physical wiring; among other things it defines the voltage levels and rules (or
protocols) that govern the transfer of data.
• Bus systems can be either unidirectional (one-way) or bidirectional (two-way).
• Within the LRU (Line replaceable units), the
dedicated digital logic and microprocessor
systems that process data locally each make
use of their own local bus system
• Modern aircraft use multiple redundant bus
systems for exchanging data between the
various avionic systems and sub-systems.
These bus systems use serial data transfer
because it minimises the size and weight of
aircraft cabling.
55
 Bus Protocol and Architecture
• In computers and digital systems communication, protocols are established to
enable the efficient exchange of data between multiple devices connected to the
same bus.
• Bus architecture is a general term that refers to the overall structure of a
computer or other digital system that relies on a bus for its operation.

56
 Bus Protocol and Architecture
• Different bus systems which consist of both serial and parallel buses are used to
harness the advantages based on the system architecture.
• Details of these buses and protocol such as ARINC 429 and 629 will be covered in
the later chapters

57
 ISO-OSI model
• International Standard Organization (ISO) Open Systems Interconnection
(OSI) model is a product of the Open Systems Interconnection effort.
• It is a prescription of characterizing and standardizing the functions of a
communications system in terms of abstraction layers.
• Similar communication functions are grouped into logical layers.
• A layer serves the layer above it and is served by the layer below it.
• The concept of a seven-layer model was provided by the work of Charles
Bachman, Honeywell Information Services.
• Still an excellent model for
conceptualizing and understanding
protocol architectures, key points are:
̶ Modular
̶ Hierarchical
̶ Boundaries between layers =
Interfaces
58
 ISO-OSI model
OSI model
Data unit Layer Function
7. Application Network process to application
Data representation, encryption and decryption,
Data 6. Presentation convert machine dependent data to machine
Host independent data
layers Inter-host communication, managing sessions
5. Session between applications
End-to-end connections, reliability and flow
Segments 4. Transport control
Packets/
Datagram
3. Network Path determination and logical addressing
Media
layers Frame 2. Data Link Point-to-point and error detection
Bit 1. Physical Media, signal and binary transmission

59
 ISO-OSI model
Hello

60
 ISO-OSI Environment
Dictates or handwritten
7 the message Read message Application
Manager Manager

Company’s Business
Corrects format error, Alerts manage of
6 prepares final version incoming message,
translates it
Presentation
Assistant Assistant

Provides needed
5 addresses and packs
letter
Open letter and make
copy Session
Secretary Secretary

4 Drives letter to post

office
Withdraw letter from
mailbox or post office Transport
Driver Driver

Sort messages for

Takes over letters and
Network
3 puts it in correct
compartment
individual city
departments
Intake and Sorting and
sorting distribution

Postal services
2
Packs letters for Unpacks packages from
individual destination various directions Data Link
Packaging Unpacking

1 Physical
Transmission medium Unloading
Loading
OSI and letter communication parallel
61
 Transmission Mediums: Physical layer

• The basic building block of any communications

facility is the transmission line (i.e. physical layer).
Capacity
• The business manager is concerned with a facility
providing:
̶ required capacity (e.g. 1Gbps)
̶ acceptable reliability (error rate in decibels or dB)
̶ at minimum cost (how much $) Reliability

Cost

Transmission
Line
62
 Transmission Mediums
• Two mediums currently driving the evolution of data communications
transmission are fibre optics and wireless technologies.

5G

63
 Networking
• Advances in technology have led to greatly increased capacity and the concept
of integration, allowing equipment and networks to work simultaneously.
• There are many way to categorize networks:
̶ MAN: Metropolitan Area Networks
̶ WAN: Wide Area Networks
̶ LAN: Local Area Networks

Voice Data

Image Video

64
 Network Topology

Full connected topology Hybrid topology

(example: combination of Star
and Bus topology)

Bus topology
Tree topology

Dual Ring topology

Star topology

Linear topology

Mesh topology Nodes Branches

Ring topology
65
 Wide Area Networks (WANs)
• A wide area network (WAN) is a telecommunication network
that covers a broad area (i.e., any network that links across
metropolitan, regional, or national boundaries)
• Span a large
geographical area
• Require the crossing of
public right-of-ways
• Rely in part on common
carrier circuits
• Typically consist of a
number of
interconnected switching
nodes
66
 Metropolitan Area Networks (MAN)
• A metropolitan area network (MAN) is a computer network that usually
spans a city or a large campus.
• A MAN usually interconnects a number of local area networks (LANs) using
a high-capacity backbone technology, such as fiber-optical links, and
provides up-link services to wide area networks (or WAN) and the
Internet.
• Covers a geographic
area such as a town, city
or suburb
• Middle ground between
LAN and WAN
• Supports both data and
voice
• Private or public
network

67
 Local Area Networks (LAN)
• A local area network (LAN) is a computer network that interconnects computers in a
limited area such as a home, school, computer laboratory, or office building using
network media.
• The defining characteristics of LANs, in contrast to wide area networks (WANs), include
their usually higher data-transfer rates, smaller geographic area, and lack of a need for
leased telecommunication lines.
• ARCNET, Token Ring and other technology standards have been used in the past, but
Ethernet over twisted pair cabling, and Wi-Fi are the two most common technologies
currently used to build LANs.

• Smaller scope, typically a single building

• LANs are usually owned by the same
organization that owns attached devices
• Internal data rates greater than WANs
• Most common configurations are
switched LANs and wireless LANs

68
 The Internet and TCP/IP
• The Internet is a global system of interconnected computer networks that use the
standard Internet protocol suite (often called TCP/IP (transmission control
protocol/internet protocol), although not all applications use TCP) to serve billions of
users worldwide.
• It is a network of networks that consists of millions of private, public, academic,
business, and government networks, of local to global scope, that are linked by a
broad array of electronic, wireless and optical networking technologies.

69
 The Internet and TCP/IP
• The Internet carries an extensive range of information
resources and services, such as the inter-linked
hypertext documents of the World Wide Web (WWW)
and the infrastructure to support email.
• Internet evolved from ARPANET (Advanced Research
Projects Agency Network).
• ARPANET was the world's first operational packet
switching network and the core network of a set that
came to compose the global Internet.
• The packet switching of the ARPANET was based on
designs by Lawrence Roberts of the Lincoln
Laboratory.
• 2.5 EB (Exa bytes or 260) of data produced every day
• 90% of the data in the world generated over the last 2
years.
• The explosion of data give rise to areas in data science,
machine learning and artificial intelligence (AI)

70
 Summary

• Basic logic circuits

̶ Logic circuit, Truth-table, Boolean equation, timing diagrams
• Combinatorial circuits
̶ Adder, multiplexer, shifter, decoder/encoder, comparator
 Sequential circuits
̶ SR latch, D and JK flip-flops, register, counters
• Transistor-level implementation of logic circuit, digital circuit design using
HDL
• Computer Architecture and Communication
• Data buses and protocol
• OSI, transmission medium, networking and network topology
 Self-test quiz
A
 1. The symbol B X is for a(n)
 (a) OR gate

 (b) AND gate

 (c) NOR gate

 (d) XNOR gate

 2. A logic gate that produces a HIGH output only when all of its inputs are
HIGH is a(n)
 (a) OR gate

 (b) AND gate

 (c) NOR gate

 (d) NAND gate

72
 Self-test quiz

 3. The expression X = A ⊕ B means

 (a) A OR B

 (b) A AND B

 (c) A XOR B

 (d) A XNOR B

 4. A 2-input gate produces the output shown. (X represents the output.)

This is a(n)
 (a) OR gate A

 (b) AND gate B

 (c) NOR gate
X
 (d) NAND gate
73
 Self-test quiz

 5. Assume an SOP expression is AB + CD. The equivalent POS expression

is
 (a) (A+B)(C+D)

 (b) (𝐴𝐴 + 𝐵𝐵)(𝐶𝐶 + 𝐷𝐷)

 (c) (𝐴𝐴 + 𝐵𝐵 )(𝐶𝐶 + 𝐷𝐷)

 (d) none of the above

 6. The truth table shown is for Inputs Output

A B X
 (a) a NAND gate
0 0 1
 (b) a NOR gate
0 1 0
 (c) an XOR gate 1 0 0
 (d) an XNOR gate 1 1 1
74
 Self-test quiz
 7. What type of output gate is needed to implement the logic expression
shown? X = ABC + A BD + B DE
 (a) 3-input AND gate

 (b) 3-input NAND gate

 (c) 3-input OR gate

 (d) 3-input NOR gate

 8. The circuit shown will have identical logic outputs if all gates are
changed to
 (a) AND gates

 (b) OR gates

 (c) NAND gates

 (d) NOR gates 75

 Self-test quiz
 9. The circuit shown is equivalent to a ___________ logic gate?

 10. Sketch the output signal for the AND gate G3.
A
A
G1
B B
G3
C C G2
D D

G3

76
 Self-test quiz

 11. For the full-adder shown, assume the input bits are as shown with A =
0, B = 0, Cin = 1. The Sum and Cout will be
 (a) Sum = 0 Cout = 0

 (b) Sum = 0 Cout = 1

 (c) Sum = 1 Cout = 0

 (d) Sum = 1 Cout = 1

 12. The output will be LOW if

 (a) A < B

 (b) A > B

 (c) both (a) and (b)

 (d) A = B
77
 Self-test quiz

 13. The decimal-to-binary encoder shown does not have a zero input. This
is because
 (a) when zero is the input, all lines
should be LOW

 (b) zero is not important

 (c) zero will produce illegal logic level

 (d) another encoder is used for zero

 14. If the data select lines of the MUX are S1S0 = 11, the output will be
 (a) LOW

 (b) HIGH

 (c) equal to D0

 (d) equal to D3
78
 Self-test quiz

 15. The output of a D latch will not change if

 (a) the output is LOW

 (b) Enable is not active

 (c) D is LOW

 (d) all of the above

 16. The D flip-flop shown will ______

on the next clock pulse
D Q
 (a) set
CLK CLK
 (b) reset
Q
 (c) latch

 (d) toggle 79
 Self-test quiz

 17. The time interval illustrated is called

 (a) tPHL

 (b) tPLH

 (c) setup time

 (d) hold time

 18. Why is serial communication more frequently used for aircraft

communication
 (a) Due to the size and weight

 (b) Due to the communication speed

 (c) As it can support bidirectional communication as opposite to unidirectional

communication

 (d) As it supports the ISO-OSI model 80

 Self-test quiz
 19. How many asynchronous
inputs does the J-K flip-flop
below have?
__________

 20. Assume the output from a leading-edge triggered J-K flip flop is
initially HIGH. With the inputs shown, indicate in the timing diagram
when will the output goes from HIGH to LOW?

81