Manual KN53 Pago

KIN G.
KN53
NAVIGATION
RECEIVER
INSTALLATION
MANUAL
006-0174-01
REVISION 1 JULY, 1981

Manufactured By
KIN G
PRINTING DIVISION
KING
KN 53
NAVIGATION RECEIVER
TABLE
OFCONTENTS
SECTION
I
INFORMATIOlli
GENERAL
Paragraph Page
1.1 Introduction 1-1

1.2 Equipment Description 1-1
1.3 Technical Characteristics 1-1
1.3.1 KN 53 General Information 1-1
1.3.2 VOR/LOC Characteristics 1-2
1.3.3 GLidestope Characteristics 1-2
1.4 Units and Accessories 1-3
1.5 Accessories Required but not Supplied 1-4

1.6 License Requirements 1-4
1.7 Requirements for TSO'd VOR/ILS Glidestope Systems 1-4
1.7.1 Glidestope Indicator Requirements 1-4
1.7.2 Localizer Converter and Indicator Requirements 1-4
1.7.3 VOR Converter and Indicator Requirements 1-5
1.7.4 King TSO'd Systems 1-6
SECTION
II
INSTALLATION
Paragraph Page
2.1 Generat Information 2-1

2.2 Unpacking and Inspecting Equipment 2-1
2.3 Equipment Installation 2-1
2.3.1 Avionics Cooting for Panet Mounted Equipment 2-1
2.3.2 KN 53 Installation 2-1
2.3.3 Molex Connector Asembly 2-2
2.3.4 NAV and Glidestope Antenna Installation 2-2
2.4 Post Installation Adjustments 2-3
SECTION
III
OPERATION
3.1 Generat 3-1
3.2 Post-Instattation Checkout 3-1
LISTOF ILLUSTRATIONS
Figure Page
2-1 Molex Information (3 Sheets) 2-5

2-2 030-0005-00 Connector Assembly 2-8
2-3 Antenna Connector 2-9
2-4 Outline and Mounting Drawing 2-11
2-5 KN 53 Installation Drawing 2-13
2-6 KN 53 Instatt Kit with Optional Diplexer Unit 2-15
2-7 KN 53 to KI 203/KI 204 Interconnect Diagram 2-17
2-8 KN 53 to KN 72/KI 206 or KNI 520 Interconnect 2-19
2-9 KN 53 to KN 72/KI 525 or KI 525A Interconnect 2-21
2-10 KN 53 to KI 208/KI 209 Interconnect 2-23
3-1 KN 53 Control Functions 3-2

i
Rev. 1, July 1981
IMOO20-6
KN 53
NAVIGATION RECEIVER
MANUAL: KN 53 --
KPN 006-0174-01
REVISION: Revision 1, July 1981
PAG_E REASON FOR CHANGE
COVER UPDATED
HISTORY REVISION ADD
TABLE OF CONTENTS UPDATED
SECTION I UPDATED
2-1 ADDED D.
2-2 ADDED NOTE
2-3 FORMATCHANGED
2-5 REV. O TO REV. 1
2-6 PAGE NO. CHANGE
2-7 PAGE NO. CHANGE
2-8 PAGE NO. CHANGE
2-9 FROM REV. O TO REV. 4
2-11 FROMREV. 1 TO REV. 3
2-13 PAGE NO. CHANGE
2-15 FROMREV. O TO REV. 1
2-19 FROMREV. O TO REV. 1
3-1 FORMATCHANGE
3-2 FORMATCHANGE
KING
KN 53
NAVIGATION RECEIVER
SECTICIN
I
INFORMATION
GENERAL
1.1 INTRODUCTION
This manual contains information relative to the physicat, mechanical, and electrical characteristics and
instattation procedures of the King Radio Corporation Silver Crown KN 53 Navigation Receiver.
1.2 EQUIPMENT
DESCRIPTION
The King KN 53 is a TSO'd panet mounted 200 channet VHF VOR/LOC Receiver with a 40 channet GLidestope
Receiver/Converter option. The NAV receiver supplies VOR/LOC information to navigation converters and
provides two out of five frequency selection for remote mounted Distance Measuring Equipment.
1.3 CHARACTERISTICS
TECHNICAL
Minimum performance requirements under standard conditions (ambient room temperature and humidity):
1.3.1 KN 53 GENERAL INFORMATION
SPECIFICATION CHARÁCTERISTIC
TSO CATEGORIES: NAV C40a DO-153

LOC C36c, class D, Cat II 00-131
G/S C34c, class D, Cat II DO-132
ENVIRONMENTALCATEGORIES: DO-160 /A1D1/A/PS/XXXXXXABABA
PHYSICAL DIMENSIONS: Width: 6.31 inches (16.0 cm)

Height: 1.30 inches ( 3.30 cm)
Depth: 9.50 inches (24.13 cm)
WEIGHT:
With G/S 2.6 Lbs (1.18 Kg)
Without G/S 2.3 Lbs (1.04 Kg)
With G/S, Rack and Conn. 3.0 lbs (1,36 Kg)
Without G/S, with Rack and Conn. 2.7 Lbs (1.23 Kg)
POWER REQUIREMENTS: 11 to 33VDC input

With G/S 9 13.75VDC .975 AMP
With G/S @ 27.5VDC .25 AMP
Without G/S 9 13.75VDC .75 AMP
Without G/S 9 27.5VDC .20 AMP
DME CHANNELING: 5 wire 2 x 5 code MHz Lines

5 wire 2 x 5 code KHz Lines
1 wire 50KHz Line
1 DME common Line
ILS ENABLE OUTPUT: Ground on ILS channets, open otherwise
Rev. 1, July 1981 Page 1-1

IMOO20-7
KING
KN 53
NAVIGATION RECEIVER
1.3.2 VOR/LOC CHARACTERISTICS (KPN 066-1067-00/01)
SPECIFICATION CHARACTERISTIC
FREQUENCYDISPLAY: Gas discharge display of one active and one

stored frequency. The stored frequency is
updated by the increment/decrement switch.
The transfer button trades the active
frequency with the stored frequency.
FREQUENCYMEMORY: Frequency data stored with no standby power

required.
FREQUENCYSTABILITY: + 0.0015%
SENSITIVITY: 2.0uV (hard) max. will provide a half-flag

navigation indication. Typical 1.0uV (hard).
SELECTIVITY: Typicat 6de at +17KHz, 80dB at +42KHz
SPURIOUS RESPONSES: Down at least 60dB
IDENT FILTERS: 15dB minimum tone rejection
AGC CHARACTERISTICS: From 5uV to 20,000uV (hard) audio output will

not vary more than 3dB. AGC active from half
flag to +6dBm (hard).
+1.5°
NAV RECEIVER ACCURACY: maximum error/95% probability
NAV OUTPUT: Adjustable O.35VRMS Loc, 0.5VRMS VOR output

into 20,000 ohms or greater
AUDIO QUTPUT: 50mw a 500 ohms
NUMBEROF CHANNELS: 200 (50KHz spacing)
FREQUENCYRANGE: 108.00MHz to 117.95MHz
1.3.3 GLIDESLOPE CHARACTERISTICS (KPN 066-1067-00 onty)
NUMBEROF CHANNELS: 40 (150KHz spacing)
FREQUENCYRANGE: 329.15MHz to 335.00MHz
SELECTIVITY: 6dB max at +21KHz, 508 min. at +129KHz
SENSITIVITY: Typicatty 12uV (hard) for half flag 2Ouv

<hard) maximum
INDICATOR OUTPUT: No Load resistors or wiring changes are

necessary for any combination of deviation or
alarm flag Loads.
Deviation: Three 1000 ohm Loads max
Flag: Three 1000 ohm Loads max
COURSE DEVIATION RESPONSE: 0.6 seconds maximum
Rev. 1, July 1981

IMOO20-7 Page 1-2
KING
KN 53
NAVIGATION RECEIVER
CENTERING ACCURACY: Less than +10uA under aLL service conditions
DEFLECTION CHARACTERISTICS: A difference in depth of modulation of

0.091ddm or 2dB tone ratio shall produce a
deflection of +78uA (+3uA typical).
1.4 UNITSANDACCESSORIES
A. King KN 53 with Glidestope (KPN 066-1067-00)
B. King KN 53 without Glidestope (KPN 066-1067-01)
C. King KN 53 Installation Kit (KPN 050-1712-00) consists of:
PART NUMBER DESCRIPTION QUANTITY

CODE -00
030-1107-30 CONN PINS (30) 1

(5-7 SPARES)
057-2193-03 DECAL, NAV 1 1

057-2193-04 DECAL, NAV 2 1
089-2353-01 CLIP NUTS 6-32 4

089-5903-07 SCR PHP 4-40X7/16 2
089-6012-08 SCR FHP 6-32X1/2 4
089-8003-34 WASHERSPLT LK #4 2
089-8252-30 WASHER 4
090-0019-07 RETAINING RING 2
030-0101-02 CONN ANT 2

030-1094-53 CONNMOLEX (30PIN) 1
030-0101-02 CONN ANT -
D. KA 139 Diplexer (071-1185-00, Optional Accessories)
1. This dipLexer may be used with 066-1067-00. This permits the glidestope receiver to use
the aircraft's navigation antenna.
2. The KA 139 Diplexer should be connected directly to the NAV antenna. Do not connect the
KA 139 to the output of another NAV splitter. Some NAV splitters which are intended to
drive two VOR/LOC NAV Receivers have a significant amount of insertion Loss when used to
drive a GLidestope Receiver. If a NAV antenna is used in common with two VOR/LOC NAV
Receivers, the KA 139 is not recommended.
3. The two antenna connectors, 030-0101-02, furnished in the instalLation kit, 050-1712-00,
witL be spares when this diplexer is used.
Rev. 1, JuLy 1981

IMOO20-7
Page 1-3
KING
KN 53
NAVIGATION RECEIVER
1.5 ACCESSORIESREQUIRED,BUTNOTSUPPLIED
A. Navigation Antenna and Cables
B. GLidestope Antenna and Cables

KA 22 (KPN 071-1008-00) or equivalent
C. 300 to 1000 ohm Headphones
D. VOR/LOC Converter and Indicator, GLidestope Indicator.

Various King Options include:
1. KN 53 (066-1067-01), KI 203 VOR/LOC Converter with VOR/LOC Indicator
2. KN 53 (066-1067-00), KI 204 VOR/LOC Converter with VOR/LOC/GS Indicator
3. KN 53 (066-1067-00), KN 72 VOR/LOC Converter, KI 206 VOR/LOC/GS Indicator
4. KN 53 (066-1067-00), KN 72 VOR/LOC Converter, KI 525A Pictorial Navigation Indicator
5. KN 53 (066-1067-00), KI 209 VORILOC Converter with VOR/LOC/GS Indicator
6. KN 53 (066-1067-01), KI 208 VORILOC Converter and Indicator
1.6 LICENSEREQUIREMENTS
No special federal communications License is required to operate the KN 53.
1.7 REQUIREMENTS
FORTSO'OYOR/ILSGLIDESLOPE
SYSTEM
The additional units used in conjunction with the KN 53 must meet the specifications Listed below to
comprise a completely TSO'd navigation system.
1.7.1 GLIDESLOPE INDICATOR REQUIREMENTS
A. The indicator shalt meet all applicable requirements of TSO C34c.
B. Centering current to be 0 + 6uA with a 95% probability under att environmental conditions
listed in RTCA Paper DO-132, Minimum Performance Standards--Airborne ILS Glidestope Receiving
Equipment, Paragraph 2.1 sub-paragraph b, Centering Accuracy.
C. The course deviation pointer shalt visibly deflect at least +_ 5/8 inch along its scate when
the input current is changed from zero to + 150uA.
D. Deflection Linearity over the deflection range from zero to 150uA shalt be within 10% of being
proportionat tothe input current. Additionally, as the current is increased beyond that
producing fuLL scale deflection to a value of + 685.7uA, the indicator deflection shall not
decrease.
E. When the input current is abruptly changed from any vaLue from zero to +_ 150uA, the pointer
shaLL reach 67% of its ultimate defLection within 2 seconds and pointer overshoot shatt not
exceed 5%.
F. The input impedance shall be 1Kohms +_ 5% for both the deviation indicator and warning signat.
G. A warning signal input current of 150uA or Less shalt produce a fuLLy visible warning flag. A
warning signat input current of 260uA or greater shalt produce a futty concealed warning flag.
1.7.2 LOCALIZER CONVERTERAND INDICATOR REQUIREMENTS
A. The converter and indicator shaLL meet att appticable requirements of C36c.
B. The Localizer centering current to be O +_ 6uA with a 95% probability under aLL environmental
conditions listed in RTCA Paper DO-131, Minimum Performance Standards--Airborne ILS Localizer
Receiving Equipment, Paragraph 2.1 sub-paragraph b, Centering Accuracy.
C. The course deviation pointer shaLL visibly deflect at least + 3/8 inch along its seate when
the input current is changed from zero to + 90uA.
Rev. 1, July 1981

IMOO20-7 Page 1-4
XING
KN 53
NAVIGATi0N RECEÌVER
D. Deflection Linearity over the range from zero to |_ 90uA shall be within 10% of being
proportional to the difference in depth of modulation of the 90 and 150Hz signals, or the
deflection shall be within 5% of standard deflection (g 90uA) of being proportional to the
differenco in depth of modulation, Whichever is greater. Additiönally, as the difference in
depth of modulation is increased beyond that producing futt scale deflection it 150uA) to a
value of 0.5ddm, the course deviation pointer deflection shalt not decrease.
E. When the input current is abruptly changed from zero to 150uA, the pointer shall reach 67%
of its ultimate deflection within 2 seconds and pointer overshoot shalt not exceed 5%.
F. The input impedance of the indicator for both the deviation indicator and warning signat shall
be 1K + 5%.
G. A warning signat input current of 125uA or Less shalt produce a futtÿ visible warning flag. A
warning signat input current of 260uA or greater shall produce a fuity concealed warning flag.
1.7.3 VOR CONVERTERAND INDICATOR REQUIREMENTS
A. The converter and indicator shall meet att applicable requirements of TSO C40a.
3o
B. The bearing error shall be Less than with a 95% probability under att environmental
conditions Listed in RTCA Paper DO-153, Minimum Performance Standards--Airborne VOR Receiving
Equipment, Paragraph 2.1, sub-paragraph 2.1.2, Bearing Accuracy.
NOTE
2.7o
FOR OLDER EQUIPMENT THE BEARING ERROR SHALL BE LESS WITH THAN
A 95% PROBABILITY UNDER ALL ENVIORNMENTALCONDITIONS LISTED IN
RTCA PAPER DO-114, MINIMUMPERFORMANCESTANDARDS--AIRBORNE VOR
RECEIVING EQUIPMENT, PARAGRAPH 2.1, SUB-PARAGRAPH B, BEARING
ACCURACY.
C. The course deviation pointer shalt visibly deflect at least 1/2 inch (for DO-153) or 3/8 inch
(for DO-115) along its scate when the input current is changed from zero to 150uA.
D. Deflection Linearity
The deflection shall be proportional to the change in phase between the two components of the
10° (+
standard VOR test signal, within 20% of the deflection produced by a 150uA) change in
phase. This reguirement shalt be met at att deflections produced when the phase difference is
-10o
varied from +10 to of that producing an "on course" indication. The pointer deflection
shall not decrease as the phase difference is increased from that producing an "on course"
indication to that producing an indication which is equivatent to + 80 from "on course".
E. Deflection Response
When the difference in phase between the two components of an "on course" standard VOR test
signal is abruptly changed, the pointer shall reach 70% of its ultimate position within 3
seconds and the pointer overshoot shalt not exceed 20%.
F. The input impedance of the indicator for both the bearing error and warning signat shall be 1K
5%.
G. A warning signat input current of 125uA or Less shalt produce a futty visible warning flag. A
warning signat input current of 266uA or greater shalt produce a futty concealed warning flag.
H. The input impedance of the TO/FROM indicator shalt be 200 ohms 200uA sensitivity.
Rev. 1, July 1981

IMDD20-7 Page 1-5
KING
KN 53
NAVIGATION RECEIVER
1.7.4 KING TS0'D SYSTEMS
A. The fottowing systems when used in conjunction with the KN 53, KPN 064-1067-00 (with or
without the KA 139 diplexer accessory) witL meet all, TSO system requirements.
1. KI 204
2. KN 72, KI 206
3. KN 72, KI 525A
4. KI 209
B. The fottowing systems when used in conjunction with the KN 53, KPN 066-1067-01, will meet all
TSO system requirements.
1. KI 203
2. KI 208
Rev.1, July 1981

IMOO20-7 Page 1-6
KING
KN 53
NAVIGATION RECEIVER
SECTION
ll
INSTALLATION
2.1 GENERAL
INFORhiãTION
This section contains information relative to the instattation and wiring of the KN 53. A close adherence
to methods and procedures discussed herein is required.
2.2 UNPACKING
ANOINSPECTINGEQUIPMENT
Exercise extreme care when unpacking the equipment. Make a visuat inspection of the unit for evidence of
damage incurred during shipment. If a claim for damage is to be made, save the shipping container to
substantiate the claim. The claim should be promptly fited with the transportation company. It would be
advisable to retain the container and packaging material after att equipment has been removed in the
event that equipment storage or reshipment should become necessary.
2.3 INSTALLATION
EQUIPMENT
2.3.1 Avionics Cooting Requirements For Panet Mounted Equipment
The greatest single contributor to increased reliability of att modern day avionics is to Limit the
maximum operating temperature of the individual units. White modern day individual circuit designs
consume much Less electrical energy, the watts per cubic inch dissipated within avionics units remains
much the same due to high density packaging techniques utilized. Consequently, the importance of
providing avionics stack cooLing is still with us.
White an individual unit may not require forced air cooling, the combined heat Load of severat units
operating in a typicaL avionics stack witL significantly degrade the reLibility of the avionics if
provisions for stack cooling are not incorporated in the initial instattation. Recommendations on stack
cooling are contained in King Radio Instattation Buttetin #55. Faiture to provide stack cooling will
certainly Lead to increased avionics maintenance costs and may void the King warranty.
2.3.2 KN 53 INSTALLATION (Figures 2-1 through 2-9)
A. Plan a Location on the aircraft panet that is clearly visible and within easy access of the
pilot.
B. Avoid mounting the KN 53 cLose to heater vents or other high heat sources.
C. Compass safe distance is 8 inches for worst case defLection of one degree.
D. When instatting two or more panet mounted units in a stack, the mounting trays shalt be spaced
.050 inches (.127 cm) apart. Newer style mounting trays have had inch (.063cm) dimples .025
built in, top and bottom, both sides, so that two new styLe trays witL automaticatty be spaced
property.
E. Instatt the mounting rack in the aircraft using 6-32 x 1/2 flat head phittips screws (KPN
089-6012-08) and 6-32 clip nuts (KPN 089-2353-01). The screws are inserted from the inside
through the hotes in the sides of the mounting rack.
F. Connect the harness wires to the connector pins and insert the connector pins into the rear of
the Molex connector. See Section 2.3.2 and Figure 2-1.
G. Mount the Molex connector in the two holes at the rear of the mounting rack. Use two 4-40 x
7/16 pan head, phittips screws (KPN 089-5903-07) and two #4 split Lock washers (KPN
089-8003-34). Orient the connector so the polarizer key is shown in Figure 2-4.
H. Connect the antenna cables to the antenna connectors (Figure 2-2).
I. Insert the antenna connector through the hole in the rear of the mounting rack from the
outside. Secure with a spacer (KPN 089-8252-30) and retaining ring (KPN 090-0019-07)
instatted from the inside of the rack.
J. Instatt the KN 53 into the mounting rack and secure by turning the hold down adjustment screw
(accessible through a hole in the front panet) clockwise with an atten hex wrench until it is
Locked into place (Figure 2-4).
Rev. 1, July 1981
IMOO20-8 Page 2-1
KING
KN 53
NAVIGATION RECEIVER.
2.3.3 MOLEX CONNECTORASSEMBLY (Figure 2-1)
A. Soldertess Contact Terminal Assembly using Molex Crimper
Refer to instructions in Figure 2-1.
B. Soldertess Contact Terminal Assembly using Pliers
1. Strip each wire 5/32" for contact terminal (KPN 030-1107-30). (The Last two digits of the
contact terminal part number indicate the number of terminats furnished).
2. Tin the exposed conductor.
3. Using needte nose pliers, fold over each conductor tab in turn, onto the exposed
conductor. When both tabs have been folded, firmly press the tabs against the conduct.
4. Repeat Step 3 for insulator tabs.
5. Apply a smalt amount of solder (using minimum heat) to the conductor/tab connection to
assure a good electromechanical joint.
C. Contact Insertion into Molex Connector Housing
1. After the contact terminals have been installed on the wiring harness, the contact
terminals can be inserted into the proper location in the connector housing (KPN
030-1094-53). The terminal cannot be inserted upside down. Be sure to push the terminal
att the way in, until a click can be felt or heard.
2. The self-tocking feature can be tested by gently putting on the wire.
D. Extraction of Contact from Molex Connector
1. Slip the flat narrow blade of a Molex contact ejector tool, HT-1884 (KPN 047-5099-01),
under the contact on the mating side of the connector. By turning the connector upside
down one can see the blade slide into the stop.
2. When the ejetor is sLid into place, the Locking key of the contact is raised, allowing the
contact to be removed by putting moderately on the Lead.
3. Neither the contact or position is damaged by removing a contact; however, the contact
should be checked visually before reinstatting in connector, to be certain that retaining
tab "A" extends as shown (See Figure 2-1) for retention in connector.
2.3.4 NAV AND GLIDESLOPE ANTENNAINSTALLATION
A. Antenna should be instatted as per Advisory circular 43.13-2 Methods and Guidelines.
B. When applicable, the KA 139 diplexer may be used; so that the glidestope receiver will use the
NAV antenna.
The KA 139 diplexer should be connected directly to the NAV antenna. Do not connect the KA
139 to the output of another NAV splitter. Some NAV splitters which are intended to drive 2
VOR/LOC NAV Receivers have a significant amount of insertion toss when used to drive a
Glidestope Receiver. If a NAV antenna is used in common with two VOR/LOC NAV Receiver, the KA
139 is to recommended.
Rev. 1, July 1981

IMOO20-8 Page 2-2
KING
KN 53
NAVI6ATION RECEIVER
2.4 POST-INSTALLATION
ADJUSTMENTS
The KN 53 has been calibrated to operate with the standard King systems noted in Section I. Adjustments
are accessible through the top and bottom covers to fine tune the navigation system if required. The
physical Location of the adjustments are noted in Figure 2-4 and their electrical functions are explained
in Sections IV and VI of the KN 53 Maintenance Manual (KPN 006-5168-00). When adjustments are required,
the self-stick covers should be replaced.
A. Composite Levet set, R368, has been preset at the factory for standard 0.35RMS LOC, 0.50RMS
VOR output.
B. Display dimmer, R546, has been preset to the King standard. R546 may be adjusted to Light
balance the aircraft panet.
C. Glidestope adjustments (KPN 066-1067-00 only)
1. Glidestope course width, R425.

2. Glidestope centering, R626.
3. 6tidestope flag, R636.
Rev. 1, July 1981

IMOO20-8
Page 2-3
KING
KN 53
NAVIGATION RECEIVER
INSULATOR CRIMP
CONDUCTOR CRIMP
SOLDERLESSCONTACTTERMINAL
KPN 030-1107-30
TAB A
HAND EJECTOR
KPN 047-5099-00/01
MOLEX PN HT-1884
FIGURE 2-1 MOLEX INFORMATION

(Dwg. No. 696-6333-00, R-1)
(Sheet 1 of 3)
Rev. 1, July 1981

IMOO20-8 Page 2-5
KING
KN 53
NAVIGATIONRECEIVER
Holding the hand crimpers as shown, release the crimper's ratchet pawl and open by squeezing tightly
on the handles, and then releasing pressure.
HAND CRIMPER
71 /8NO
NLOX 461 10
-
50
0 E 1
Close crimpers until ratchet begins to engage. Then insert the terminal into the jaws from the back
side. (See Figures at bottom of page) For 24 to 30AWGwire, it will be necessary to start the crimp
in jaw A and then complete it in jaw B.
JAW TERMINAL WIRE SIZE INSULATIONRANGE
A 030-1107-30 18 to 24 AWG .110 to .055
8 030-1107-30 24 to 30AWG .055 to .030
WIRE STOP INSilLATION TABS-
TERMINAL
Terminal is in correct position when insulation tabs are flush with outside face of crimp jaws.

{Dwg. No. 696-6333-00, R-1)
(Sheet 2 of 3)
Rev. 1, July 1981

IMOO20-8 Page 2-6
KING
KN 53
NAVIGATION RECEIVER
Once the terminal is in the correct position, close the jaws gently until the terminal is held loose
in place. Push wire stop down so that it rests snugly behind the contact portion of the terminal.
Strip the wire insulation back 1/8 inch and insert the wire through the insulation tabs into the
conductor tabs until the irisulation hits the conductor jaw face or until the conductor touches the
wire stop.
WIRE STOP
CONDUCTOR JAWS
CONDUCTOR JAW FACE

Squeeze the handles until the crimp jaws close and the ratchet releases.
Straighten the terminal if necessary, then release the plier grips and remove the crimped terminal.
CRIMPINGPRESSUREADJUSTMENT
If too much or too little pressure is needed to release the crimper's ratchet pawl at the end of
the crimp stroke, the ratchet can be easily adjusted. A spanner wrench provided with the tool can
be used to loosen the lock nut, and rotate the keyed stud clockwise for increased pressure and
counter-clockwise for decreased pressure. Once the desired pressure has been set, the lock nut
must be tightened again. Newer models may have screwdriver adjustment.
KEYED
PA NCH
LOCK NUT
(OPPOSITE SIDE)

(Dwg. No. 696-6333-00, R-1)
(Sheet 3 of 3)
Rev. 1, July 1981

IMOO20-8 Page 2-7
KING
KN 53
NAVIGATION RECEIVER
TRIM OUTER JACKET TO DIMENSION

SHOWN.
COMB OUT BRAID AND TRIM DIELEC-

TRIC TO DIMENSION SHOWN.
TAPER BRAID OVER DIELECTRIC AND

SLIP CABLE NUT WASHER(WHENFUR-
2 NISHED) AND V-GROOVE GASKET

OVER CABLE. POSITION BRAID CLAMP
WITH SHOULDER TIGHT AGAINST OUT-
1. ER JACKET. FOLD BRAID BACK OVER
32
BRAID CLAMP
3
TRIM OFF EXCESS BRAID. POSIT-
lON WASHER AND GASKET AS SHOWN
; y
-
AND SOLDER PlN TO CENTER CON-
DUCTOR. PLACE INSULATOR OVER
PIN, (fF FURNISHED).
INSERT CABLE AND HARDWARE INTO

CONNECTOR MOUSING AND T1GHTEN
CABLE NUT.
FIGURE 2-2 030-0005-00 CONNECTORASSEMBLY

(Dwg. No. 155-5267-00, R-0)
IMOO20-8 Page 2-8

KING
KN 53
NAVIGATION RECEIVER
DIPLEXER UNIT KAI39 (OPTIONAL)

200- 2390 -00
¾ THESE ITEMS ARE PART OF OTI-IIB5-OO, KA139 DIPLEXER.

NOTE:1. THE TWO 030-0101-02 CONNECTORS SUPPLIED IN THE KN53
INSTALLATIONKIT, 050-1712-00, ARE SPARES WHEN THE
KAl39 DIPLEXER IS USED.
2. THE KAl39 DIPLEXER SHOULD SE CONNECTED DIRECTLY TO THE NAV ANTENNA.
DO NOT CONNECT THE KA139 TO THE OUTPUT OF ANOTHER NAV SPLITTER.
SOME NAV SPIJTTERS WHICH ARE INTENDED TO DRlVE TWO VOR/LOC NAV RECEIVERS,
HAVE A SIGNIFICANT AMOUNT OF INSERTION LOSS WHEN USED TO DRIVE A GL1DESLOPE
RECEIVER.IFA NAV ANTENNA IS USED IN COMMON WITH TWO VOR/LOC NAV RECEIVERS,
THE KAI39 IS NOT RECOMMENDED.
FIGURE 2-6 KN 53 INSTALLATION KIT WITH OPTIONAL DIPLEXER UNIT

(Dwg. No. 155-5314-00, R-1)
Rev. 1, July 1981

2-o
IMOO20-8 Page
KING
KN 53
NAVIGATION RECEIVER
030-1094-53 P/OO30-lO94-53
P621
P532
D MA 12
H MB NC
5 MC 9 K o
11 MD 8 N P
F ME 11
6 K? 7
M KB NC
O
10 KO 4
L I'O D N
6
J KE H
C5 L I
N M W CCI.II.lCll E
L_ ______J
P/O 030-2272-00
K P2o3;e2o4
N 12 ILS ENABLE
RGl88
5 B COMPOSITE Y
15 COMPOSITECOMMON K I
' ' I N
2 500 OHMAUDIO OUT
S AUDIO COMMON
R (SEENOTE I SEE NOTE 2,
O I
p k
C 13
SEENOTE
FLAC ,1 SEE NOTE 2, 3 C
SEENOTEI) ,¾ SEE NOTE 2
V SEENOTE ) SEE NOTE 2
"4
R
-
2 T
22 AWG SWITCHEDA+ 22 AWG
4 b 0 0
4 R
3 A+ IN "---(13.75/27.5VDC)
(TWO22AWG) 2A
C A+ IN
(TWO 2 DAWG) 22 AW
A
P 31 0300N010
ENNA
P533 030-0101-02
TO GLIDESLOPE ANTENNA
(SEE NOTE 1)
NOTES:
1. THESE INPUTS/OUTPUTS ARE ONLYVALID WITH KN 53 GLIDESLOPE OPTION (066-1067-00).
2. NOTAPPLICABLEON KI 203.
3. WIRE SIZES: A+, SWITCHEDA+, ANDPWRGND ARE 22AWG. ALL OTHERSARE 24AWG,
4. KN 53 PIN DESIGNATORSNOT SHOWNARE N.C.
FIGURE 2-7 KN 53 TO KI 203/204 INTERCONNECTDIAGRAM

(Dwg. No. 155-1328-00, R-0)
IMOO20-8 Page 2-17

KING
KN 53
NAVIGATION RECEIVER
030-1094-53 P/0030-1094-53
P532 P621
D MA 12
H MB NC O
5 MC 9 N p
11 MD 8
6
11
y
F ME
6 KA 7
M KB NC
10 KC 4 N
L KD 6 ^
D
J KE H L
E EOK||L 5 M
N DMESW COftuon c E
L.._ ______J
K e/o o3o 2227_os

N P2081/P2091
12 ILS ENABLE 4
RGl88 COMPOSITE 2
B
15 COMPOSITECOMMON I N
2 D
'' 500 OHMAUDIO OUT
2 O
S AUDIO COMMON
R SEE NOTE 2 3
(SEENOTEI) 'O
p SEE NOTE 2 A
C (SEENOTEI)+FLAG
13 SEE NOTE 2
ISEENOTE 1)-FLAG
R SEE NOTE 2
(SEENOTEI)+DOWN
R 14 -
0 o
22 AWG
4 SWITCHEDAi 8 9 R
3 INN -B(13.75/27.5VOC)
(TWO22AWG)AA+
C 22AWG
l PWRGND ILS COMMON-- 1
(TWO22 AWG)PNR
A GND
31 030 10Al 2ENNA
P533 030-0101-02
(SEENOTEI)
NOTES:
1. THESE INPUTS/0UTPUTS ARE ONLY VALID WITH KN 53 GLIDESLOPE OPTION (066-1067-00).
2. NOT APPLICABLE ON KI 208.

3. WIRE SIZES: A+, SNITCHED A+, AND PWR GND ARE 22AWG. ALL OTHERS ARE 24AWG.
4. KN 53 PIN DESIGNATORSNOT SHOWNARE N.C.
FIGURE 2-10 KN 53 TO KI 208/KI 209 INTERCONNECT

(Dwg. No. 155-1331-00, R-0)
IMOO20-8 Page 2-23

KING
KN 53
NAVIGATION RECEIVER
SECTION
III
OPERATICIN
3.1 GENERAL
It is recommended that power to the KN 53 be turned on only after engine start-up, as this procedure
increases the reliability of the solid state circuitry.
The KN 53 front panet controts consist of:
A. OFF/VOL/IDENT
B. Frequency Select
C. Frequency Transfer
The unit is turned on by rotating controt A clockwise. The power off position is felt by
counterctockwise rotation into a positive switch detent action. The NAV volume output is increased by
clockwise rotation of control A. Voice NAV information is heard when control A is pushed in. When
control A is pulled out, the Ident signal plus voice information may be heard.
The outer knob of control B is the MHz select and moves CW or CCW in one MHz steps. The inner knob is
the KHz select and moves CWor CCWin 50KHz steps.
NOTE
TO INCREASE FREQUENCY ROTATE KNOBS CLOCKWISE; TO DECREASE

FREQUENCY ROTATE KNOBS COUNTERCLOCKWISE. MOVING EITHER KNOB OF
CONTROL B WILL ONLY UPDATE STANDBY DISPLAYED FREQUENCY. REMOTE
DME, INTERNAL GLIDESLOPE (KPN 066-1067-00 ONLY), AND ILS
CHANNELINGARE ALSO PERFORMEDBY THIS CONTROL.
The standby frequency can be moved to the use (active) frequency by momentarity depressing the frequency
transfer switch, control C {i.e. when the frequency transfer switch is energized, the use frequency and
standby frequency trade places).
The KN 53 gas discharge display brightness witL automatically compensate for changes in ambient Light
Level. The dimming is controtted by a photoceLL mounted behind the front panet Lens to the Left of the
display.
The KN 53 has 2 x 5 DME channeling information outputs. DME's Like the King KN 62 can be channeled by
the KN 53 outputs. (The KN 62 must be in the RMT mode). See Section II of this Installation Manual for
interconnect information).
3.2 POST-INSTALLATION
CHECKOUT
An operational performance flight test is recommended after the installation is completed to insure
satisfactory performance of the equipment in its normal environment.
To check the VOR/ILS system, select a VOR frequency within a forty nautical mite range. Listen to the
VOR audio and insure that no electrical interference such as magneto noise is present. Check the tone
identifier filter operation. Fly inbound or outbound on a selected VOR radiat and check for proper
LEFT-RIGHT and TO-FROM indications. Check the VOR accuracy.
Rev. 1, July 1981

IMOO20-9 Page 3-1
KING
KN 53
NAVIGATION RECEIVER
NOTE
AT LOWALTITUDES VOR GROUND STATION SCALLOPING MAYBE PRESENT.
Flight test the ILS operation by flying a simulated ILS approach. Check Localizer LEFT-RIGHT deflection
and, if applicable, glidestope deflection. Check the Localizer accuracy in relation to the ILS runway.
Check the glidestope accuracy .in relation to the pubLished ILS approach attitude.
ACTIVE STANOBY
FRER.DISPLAY FREQ DISPLAY KHz KNOB
ACTIVESTANOBY ON/0FF VOL

PULL-IDENT MHz KNOB
TRANSFER BUTTON
FIGURE 3-1 KN 53 CONTROLFUNCTIONS
Rev. 1, July 1981

IMOO20-9 Page 3-2
MAINTENANCE/0VERHAUL
MANUAL
KN53
RECEIVER
NAVIGATION
MANUAL NUMBER 006-5174-01
REVISION NUMBER 1
FIRST PRINTING JULY, 1978
KING RADIO CORPORATION,

400 NORTH ROGERS ROAD OLATHE, KANSAS, U.S.A.
KINGRADIO MAINTENANCE MANUAL INSTRUCTIONS
REVISION ANDllISTORY
MANUAL KN 53 KPN 006-5174-01
REVISION1, August 1981
Where R&R appears in the action column, remove the page now in the maintenance manual and
replace it witl the enclosed page; otherwise, ADD or DESTROY pages as listed. Retain these
instructions ir the front of the maintenance manual as a Record of Revisions.
PA6E ACTION REASONFOR CHANGE
Cover R&R Updated

Rev. His. Add Updated
i R&R Updated
ii R&R Updated
iii R&R Updated
4-i R&R Updated
4-ii R&R Updated
4-7 R&R Rev. Change
4-17 R&R Updated
4-18 R&R Changed Table
4-19 R&R 02 to 02
4-20 R&R Page No. Change
4-25 R&R +7 to.+9
4-26 R&R Fig. No. Change
4-31 R&R Page Change
4-32 R&R Added a Paragraph (2)
4-35 R&R Time Change
4-37 R&R L309 to L304
4-38 R&R Comp. Designation Changes
4-39 R&R Corrected Spelling
4-40 R&R Comp. Designation Changes
Section V
5-1 Add Updated
5-6 R&R Added Overlay
5-13 R&R 50uV to 6uV
5-14 R&R 50uV to 30uV
5-28 R&R 154Hz to 150Hz
5-53 R&R Changed From Section IV to V
Section VI
Total
Replacement R&R Updated
KING
KN 53
NAVIGATION RECEIVER
TABl.E
OFCONTENTS
SEttil0NI'W
OFOPERATION
THEORY
Paragraph Page
4.1 Generat 4-1

4.1.1 Basic VOR Principles 4-1
4.1.1.1 Generat 4-1
4.1.1.2 VOR Generation 4-1
4.1.2 Basic Localizer Principles 4-3
4.1.3 Basic Glidestope Principles 4-3
4.2 Simplified Circuit Theory 4-4

4.2.1 Navigation Receiver Synthesizer Simplified Theory 4-5
4.2.2 Glidestope converter section 4-5
4.2.3 Glidestope Synthesizer 4-5
4.2.4 Display Simplified circuit Theory 4-5
4.2.5 Microprocessor and Input/Output Expander 4-9
4.2.6 Navigation Receiver Simplified circuitry 4-9
4.2.7 Power Supply Module 4-9
4.2.8 Glidestope Receiver Section 4-9
4.3 Detailed Circuit Theory 4-17

4.3.1 Generat 4-17
4.3.2 Digital Board 4-17
4.3.3 Navigation Synthesizer 4-17
4.3.3.1 Tuning Information 4-17
4.3.3.2 Programmable Divider 4-17
4.3.3.3 Megahertz Divider 4-18
4.3.3.4 Prescater Divider Detailed circuit Theory 4-19
4.3.3.5 Reference Oscittator 4-19
4.3.3.6 Phase comparator 4-19
4.3.4 GLidestope Synthesizer 4-19

4.3.4.1 Glidestope Synthesizer Divider 4-24
4.3.4.2 Phase comparator 4-24
4.3.4.3 Glidestope converter 4-24
4.3.5 Gas Discharge Display 4-26

4.3.6 Microprocessor Section 4-31
4.3.6.1 Basic System Controts and Timing 4-31
4.3.6.2 Program controtted System Function 4-32
4.3.7 Navigation Receiver Detailed circuit Theory 4-37

4.3.7.1 RF Preselector 4-37
4.3.7.2 Mixer 4-37
4.3.7.3 IF 4-37
4.3.7.4 Detector 4-37
4.3.7.5 Audio Pre-Amp and Ident Fitter 4-38
4.3.7.6 Low Pass Audio Fitter 4-38
4.3.7.7 50mw, 500 ohm Audio Output 4-38
4.3.7.8 IF AGC Amp 4-38
4.3.7.9 RF AGC 4-38
4.3.7.10 Loop Fitter 4-38
4.3.7.11 VCO 4-38
4.3.7.12 Receiver Buffer 4-38
4.3.7.13 Counter Buffer 4-38
4.3.7.14 Ringing Choke Switching Regulator 4-39
4.3.8 GLidestope Receiver Section 4-40
i
Rev. 1, August 1981
MMOO40-6
KING
KN 53
NAVIGATION RECEIVER
OF CONTENTS
TABLE
Paragraph V
SECTION Pase
5.1 General Information MAINTENANCE

5.2 Test Procedures 5-1
5.2.1 Test Equipment Required 5-1
5.2.2 Test Procedures 5-5
5.2.2.1 Standard Test Signal Description 5-5
5.2.2.2 Power Supply Tests 5-6
5.2.2.3 NAV Receiver 5-6
5.2.2.4 Localizer Characteristics 5-7
5.2.2.5 Glidestope Characteristics 5-7
5.2.3 ALignment 5-8

5.2.3.1 Atignment conditions 5-9
5.2.3.2 NAV Receiver and Synthesizer Atignment 5-13
5.2.3.3 Dimmer Adjust 5-13
5.2.3.4 GLidestope Board Alignment Procedure 5-14
5.3 Overhaut 5-15

5.3.1 Inspection 5-15
5.3.2 Cleaning 5-16
5.3.3 Repair 5-16
5.3.4 Disassembly Procedures 5-16
5.3.4.1 Top cover Removat 5-17
5.3.4.2 Bottom cover Removat 5-17
5.3.4.3 Power Supply Removat 5-17
5.3.4.4 NAV Receiver Removat 5-17
5.3.4.5 GLidestope Receiver Removat 5-17
5.3.4.6 Digitat Board Removal 5-17
5.4 Troubleshooting 5-18

5.4.1 System Troubleshooting 5-18
5.4.2 Power Supply Troubleshooting 5-18
5.4.3 NAV Synthesizer Troubleshooting 5-22
5.4.4 GLidestope Troubleshooting 5-27
5.4.5 Display Troubleshooting 5-37
5.4.6 Processor Troubleshooting 5-43
5.4.7 NAV Receiver Troubleshooting 5-47
SECTION
VI
PARTS
ILLUSTRATED LIST
Item Page
6-1 Finat Assembly 6-1

6-2 Power Supply 6-7
6-3 switch Board 6-11
6-4 NAV Receiver 6-15
6-5 Glidestope Receiver 6-25
6-6 Digitat Board 6-33
ii
Rev. 1, August 1981
MMOO40-6
KING
KN 53
NAVIGATION RECEIVER
TABLE
OFCONTENTS
LISTOFILLUSTRATIONS
Figure Page
4-1 VOR Signal Generation 4-2

4-2 Localizer Signal Generation 4-3
4-3 Glidepath 4-4
4-4 KN 53 Digital Board Block Diagram 4 7
4-5 NAV Receiver Board Block Diagram 4-11
4-6 KN 53 Power Supply Block Diagram 4-13
4-7 Glidestope Block Diagram 4-15
4-8 Timing Diagram for NAV Synthesizer 4-21
4-9 Prescater Timing Diagram 4-25
4-10 Pairings 4-27
4-11 Display Timing Diagram 4-29
4-12 Block Diagram of 1519 4-37
5-1 KN 53 Test Fixture 5-3

5-2 Alignment Adjustment Locations 5-11
5-3 KN 53 System Troubleshooting Flowchart 5-19
5-4 Power Supply Troubleshooting Flowchart 5-21
5-5 NAV Synthesizer Troubleshooting Flowchart 5-25
5-6 Glidestope Troubleshooting Flowchart (3 sheets) 5-31
5-7 Display Troubleshooting Flowchart (2 sheets) 5-39
5-8 Processor Troubleshooting Flowchart 5-45
5-9 NAV Receiver Troubleshooting Flowchart (2 Sheets) 5-49
5-10 KN 53 Internal Interconnect 5-53
6-1 KN 53 Final Assembly 6-5

6-2 Power Supply Assembly and Schematic 6-9
6-3 Switch Board AssembLy 6-13
6-4 NAV Receiver Assembly 6-21
6-5 NAV Receiver Board Schematic 6-23
6-6 Glidestope Receiver Board Assembly and Schematic 6-32
6-7 Digital Board Assembly 6-41
6-9 Digital Board Schematic 6-45
TABLES
Table Page
4-1 Megahertz Preset Numbers for Decade and Binary Counters 4-18
4-2 Kilohertz SLip Start Coding 4-20
4-3 Glidestope code conversion (2 sheets) 4-22
4-4 Microprocessor Interface 4-31
4-5 Listing of DME ILS NAV Synth, from Spec. (2 sheets) 4-33
4-6 EAROM controt codes 4-36
4-7 GS Frequency Table (2 sheets) 4-41
iii
Rev. 1, August 1981
MMOO40-6
KING
KN 53
NAVIGATION RECEIVER
TABI.EOF CONTENTS
IV
SECTION
THEORY
OFOPERATION
Paragraph Pac
4.1 Generat 4-
4.1.1 Basic VOR Principles 4-
4.1.1.1 Generat 4-
4.1.1.2 VOR Generation 4-
4.1.2 Basic Localizer Principles 4-
4.1.3 Basic Glidestope Principles 4-
4.2 Simplified circuit Theory 4-2

4.2.1 Navigation Receiver Synthesizer Simplified Theory 4-!
4.2.2 Glidestope converter Section 4-!
4.2.3 GLidestope Synthesizer 4-!
4.2.4 Display Simplified circuit Theory 4-!
4.2.5 Microprocessor and Input/0utput Expander 4-6
4.2.6 Navigation Receiver Simplified circuitry 4-!
4.2.7 Power Supply Module 4-6
4.2.8 Glidestope Receiver Section 4-1
4.3 Detailed circuit Theory 4-

4.3.1 Generat 4-
4.3.2 Digital Board 4-
4.3.3 Navigation Synthesizer 4-
4.3.3.1 Tuning Information 4-
4.3.3.2 Programmable Divider 4-
4.3.3.3 Megahertz Divider 4-
4.3.3.4 Prescater Divider Detailed Circuit Theory 4-
4.3.3.5 Reference Oscillator 4-
4.3.3.6 Phase Comparator 4-
4.3.4 Glidestope Synthesizer 4-

4.3.4.1 GLidestope Synthesizer Divider 4-
4.3.4.2 Phase Comparator 4-
4.3.4.3 Glidestope converter 4-
4.3.5 Gas Discharge Display 4-

4.3.6 Microprocessor Section 4-
4.3.6.1 Basic System Controts and Timing 4-
4.3.6.2 Program controtted System Function 4-
4.3.7 Navigation Receiver Detailed circuit Theory 4-

4.3.7.1 RF Preselector 4-
4.3.7.2 Mixer 4-
4.3.7.3 IF 4-
4.3.7.4 -
Detector 4-
4.3.7.5 Audio Pre-Amp and Ident Fitter 4-
4.3.7.6 Low Pass Audio Fitter 4-
4.3.7.7 50mw, 500 ohm Audio Output 4-
4.3.7.8 IF AGC Amp 4-
4.3.7.9 RF AGC 4-
4.3.7.10 Loop Filter 4-
4.3.7.11 VCO 4-
4.3.7.12 Receiver Buffer 4-
4.3.7.13 Counter Buffer 4-
4.3.7.14 Ringing Choke Switching Regulator 4-
4.3.8 Glidestope Receiver Section 4-
Rev. 1, August 1981

MMOO40-7
RING
KN 53
NAVIGATION RECEIVER
TABLE
OFCONTENTS
LISTOFILLUSTRATIONS
Figure Page
4-1 VOR Signal Generation 4-2

4-2 Localizer SignaL Generation 4-3
4-3 GLidepath 4-4
4-4 KN 53 Digital Board Block Diagram 4-7
4-5 NAV Receiver Board Block Diagram 4-11
4-6 KN 53 Power SuppLy Block Diagram 4-13
4-7 Glidestope Block Diagram 4-15
4-8 Timing Diagram for NAV Synthesizer 4-21
4-9 Prescater Timing Diagram 4-25
4-10 Pairings 4-27
4-11 Display Timing Diagram 4-29
4-12 Block Diagram of I519 4-37
TABLES
Tabte Page
4-1 Megahertz Preset Numbers for Decade and Binary Counters 4-18
4-2 Kitohertz Stip Start Coding 4-20
4-3 Glidestope Code conversion (2 sheets) 4-22 ""
4-4 Microprocessor Interface 4-31
4-5 Listing of DME ILS NAV Synth, from Spec. (2 sheets) 4-33
4-6 EAROMControl Codes 4-36
4-7 GS Frequency Table (2 sheets) 4-41
Rev. 1, August 1981

MMOO40-7
KING
KN 53
NAVIGATION RECEIVER
SECTION
IV
THEORY
OFOPERATION
4.1 GENERAL
Section 4.1 includes the basic principles of VOR, LOC, and glideslope operation. Section 4.2 contain
simplified circuit theory and block diagram operation of various systems within the KN 53. Section 4.
pertains to detailed circuit theory and sàhëmatics for the KN 53. Refer to section V for troubleshootin
and maintenance procedures.
4.1.1 BASIC VOR PRINCIPLES
4.1.1.1 General
The basic function of VHF Omnidirection Range (VOR) is to provide a means to determine an aircraft'
position with reference to a VOR ground station ànd also to follow a certain path toward or away from th
station. This is accomplished by indicating when the aircraft is on a selected VOR station radial or b
determining which radial the aircraft is on. A means to differentiate between radials and identify the
is necessary. For this purpose, advantage is taken of the fact that the phase difference between tu
signals can be accurately determined. Íhe phase difference between two signals which are generated t
the VOR station is varied as the direction relative to the station changes so that a particular radial i
represented by a particular phase difference. Refer to Figure 4-1. One non-directional reference signë
is generated with a phase that at any instant is the same in all directions. A second signal i
generated with a phase that at any instant is different in different directions The phase of tt
variable phase signal is the gameas the phase of the reference signal only at the 0 radial (north). I
the angle measured from the 0 radial increases, the phase of the vgriable phase signal lags the phase c
the reference signal by the number of degrees of the angle from 0 The reference
• and variable phat
signals, which are 30Hz voltages, are carried by RF to make radio transmission and reception possibit
The VOR receiving equipment must separate the 30Hz reference and variable phase signals from the i
carrier and compare the phase of the two signals. The phase difference is indicated on a cours
indicator or RMI.
4.1.1.2 VOR Generation
The VOR electromagnetic field is composed of the radiation from two ground based antennas radiating i
the same carrier frequency. The first is a non-directional antenna radiating an amplitude modulate
carrier. The frequency of the modul ating signal varies from 9480Hz to 10,440Hz back to 9480Hz 30 time
per second. That is, a 9960Hz subcarrier amplitude modul ates the RF carrier and is frequency modul att
by 30Hz.
The second antenna is a horizontal dipole which rotates at the rate of 30 revolutions peg second. Tl
dipole produces a figure 8 field pattern. The RF voltages within the two lobes are 180 out of phat
with each other. The RF Within one of the lobes is exactly in phase with the RF radiated from t\
non-directional field. The rotating figure 8 pattern reinforces the non-directional pattern on the sit
(see Figure 4-1). This results in a cardioid field pattern which rotates at the rate of 30 revolutioi
per second, the rate at which the dipole antenna rotates.
The signal at an aircraft within radio range of the VOR station is an RF carrier with amplitude varyii
at the rate of 30Hz because of the rotation of the cardoid pattern. The carrier is also amplitui
modulated at the station by the 9960Hz signal which is, in turn, frequency modulated on a sub-carrier
that it may be separated from the 30Hz variable phase signal.
MMOOO3 Page 4-1

KING
KN 53
NAVIGATION RECEIVER
REFERENCE PHASE
SIGNAL (FM)
ALL RADIALS
+ ---
lO440Hz
VARIABLE PHASE O -
9960Hz
SIGNAL (AM)
- ------ ---9480Hz
I
--
SECOND
O 30
RESULTANT -
ROTATING PATTERN \ i
1
i I
(30 REVOLUTlONS PER SECOND) O
1 30
-
SECOND
1
10°RADIAL
UNMODULATED l 9960Hz SUBCARRIER
ROTATING FREQ. MOD. AT 30Hz.
DIPOLE PATTERN
270° RADIAL 90° RADlAL
O O
SECOND SECOND
3
80 RADIAL
4/O
I
I i
I
i
f
I
O I
-SECOND
30
o o
REFERENCE PHASE VOLTAGE
O e
(AFTER FM DETECTION)
I 1 I
I I- I- I- I
I- (\I
VOLTAGES AT AIRCRAFT
ON 240° RADIAL
240°-
VARIABLE PHASE VOLTAGE D1RECTlON OF POSITIVE LOBE

O a
(AFTER AM DETECTlON) OF ROTATING ANTENNA.
FIGURE 4-1 VOR SIGNAL GENERATION

(Dwg. No. 696-0714-00, R-0)
MMOOO3 Page 4-2

KING
KN 53
NAVIGATION RECEIVER
4.1.2 BASÏC LOCALIZER PRINCIPLES
The localizer facility provides a visual display of the aircraft's position relative to a straigh
approach to the runway.
line The ground based localizer antenna system generates two patterns. Refer t
Figure 4-2. One pattern is directed toward the right side of the runway, the second to the left. Th
two patterns have the same carrier frequency but different audio modulation signals. The pattern to th
left of the runway (in normat approach) is 90Hz amplitude modulated which the pattern to the right i
150Hz amplitude modulated. The ratio of 90Hz to 150Hz audio, after demodulation, is dependent only upoi
the position of the aircraft within the patterns. The patterns are adjusted so they are of equa
strength on a vertical plane extending out from the runway centerline. When the aircraft is on thi
plane, the 90Hz and 150Hz voltages will be equal.
l50Hz
NORMAL
APPROACH EQUAL SlGNAL
STRENGTHS
90Hz
LOCALIZER ANTENNA PATTERN

(TOP VIEW)
150Hz
ULAALN
E9OOHFz
EQ
LOCAALZDER50MHOzDULATION
90H2
FRONT COURSE
FIGURE 4-2 LOCALIZER SIGNAL GENERATION

(Dwg. No. 696-0705-00, R-0)
4.1.3 BASIC GLIDESLOPE PRINCIPLES
The glideslope signal is radiated by a directional antenna array located near the approach end of th
runway. The signal consists of two intersecting tobes of RF energy. The upper lobe contains 90H
modulation and the lower lobe contains 150Hz modulation. The equal tone amplitude intersection of thes
two lobes forms the glidepath. A typical glide angle is 2.5 degrees. If the aircraft is on th
glidepath, equal amplitudes of both tones will be received and the deviation bar will be centered. I
the aircraft is above the glidepath, 90Hz modulation predominates and the visual display is displace
downward. If below the glidepath 150Hz predominates and the display is displaced upward. Refer t
Figure 4-3.
There are 40 glideslope frequencies in use today with a channel separation of 150KHz and each of these i
paired with a localizer frequency.
MMOOO3 Page 4-3

KING
KN 53
NAVIGATION RECEIVER
4.2 SIMPLIFIEDCIRCUITTHEORY
Figure 4-4 shows the simplified block diagram of the digital board. This diagram contains information on
the fol lowing:
A. Navigation Synthesizer
B. Glidestope Synthesizer
C. Gl ides lope converter

D. Display Circuitry
E. Microprocessor Circuitry
90Hz PREDOMINATES
ISOHz PREDOMINATES
FIGURE 4-3 GLIDEPATH

(Dwg. No. 696-1539-00, R-0)
Page 4-4
MMOOO3
KING
KN 53
NAVIGATION RECEIVER
Figure 4-5 shows the NAV receiver block diagram. Figure 4-6 shows the power supply block diagrar
Figure 4-7 shows the glideslope receiver block diagram. The individual diagrams are discussed briefly
this section. For a more detailed discussion see Section 4.3, Detailed circuit Theo y.
4.2.1 NAVIGATION RECEIVER SYNTHESIZER SIMPLIFIED THEORY
The navigation synthesizer board block diagram is included in Figure 4-4 of this section. TI
synthesizer consists of a voltage controlled oscillator (not shown), a programmable divider, and a 50KI
reference oscillator. The synthesizer maintains the oscillator frequency by dividing the loca
oscillator frequency by a number determined by a parallel code from to the microprocessor and the
comparing the divided down frequency to 50KHz.
The programmable divider uses a technique known as variable modulus prescaling, The ECL prescalf
divides by either 10 or 11. By varying the number of divide by 10 and divide by 11 cycles, a wide ran<
equivalent divide ratios can be obtained. The ECL prescaler is followed by a TTL divide by 2 to comple
the 120/21 divider.
The divided output should be 50KHz, the same as the reference. If not, the filtered output produced fri
the phase comparator will tend to move the VCO frequency so that its divided down frequency is 50KH:
The output of the loop filter is also used to tune varactor diodes in the RF section.
4.2.2 GLIDESLOPE CONVERTERSECTION
The converter section, included in Figure 4-4, of the glideslope receiver receives the detected IF (
"audio" and filters out the 90Hz and 150Ñz modulations. The additive detector then detects these ti
modulations and adds them together to produce a voltage at the output of the flag driver sufficient
drive the flag out of view only when both modulations are present. The subtractive detector detec1
these same two modulations but subtracts one from the other such that the output of the deviation-bi
driver will cause a centered indications when, and only when the amplitude of the 90Hz and 1501
modulations are exactly equal. The D-bar driver will cause the D-bar on an indicator to deflect in tl
proper direction and by a distance that is directly proportional to the difference in depth of modulatic
(ddm) of the glideslope signal received by the antenna.
4.2.3 GLIDESLOPE SYNTHESIZER
The glideslope synthesizer shown in Figure 4-4 converts the serial glideslope tuning code to paralli
code in the serial to parallel converter. This output presets the programmable counters.
The 19/±14 is controlled by the output of the programmable counters. When the loop is locked the counti
output is 11.1KHz into the phase comparator. The phase comparator controls the VCO frequency I
comparing the variable counter output to an 11.1KHz reference oscillator. The 100KHz signal is dividi
by 9 to obtain the 11.1KHz reference.
The 781.25Hz dither frequency is injected in the loop mixer to pull the VCO about +3KHz. This ditherii
is done to eliminate any zero beats that might occur in the mixer output by everchinging the intermedia
frequency within the 33.3KHz bandpass of the IF filter.
4.2.4 DISPLAY SIMPLIFIED CIRCUIT THEORY
The display of the KN 53 is time multiplexed at about a 125Hz rate. This insures a steady image to ti
eye. BCD coded cathode (segment) information from the microprocessor is decoded and brought to level
the display can function on by the decoder-driver as in Figure 4-4. Anode (digit) information from tl
microprocessor (mux clock, reset) is connected to a 8-bit Johnson counter to synchronize the digit to tl
corresponding groups of segment information. The active output of the digit counter is then transforms
to level use for the display by the anode driver.
A dimmer circuit varies the duty cycle and current programming to the cathode driver to adjust tl
brightness of display during varying light conditions.
MMOOO3 Page 4-5

KING
KN 53
NAVIGATION RECEIVER
4.2.5 MICROPROCESSORAND INPUT/0UTPUT EXPANDER
The KN 53 uses an eight bit microprocessor with a I/0 expander to control many of the functions of the
unit. The microprocessor receives information from the increment/decrement switches for frequency data,
the transfer switch for data storage, and the power supply reset for low aircraft power data. From this
input information the microprocessor controls the NAV synthesizer, controls and times the display,
supplies proper DME channel ing code, coñtrols optional glideslope synthesizer, and supplies data to and
control for the EAROM. The EAROM (electrically alterable read only memory), is capable of retaining
stored data for years with no power applied to the device. In the KN 53 the EAROM is used to store
frequency data during power down or momentary power interruption conditions.
4.2.6 NAVIGATION RECEIVER SIMPLIFIED CIRCUITRY
The navigation receiver board block diagram is shown in Figure 4-5 of this section. The receiver is a
single conversion superhetrodyne design with a monolithic crystal IF filter. The receiver generates VOR
or localizer composite for external converters. Audio is separated from the composite and amplified.
The RF section of the receiver has two poles of selectivity both before and after the RF amplifier. The
RF stages and VCO are varactor controlled from the synthesizer tuning line.
The synthesizer uses a stabilized master oscillator (SMO) to generate a local oscillator frequency
11.1MHz below the received frequency.
The 11.1MHz output is selected with crystal filters and amplified by an AGC controlled IF amplifier. The
detected output contains VOR/ILS composite and audio. The audio between 350Hz and 2500Hz is amplified in
the audio section to produce up to 50mw. 1020Hz ident tones are suppressed when the ident filter is
switched into the circuit.
4.2.7 POWER SUPPLY MODULE
This module (Figure 4-6) converts the aircraft power (11-33V) into the the DC voltages required by the KN
53. The aircraft power is filtered and connected to the primary of the power supply transformer. A
transistor switch causes current to flow into the primary. Energy produced in the transformer is
rectified and filtered to produce +190V, +9V, +5v and -26V DC.
The voltage of the 9V line is sensed and compared to a precision voltage reference. The error signal is
used to alter the off time of the transistor switch to regulate the line. Peak current in the primary is
detected and also alters the duty cycle of the switch. In doing this a soft turnon is accomplished.
A current limit circuit is provided on the 190V line to protect the display drivers in the event of a
momentary are in the display.
If the aircraft power is interrupted, a reset 'signal is generated and sent to the digital board to ensure
that the active and standby frequecies remain stored.
4.2.8 GLIDESLOPE RECEIVER SECTION
The KN 53 glideslope receiver (Figure 4-7) is designed to utilize the local oscillator frequency produced
by the naviation receiver frequency synthesizer. This provides the advantages of an accurate crystal
referenced frequency synthesizer without the cost of an additional crystal. This method also reduces to
a minimum the counter circuitry required in the glideslope frequency synthesizer.
The receiver is a single conversion superheterodyne design with an IF frequency of 33.3KHz. The local
oscillator is injected into the mixer at 11.1KHz below the operating frequency divided by 3.
ie: fop -
11.1KHz =
fop -
33.3KHz = Local Oscillator
The mixer combines the third harmonic of the local oscillator with the received signal that has been
amplified and filtered by the preselector to produce the 33.3KHz IF output.
In the loop mixer the NAV receiver L.O. injection is mixed with the glideslope VCO frequency. This
difference frequency is filtered and buffered before being injected into the glideslope synthesizer
counters.
MMOOO3 Page 4-9

KING
KN 53
NAVIGATION RECEIVER
The 33.3KHz is selected by the bandpass filter network and amplified by an AGC controtted amplifier.
buffered output of the detector contains the glidestope audio signal that drives the converter sectic
the digital board.
4.3 DETAILED
CIRCUITTHEORY
4.3.1 GENERAL
Figure 5-10 shows the KN 53 internal interconnect. This figure will be helpful in understanding
general signal flow inside the unit.
The KN 53 with glidestope, 066-1067-00, contains att the assemblies discussed in this section. The 8
without glidestope, 066-1067-01, does not contain the glidestope receiver board or any of the 600 se
components used on the digital board. Figure 6-9 is the digitat board schematic. Figure 6-7 shows
500 and 600 series parts components used on the digital board. Figure 6-8 shows only 500 se
components.
4.3.2 DIGITAL BOARD
The KN 53 digitat board contains the foLlowing major portions of the radio:
A. Navigation Synthesizer
B. Glidestope Synthesizer
C. GLidestope Converter
D. Display Driver
E. Microprocessor
In addition to the above the digitat board also contains power supply protection, unit interconnecti
RFI protection, and J532 for external connections.
Protection for the +5VDC supply is accomptished with F502 and CR512. If there is a short on the 5
Line, F502 witL open; or if the +5VDC Line is putted high CR512 will conduct and bLow F502. Protec
for the +9VDC supply and the -26VDC Lines is accomplished in the same manner as the +5VDC supply t
F501-CR511-F503-CR513 respectively. Internally protected I506 supplies +12VDC to the NAV receiver a
output directLy from the switches A+ Line.
When the gLidestope option is utiLized, 4604 suppties +9VDC switched to the glidestope receiver whe
ILS channet is in the active window. The ILS Line, pin 17 of I502, is Low until an ILS channet i
use, then it goes high switching pin 14 of I505 (base of 0508) Low which in turn switches +9VDC to
cottector of 0604. C603, L601, and C604 filter the +9VDC Line to isotate the switched +9VDC from
rest of the radio.
The digital board interconnects aLL of the boards as shown in Figure 4-8. This is accomptished by e
pins and recepticLes that are soldered soLidLy to the boards. This method of construction heLp
eliminate internaL wiring.
The J532 inputs and outputs are RFI protected by L501 thru L517, L602, C603, L604, C615, C616, C617,
thru C531, and R520.
4.3.3 NAVIGATION SYNTHESIZER (Reference Figure 6-9)
4.3.3.1 Tuning Information
The microprocessor suppties information to the megahertz counter and for the kilohertz comparator. T
codes are shown in Tabtes 4-1 and 4-2.
4.3.3.2 Programmabte Divider
The frequency of the Locat oscittator is divided down to 50KHz (pin 11 IS20) with the programa
divider. The Locat oscittator used in the KN 53 which is 11.1MHz beLow the received frequency cove
range from 96.9MHz to 106.85MHz. Divide ratios are needed for every integer vaLue from 1938 to 2
These divide ratios are obtained by cascading programmabte dividers. The first stage, the presca
divides by either 20 or 21. The second stage divides by 95 through 105. By controtting the se
divider with megahertz information from the computer and controtting the number of divide by 20'
divide by 21's in a cycLe with the kitohertz information, att of the needed divide ratios car
obtained.
Rev. 1, August 1981

MMOO40-7 Page 4-17
KING
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NAVIGATION RECEIVER
The fottowing section describes how the dividers are controtted.
4.3.3.3 Megahertz Divider
The megahertz divider composed of I520 and 1521 divides by a number determined by the microprocessor's
megahertz information (See Table 4-5). Since 1521 is a decade counter and I520 is a 4 bit binary
counter, divide ratios up to 160 (10 x 16) could be obtained. Only 11 of the possible divide ratios are
used (95 through 105). These ratios are obtained by presetting the counters I520 and I521 with the
number contained in the microprocessor information and counting to a futL count. When futt terminal
count is obtained, the carry out (pin 15) of I520 becomes high, the counters again Latch the preset
numbers, and the cycLe starts over. See Tabte 4-1.
Input to the divider is the clock input of the counters (pin 2 of I521) and output is the most
significant bit of the binary counter (pin 11 of I520).
Table 4-1 Lists the numbers to which the counter is preset for each megahertz frequency. Notice that the
XXX.0X frequencies are preset to the Lower megahertz code. This offset wilt show up when the stip-start
codes are described.
I>20 BINAtY I521 DiCADE

Preset No.
Pin 6 Pin 5 Pin 4 Pin 3 Pin 6 Pin 5 Pin 4 Pin 3 (Dec. Equiv.) Divide Ratio
108.0L 0 1 1 0 0 1 0 1 65 95
108.KL O 1 1 0 0 1 0 0 64 96
109.0L 0 1 1 0 0 1 0 0 64 96
109.KL 0 1 1 0 0 0 1 1 63 97
110.0L 0 1 1 0 0 0 1 1 63 97
110.KL 0 1 1 0 0 0 1 0 62 98
111.OL 0 1 1 0 0 0 1 0 62 98
111.KL 0 1 1 0 0 0 0 1 61 99
112.0L 0 1 1 0 0 0 0 1 61 99
112.KL 0 1 1 0 0 0 0 0 60 100
113.0L 0 1 1 0 0 0 0 0 60 100
113.KL 0 1 0 1 1 0 0 1 59 101
114.0L 0 1 0 1 1 0 0 1 59 101
114.KL 0 1 0 1 1 0 0 0 58 102
115.0L 0 1 0 1 1 0 0 0 58 102
115.KL 0 1 0 1 0 1 1 1 57 103
116.0L 0 1 O 1 0 1 1 1 57 103
116.KL 0 1 0 1 0 1 1 0 56 104
117.0L 0 1 0 1 0 1 1 0 56 104
117.KL O 1 0 1 0 1 0 1 55 105
Let K = Integers from 1 to 9 inclusive

Let L =
0 or 5
Rev. 1, August 1981 TABLE 4-1 MEGAHERTZPRESET NUMBERS FOR DECADE AND BINARY COUNTERS
MMOO40-7 Page 4-18
KING
KN 53
NAVIGATION RECEIVER
4.3.3.4 Prescater Divider Detailed Circuit Theory
Divide ratios resuLting from changes in kitohertz information are obtained by aLtering the numbe
"divide by 21's" compared to the number of "divide by 20's" of the prescater.
The divider begins dividing by 21 when the MHz counter reaches a value that corresponds to KHz tt
data and stops dividing by 21 when the value of the MHz counter reaches decimal count. Stip-star
defined to be the time the prescater starts dividing by 21 and stip-stop is defined to be the time
the counter stops dividing by 21.
a. Stip Start/Stip Stop Detection
Division by 20 or 21 is determined by the state of flip-flop I511B. When the 0 outpt

high, the prescater witt divide by 20. When the 02 output is Low, the prescater witL d
by 21. The KHz comparator {I522) monitors the state of the MHz counter. When the
pattern of the counter is identical to the kitohertz number Listed in Table 4-2, anc
counter is enabled, decimal count is greater than 120 (see Table 4-2), the A = B output,
14 of I522, is switched high. The high on the A = B Line causes the J-K flip-flop I51"
set the 02 output, which will be forced Low, driving the divided by 10 control Line, y
of I512, tow.
b. Divide by 20/Divide by 21
Refer to Figure 4-9 for a timing diagram of this stage. This stage divides by either i
21, depending upon the output of I511B, the slip start/stop flip-flop. The divide by ;
stage consists of I512 and I511A. I512 will divide by 11 if both PE inputs (pins 2 ar
are LO. Otherwise it will divide by 10.
I511A functions as a divide by 2 but also feeds back its output to one of the PE inpui
I512. Both PE inputs of I512 must be Lo to cause a divide by 11. As Long as pin 2 -
(divide 20), the state of pin 3 is irrelevant, I512 will divide by 10 and I511A witt d
by 2, thus accomptishing a divide by 20.
If, however, pin 2 of I512 is LO (divide 21), the fottowing action takes place. I512
divide by 11 whenever both pins 2 and 3 are LO. Thus, when slip start (pin 2 LO) oci
I512 will keep dividing by 10 for 10 more input pulses at pin 1. Thereafter, it
atternately divide by 10 and 11, as determined by the state of pin 3, thus accomptish
divide by 21. This action witt continue until I5118 is reset which is reset by a tert
count on the programmable counters.
For each 50KHz increment in the VCO frequency, an additional divide by 21 cycle is addt
the slip intervat. Note that an extra megahertz of 50KC increments are added during the
and .05KHz settings. This accounts for the Lost megahertz on these frequencies in
megahertz presetting.
4.3.3.5 Reference OsciLlator
I509 is the reference osciLlator and divider. Y501, a 3.2MHz crystat, is the frequency controL foi
3.2MHz oscillator. C303 is used to trim the oscittator on frequency. The divider portion of
divides the 3.2MHz to produce controlled frequencies of 3.2MHz, 100KHz, 50KHz, 12.5MHz, and 781.25Hz
in the KN 53.
4.3.3.6 Phase Comparator
I510 is the phase comparator. The comparator generates the error output by comparing the i
reference, I509, pin 4, to the 50KHz variable, I520, pin 11. 0504 is an inverter that transtatet
variabLe 50KHz TTL output of the programmabLe divider to CMOS Levels to drive I510. The error outpt
pin 13 is used as the controL voltage for the VCO and tuning controt for the NAV pre-selector.
4.3.4 GLIDESLOPE SYNTHESIZER (Ref Figure 6-9)
I601 is an 8-stage serial shift register having a storage Latch associated with each stage for stri
data from the serial input to parattet buffered outputs. The serial data input from the microproce:
I501, is expLained in paragraph 4.3.6.2c. The I601 glidestope parattet code conversion outputs are :
in TabLe 4-3. These output codes preset the binary programmable counters, I606 and I607.
Rev. 1, August 1981

MMOO40-7 Page 4-19
KING
KN 53
NAVIGATION RECEIVER
IL20 I521 Slip Start

Start
Pin 11 Pin 12 Pin 13 Pin 14 Pin 11 Pin 12 Pin 13 Pin 14 Dec. Equiv.
.00 1 1 0 0 0 0 0 1 121
.05 1 1 0 0 0 0 0 0 120
.10 1 1 0 1 1 0 0 1 139
.15 1 1 0 1 1 0 0 0 138
.20 1 1 0 1 0 1 1 1 137
.25 1 1 0 1 0 1 1 0 136
.30 1 1 0 1 0 1 0 1 135
.35 1 1 0 1 0 1 0 0 134
.40 1 1 0 1 0 0 1 1 133
.45 1 1 0 1 0 0 1 0 132
.50 1 1 0 1 0 0 0 1 131
.55 1 1 0 1 0 0 0 0 130
.60 1 1 0 0 1 0 0 1 129
.65 1 1 0 0 1 0 0 0 128
.70 1 1 0 0 0 1 1 1 127
.75 1 1 0 0 0 1 1 0 126
.80 1 1 0 0 0 1 0 1 125
.85 1 1 0 0 0 1 0 0 124
.90 1 1 0 0 0 0 1 1 123
.95 1 1 0 0 0 0 1 0 122
SLIP START CODESO
AM Freq. 1 1 1 1 O 1 159
Rev. 1, August 1981 TABLE 4-2 KILOHERTZ SLIP START CODING

MMOO40-7 Page 4-20
KING
KN 53
NAVIGATION RECEIVER
1522
PIN I NAV MHz PRESET REGION
PIN Q3
PIN Q2
l2
15204
PIN
PIN g
PIN Q3
PI2N Q2
I521
PIN Q
13
PIN QO
14 55 65 75 80 95 1 I I I 1 I I
01223456
05055550
I512 PIN et TERMINAL

8
SLIP START SLIPSTOP---+
REGION
FIGURE 4-8 TIMING DIAGRAM FOR NAV SYNTHESIZER

(Dwg. No. 696-7606-00, R-0)
Rev. 1, August 1981

MMOO40-7
Page 4-21
KING
KN 53
NAVIGATION RECEIVER
ACTIVE NAV 1605 OUTPUT DIVIDE RATE Pin 11 Pin 12 Pin 13 Pin 14 Pin 7 Pin 6
FREQUENCY Pin 11 (MHz) 1606 & I607 GF GE GD GC GB GA
108.10 1.6111 145 0 0 0 0 0 0
108.15 1.6000 144 0 0 0 0 0 1

108.30 1.5667 141 0 0 0 1 0 0
108.35 1.5556 140 0 0 0 1 0 1
108.50 1.3889 125 0 1 0 1 0 0
108.55 1.3778 124 0 1 0 1 0 1
108.70 1.3889 125 0 1 0 1 0 0
108.75 1.3778 124 0 1 0 1 0 1
108.90 1.3222 119 0 1 1 0 1 0
108.95 1.3111 118 0 1 1 0 1 1
| 109.10 1.3778 124 0 1 0 1 0 1
. 109.15 1.3667 123 0 1 0 1 1 0
109.30 1.3778 124 O 1 0 1 0 1
109.35 1.3667 123 0 1 0 1 1 I O
109.50 1.3788 124 0 1 0 1 0 1
109.55 1.3667 123 0 1 0 1 1 0
109.70 1.3778 124 0 1 0 1 0 1
109.75 1.3667 123 0 1 0 1 1 0
109.90 1.3778 124 0 1 0 1 0 1
109.95 1.3667 123 0 1 0 1 1 0
110.10 1.3778 123 0 1 0 1 0 1
110.15 1.3667 123 0 1 0 1 1 0
110.30 1.3778 124 0 1 0 1 0 1
110.35 1.3667 123 0 1 0 1 1 0

110.50 1.1556 104 1 0 1 0 0 1
110.55^
1.1444 103 1 0 1 0 1 0
110.70 1.1556 104 1 0 1 0 0 1
110.75 1.1444 103 1 0 1 0 1 0
110.90 1.1556 104 1 0 1 0 0 1
TABLE 4-3 GLIDESLOPE CODE CONVERSION
(Sheet 1 of 2)
Rev. 1, August 1981

MMOO40-7 Page 4-22
KING
KN 53
NAVIGATION RECEIVER
ACTIVE NAV I605 OUTPUT DIVIDE RATE Pin 11 Pin 12 Pin 13 Pin 14 Pin 7 Pi
FREQUENCY Pin 11 (MHz) I606 & 1607 GF GE GD GC GB G
110.95 1.1444 103 1 0 1 0 1
111.10 1.1667 105 1 0 1 0 0
111.15 1.1556 104 1 0 1 0 0
111.30 1.1667 105 1 0 1 0 0
111.35 1.1556 104 1 0 1 0 0
111.50 1.1667 105 1 0 1 0 0
111.55 1.1556 104 1 0 1 0 0
111.70 1.1667 105 1 0 1 0 0
111.75 1.1556 104 1 0 1 0 0
111.90 1.0556 095 1 1 0 0 1
111.95 1.0444 094 1 1 0 0 1
ILS ENABLE, pin 17 of I502, is inactive (Low) on att frequencies not Listed above and GA, GB, GC, G
and GF are not defined.
TABLE 4-3 GLIDESLOPE CODE CONVERSION

(Sheet 2 of 2)
Rev. 1, August 1981
MMOO40-7
Page 4-23
KING
KN 53
NAVIGATION RECEIVER
4.3.4.1 GLidestope Synthesizer Divider
The programmable divider consists of a divide 14/divide 9 prescater, I605, and the main divider
consisting of I606 and 1607. When the main divider reaches terminal count I518, pin 11, goes Low and
I605 does one divide 14 cycle. At the end of the divide 14 cycte, I605, pin 11, goes high and I606 and
I607 are preset to the programming code from I601. I605 then does divide 9 cycles and increments
I606-I607 for each divide 9 cycle until terminal count is reached when the cycLe repeats. At terminal
count I607 is in state 9 and I606 is in state 0. For details see Figure 4-10.
4.3.4.2 Phase comparator

The phase comparator, I603, compares the 11.1KHz variable from I607, pin 11, to the reference 11.1KHz
signat from 1602 pin 12. The phase comparator output, pin 13, has the dither frequency, 781.25Hz,
superimposed on it by R604 and C606. R601, R602, R603, and C607 fitter any 11.1KHz off the VCO controt
vottage before it is sent to the glidestope receiver board. I602 divides the 100KHz output from the
reference osciLLator/divider, I509, by 9 to produce the 11.1KHz reference signat.
4.3.4.3 GLIDESLOPE CONVERTER (Reference Figure 6-9)
I608D fitters out and amplifies any 150Hz present in the audio. I608C does the same for 90Hz. Both
I608D and A are referenced to one-hatf supply vottage so their outputs witL have the 90 or 150Hz
moduLations superimposed on 4.5V. CR603 and CR604 both conduct during the negative haLf cycLe of both
fitter outputs thereby creating a current that is on the average proportionat to the sum of both
moduLations. The fLag driver, I608A, then generates a vottage output to keep pin 1 at 4.5V. The flag
wiLL be forced out of view when pin 13 of J532 is heLd at Least 260mv above pin R of J532. R629 provides
an offset current to insure that both 90Hz and 150Hz modulations are present before the flag is driven
out of view. CR605 detects on the negative haLf cycLe of the 150Hz fitter output white CR606 detects on
the positive haLf cycLe of the 90Hz fitter output. Therefore, when both moduLations are of equaL
amptitude, there wiLL be no net current required through R631 to keep I608B pin 7 at 4.5V. For this
condition, the deviation-bar (D-bar) would be centered. When one modulation is greater than the other,
the direction and amount of current through R631 required to maintain the virtuaL reference voLtage at
I608B, pin 6, wiLL cause the voLtage differentiat between pins P and 14 of J532 to be the proper poLarity
and amptitude to drive the D-bar the correct distance in the proper direction. When J532 pin P is
positive with respect to pin 14, the D-bar witt defLect up. This witt occur when the 150Hz modulation is
greater than the 90Hz which means that the pLane would be below the glidepath.
Rev. 1, August 1981

MMOO40-7 Page 4-24
KING
KN 53
NAVIGATION RECEIVER
I605-2
cl<
TC 1605-1!
O 1605-8
I I Isos-c
I605-1
3 - I605-I
PRESET
I605 -
14 9
I605-
CLOCi<
I606 T.C 1606-
1606-
0
I 1606 -
LSASTESHOWN 1606-
2
PRESET DATA
I606-
3
1607-
ol
I606-
I
2 I606-
3 1607 -
PRESET I518 -
ENABLE
I 606 a I607
JUST PRIOR TO TERMINAL COUNT AND PRESET
FIGURE 4-9 PRESCALER TIMING DIAGRAM

(Dwg. No. 696-7607-00, R-1)
Rev. 1, August 1981

MMOO40-7
Page 4-25
KING
KN 53
NAVIGATION RECEIVER
4.3.5 GAS DISCHARGE DISPLAY (Reference Figure 6-9)
The KN 53 has a gas discharge display that is driven in a multipLexed fashion. The display contains six
7-segment digits, two 9-segment doubte digits, two decimat points, and character "T" that is unused in
the KN 53. Each anode of the display corresponds to an entire digit or double digit. Each cathode is a
particular segment of a digit or a decimal point. C thode designations are shown in Figure 4-10.
When they are not being fired, the anodes set at 100 votts and the cathodes at about 70 voLts. The
resutting voltage is insufficient to ionize the gas and fire the tube. In order to display a particular
number or decimal the required cathode segments must be putted Low by 1508 white the proper anode segment
is putted to +190 volts by IS14. For example to make a "1" appear as the Last digit on the right of the
display cathode "b" and "c" would have to be putted Low while anode 8 is pulled high.
The anodes of the display are fired sequentially by IS14 in the fottowing order, 1, 5, 2, 6, 3, 7, 4, 8
(figure 4-12). I514 is driven by a eight bit ring counter, I513. A Logic "1" at any of the outputs
causes the corresponding anode of the display to go to +190 votts. Care should be exercised as the ring
counter, IS13, and anode driver are operating at +190V. The control Lines are capacitively coupted to
the microprocessor, which synchronizes the anodes and cathodes.
The cathodes of the dispLay are driven by a decode driver 1508. BCD segment information, synchronized to
the anode drivers, is supplied by microprocessor.
.the
The g and h segments are not coded but are
negative Logic. The purpose of I508 is to putt the selected cathode to a Low potentiat to cause it to
fire. When the segments are first fired a ionization voltage of about 150 volts must be overcome. After
the segment is fired, a sustaining voltage of 130V is required.
Two keep atives are included, the anodes are tied to +190V through RS75 and R576, the cathodes are
connected to ground by RS77 and RS78. These keep aLives insure the display witL fire quickly and
eliminate digits fLickering during Low ambient Light conditions.
The photoceLL activated dimming circuit adjusts the brightness of the display to compensate for changes
in ambient Light LeveL. Dimming is accomplished by varying both the duty cycle and the amptitude of the
cathode programming current.
The microprocessor supplies a 1KC trigger to I515 that is synchronous with the multiplex clock. I515 is
a one-shot with a variable time constant from 80us to 975us. The output of the one shot is a 1KHz square
wave with a variable duty cycle.
I516A is wired as a constant current source whose output current is used to charge C533 the timing
capacitor for the one-shot. The time constant is determined by the magnitude of the current from I516A,
which in turn is controLled by photoceLL, R542. In darkness the output current from I516A is at its
maximum value of about giving
.75ma, the one shot a time constant of about 80us. As ambient Light
increases, the current from I516A decreases, causing the time constant of I516A to increase until it
reaches its maximum value of 975us (Figure 4-11). The maximum time constant of I516A is Limited by the
duty cycLe of the 1KHz trigger from the microprocessor. When the trigger goes Low it forces the one shot
to reset. R546 controts the minimum time constant of the one-shot and is used to adjust the minimum
brightness Levet.
The output of IS15 is filtered by R548 and C512. This DC voLtage controts the magnitude of current from
I5168, another constant current source. The current from I5168 varies from about 290ua in darkness to
about 860us in bright Light. This current is used as the programming current for the cathode driver,
I508.
Rev. 1, August 1981

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NAVIGATION RECEIVER
4.3.6 MICROPROCESSORSECTION (Reference Figure 6-9)
4.3.6.1 Basic System controts and Timing
A. Processor Clock
The primary 3.2MHz clock isgenerated by Y501 and I509 and apptied to I501-2 througt
inverting buffer consisting of 1507-11-12. Internatty 1501 divides the 3.2MHz clock b:
to form the machine cycle of 4.68usec.
b. Processor Reset
Proper operation requires that the reset I501-4 be held Low during power up and power d
The power supply reset circuits puLL I501-4 Low through CR514 when insufficient voltagi
available to operate the power suppLy. When the power suppLy stabiLizes, its reset circ
drive the cathode of CR514 high which allows C501 to charge through a putt up resisto
I501. When the vottage on I501-4 exceeds a threshold, I501 begins execution of its st
program. The reset Line can also be putted Low through CR509 if 1501 should happen to
into a false program Loop and try to fetch nonexistant instructions. Normally this n
occurs. The 12.5KHz clock for I519-5 is also grounded through CR510 when the reset
from the power suppLy goes tow. This prevents partial erasure of I519 during power down
c. Interface of I501 and I502
I502 is an expander port designed to work with I501. Four parattet data bits ma)
transferred to one of four 4-bit wide ports on I502 under program control of 1501. 0
functions are possible but not used in this circuit. A four bit address is sent
1501-21, 22, 23, 24 to 1502-11, 10, 9, 8 and Latched when I501-25 drives ISO2-7 Low.
address specified the operation and the port on 1502 which is to be used.
The data then replaces the address and the data is Latched when I501-25 goes high.
Table 4-4 for details.
Port Sebection Port Pin #

Address Corresponding to Pin
I502-
Pin Pin
11 10 Port Name 11 10 9 8
0 0 Port 4 2 3 4 5
0 1 Port 5 1 23 22 21
1 0 Port 6 20 19 18 17
1 1 Port 7 13 14 15 16
Function Selection
Address
1502-
Pin Pin
9 8 Function
0 0 Read Port to I501 Not Used
0 1 Write Data to Port
1 0 Or Data to Port Not Used
1 1 And Data to Port Not Used
TABLE 4-4 MICROPROCESSOR INTERFACE

Rev. 1, August 1981
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4.3.6.2 Program ControLLed System Function
a. Program Structure
The program can be divided into 4 conceptual blocks: Power up routine, main, interrupt, and
EAROMwrite.
The "power up routine" reads the previous "use" and "stby" frequencies from I519 and sets up
the required internal registers in I501. This section is executed once each time the power
is applied and the reset Line goes high. On completion of this routine, the program jumps
to the "main routine".
The "main routine" converts the "USE" frequency to the various codes required for the DME,
NAV synthesizer, and glidestope synthesizer. It also performs various functions required
but not time critical in the program. The "main routine" Loops back on itself and repeats
as Long as power is applied. However each millisecond the main routine is interrupted and
the program control is passed to the "interrupt routine". When program controL is returned
to the "main routine" it picks up exactly where it was interrupted.
The "interrupt routine" services the display and reads the switches it also partially
decodes the switches and takes care of severat internat functions required by the interrupt
of the main routine. On completion, the "interrupt routine" passes control to the "EAROM
write routine".
The "EAROM write routine" checks to see if the frequency has been changed. If the frequency
has not changed, it returns control to the "main routine". If the frequency has changed, it
sets some flags and starts the process of writing the new data to I519. As the process
takes nearty 1/4 second this routine breaks it into severat short sections and does one
section and then returns control to the main routine. Each time the EAROM write routine
gets control, it does the next section and then returns control to the "main routine". In
this way the time critical functions are intertaced with the EAROMwrite so as not to affect
the display or switch sensing functions.
b. Parattet Data Lines (S/N 4484 and beLow)
Tuning data for the NAV and GS synthesizer, the ÏLS Line and DME tuning data are determined
by the microprocessor. The "main routine" converts the "USE" frequency into the appropriate
codes and outputs these codes to the proper pins on I501 and I502. Refer to Table 4-5 for a
detailed Listing. The output buffers for the DME channet data (4511 thru 0521) are enabled
when the DME common (J532-N) is Low. This turns 0509 and 9511 off which turn 0510 on
thereby grounding the emitters and enabling the bases of the buffer transistors. The ILS is
buffered by 9508. The parattet tuning data to the NAV synthesizer is connected directly
from I502 to the TTL used in the synthesizer.
c. Serial Data Lines (S/N 4485 and above)
A 3 wire serial data buss is used to output the glidestope data corresponding to the
selected "USE" frequency. 1501-36 is the clock and is connected to 1601-3. I501-37 is the
data and is connected to I601-2. I501-38 is the strobe and is connected to I601-1. I601 is
a 8 bit serial input shift register with a 8 bit output Latch. The data is shifted into the
shift register on each rising edge of the clock and a high Levet on the strobe Line forces
the outputs to equat the shift register contents. When the strobe Line is Low, the outputs
are Latched which allows the shift register to be serially loaded without affecting the
outputs. The timing of the serial data witt appear erratic because the output routine is
part of the "main" program routine and is interrupted each mittisecond. This has no effect
on the outputs of I601 because of the Latch. See Table 4-3 for code Listing.
Rev. 1, August 1981

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NAVIGATIONRECEIVER
The DME SELECT, NAV SYNTHESIZER, and ILS ENABLE Lines are controhled by the frequency in the
window. The fotiowing tables specify the appropriate codes. The folkowing tabies should be check
the DME common open (no connection). The ILS ENABLE, pin 17 of ISO2, is inactive (how)
frequencies not histed in Table 4-3.
Let K = integers from 1 to 9 inchusive
Let L = 0 or 5 Let N =
0 or 1 0 = Most Negative
1 = Most Positive
Let X = integers from 0 to 9 inchusive
NAV SYNTHESIZER CODE DME CODE
1502 PINS I501 PINS
NAV. Freq. 22 21 20 19 18 31 30 29 28 27
PO P1 P2 P3 PA MA MB MC MD ME
108.0L 1 0 1 0 0 1 0 0 1 0
108.KL 0 0 1 0 0 1 0 0 1 0
109.0L 0 0 1 0 0 1 0 0 0 1
109.KL 1 1 0 0 0 1 0 0 0 1
110.0L 1 1 0 0 0 0 1 0 0 1
110.KL 0 1 0 0 0 0 1 0 0 1
111.0L 0 1 0 0 0 1 1 0 0 0
111.KL 1 0 0 0 0 1 1 0 0 0
112.0L 1 0 0 0 0 1 0 1 0 0
112.KL 0 0 0 0 0 1 0 1 0 0
113.0L 0 0 0 0 0 0 1 1 0 0
113.KL 1 0 0 1 1 0 1 1 0 0
114.0L 1 0 0 1 1 0 1 0 1 0
114.KL 0 0 0 1 1 0 1 0 1 0
115.0L 0 0 0 1 1 0 0 1 1 0
115.KL 1 1 1 0 1 0 0 1 1 0
116.0L 1 1 1 0 1 0 0 1 0 1
116.KL 0 1 1 0 1 0 0 1 0 1
117.0L 0 1 1 0 1 0 0 0 1 1
117.KL 1 0 1 0 1 0 0 0 1 1
TABLE 4-5 LISTING OF DME ILS NAV SYNTH FROM SPEC.

(Sheet 1 of 2)
Rev. 1, August 1981

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NAVIGATION RECEIVER
DME
I502 PINS 1501 PINS
4 5 1 23 19 18 34 33 32
NAV Freq. B1 B2 B3 B4 KA KB KC KD KE
1NX.0L 0 0 0 0 0 1 0 0 1
1NX.1L 0 0 1 1 1 1 0 0 0
1NX.2L 1 1 0 1 1 0 1 0 0
1NX.3L 0 1 0 1 0 1 1 0 0
1NX.4L 1 0 0 1 0 1 0 1 0
1NX.5L 0 0 0 1 0 0 1 1 0
1NX.6L 0 0 1 0 0 0 1 0 1
1NX.7L 1 1 0 0 0 0 0 1 1
1NX.8L 0 1 0 0 1 0 0 1 0
1NX.9L 1 0 0 0 1 0 0 0 1
I502 PINS
3 2
BO DME Seheet 50KHz
1NX.XO 1 0
1NX.X5 0 1
TABLE 4-5 LISTING OF DME ILS NAV SYNTH FROM SPEC.

(Sheet 2 of 2)
Rev. 1, August 1981
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d. Switch Read
I501 samples the switch states during the "interrupt" portion of the program. The switc
are sampted white I501-35 is Low. A closed switch causes the corresponding pin on I501
be Low when it is sampted. I501-6 corresponds to (S501) the "transfer switch".
"increment switch" grounds I501-24 through CR508. The "decrement switch" grounds I50"
through CR507. The "MHz switch" grounds 1501-22 through CR505. The "KHz switch" grot
I501-21 through CR506. Note that I501-24, 23, 22, 21 are shared with I502 but I502 does
use these Lines white I501-35 is Low. The "interrupt routine" internally debounces S501
decodes the frequency select Lines.
e. Increment Decrement Switches
Functionally the KHz and MHz switches are identicat. Each switch has 3 contacts ar
common wiper. The 3 contacts are shorted to common sequentially as the switch is turi
The first contacts shorted as either switch is turned clockwise are increment contacts.
f. Display
The code for the segments are output on I501-12, 13, 14, 15, 16, 17. I501-35 is putted
then thesegment codes are changed to the next digit and a short Low going pulse
generated on 1501-10 which clocks I513 through I507-5, 4 and C505. Every eighth dig-
short Low going putse is generated on 1501-8 which resets I513 through I507-7, 6 and C.
After the switches are read ISO1-35 returns high which triggers I515 and starts the disp
g. EAROMInterface (Ref Table 4-6)
I519 is an electricatty atterable read only memory. A 12.5KHz clock from I509 clock I51
The 12.5KHz clock is converted to 5V by I507-14, 15 and sent to I501-1. I519-1 i
bidirectional pin and data read from I519 is converted to 5V by I507-3,2 and sent
I501-39. The control data is output on I502-14, 15, 16 and converted to 9V Levels by
and sent to the control inputs I519-Ë, 7, 6. When1519-7 is Low 4506 is turned on thr
R574. This enables a pull up resistor R562 to I519-1. This allows data from I502-13 t
sent to I519-1 through 1517.
h. EAROMOperation
During power up I501 reads two words stored in I519 to determine the "STBY" and "
frequencies that are to.be used. The data is in BCD representation. .The first 4
represent MHz with the 10MHz and 100MHz implied. The second 4 bits represent 100KHz a
bit represents 50KHz. The Last 5 bits are not used.
To read the data, the "USE" word is addressed by sending at least 8 "Hs" fottowed i
"HLHHHH" series fottowed by another "HLHHHH" series to the address register in I519.
Figure 4-13. This is followed by a read command and then data is shifted out of the
register in I519 to I501-39. The "STBY" word is then addressed by shifting a single
into the address register fottowed by a read command and then the data is shifted from
data register in IS19 to I501-39. I501 then readdresses I519 as for the "USE" word t
ready for any updates. After this power up sequence any changes in the frequencies by
operator causes I501 to store the updated frequencies in I519.
I501 waits 1 second after the Last change by the operator before updating I519 to a
unnecessary updates.
To update I519 the "USE" frequency MHz data fottowed by the KHz data is shifted into
data register of I519. Next an erase command is sent for 24ms to clear the old data.
a write command is sent for 24ms to store the new data. A "H" is then shifted into
address register to address the "STBY" word. The same procedure for writing the "USE"
is repeated except the "STBY" data is used. On completion, the address for the "USE"
is shifted into the address register in I519. The standby command is sent to I519 bet
operations.
Rev. 1, August 1981

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NAVIGATION RECEIVER
1519
C1 C2 C3
Pin 6 Pin 7 Pin 8
H H H Standby
H L L Shift data to address register
L H H Load data from addressed memory to data register
L H L Shift data register out
H L H Erase addressed memory location
L L L Shift data into data register
L L H Write data register contents to addressed memory kocation
H H L Invalid
Note: H = +9V
L = OV
Output data changes on rising edge of ciock. Input data is shifted on fah§ing edge of clock.
Controb inputs (C1, C2, C3) are changed on the rising edge of chock.
TABLE 4-6 EAROMCONTROLCODES
Rev. 1, August 1981

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NAVIGATION RECEIVER
14bit DATA REGISTER T/O : DATA T/D PIN I

----
BUFFER
MEMORŸ ARRAY MODE C PIN 6

100X14 CONTROL C HN7
C PINS
. . CLOCK i
t CLOCK PIN5
\t Nr DRIVER
TEN'S ADDRESS UNITSADDRESS
FIGURE 4-12 BLOCK DIAGRAMOF I519
4.3.7 NAVIGATION RECEIVER DETAILED CIRCUIT THEORY (Reference Figure 6-5)
4.3.7.1 RF Preselector
The RF signal input (108.00 to 117.95MHz) is coupted into the first filter pote, L311, by C301. L31
varactor tuned by CR306. The signal is then coupted into the second fiLter poLe, L301, by C365. L30
varactor tuned by CR301. The RF signal is then capacitiveLy coupted into G1 of the RF ampLifier, 03C
duaL gate, enhancement mode, DMOS FET.
R300, R302, R303, and R304 set the bias on 0301. The RF amplifier AGC is applied to G2 of 0301.
voltage at G2 wiLL be approximateLy 8.5VDC (fuLL RF gain) from no signaL up to 50uv (hard) input.
50uv input, tne RF AGC wiLL attack and the AGC voltage witL decrease according to the Levet of the i
signal. At high RF Levet inputs, the G2 voLtage may be as Low as OVDC.
The ampLified RF signaL is coupted into the third fiLter pote, L303, by C308. L303 is varactor tune
CR302. The signal is then coupted into the fourth fiLter pole, L304, by C311. L304 is varactor tune
CR303. The RF signaL is then coupLed into the mixer, 0302, by C314.
4.3.7.2 Mixer
The fittered, amplified RF signat is applied to G1 of 0302. The buffered VCO (Local oscittator) si
is coupted into G2 by c316, R308, and C356. G1 and G2 are biased by R309, R310, R311, and R313.
4.3.7.3 IF
T301 impedance matches the 11.1MHz mixer output into the monoLithic crystaL filter FL301. T302 impec
matches the FL301 output into the differential input of the first IF ampLifier, I301. T303 matches
output of I301 to the input of 9303, the second IF amplifier.
4.3.7.4 Detector
The 11.1MHz is fed into the active detector by T304. Transistor 0304 and R326 develop the base bias
0305. With the cottector shorted to the base, 0304 is functioning as a diode which has the same the
characteristics as transistor 0305. On negative swings 0305 witt conduct and on positive swings
wiLL be turned off, thus providing detection.
Rev. 1, August 1981

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NAVI6ATION RECEIVER
4.3.7.5 Audio Pre-Amp and Ident FiLter
The detected audio at the base of 0306 has been fiLtered by R327 and 0334, which are active about 20KHz.
The Ident filter is active when the Ident Line is not shorted to ground. The paraLlet resonant circuit
of C337 and L305 is a high impedance at 1020Hz. This resonance in the emitter of 0306 greatty reduces
its gain at 1020Hz. When the fitter is active, 1020Hz wiLL be attenuated a minimum of 15dB down from the
inactive state.
4.3.7.6 Low Pass Audio FiLter
The 4315 circuitry is a Low pass active audio fitter designed with 350Hz as the Lower frequency cut off.
C336 couples the audio signaL into the votume control as well as further roLLing off the Low end
frequency response.
4.3.7.7 50mw, 500 ohm Audio Output
R330 and C335 fiLter high frequency signals off the audio that may be picked up in the unit's internaL
cabling. I302 ampLified the fiLtered audio. C339 couples the audio signat into T305 and aLso keeps DC
out of T305. T305 is an autoformer that transforms the I302 output impedance into 500ohms. R320 and
C370 keep I302 from any osciLLatory modes.
4.3.7.8 IF A6C AMP
The AGC circuit amplifies the DC component of the detected composite signal. R331 and C333 attenuate the
AC components of the composite signaL. The DC component is appLied to the input of the differential amp
9307 and 0308. R368, R334 and R333 set the attack point of the differential amp by biasing the base of
0308 to approximately 1.65VDC. 4308 is suppLying alL the current through R332 and the cotLector of 9308
will be Low. This Low coLlector voLtage demands near maximum gain from 1301. When the base of 0307 is
at 1.65VDC, 9307 turns on and emitter current is supptied to R332. This current from 0307 towers the
current that 0308 was supplying, thus raising the 0308 collector voltage. When the 0308 collector
voltage raises, 1301 gain is reduced.
4.3.7.9 RF A6C
The RF AGC is an integrator circuit with C341 and C342 as the feedback around the amplifier. The RF AGC
has a much slower response time than the IF A6C. The amplifier has two inputs: the variable or IF AGC
voltage and the reference or RF AGC set. The RF AGC set is adjusted so the ampLifier attacks at 50uv
(hard) RF input. As Long as the 0311 base voltage is lower than the 0309 base voltage, 0309 is supplying
aLL the emitter current through R343. This action makes the 0309 collector voltage less than when 0311
turned on. 0310 inverts the 0309 collector voltage; so that at Low signal inputs the RF AGC output
voltage appLied to G2 of 0301 is at the supply voltage or 9VDC.
4.3.7.10 Loop Filter
The phase detector output signaL passes into the loop fiLter. The output of the filter is essentiatty
pure DC, giving the VCO a clean spectrum with tow sideLobes. L306 and C344 resonate at 50KHz to filter
the reference and variable 50KHz off the tuning Line.
4.3.7.11 VCO
The VCO output is taken from the emitter of 9312. L308, C352, CR305, C347, C349, and C350 form the
resonant circuit. The varactor, CR305, is controtted by the output of the loop fiLter. This tuning
voltage varies the frequency of the VCO.
4.3.7.12 Receiver Buffer
0313 is the receiver buffer. The VCO signat is capacitvely coupted into the base of 0313. The output of
0313 is coupted into the counter buffer by C355 and into the mixer by C356.
4.3.7.13 Counter Buffer
0314 is the counter buffer. The 4314 coLLector drives the ECL divide by 10/11 divider on the digital
board through C359. The glidestope injection is also taken off the collector by C357.
Rev. 1, August 1981

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NAVI6ATION RECEIVER
4.3.7.14 Ringing Choke Switching Regulator (Power Supply Reference Figure 6-2)
DC current flowing through the primary of the power supply transformer, T101, is atternately switchel
and off by 0102. When current is flowing, energy is stored in the transformers magnetic field. Du
the off time this energy is coupted to the secondary. Current from four taps on the transfori
secondary are rectified and filtered to produce the voLtages needed by the KN 53.
Voltage regulation is performed by varying the duty cycle of the switching signal that drives 0102.
+9.0 voLt output is divided down to S.0V by a precision voltage divider R101 and R102. This voLtagi
compared by I102D to a 5.0V precision voLtage reference I101. The DC output of comparator I102D is
to control the voltage controtted osciLlator I102C. The timing capacitor C106 is continuatLy charged
discharged through R118. The output is a square wave with a constant Low time of approximateLy 14
and a variabLe high. This signaL is buffered by 0101 and used for base drive for the switc
transistor 0102. Other vottages are reguLated by the turns ratio of the secondary of T101.
R125 senses the peak current through the transformer's primary. The voltage developed across R125
compared to a voltage deveLoped from the +5V Line and resistive devices R106 and R107. When the KN 5
initially turned on the voLtage of the SV Line is zero. The voltage that is estabLished by the de
starts at zero and rises as the +5V tine rises. By doing this a soft start is achieved. Maximum
current with the +5V Line at 5V is about 6 amps.
The high voltage is current Limited by R123, CR109, CR110 and 4103. As the current drawn through
approaches .6V the transistor 0103 is turned off more. Maximum current is thus Limited at about 2
Limiting this current protects the dispLay drivers against momentary arcs in the dispLay.
The switched aircraft voLtage is divided by R108 and R109 and compared to the 5 volt precision refer
by I1028. If the switched aircraft voltage fatts below nine volts a reset pulse is sent to
microprocessor.
Rev. 1, August 1981

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NAVIGATION RECEIVER
4.3.8 GLIDESLOPE RECEIVER SECTION (Reference Figure 6-6)
0401 and 0402 are both dual gate FET RF ampLifiers. They are both AGC'd and they provide sufficient
isotation of the LocaL osciLlator from the antenna. L401, 402, and 403 are adjusted to provide the
required bandpass of 329.15 to 335.00MHz. 4403 is a dual gate FET mixer. It mixes the received RF with
the third harmonic of the glidesLope VCO output, yielding an intermediate frequency of 33.3KHz that
varies slightLy due to the dither of the VCO. Since the dither causes a VCO frequency modulation of
about +3KHz, the output frequency of the mixer witL vary +9KHz. This is to prevent an undesired Low
frequency beat.
The 33.3KHz bandpass filter, L404, L405, L406, c419, C420, C421, C422, C423, C424, and C425, setects the
desired mixer product and C426 couples the signal into I401. A MC1350 is used as an IF ampLifier (IA01)
and it provides 50dB of gain with 60dB of AGC. 0404 is a common emitter IF amplifier which drives the IF
detector. 0406 provides the 0.7V bias required by the active detector, 0405. The detected IF is sent to
the converter and also to the AGC amplifier. The course width adjust, R425, determines the amplitude of
the detected IF or "audio" reaching the converter active fiLters. 0407 provides a Low impedance source
to drive these filters.
0408 and 0409 form a temperature compensated differential amplifier which keeps the average detected IF
present at the base of 0409 equal to the DC reference voLtage present at the base of 0408. As the
amptitude of the detected IF increases, the 0409 voltage decreases untit it equals the vottage at the
base of 0408, at which time 0409 begins to conduct causing an increasing DC voltage at TP404 which
reduces the gain of IA01, holding the detected IF amptitude constant. If the RF signat strength is
increased, the AGC voltage at TP404 will continue to rise and at a point determined by the setting of
R435, causing 0410 to begin conducting. 0410 and 0411 form another differential amplifier such that when
0410 begins conducting, 0411 will begin reducing its conduction which reduces the current passing through
0411 thereby causing the RF AGC voltage at TP405 to drop. This reduces the gain of the two RF
amplifiers, 0401 and 0402. Therefore, R435 determines the RF signat strength at which IF AGC stands
still and Lets the RF AGC action take over. This is to allow the noise figure to improve before RF AGC
action begins. If the RF input signat shouLd increase to the extent that att RF AGC action is expended,
then the IF AGC will resume control. The RF AGC action is desirable as soon as practical to attenuate
aLL undesired received signats before they reach the mixer.
0413, the VCO transistor, is resonated by T401, C444, C443, C442, and CR401. The varactor, CR401 is
controlled by the output of the loop filter. This tuning voltage varies the frequency of the VCO. When
the VCO controt voltage is high, the oscittator is running at Lower frequencies and when it is Low the
osciLLator is running at higher frequencies.
One of the VCO outputs is coupted into the buffer stage 0414 by C447. 0414 is biased by 0415 and L407 so
that its output witt be rich in harmonics. This signat is coupted into Gate 2 of the mixer 0403 by c415.
The mixer uses the third harmonic of this VCO injection mixed with the incoming signal to generate the
33.3KHz IF signal.
The other VCO output is tapped down from the VCO emitter by R442 and R443. This signal is mixed with the
glidestope injection signal from the navigation receiver VCO. 0416 is the loop mixer FET. C455 and L409
filter the mixer product that varies from 9.465MHz to 14.556MHz (depending on the channet selected). The
filtered signat is buffered by 9417 and 0418 before it is sent to the gLidestope synthesizer. CR403 and
R460 bias 0417 and 0418 at a 5 volt supply so that the computer injection signal is compatible with the 5
volt TTL counters on the digital board.
The +9V supply to the glidesLope board is switched on by the digitat board transistor 0604. The
glidestope receiver will only be energized when an ILS channet is displayed in the "USE" window. These
channets and the frequency scheme of the KN 53 glidestope system are shown in Tabte 4-7.
Rev. 1, August 1981

MMOO40-7 Page 4-40
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NAVIGATION RECEIVER
NAV FREG
ACTIVE LOC NAV VCO GS REC GS LO GS VCO LOOP MIXEF
FREG (MHz) (MHz) (MHz) (MHz) (MHz
(MHz) E407 J533 GSVCO x 3 TP906 TP901
108.10 97.00 334.700 334.666 111.556 14.55¢
108.15 97.05 334.550 334.517 111.506 14.454
108.30 97.20 334.100 334.067 111.356 14.15¿
108.35 97.25 333.950 333.917 111.306 14.05(
108.50 97.40 329.900 329.867 109.956 12.55(
108.55 97.45 329.750 329.717 109.906 12.45(
108.70 97.60 330.500 330.467 110.156 12.55(
108.75 97.65 330.350 330.317 110.106 12.45(
108.90 97.80 329.300 329.267 109.756 11.954
108.95 97.85 329.150 329.117 109.706 11.85¢
109.10 98.00 331.400 331.367 110.456 12.454
109.15 98.05 331.250 331.217 110.406 12.35¿
109.30 98.20 332.000 331.967 110.656 12.45¢
109.35 98.25 331.850 331.817 110.606 12.35¢
109.50 98.40 332.600 332.567 110.856 12.454
109.55 98.45 332.450 332.417 110.806 12.354
109.70 98.60 333.200 333.167 111.056 12.45(
109.75 98.65 333.050 333.017 111.006 12.35¿
109.90 98.80 333.800 333.767 111.256 12.45(
109.95 98.85 333.650 333.617 111.206 12.35¿
110.10 99.00 334.400 334.367 111.456 12.45¢
110.15 99.05 334.250 334.217 111.406 12.35¿
110.30 99.20 335.000 334.967 111.656 12.45¢
110.35 99.25 334.850 334.817 111.606 12.35¿
110.50 99.40 329.600 329.567 109.856 10.45(
110.55 99.45 329.450 329.417 109.806 10.35¿
110.70 99.60 330.200 330.167 110.056 10.45(
110.75 99.65 330.050 330.017 110.006 10.35¿
TABLE 4-7 GS FREQUENCYTABLE

(Sheet 1 of 2)
Rev. 1, August 1981
MMOO40-7
Pana -&1
KING
KN 53
NAVIGATION RECEIVER
NAV FREQ
ACTIVE LOC NAV VCO GS REC GS LO GS VCO LOOP MIXER OUT
FREG (MHz) (MHz) (MHz) (MHz) (MHz)
110.90 99.80 330.800 330.767 110.256 10.456
110.95 99.85 330.650 330.617 110.206 10,356
111.10 100.00 331.700 331.667 110.556 10.556
111.15 100.05 331.550 331.517 110.506 10.456
111.30 100.20 332.300 332.267 100.756 10.556
111.35 100.25 332.150 332.117 110.706 10.456
111.50 100.40 332.900 332.867 110.956 10.556
111.55 100.45 332.750 332.717 110.906 10.456
111.70 100.69 333.500 333.467 111.156 10.556
111.75 100.65 333.350 333.317 111.106 10.456
111.90 100.80 331.100 331.067 110.356 9.556
111.95 100.85 330.950 330.917 110.306 9.456

(Sheet 2 of 2)
Rev. 1, August 1981
MMOO40-7 Page 4-42
KING
KN 53
NAVIGATION RECEIVER
4.3.7.14 Ringing choke Switching Reguiator (Power Suppby Reference Figure 6-2)
DC current fbowing through the primary of the power suppby transformer, T101, is akternateiy switche
on and off by 0102. When current is flowing, energy is stored in the transformers magnetic fiel<
During the off time this energy is couphed to the secondary. Current from four taps on the transformer
secondary are rectified and fiktered to produce the voitages.needed by the KN 53.
Voitage regulation is preformed by varying the duty cycle of the switching signai that drives 0102. TP
+9.0 voit output is divided down to 5.OV by a precision voltage divider R101 and R102. This voltage -
compared by I102D to a 5.0V precision voitage reference 1101. The DC output of comparator I1002D is use
to contros the voktage controbbed oscikkator I102C. The timing capacitor C106 is continually charged ar
discharged through R118. The output is a square wave with a constant how time of approximately 14mst
and a variabie high. This signak is buffered by 0101 and used for base drive for the switchir
transistor 0102. Other voltages are reguiated by the turns ratio of the secondary of T101.
R125 senses the peak through the transformer's

current primary. The voitage devekoped across R125 -
compared to a voltage devekoped from the +5V iine and resistive devices R106 and R107. When the KN 53 -
initiaiky turned on the voitage of the 5V line is zero. The voltage that is established by the devit
starts at zero and rises as the +5V iine rises. By doing this a soft start is achieved. Maximum pe
current with the +5V iine at 5V is about 6 amps.
The high voitage is current kimited by R123, CR109, CR110 and 0103. AS the current drawn through R1
approaches .6V the transistor 0103 is turned off more. Maximum current is thus limited at about 25m
Limiting this current protects the dispiay drivers against momentary arcs.in the display.
The switched aircraft voltage is divided by R108 and R109 and compared to the 5 voit precision referent
by I102B. If the switched aircraft voitage fai§s below nine volts a reset puise is sent to ti
microprocessor.
MMOOO3 Page 4-43

KING
KN 53
NAVIGATION RECEIVER ,-
4.3.8 GLIDESLOPE RECEIVER SECTION (Reference Figure 6-6)
0401 and 0402 are both duai gate FET RF ampkifiers. They are both AGC'd and they provide sufficient
isokation of the hocal oscibiator from the antenna. L401, 402, and 403 are adjusted to provide.the
required bandpass of 329.15 to 335.00MHz. 0403 is a dual gate FET mixer. It mixes the received RF with
the third harmonic of the giideskope VCO output, yiehding an intermediate frequency of 33.3KHz that
varies siighthy due to the dither of the VCO. Since the dither causes a VCO frequency modulation of
about
freque¯cy+3KHz, the output frequency of the mixer wiki vary +9KHz. This is to prevent an undesired how
beat.
The 33.3KHz bandpass fitter, L404, L405, L406, C419, C420, C421, 0422, 0423, 0424, and C425, seiects the
desired mixer broduct and C426 couples the signal into IA01. A MC1350 is used as an IF ampiifier (IA01)
and it provides 50dB of gain with 60dB of AGC. 0404 is a common emitter IF ampkifier which drives the IF
detector. 0406 provides the 0.7V bias required by the active detector, 9405. The detected IF is sent to
the converter and aiso to the AGC ampkifiers The course width adjust, R425, determines the amphitude of
the detected IF or "audio" reaching the converter active filters. 0407 provides a bow impedance source
to drive these fikters.
0403 and 0404 form a temperature compensated differentiak ampiifier which keeps the average detected IF
present at the base of 9409 equai to the DC reference voitage present at the base of 0408. As. the
amphitude of the detected IF increases, the 0409 voltage decreases until it equais the voitage at the
base of 0408, at which time 0409 begins to conduct causing an increasing DC voitage at TP404 which
reduces the gain of 1401, hobding the detected IF amplitude constant. If the RF signai strength is
increased, the AGC voltage at TP404 wiki continue to rise and at a point determined by the setting of
R435, causing 0410 to begin conducting 0410 and 0411 form another differentiak amplifier such that when
0410 begins conducting, 0411 wiki begin reducing its conduction which reduces the current passing through
0411 thereby causing the RF AGC voitage at TPAD5 to drop. This reduces the gain of the two RF
ampiifiers, 0401 and 0402. Therefore, R435 determines the RF signai strength at which IF AGC stands
stiti and hets the RF AGC action take over. This is to a§§ow the noise figure to improve before RF AGC
action begins. If the RF input signal shouãd increase to the extent that aki RF AGC action is expendeg,-
then the IF AGC wiki resume controb. The RF AGC action is desirable as soon as practical to attenua
aik undesired received signais before they reach the mixer.
0413, the VCO transistor, is resonated by T401, C444, C443, C442, and CR401. The varactor, CR401 is
controbbed by the output of the koop filter. This tuning voltage varies the frequency of the VCO. When
the vc0 controi voitage is high, the oscillator is running at lower frequencies and when it is how the
oscillator is running at higher frequencies.
One of the VCO outputs is coupbed into the buffer stage 0414 by C447. 0414 is biased by 0415 and LA07 so
that its output wiki be rich in harmonics. This signak is coupied into Gate 2 of the mixer 0403 by CA15.
The mixer uses the third harmonic of this VCO injection mixed with the incoming signai to generate the
33.3KHz IF signab.
The other VCO output is tapped down from the VCO emitter by R442 and R443. This signat is mixed with the
gbidestope injection signab from the navigation receiver VCO. 0416 is the loop mixer FET. C455 and L409
fikter the mixer product that varies from 9.465MHz to 14.556MHz (depending on the channei sebected). The
filtered signal is buffered by 0417 and 0418 before is is sent to the gkideskope synthesizer. CR403 and
R460 bias 0417 and 0418 at a 5 voit suppby so that the computer injection signai is compatible with the 5
voit TTL counters on the digital board.
The +9V suppby to the gbideskope board is - switched on by the digitai board transistor 0604. The
gkides§ope receiver wiki oniy be energized when an ILS channeV is displayed in the "USE" window. These
channebs and the frequency scheme of the KN 53 giideskope system are shown in Tabie 4-7.
MMOOO3 Page 4-44

KING
KN 53
NAVIGATION RECEIVER
NAV FREQ
ACTIVE LOC NAV VCO GS REC GS LO GS VCO LOOP MIXER Ol
FREQ (MHz) (MHz) (MHz) (MHz) (MHz)
(MHz) E407 JS33 GSVCO x 3 TP906 TP907
108.10 97.00 334.700 334.666 111.556 14.556
108.15 97.05 334.550 334.517 111.506 14.456
108.30 97.20 334.100 334.067 111.356 14.156
108.35 97.25 333.950 333.917 111.306 14.056
108.50 97.40 329.900 329.867 109.956 12.556
108.55 97.45 329.750 329.717 109.906 12.456
108.70 97.60 330.500 330.467 110.156 12.556
108.75 97.65 330.350 330.317 110.106 12.456
108.90 97.80 329.300 329.267 109.756 11.956
108.95 97.85 329.150 329.117 109.706 11.856
109.10 98.00 331.400 331.367 110.456 12.456
109.15 98.05 331.250 331.217 110.406 12.356
109.30 98.20 332.000 331.967 110.656 12.456
109.35 98.25 331.850 331.817 110.606 12.356
109.50 98.40 332.600 332.567 110.856 12.456
109.55 98.45 332.450 332.417 110.806 12.356
109.70 98.60 333.209 333.167 111.056 12.456
109.75 98.65 333.050 333.017 111.006 12.356
109.90 98.80 333.800 333.767 111.256 12.456
109.95 98.85 333.650 333.617 111.206 12.356
110.10 99.00 334.400 334.367 111.456 12.456
110.15 99.05 334.250 334.217 111.406 12.356
110.30 99.20 335.000 334.967 111.656 12.456
110.35 99.25 334.850 334.817 111.606 12.356
110.50 99.40 329.600 329.567 109.856 10.456
110.55 99.45 329.450 329.417 109.806 10.356
110.70 99.60 330.200 330.167 110.056 10.456
110.75 99.65 330.050 330.0017 110.006 10.356
TABLE 4-7 G5 FREQUENCYTABLE

(Sheet 1 of 2)
MMOOO3 Page 4-45

KING
KN 53
NAVIGATION RECEIVER
ACTIVE LOC NAV VCO GS REC GS LO GS VCO LOOP MIXER OUT

FREG (MHz). (MHz) (MHz) (MHz) (MHz)
110.90 99.80 330.800 330.767 110.256 10.456
110.95 99.85 330.650 330.617 110.206 10.356
111.10 100.00 331.700 331.667 110.556 10.556
111.15 100.05 331.550 331.517 110.506 10.456
111.30 100.20 332.300 332.267 100.756 10.556
111.35 100.25 332.150 332.117 110.706 10.456
111.50 100.40 332.900 332.867 110.956 10.556
111.55 100.45 332.750 332.717 110.906 10.456
111.70 100.69 333.500 333.467 111.156 10.556
111.75 100.65 333.350 333.317 111.106 10.456
111.90 100.80 331.100 331.067 110.356 9.556
111.95 100.85 330.950 3300.917 110.306 9.456

(Sheet 2 of 2)
MMOOO3 Page 4-46

SERVICEBULLETIN
RADIO
, SERVICE
SALES BULLETIN NO. KN 53-1
EFFECTIVITY
KN 53 serial number 1979 and below.
REASON
To reduce local oscillator radiation from the glideslope antenna

wnich tenös to desensitize a second glideslope receiver in the
same aircraft when both are channeled to the same frequency.
DESCRIPTION
This modification consists of removing and replacing the glide-

slope receiver assembly with a factory modified assembly.
COMPLIANCE
Required on all KN 53's with the glideslope option, KPN

066-1067-00, when installed in dual glideslope installations. Not
required on KN 53's without glideslope option, KPN 066-1067-01.
WARRANTY INFORMATION
Warranty credit or payment will be issued for this modification if

the unit is still under the original new product warranty and the
moóification is completed by an appropriately rated King Service
Center. A properly completed warranty claim for 1.5 hours labor
plus parts may be submitted.
APPROVAL
Conforms to FAA TSO C40a DO 153, C36c Class D Cat. II DO 131, and
C34c Class D Cat. II DO 132.
MANPOWER
One and one-half (1.5) hours.
REFERENCES
KN 53 Maintenance/Overhaul Manual, KPN 006-5174-00.
DATE: July, 27, 1979 KN 53-1

SB0004-38 KPN 600-1162-10 PAGE: 1 of 4
MODIFICATION PROCEDURE
l. Remove the top cover by removing the two (2) screws on each
side and one (1) screw on the top.
2. Unsolder the jumper wires from E407 and E408. (Refer to
Figure 1 of this bulletin.)
3. Remove the three (3) pan head screws from the corners of the
glideslope receiver board and the one (1) flat head screw from
the rear plate.
4. Lift the glideslope receiver board straight up.
5. Install the new glideslope board, KPN 200-6075-00, which is
marked mod 1 on the mod status tag, by following steps l
through 4 of this bulletin in reverse order.
TESTING PROCEDURE
1. Align the glideslope in accordance with Section 5.2.3.4, Page

5-14 of the KN 53 Maintenance/Overhaul Manual.
2. Perform a functional test in accordance with Section 5.2.2,
Page 5-5 of the KN 53 Maintenance/Overhaul Manual.
IDENTIFICATION PROCEDURE
Stamp an "X" on the mod status tag to indicate Mod 1 is complete.
MATERIAL INFORMATION
The only part necessary to modify one (1) KN 53 per this service
bulletin is listed below.
KING PART NUMBER QUANTITY AON PRICE DESCRIPTION
200-6075-00 1 $350.00 Glideslope Receiver
Price Subject to Change
DATE: July, 27, 1979 KN 53-1
SBOOO4-38 KPN 600-1162-10 PAGE: 2 of 4

SERVICE BULLETIN
RADIO
SERVICE
SALES
E408 E407-
I
4
4 I
MO 2 3 o&
KN 53 GLIDESLOPE BOARD AFTER MOD 1

FIGURE 1
DATE: July, 27, 1979 53-1

KN
SBOOO4-38 KPN 600-1162-10 PAGE: 3 of 4
SERVICEBULLETIN
RADIO
SERVICE
VOR/ILS Receiver
EFFECTIVITY
066-1067-00 serial number 2549 and below.

066-1067-01 serial number 50875 and below.
REASON
To improve power supply starting ability and reliability.
DESCRIPTION
This modification consists of changing 0102, Rl20, Rl21 and adding

CR103 and R122.
COMPLIANCE
This service bulletin should be incorporated in the event of a

power supply failure or during normal maintenance.

modification is completed by an appropritly rated King service
center. A properly completed warranty claim for 2.5 hours labor
plus parts maybe submitted.
APPROVAL
Conforms to FAA TSO C40a, DOl53: C36c Class D Cat II DO131; C34c
class D Cat II DO-132; DO 160 A1D1/A/PS/xxxxxxABABA
MANPOWER
Two and a half hours (2.5) including testing.
REFERENCES
Refer to KN 53 Maintenance/Overhaul Manual, KPN 006-5174-00.
1. Place unit on bench. Remove top cover by extracting the four

(4) KPN 089-6004-03 flat head screws from the side rails and
the one (1) KPN 089-6004-03 flat head screw from the top
cover.
DATE: October 8, 1980 KN 53-2
SBOOO6-l5 KPN 600-1162-20 PAGE: 1 of 5

2. Remove power supply board. This is accomplished by removing
four (4) KPN 089-58874-03 screws that hold the power supply
cover KPN 047-4750-01. Remove cover. Next remove the four (4)
standoff's, KPN 076-0171-07, and the KPN 089-6298-03 flathead
screw in the side rail. The power supply board will now lift
straight up out of the chassis.
3. Refer to Fig. 1 (Parts Layout)
4. Remove Ql02, KPN 007-0230-05, and replace with KPN 007-0381-02.
5. Solder the new diode CRIO3, KPN 007-6105-00, from the collector
of Q102 (middle lead) to ground side of Rl20. Use teflon
sleeving on diode lead attached to 0102.
6. Remove R120, an 18 ohm resistor, KPN 130-0180-23, and replace
it with a 120 ohm resistor, KPN 130-0121-23.
7. Remove Rl21, a 12 ohm resistor, KPN 130-0120-23, and replace it
with a 68 ohm resistor, KPN 130-0680-23.
8. To add Rl22 (KPN 130-0102-23), unsolder the base lead (center
lead) of 0101. Pull the lead straight up. Install one end of
Rl22 into the hole vacated by the base lead of Ql01. Solder
and trim excess lead length. Next wrap together the base lead
of Ql01 and the remaining lead of Rl22, solder and trim.
9. Refer to Fig. 2 (Backside of Board).
10. Turn the board over. Locate the ungrounded end of Rl20. Add a
piece of insulated wire to this end and solder it to the end of
R121 that connects to the emitter of Ql01.
11. The circuit foil must now be cut at the ungrounded end of Rl20
where the insulated wire was added. This will leave a small
amount of circuit foil around the lead of Rl20 just to secure
it to the board.
12. This completes the modification. The radio should be reassem-
bled and tested for proper operation as outlined in Section
5.2.2 page 5-5 of the KN 53 Manual.
Stamp an "X" on the mod status tag to indicate Mod 2 is complete.
A parts kit is available under KPN 050-1905-00 to fully modify one

(1) KN 53 per this service bulletin. This kit contains the
following items:
007-0381-02 1 Transistor
007-6105-00 1 Diode
130-0121-23 1 120 ohm Resistor
130-0680-23 1 68 ohm Resistor
130-0102-23 1 1K ohm Resistor
$ 9.40 Price Subject to Change
SBOOO6-15 KPN 600-1162-20 PAGE: 2 of 5

SERVICE BULLETIN
RADIO
SERVICE
SALES
FIGURE 1: Parts Layout

SBOOO6-15 KPN 600-1162-20 PAGE: 3 of 5
Install mag
wire here
Cut path
here
FIGURE 2: Backside of board
SBOOO6-15 KPN 600-1162-20 PAGE: 4 of 5

SERVICEBIJLLETIN
SERVICE
SALES BULLETIN NO. KN 53-3 Revised
EFFECTIVITY
KN 3 o l number 3500 and below
REASON
To improve the stability of the Glideslope D-Bar . Some units will

display a jittery Glideslope D-Bar at some input voltages between
11 VDC and 33 VDC induced by radiated noise from the power supply.
DESCRIPTION
This modification consists of adding a shield under the power

supply board and changing the length of the power supply cover
stand offs.
Serial number 3319 and below need both, the shield and shorter
standoffs. Serial number 3320 through 3500 need only the shorter
standoffs.
COMPLIANCE
Required on all KN 53's with Glideslope option, KPN 066-1067-00.

Not required on KN 53's without Glideslope option, KPN
066-1067-01.

the modification is completed by an appropriately rated King
Service Center. A properly completed warranty claim for 1.5 hours
labor plus parts may be submitted. To insure payment the claim
must be marked to show that KN 53 mod 3 revised was performed.
APPROVAL
Conforms to FAA TSO C40a DOl53, C36c class D Cat. II DO 131, and
C34c class D Cat. II DO 132.
MANPOWER
REFERENCES
Date: June 20, 1980 KN 53-3

Rev. 1, March 13,.1981
SBOOO6-30 KPN 600-1162-31 Page: 1 of 2
MODIFICATION.PROCEDURE
1. Refer to page 5-16, Section 5.3.4, Disassembly Procedures, and

page 6-5, Figure 6-1 for the following steps.
2. Remove the top cover.
3. Remove the Power Supply cover, KPN 047-4750-01.
4. Remove the plug in the Power Supply Assembly, KPN 200-6074200.
5., Install the shield,

new (with .insulator), KPN 047-5633-02, so
that the four screw holes line up with the swedge nuts in the
chassis. The shield extends horizontally under the Power
Supply Board and vertically between the Power Supply and
G1ideslope Board.
6. Reinstall-the Power Supply Assembly and covers using the four

I (4) shorter standoffs, KPN 076-0171-11.
7. Per.form functional test.
TESTING PROCEDURE
Perform funtion test in accordance with page 5-5, Section 5.2.2 of

the KN 53 Maintenance/Overhaul Manual, KPN 006-5174-00.
Stamp an "X" on the mod status tag to indicate mod 3 is complete.
All parts necessary to modify one (1) KN 53 per this service

bulletin are listed below:
KING PART NUMBER QUANTITY AON PRICE DESCRIPTION.
047-5633-02 1 $16.40 Power Supply Shield

076-0171-11 4 1.10 ea. Standoff
Date: June 20, 1980 KN 53-3

Rev. 1, March 13, 1981
SB0006-30 KPN 600-1162-31 Page: 2 of 2
SERVICEBULLETIN
SERVICE
SALES
SERVICE BULLETIN: KN 53-4
Nav Receiver
EFFECTIVITY
KN 53, KPN 006-1067-00, serial numbers 3664 and below.

REASON
To prevent the KN 53 from loading the DME common and causing DME
mis-channeling when the KN 53 is turned off.
When the KN 53 is used a channeling

as source for a KN 63 or
KDM 706 and the power is removed, the KN 53 DME common becomes a
low impedance on the output of the master indicator, KDI 572, KDI
574, or KPI 553A.
DESCRIPTION
This modification consists of adding a diode CR501 and changing

the value of R501, R502, R503, R568, R569.
COMPLIANCE
Recommended when the KN 53 is

used as part of a NAV 1 -
NAV 2
channeling of a KN 63 or KDM 706.
Warranty payment
credit or
will be issued for this modification if
the unit is under
still the original new product warranty and the
modification is completed by an appropriately rated King Service
APPROVAL
Conforms to FAA TSO C40a DO 153, C36a Class # CAT II DO 131, and
034c Clas D CAT II DO 132.
MANPOWER
One and one-half (1.5) hours, including testing.
REFERENCES
Date: August 3, 1981 KN 53-4
SB0006-45 KPN 600-1162-40 Page: 1 of 5

1. Remove the bottom cover of the KN 53.

2. Remove the Digital Board from the KN 53. Refer to Paragraph
5.3.4.6, Page 5-17 of the KN 53 Maintenance/Overhaul Manual
for removal instructions.
3. Locate and cut the printed circuit path on the back side of
the Digital
Board between L511 AND R501.
4. Install the
new CR501 diode, KPN 007-6046-05, on the top side
of the circuit board between L511 and R501 as shown in Figure
1. Wrap the CR501 diode leads around the component leads of
L511 and R501 with the cathode connected to L511.
5. Locate and replace the following resistors
with the value shown below: (Refer to Figure 1 for parts
location.
A. R501 from a 5.1K to a 1K KPN 130-0102-23

B. R502 from a 10K to a 4.3K KPN 130-0432-23
C. R503 from a 10K to a 2K KPN 130-0202-23
D. R568 from a 10K to a 5.6K KPN 130-0562-23
E. R569 from a 10K to a 2K KPN 130-0202-23
6. Reassemble unit and test.

TESTING PROCEDURE
Test the radio in accordance with Section 5.2.2 of the maintenance

manual.

007-6046-05 1* $.26 ea. Diode 1N916

130-0102-23 1* .30 ea. Resistor FC 1K QW 5%
130-0432-23 1* .30 ea. Resistor FC 4.3K QW 5%
130-0562-23 1* .26 ea. Resistor FC 5.6 QW 5%
* Minimum order quantity 10
Prices subject to change

SBOOO6-45 KPN 600-1162-40 Page: 2 of 5
SERVICE BULLETIN
RADIO
SERVICE
SALES
FIGURE 2
KN 53 Digital Board Artwork (Farside)
SBOOO6-45 KPN 600-1162-40 Page: 4 of 5

SERVICEBULLETIN
RADIO
SERVICE
Navigation Receiver
EFFECTIVITY
KN 53, 066-1067-00, serial numbers 4431 and below.

KN 53, 066-1067-01, serial numbers 52244 and below.
REASON
To eliminate a mechanical interference between the unit panel lock

device and R558. When the KN 53 panel lock is over tightened into
the panel, the cover can flex and allow the lock device to short
R558 to ground, rendering the KN 53 inoperative.
DESCRIPTION
This modification consists of moving R558 to allow more clearance

for the panel lock device.
COMPLIANCE
Recommended whenever the above mentioned condition is noticed or

during normal maintenance.

Center. A properly completed warranty claim for 1.0 hour labor
APPROVAL
Conforms to FAA TSO C40a, DOl53; C36c, Class D, Cat. II, DOl31;
and C34c, Class D, Cat. II, DOl32.
MANPOWER
REFERENCES

SBOOO7-55 KPN 600-1162-50 Page: 1 of 3
1. Remove the bottom cover.

2. Locate and remove R558, a 10K ohm, QW, 5% resistor. (Refer to
Figure 1 for parts location.)
3. Install the new R558, a 10K ohm, EW, 5% resistor, KPN
131-0103-13, as shown in Figure 1, from one of the original
pads to the collector lead of Q504.
4. Cut the circuit path beside Q504, as shown in Figure 1, to
prevent possible shorting to panel lock device on the bottom
cover.
5. Reassemble the unit and perform a functional test.
TESTING PROCEDURE
Perform a functional test in accordance with Section 5.2, Page 5-1

of the KN 53 Maintenance/Overhaul Manual.
Stamp and "X" on the mod status tag to indicate mod 5 is complete.

131-0103-13 1 $ .28
ea* 10K, ohm, EW, 5% Res.
* 10.
Minimum Order Quantity
Price Subject to Change.

SBOOO7-55 KPN 600-1162-50 Page: 2 of 3
o
Cut path here
Move resistor here
es esos
O 604
$501
0530
CO3
coo9 os
25
SI
Iso
4oi
coeeeeeeeeeeeeeeeeeg e -
L
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--R558
-GUT PATM
1507
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E 2 -
L5t8 C 532 E113 P 02
2 13 303
1519
1517 152t 152
YSOI ISOS 1510 GR5p
CR508
L-MINAU
SERVICE BULLETIN: KN 53-4
Nav Receiver
EFFECTIVITY

REASON
To prevent the KN 53 from loading the DME common and causing DME
mis-channeling when the KN 53 is turned off.
When the KN 53 is used as a channeling source for a KN 63 or

KDM 706 and the power is removed, the KN 53 DME common becomes a
low impedance on the output of the master indicator, RDI 572, KDI
574, or KPI 553A.
DESCRIPTION
This modification consists of adding a diode CR501 and changing

the value of R501, R502, R503, R568, R569.
COMPLIANCE
Recommended when the KN 53 is used as part of a NAV 1 -

NAV 2
channeling of a KN 63 or KDM 706.

APPROVAL
Conforms to FAA TSO C40a DO 153, C36a Class # CAT II DO 131, and
C34c Clas D CAT II DO 132.
MANPOWER
One and one-half (1.5) hours, including testing.
REFERENCES

SBOOO6-45 KPN 600-1162-40 Page: 1 of 5
1. Remove the bottom cover of the KN 53.

2. Remove the Digital Board from the KN 53. Refer to Paragraph
5.3.4.6, Page 5-17of the KN 53 Maintenance/Overhaul Manual
for removal instructions.
3. Locate and cut the printed circuit path on the back side of
the Digital Board between L511 AND R501.
4. Install the new CR501 dioder KPN 007-6046-05, on the top side
of the circuit board between L511 and R501 as shown in Figure
1. Wrap the CR501 diode leads around the component leads of
L511 and R501 with the cathode connected to L511.
5. Locate and replace the following resistors
with the value shown below: (Refer to Figure 1 for parts
location.
A. R501 from a 5.lK to a 1K KPN 130-0102-23

B. R502 from a 10K to a 4.3K KPN 130-0432-23
C. R503 from a 10K to a 2K KPN 130-0202-23
D. R568 from a 10K to a 5.6K KPN 130-0562-23
E. R569 from a 10K to a 2K KPN 130-0202-23
6. Reassemble unit and test.

TESTING PROCEDURE
Test the radio in accordance with Section 5.2.2 of the maintenance

manual.


007-6046-05 1* $.26 ea. Diode 1N916

130-0432-23 1* .30 ea. Resistor FC 4.3K Qw 5%
130-0562-23 1* .26 ea. Resistor FC 5.6 QW 5%
* Minimum order quantity 10
Prices subject to change

SBOOO6-45 RPN 600-1162-40 Page: 2 of 5
Replace these o la
resistors
ste NOTE 7
SEE Nort 9
oso 2316 oo
oom-nory-o!-
oss 214o-oct2
Et NOTE"9 stE NOTE 6" e-ooo2 ootsi oso 2323-09
oss 5438-o*2
tapecs1 EtooPusEDTosEcunEwinti
FIGURE 1
KN 53 Digital Board Parts Layout
8150006-45 KPN 600-1162-4.0 . Page: 3 of 5
FIGURE 2
KN 53 Digital Board Artwork (Farside)
520006-45 KPN 600-1162-40 Page: 4 of 5

KN 53 Digital Board Schematic
Date: August 3, 1981 KN 53-·4
880006-45 KPN 600-1162-40 ADDENDUM
BIJLLETIN
SERVICE
RADIO
SERVICE
Navigation Receiver
Subject: There is NOT a Service Bulletin issued covering the Mod

6 status which has been mistakenly stamped as complete
on some KN 53 units. In the interest of conforinity, the
KN 53-6 Service Bulletin number will not be assigned.

SBOOO7-52 KPN 600-1162-60 Page: 1 of 1
BULLETIN
SERVICE
SERVICE
Navigation Receiver
EFFECTIVITY
KN 53, KPN 066-1067-00, above serial number 4484 but below serial
number 4641.
KN 53, KPN 066-1067-01, above serial number 52249 but below serial
number 52549.
This modification may be installed in lower serial number units if

DME channeling problems are suspected.
REASON
To correct DME channeling. Leakage through the DME channeling

transistors can prevent the outputs from reaching an effective
HIGH state.
DESCRIPTION
This modification consists of changing CR515, CR516 and CR517 and

adding eight (8) diodes, CR611 through CR618.
COMPLIANCE
Recommended for all units where DME channeling is complained of

being inoperative or intermittent. This modification is most
necessary in the above mentioned serial numbers where I503, I504
and I505 have been replaced by discrete transistors 0509-0521.

APPROVAL
Comforms to FAA TSO C40a, DOl53; C36c, Class D Cat, II, DOl31; and
C34c, Class D, Cat. II, DOl32.
SBOOO7-56 KPN 600-1162-70 Page: 1 of 4

MANPOWER
One and one half (1.5) hours.
REFERENCES
1. Remove thebottom cover.

2. Locate and replace CR515, CR516, and CR517, 1N4154 diodes,
with 1N270 diodes, KPN 007-6033-00. (Refer to Figure 1 for
parts location.)
3. Install a 1N270 diode, KPN 007-6033-00, across each of the
eight (8) resistors, R505 through R512. Connect the cathodes
to the collector of Q507 and the anodes to the microprocessor
outputs. (Refer to Figure 1 for parts location.)
4. Reassemble the unit and perform functional test.
TESTING PROCEDURE
Perform a functional test in accordance with Section 5.2, Page 5-1

of the KN 53 Maintenance/Overhaul Manual.
Stamp and "X" on the mod status tag to indicate mod 7 is complete.

bulletin are listed below.
007-6033-00 11 $ 1.00 ea. 1N270, Diode
Price Subject to Change
SBOOO7-56 KPN 600-1162-70 Page: 2 of 4

SERVICE BULLETIN
RADIO
SERVICE
SALES
LSO4 050/
CRS
ddethe
CS &O c 609
es 4 shown .
L5 C CR61
L5 C
C
C CR61)
L
L50 C
L5 2
C
R504
L5 C 4
R517 2613
Leo C E514
R6l L519
L5 C 7 521 Replace with
L5 C 6 1N 270 diodes
E512 P302 (KPN 007-6033-00)
3
C $29 7 5 3 I
P¾
dd ese
CRS 5
516 shown.
CR6f 7
519
CR6l
C 53 574
R61
SIO RO73
CR '
I 506 F
CR
13
FIGURE 1
KN 53 Digital Board Parts Layout (Partial)
SBOOO7-56 KPN 600-1162-70 Page: 3 of 4

KING
KN 53
NAVIGATION RECEIVER
TABLE
OF CONTENTS
SECTION
Y
MAINTENANCE
Paragraph
5.1 Generat Information
5.2 Test Procedures

5,2.1 Test Equipment Required
5.2.2 Test Procedures
5.2.2.1 Standard Test Signal Description
5.2.2.2 Power Supply Tests
5.2.2.3 NAV Receiver
5.2.2.4 Localizer Characteristics
5.2.2.5 GLidesLope Characteristics
5.2.3 Alignment
5.2.3.1 Atignment conditions
5.2.3.2 NAV Receiver and Synthesizer ALignment
5.2.3.3 Dimmer Adjust
5.2.3.4 Glidestope Board Alignment Procedure
5.3 Overhaut
5.3.1 Inspection
5.3.2 Cleaning
5.3.3 Repair
5.3.4 Disassembly Procedures
5.3.4.1 Top Cover Removat
5.3.4.2 Bottom Cover Removat
5.3.4.3 Power Supply Removat
5.3.4.4 NAV Receiver Removat
5.3.4.5 Glidestope Receiver Removat
5.3.4.6 Digital Board Removat
5.4 Troubleshooting
5.4.1 System Troubleshooting
5.4.2 Power Supply Troubleshooting
5.4.3 NAV Synthesizer Troubleshooting
5.4.4 Glidestope Troubleshooting
5.4.5 Display Troubleshooting
5.4.6 Processor Troubleshooting
5.4.7 NAV Receiver Troubleshooting
LISTOF ILLUSTRATIONS
Figure
5-1 KN 53 Test Fixture

5-2 Alignment Adjustment Locations
5-3 KN 53 System Troubleshooting Flowchart
5-4 Power Supply Troubleshooting Flowchart
5-5 NAV Synthesizer Troubleshooting Flowchart
5-6 Glidestope Troubleshooting Flowchart (3 sheets)
5-7 Display Troubleshooting FLowchart (2 sheets)
5-8 Processor Troubleshooting Flowchart
5-9 NAV Receiver Troubleshooting Flowchart (2 Sheets)
5-10 KN 53 Internal Interconnect
5-i
Rev. 1, August 1981
MMOO40-8
KING
KN 53
NAVIGATION RECEIVER
SECTION
V
MAINTENANCE
INFORMATION
5.1 GENERAL
This section contains test, alignment, inspection, cleaning, repair, and troubleshooting procedures for
the KN 53. Included are detailed assembly/disassembly instructions and troubleshooting flowcharts.
Information concerning semiconductor test equipment, semiconductor and integrated circuit maintenance,
and specific integrated circuits used in the KN 53 may be found in Appendix A at the end of this manual.
It is suggested that Appendix A be consulted before attempting to service the KN 53.
5.2 TEST PROCEDURES

The test procedures of Section 5.2.2 may be followed to determine if the KN 53 is operating properly. If
it is not, the alignment procedures are given to bring the KN 53 up to minimum performance standards.
5.2.1 TEST EQUIPMENT REQUIRED
The following test equipment or equivalent is needed to align and troubleshoot the KN 53,
A. Power Supply - 11-33VDC at 1.5 amps
B. Oscilloscope -
Tektronix 465
C. Digital Voltmeter -
FI uke 8600A
D. VOR RF Generator
1. Boonton 211A or
2. TIC T211A
E. VOR Modulator -
Collins 4795-3
F. Attenuator
6dB pad, 50 ohm input/output impedance
G. Audio VTVM -
Ballentine 310A/B
H. Frequency Counter -
Eldorado 1615C
I. Glideslope Generator -
Boonton 232A
J. Audio Oscillator -
Hewlett Packard 200CD
K. KN 53 Test Fixture (See Figure 5-1)
MMOOO3 Paae 5-1

KING
KN 53
NAVIGATION RECEIVER
5.2.2 TEST PROCEDURES
This section includes a set of tests measuring overall KN 53 performance. Should any requirements not
met, refer to the alignment and troubleshooting sections. Figure 5-1 shows a typical test set.
signal strength readings are in hard microvolts. Hard microvolt readings are taken With a 50 ohm, 6dB
between the signal generator and radio.
Unless otherwise stated, testing should be performed With standard test signals as defined in Sect
5.2.2.1 and With the foi lowing set of input conditions:
A. Input voltage to Power Supply: 13.75V
B. NAV Channel: 112.30MHz
C. NAV Signal RF Level: 100uv
5.2.2.1 standard Test Signal Description
a. Standard VOR Test Signal
An RF carrier, amplitude modulated simultaneously (a) 30 +_ 1% by a 9960Hz subcarrier wt

is, in turn, frequency modulated at a deviation ratio of 16 by which¯can
a 30 + 1Hz "reference pl
signal" and (b) 30 + 1% by a 30 + 1%Hz "variable phase signal" be varied in pl
with respect to the reference phase signal.
b. Standard Audio Test Signal
An RF carrier amplitude modulated 30% at 1000Hz.
c. Standard Localizer Test Signal
An RF carrier modulated simultaneously with 90Hz + .3% and 150Hz + .3% signals so that
sum of their separate modulation percentages equal'š 40 + 2%.
d. Standard Localizer Centering Signal
A standard localizer test signal in which the difference in depth of modulation is less
.002 (.1dB).
e. Standard Localizer Deviation Signal
A standard localizer test signal in which the difference in depth of modulation of the
and 150Hz signal is .093 + .002 (4 +.1dB).
f. Standard Glideslope Test Signal
A 700pv RF carrier amplitude modulated simultaneously with 90Hz and 150Hz of each leve
that when each signal is applied independently, the carrier is modulated 40 j_ 2%.
g. Standard Glideslope Centering Signal
A standard glideslope test signal in which the difference in depth of modulation of th

and 150Hz signals is less than .002.
h. Standard Glideslope Deviation Signal
A standard glideslope test signal in which the difference in depth of modulation of th

and 150Hz signals is 0.091 j_ .002 (2 j_ .1dB).
MMOOO3 Page 5-5

KING
KN 53
NAVIGATION RECEIVER
5.2.2.2 Power Supply Tests
a. Input current
The A+ input current to the KN 53 should be .75 amps or less at 13.75VDC and .25 amps or
less at 27.5VDC.
INPUT CURRENT: amps at 13.75V amps at 27.5V
b. Power Supply Voltages
Using a digital voltmeter, check the power supply voltages to see if they are within the
tolerances listed below:
LOCATION VOLTAGE
P103 voc (+192 + 6VOC)
P301, Pin 3 VDC (+12 + 1VOC)
P101, Pin 3 VOC (+9.00 + .25900)
P101, Pin 4 VDC (+5.0 + .25VOC)
P101, Pin 1 VDC (-26 + 145V6Ç)

5.2.2.3 NAV Receiver
a. RF Sensitivity
Using a signal level of 2uv (hard), with an audio voltmeter, measure the audio level of the
receiver with no modulation and with a signal modulated 30% at 1000Hz. Make sure the Ident
switch is in the Out (Ident Enabled) position.
FREG S+N (6dB MIN)
108.00 dB
114.90 dB
117.95 dB
b. Quieting
Measure the quieting at the audio output With a 100uv unmodulated signal.
Quieting de (20dB minimum)
c. Selectivity
Measure the selectivity of the receiver at 112.30MHz by measuring the NAV IF AGC voltage
with a 10uv unmodulated RF signal and then finding the 6dB bandwidth of the receiver by
increasing the signal to 2Ouv and finding the generator frequencies that give an equivalent
AGC voltage.
10uv AGC voltage volts
6dB Bandwidth Points
Upper Frequency MHz (112.315 min)
Lower Frequency MHz (112.285 max)
6dB Bandwidth MHz (.032MHz min)
MMOOO3 Page 5-6

KIN6
KN 53
NAVIGATION RECEIVER
Increase the RF signal to 10,000uv and measure the 60dB bandwidth points.
60dB bandwidth
Upper Frequency NH2 (112.342 max)
Lower Frequency MHad1Í2,258 min}
d. Audio Output
A 2Duv standard audio test signal should produce 50mw (5VRMS into 500 ohms). The I
control must be in the out position for this measurement,
e. Audio Frequency Response
The frequency response should have less than a 6dB variation between 350 and 2500KHz.
1KHz Ref dB
350Hz dB
2500Hz dB
f. Voice/Ident Response
Measure the audio output for a 1020Hz tone with the Ident switch in both positions.
difference in audio level should be at least 15dB.
Audio Level Ident Switch Out: VRMS
Audio Level Ident Switch In: VRMS
Ident Filter Attenuation: dB
5.2.2.4 Localizer Characteristics
a. Composite Level Set
Measure the composite level using the audio VTVM with a standard localizer centering si
applied at 1000uv RF Ievel.
(0.35 +.01 VRMS)
5.2.2.5 Glideslope Characteristics
a. Sensitivity
Measure the half flag sensitivity, the current needed to give 190uv flag voltages at
following frequencies:
329.15MHz (108.95) 20av nax;
332.00MHz (109.30) 2Cuv max.
335.00MHz (110.30) 20uv max.
b. Selectivity
Measure the 6dB bandwidth by increasing the RF voltage to 4 times the 1/2 flag sensit-
at 332.00MHz and finding the 1/2 flag frequency points.
6dB Upper Frequency (>332.025MHz min)
6dB Lower Frequency <331.975MHz max)
MMOOO3 Page 5-7

KING
KN 53
NAVIGATION RECEIVER
Measure the 30dB bandwidth by increasing the RF voltage to 32 times the half flag
sensitivity and finding the 1/2 flag sensitivity points.
30dB Upper Frequency (<332.150MHz max)
30dB Lower Frequency (>331.850MH2 min)
c. Centering
Measure the glideslope centering under the following conditions:
Maximum allowed centering error is +10ua.
FREQUENCY(MHz) 100uv RF 10,000uv RF
329.15 (108.95) ua ua
332.00 (109.30) ua ua
335.00 (110.30) ua ua
d. Deflection
Measure deflection for a standard glideslope deviation test signal.
Deflection voltage should be 78 + 12ua. Check to see that deflection is monotonic.
Deflection UP ua
Deflection DOWN ua
Monotonic OK
e. Flag Characteristics
Measure flag voltage under the foi lowing conditions:
RF Signal absent ua (125ua max)
90Hz absent ua (125ué max)
150Hz absent ua (125ua max)
Standard Test Signal tir (260-390ual
5.2.3 ALIGNMENT
The foi lowing procedures describe how to align the KN 53 once the test procedures have been completed to
prove alignment is necessary. A sequential order has been followed for complete alignment. Refer to the
schematics and assembly drawings for location of components, test points, and adjustments. The numbering
sequence is as folloWS:
SCHEMATICS COMPONENTOR TEST POINT DESIGNATORS
Power Supply Board 101-199
Switch Board 201-299
NAV Receiver Board 301-399
Glideslope Receiver Board 401-499
Digital Board 501-599
Digital Board
(Glideslope components) 601-699
Refer to Figure 5-1 for a typical KN 53 test set-up.

MMOOO3 Page 5-8
KING
KN 53
NAVIGATION RECEIVER
5.2.3.1 Al ignment conditions

Unless otherwise stated, alignment should be performed with standard test signals and input conditi
defined in Section 5.2.2.1.
MMOOO3 Page 5-9

KING
KN 53
NAVIGATION RECEIVER
03
LEE
ENT
L401
-+
ADJ.
PRE-SELECTOR istPOLE
PRE-SELECTOR
RF AGC
d3003LE GLIDESLOPER626
dO20LE RF AGC SET 3
R34l CENTERING
R 4L3h0mLE
406
L40 R368 T301
BAND PASS L405 COMPOSITE
3rd POLE MIXE
FILTER ADJ.
LOW END ADJ.
L404
L308 R636
VCO GLIDESLOPE FLAG
ADJUSTMENTS ADJUST
VCO ADJ C352 T302
T40 RANGE ALD306 Fl /IF
T303
R425 IF
C URDSHE
THE SLUG IN L306
IS ADOUSTED FLUSH
Q CSO3
REFERENCE
ADJ
WITHTHE TOP SURFACE T304 OSCILLATOR
OF THE METAL CAN. IF/DETECTOR TR I M
RSS
LAY
DI MMER
GLIDESLOPE
RECEIVER BOARD
NAV.RECEIVER BOARD
DIGITAL BOARD
FIGURE 5-2 ALIGNMENTADJUSTMENT LOCATIONS

(Dwg. No. 696-7613-00, R-0)
MMOOO3 Page 5-11

KING
KN 53
NAVIGATION RECEIVER
5.2.3.2 NAV Receiver and Synthesizer Alignment
a. Center all pots.
b. Reference Oscittator Adjustment
Monitor I509, pin 9, with a counter and adjust c503 for 3.2MHz j 3Hz.
c. VCO Alignment
(1) Tune KN 53 to 108.00MHz.
(2) Monitor TP305 with a DVMand adjust L308 for approximately 2.7VDC.
(3) Tune KN 53 to 117.95MHz.
(4) Adjust C352 for approximately 7.2VDC.
(5) Repeat 1, 2, 3, and 4, until 2.70 j_ .02VDC at 108.00MHz and 7.20 j_ .02VDC at 117.1
are achieved.
d. Preselection and IF Alignment
(1) Apply the standard audio modulated RF signal at 112.00MHz and a Levet of 100uV tc
antenna input.
(2) Tune the KN 53 to 112.00MHz.
L303, L304,
°
(3) Monitor TP301 or J532, pin 7, with DVMand adjust L311, L301, T301,
T303, and T304 for maximum IF AGC voltage.
(4) Decrease the signal generator Levet to 10uv and repeat (3).
e. RF AGC Alignment
(1) Set the signat generator Levet to 6uV.
(2) Monitor TP302 or J532, pin 8, with the oscittoscope and adjust R341 for 8VDC.
f. Composite Levet Set
(1) Apply the standard Localizer centering test signal at 110.10MHz and a Levet of 1(
to the antenna input.
(2) Tune the KN 53 to 110.10MHz.
(3) Set R368 for 0.35 + .01VAC RMS output with the VTVMat J532, pin B.
g. Ident Filter ALignment
(1) Apply a 112.00MHz signal modulated 30% by a 1020Hz tone to the antenna input.
. (2) Set the Ident On/0ff switch to the IN position.
(3) Monitor TP304 with a VTVMand adjust L305 for a minimum RMS voltage.
5.2.3.3 Dimmer Adjust
Tape the photoceLL, R542, and adjust R546 for a positive pulse width of 120usec at I515, pir
NOTE
THE TAPE USED SHOULD NOT TRANSMIT ANY LIGHT THROUGHTO THE
PHOTOCELL. BLACK ELECTRICAL TYPE TAPE IS RECOMMENDED.
Rev. 1, August 1981

MMOO40-8 Page 5-13
KING
KN 53
NAVIGATION.RECEIVER
5.2.3.4 Glidestope Board ALignment Procedure
Center pots: R435, R425, R626 and R635.
a. VCO
{1) Connect DVM to 3401, pin 1.
(2) Select ILS frequency 109.3MHz.
(3) Adjust T401 for 5.0V + .1V.
b. Bandpass Fitter Adjustment
{1) Disconnect CJ401 (Lift mixer side connection)
(2) Monitor TP404 with DC coupted oscilloscope.
(3) Inject audio oscittator into the Lifted end of CJ401 so .that the audio is directly
coupted into L404. The audio Levet may need to be adjusted for a maximum nutt at TP404
in the foLlowing steps.
{4) Adjust L404 for a dip in the AGC voltage (TP404) at 188KHz. SimitarLy adjust L405 for
91KHz and L406 for 109KHz.
{5) Reconnect CJ401.
c. Preselector Adjustment
(1) Select the ILS frequency of 111.9MHz.
(2) Tune signat generator to 331.1MHz.
(3) AppLy a standard glidestope centering signat and increase RF output to produce a flag
current of about 150uA. Adjust R425 if necessary.
{4) Tune L401, L402 and L403 atternateLy to produce maximum fLag .current, reducing signat
generator power output to keep flag current beLow 300uA.
d. RF AGC Attack Adjust
{1) {ILS frequency 109.30MHz, signat generator 332,00MHz, 700uV standard glidestope
centering signal).
(2) Check that flag current is between 300 and 350uA. If it isn't, adjust R425.
{3) Monitor TP405 (RF AGC) with a DC coupted scope.
(4) Reduce signat generator output to 30uV.
(5) Adjust R435 untit DC voltage on TP405 just begins to drop (about 6V).
e. Centering Adjust
(1) Set signat generator for a standard glidestope centering signat (700uV).
{2) Adjust R626 for 0 + 1uA deflection.
f. Course Width Adjust
(1) Set signal generator for a standard glidestope deviation signal (700uV).
(2) Adjust R425 for a deflection of 78uA + 2uA.
(3) Check centering adjust and readjust if necessary.
Rev. 1, August 1981

MMOO40-8 Page 5-14
KING
KN 53
NAVIGATION RECEIVER
g. Flag current Adjust
(1) Set signal generator for a standard glideslope centering signal (700uv).
(2) Adjust R636 for a flag of 325 + 5ua.
5.3 OVERHAUL
5.3.1 INSPECTION
This section contains instructions to assist in determining, by inspection, the condition of 7

assemblies. Defects resulting from wear, physical damage, deterioration, or other causes can be fou
these inspection procedures. To aid inspection, detailed procedures are arranged in alphabetical or
A. Capacitors, Fixed
Inspect capacitors for case damage, body damage, and cracked, broken, or charred insula
Check for loose, broken, or corroded terminal studs, lugs, or leads. Inspect for I
broken, or improperly soldered connections.
B. Capacitors, Variable
Inspect trimmers for chipped and cracked bodies, damaged dielectrics and damaged contacts
C. Chassis
Inspect the chassis for deformation, dents, punctures, badly worn surfaces, dai
connectors, damaged fastener devices, component corrosion, and damage to the finish.
D. Connectors
Inspect connectors for broken parts, deformed shells or ci amps, and other irregul ari
Inspect for cracked or broken insulation and for contacts that are broken, deformed, or o
alignment. Also, check for corroded or damaged plating on contacts and for loose, imprc
soldered, broken, or corroded terminal connections.
E. Covers and Shields
Inspect covers and shields for punctures, deep dents, and badly worn surfaces. Also,
for corrosion and damage to finish.
F. Insulators
Inspect insulators for evidence of damage, such as broken or chipped edges, burned areas
presence of foreign matter.
G. Jacks
Inspect all jacks for corrosion, rust, loose or broken parts, cracked insulation
contacts, or other irregularities.
H. Potentiometers
Inspect all potentiometers for evidence of damage such as dents, cracked insulation, or
irregularities.
I. Resistors, Fixed
Inspect the fixed resistors for cracked, broken, blistered, or charred bodies and
broken, or improperly soldered or corroded terminal connections.
J. RF Coils
Inspect all RF coils for broken leads, loose mountings, and loose, improperly soldere
broken terminal connections. Check for crushed, scratched, cut or charred windings. Il
the windings, leads, terminals and connections for corrosion or physical damage. Chet
physical damage to forms and tuning slug adjustment screws.
MMOOO3 Page 5-15

KING
KN 53
NAVIGATION RECEIVER
K. Transformers
1. Inspect for signs of excessive heating, physical damage to case, cracked or broken
insulation, and other abnormal conditions.
2. Inspect for corroded, poorly soldered, or loose connecting wires.
L. Wiring
Inspect wiring for breaks in insulation, conductor breaks, and improper dress in relation to
adjacent wiring or chassis.
5.3.2 CLEANING
A. Using a. clean, lint-free cloth lightly moistened with a regular cleaning detergent, remove the
foreign matter from the equipment case and unit front panels. Wipe dry using a clean, dry,
lint-free cloth.
B. Using a hand controlled dry air jet (not more than 15psi), blow the dust from inaccessible
areas. Care should be taken to prevent damage by the air blast.
C. Clean the receptacles and plugs with a hand controlled dry air jet (not more than 25psi), and
a ci ean, lint-free cloth lightly moistened with an approved cleaning solvent. Wipe dry with a
clean, dry, lint-free cloth.
5.3.3 REPAIR
This section describes the procedure, along with any special techniques, for replacing damaged or
defective components in the KN 53.
A. Diodes
Diodes used in the KN 53 are silicon and germanium. Use long nose pl iers as a heatsink under
normal soldering conditions. Note the diode polarity before removal.
B. Integrated Circuits
The microprocessor, I501, is mounted a in socket for easy replacement. Be careful to avoid
breaking the IC package during removal and insertion. Carefully line up the pins of the IC
with the holes in the socket when replacing it. Be sure pin 1 (marked with a dot on the case
or slot in the pin) is oriented properly. The medium scale integrated circuits are soldered
to the PC boards. Refer to the integrated circuit maintenance section in the Appendix for
removal and replacement instructions. The microprocessor, expander, EAROM, and CMOS
integrated circuits may be damaged by static electricity and should be kept in conductive
packaging when not installed.
C. PC Boards
Use a low wattage soldering iron to avoid damaging the boards by excessive heat. A path that
has opened up on the top or bottom of a board can be replaced with insulated hookup wire.
D. Transistors
Refer to semiconductor maintenance section in the Appendix for removal and replacement
instructions.
5.3.4 DISASSEMBLY PROCEDURES
The KN 53 assembly drawings are located in Section VI. The board to board interconnects are accomplished
by solid x
.025 pins that are soldered
.025 to the NAV receiver, glideslope, and power supply boards.
The pins plug into receptacles on the digital board. Care must be exercised when removing boards so that
these pins do not get damaged.
MMOOO3 Page 5-16

KING
KN 53
NAVIGATION RECEIVER
5.3.4.1 Top Cover Removal
When the top cover is removed, the NAV receiver, power supply and glideslope receiver boards a
accessible. Remove the four 089-6004-03 flat head screws from the siderails and the 089-6004-03 fl
head screw from the cover top. Assembly may be accomplished by following the above steps in revei
order.
5.3.4.2 Bottom Cover Removal
When the bottom cover is removed, the digital board is accessible. Remove the four 089-6004-03 flat hi
screws from the side rails and the 089-6004-03 flat head screws from the bottom cover. Assembly may
accomplished by following the above steps in reverse order.
NOTE
WHENTHIS COVER IS REMOVED+190VDC IS EXPOSED ON THE DIGITAL
BOARD!
5.3.4.3 Power Supply Removal
Remove the four 089-5874-03 screws that hold the power supply cover 047-4750-01, intact. The po
supply cover will not lift out easily.
NOTE
WHENTHIS COVER IS REMOVED+190VDC IS EXPOSED!
Next remove the four standoffs, 076-0171-07, and the 089-6298-03 flat head screw in the side rail.
power supply board will now lift straight up out of the chassis. Assembly may be accomplished
following the above steps in reverse order.
5.3.4.4 NAV Receiver Removal
Unsolder the wires from E319 and E320 if the unit is equipped with glideslope. Remove the f
089-5874-03 pan head screws and the 076-0171-09 spacer from the board. Next remove the 089-6298-03 f
head screw from the rear plate. The receiver board will now lift straight up out of the chass
Assembly may be accomplished by following the above steps in reverse order.
5.3.4.5 Glideslope Receiver Removal
Unsolder the wires from E319 and E320. Remove the three 089-5874-03 pan head screws from the boa
Next remove the 089-6298-03 flat head screw from the rear plate. The glideslope board will now I
straight up out of the chassis. Assembly may be accomplished by following the above steps in reve
order.
5.3.4.6 Digital Board Removal
The digital board is the largest and most difficult board to remove. Please note that the majority
part replacements required and unit troubleshooting can be accomplished without removing the board.
PC board material insulators underneath all the boards protect against any shorts to the center portic
a. Remove the four black 089-6303-03 flat head screws that hold on the front panel.
b. Pull the front panel, 073-0387-20, straight out to remove it from the unit.
c. Remove the three screws from the display/switch board area: 089-5899-10, 089-5899-05
089-5874-04.
d. Remove the seven 089-5874-03 pan head screws from the board.
e. Remove the 076-0171-08 standoff from the board.
MMOOO3 Page 5-17

KING
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NAVIGATION RECEIVER
f. Remove the NAV receiver board and the glideslope receiver board.
g. The digital board can now be removed, the switch board, display, and transfer switch will
come with it. When this assembly is removed and unprotected out on the bench, delicate
parts are exposed so extreme care should be used.
h. Assembly may be accomplished by following the above steps in reverse order.
5.4 TROUBLESHOOTING
Included in this section are troubleshooting flowcharts, and detailed troubleshooting procedures. The
detailed troubleshooting procedures should be used in conjunction with the troubleshooting flowcharts.
Waveforms may be found on the schematics (Section VI) and in timing diagrams in the Theory of Operation
(Section IV).
5.4.1 SYSTEM TROUBLESHOOTING
The system troubleshooting flowchart, Figure 5-3, is to be used to isolate a problem to the general area
of the unit. If the problem has been isolated to a particular circuit, refer to the appropriate
paragraph in this section and Section IV, Theory of Operation.
5.4.2 POWERSUPPLY TROUBLESHOOTING
A. The correct power supply voltages and currents are given in paragraph 5.2.2.2 a and b.
B. Short circuits may be located by removing circuit boards from the KN 53.
C. Refer to Section 4.3.1 of the Theory of Operation and the Power Supply Troubleshooting
Flowchart, Figure 5-4.
MMOOO3 Page 5-18

KING
KN 53
NAVIGATION RECEIVER
CHECK FOR SHORTS

ARE ALL POWER IS FIOI BLOWN
START LINES DEAD ON A+LINE S
JIOl PINS I,3,4 BulO3 CHECK GIO2

REPLACE F101
NO NO
ARE ALL LINES IS DC LEVEL IS SIGNAL REPLACE 0101

YES YES
HIGH AT IlOl PIN I PRESENT AT
AT LEAST 9V ILO2 PIN 13
NO YES NO NO
CHECK FOR SHORT

ARE ALL LINES LOW IS THE VOLTAGE INCREASE D.C. 1102 PIN7, PIN 14
AT IIOI PIN 2 LEVEL AT Il01 PINII. IF NO SHORT
5V i 3% PIN I
IS PRESENT REPLACE
IfDE
NO NO
REPLACE IIOl
CHECK 0103, S
IS 190V LINE LOW
YES CHECK FOR
EXCESStVE LOADING
ON 190V LINE
FIGURE 5-4 POWER SUPPLY TROUBLESHOOTINGFLOWCHART

(Dwg. No. 696-7615-00, R-0)
MMOOO3 Page 5-21

KING
KN 53
NAVIGATION RECEIVER
5.4.3 NAV SYNTHESIZER TROUBLESHOOTING
A. Phase Detector Lock Up
Pin 1, I510
B. 50KHz Reference
Check waveform with an oscisioscope input and check frequency with a counter attached to the
output of the oscisioscope (pin 4, I509).
C. 3.2MHz Reference Oscibiator
verify frequency with counter (pin 9, I509).
D. 50KHz From Divider
1. Tune the KN 53 to 108.000MHz.
2. Lift R345 on receiver board.
3. Appby externai tuning voitage to the receiver (R345) at a bevei of 2.7 vokts.
4. Check waveforms with an oscihkoscope input and check frequency with a counter attached to
the scope output of the osciMoscope, (pin 3, I510).
E. Counter Injection
2. Appby externak tuning voitage to the receiver (R345) at a beveh of 2.7 vokts.
3. Check amphitude with an osciMoscope, and check frequency with a counter attached to the
output of the oscisioscope. (Frequency shoukd be 96.9MHz). (Pin 1, I512)
F. Programmabie Divider Output
1. Appby external tuning voktage to receiver (R345) at a bevel of 2.7 volts.
3. Verify 9V peak to peak waveform with the osciboscope, and 50KHz frequency with counter
attached to scope output (pin 11, I520).
G. Divide by 20/21
1. Appby externab tuning voltage to receiver (R345) at a kevel of 2.7 voits.
3. Verify signah with oscihkoscope (pin 6, I511).
H. BCD Counter G Outputs
1. Appby external tuning voitage to receiver (R345) at a kevel of 2.7 vokts.
3. Verify count sequence (pin 11, 12, 13, 14, I520).
I. BCD Counter Program Pins
2. Verify that the bogic bevels on I520; pin 3 is bow, pin 4 is high, pin 5 is high, pin 6
S UOW.
MMOOO3 Page 5-22

KING
KN 53
NAVIGATION RECEIVER
J. Decode counter Output
1. Tune the KN 53 to 108MHz.
2. Verify count sequency (pin 11, 1Ž, 13, 14, I521).
K. Ainary Counter Program Pins
2. Verify a logic high at pin 3 of I521 and a hogic how at pin 4, kogic high at pin 5 ar
logic bow at pin 6.
L. Refer to Section 4.3.7 of the Theory of Operation and the NAV Synthesizer Troubieshootir
Fiowchart, Figure 5-5.
MMOOO3 Paae 5-23

KING
KN 53
NAVIGATION RECEIVER
5.4.4 GLIDESLOPE TROUBLESHOOTING
NOTE
Use this procedure in conjunction with troubleshooting
flowchart, Figure 5-6.
A. Power Supply
Verify the presence of 9V at pin 5 of J401 when an ILS channel is selected.
B. Frequency Synthesizer
1. VCO Output Level
Verify that the VCO output is at least 3.5V p-p at TP406.
2. Inputs
Verify the presence of a 100KHz reference at I602 pin 14, and glideslope injection
frequency at E407. The glideslope injection frequency is the selected channel frequency
minus 11.1MHz.
3. I601 Outputs
verify that the I601 outputs are correct according to Table 4-4 of the detailed circuit
theory.
4. Manually Tuning the VCO
Successively jumper pin 1 of J401 to +9V and ground VCO should go from minimum to maximum.
5. Counter Buffer
Verify that the counter buffer has a 5V p-p output at a frequency equal to the difference
between the glideslope VCO frequency.
6. Manually Tuning the VCO to Produce Different Frequencies
can the VCO be manually tuned to produce 16.667KHz at I603, pin 14?
Lift R439 to break the loop. The wiper of a 10K pot with the pot between +9V and ground
can be used to tune the VCO manually. Determine whether the correct VCO frequency and
16.667KHz at 1603, pin 14 can be obtained.
C. Receiver
1. Dither
Verify the presence of a 781.25Hz triangle wave at the junction of C606 and C607.
2. RF AC
When the collector of 9405 is jumpered to 9V the RF AGC voltage at TP405 should rise to
6.5V. When jumpered to ground, the RF AGC voltage should go to ground.
3. RF AGC
When the collector of 9405 is jumpered to 9V or ground TP404 should go low or high
respectively.
4. Preselector Alignment
Verify that the preselector is aligned properly.
MMOOO3 Page 5-27

KING
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NAVIGATION RECEIVER
5. IF Gain
With TP405 grounded, successiveLy jumper TP404 to ground and 9V. A change in signat Levet
at TP402 shouLd be apparent. Maximum signat shouLd occur when TP404 is grounded.
6. RF Gain
Changing the vottage at TP405 should change the voLtage drop across R402 and R403.
7. Transistor VoLtages
Check the vottages for 0401 through 0404 using schematic overLay.
8. IF Bandpass
Check the inductors in the IF bandpass fitter for an open condition.
D. Converter
1. Detector
Check the signaL at .the cottector of 0405.
2. FLag current
Verify that 325 |_ 25uA of fLag current exists.
3. Centering Adjust
Verify that R626 is good.
4. Subtractive Detector
Verify that CR603 and CR604 are good.
5. D-Bar Driver
Verify that 16088 is good.
6. Course Width
Verify that R425 is good.
7. Audio Buffer
Verify that 0407 .is good.
8. Reference Voltage
Check voltage at pin 14 or R of rear connector (J532).
9. I608
Verify that 1608 is good.
10. Active Fitter Frequency Response
Lift R614 and R635 and connect them to an audio generator. Vary the frequency of the
generator and notice where the D-bar peaks. These frequencies shouLd be 90Hz and 150Hz j
5%.
E. AGC
Check the adjustment of R435 before entering into the AGC troubleshooting procedures in the
receiver troubleshooting section.
Rev. 1, August 1981

MMOO40-8 Page 5-28
KING
KN 53
NAVIGATION RECEIVER
F. Sensitivity
After checking RF AGC adjustment (R435), enter the receiver troubl eshooting procedure at the
point of checking preselector alignment.
G. Selectivity
1. Dither
Verify that the signal at JA01 pin 1 is dithered 781.25Hz.
2. IF Low Pass Fil ter
Verify that the parts in the IF loW pass filter are good.
MMOOO3 Page 5-29

KING
KN 53
NAVIGATION RECEIVER
5.4.5 DISPLAY TROUBLESHOOTING
NOTE
Use this procedure in conjunction with troubleshooting

flowchart, Figure 5-7.
A. Anodes
1. Clock
Verify the presence of a clock signal at pin 4 of I507.
2. Johnson Counter
Verify the count sequence of pins 1, 2, 3, 4, 5, 7, 10, and 11 of I513.
3. High Voltage Level Shifter
Verify that the emitter of 0502 is at approximately 95 volts.
4. Verify that the anode drivers are OK (see display timing diagram).
B. Display Data
1. Inputs
Verify that I508 inputs are correct (see display timing diagram).
2. Cathode Drivers
Verify that the output signals for I508 are OK (see display timing diagram).
C. Display Intensity
1. Variable Duty Cycle Ramp
Verify that the duty cycle of the ramp at pin 7 of I515 varies with the ambient lig
intensity into the photo resistor.
2. Cathode Programming
Verify that a variable amplitude and width pulse is present at I508 pin 1.
D. Keep Al ives
1. Keep Alive Resistors
Verify that a 95 volt drop exists across R575, R576, R577, and R578.
MMOOO3 Page 5-37

KING
KN 53
NAVIGATION RECEIVER
5.4.6 PROCESSOR TROUBLESHOOTING
See processor troubleshooting flowchart (Figure 5-8) and detailed circuit theory.
MMonn3 Paae 5-43

KING
KN 53
NAVIGATION RECEIVER
5.4.7 NAV RECEIVER TROUBLESHOOTING
Unless otherwise specified, use a standard audio modulated RF signal of 112.00MHz modulated 30% by 1000&
at a level of 100uv.
A. 500 Ohm Audio Output
Verify that a 3VRMS 1000Hz tone at the 500 ohm audio output is dropped 6dB by a 500 ohm loat
A high impedance voltmeter should be used for this test.
B. NAV Volume
verify with an oscilloscope that turning the volume control varies the 1000Hz tone level a p
6 of 1302.
C. NAV volume HI
Verify the presence of a 1000Hz tone at J302 pin 14 with an oscilloscope.
D. Composite
Verify the presence of a 1000Hz tone at TP303 with an oscilloscope.
E. Detector Input
Verify the presence of a 1000Hz modulated RF signal at the base of 0305 with an oscilloscope
F. 0303 Output
Verify the presence of a 1000Hz modulated RF signal at the collector of 0303 wih
oscilloscope.
G. 0302 Input
Verify the presence of a 1000Hz modulated signal at the base of 0303 with an oscilloscope
quickly increasing the level of the signal generator from 100uv to 10K uv.
H. I201 Output
Verify the presence of a 1000Hz modulated RF signal at pin 1 of I301 with an oscilloscope
quickly increasing the level of the signal generator from 100uv to 10K uv.
I. IF AGC
Verify that the IF AGC at TP301 is approximately 1.6V with DVM.
J. 1801 Input
Verify the presence of a 1000Hz modulated RF signal at pin 4 of 1301 by quickly increasing t
level of the signal generator from 100uv to 10K uv.
K. T801 Input
Verify the presence of a 1000Hz modulated RF signal at the drain of 0302 with an oscilloscc
by quickly increasing the level of the signal generator from 100uv to 10K uv.
L. LO Injection
1. Tune the KN 53 and generator to 108.00MHz.
2. Verify the presence of an RF signal of approximately 1V peak to peak with an oscilloscc

at gate 2 of 0302.
MMnnnX Paae 5-47

KING
KN 53
NAVIGATION RECEIVER
M. Phase Detector Output
1. Tune the KN 53 and generator to 108.00MHz.
2. Verify the phase detector output level of 2.7vDC.
N. Voltage Drop Across R345
Verify no voltage drop across R345.
O. VCO Output
1. Apply external tuning voltage of 2.7 volts.
2. Verify 96.9MHz output at C353 with counter.
P. Receiver Buffer Output
Verify the presence of an RF level of appro×1mately 100mv p-p at C355 with an oscilloscope.
G. Counter Buffer Output
Verify the presence of an RF level of appro×imately .8V p-p at J306 with an oscilloscope.
R. 0302 voltages
Verify these voltages with the signal generator disconnected from the antenna connector: Gate
1 approximately
-
3.6 volts, Gate 2 -

approximately 3.6 volts, drain -
approximately 9 volts,
source approximately
-
1.9 volts.
S. 0301 Voltages
Verify these voltages with the signal generator disconnected from the antenna connector: Gate
1 -
approximately 3.8 volts, Gate 2 -
appro×imately 9 volts, source approximately

-
1.3 volts.
Use a digital voltmeter.
T. Preselector Alignment
Verify alignment of RF poles by adjusting L311, L301, L303, and L304 for maximum IF AGC
monitored with digital voltmeter.
U. Refer to Section 4.3.6, Theory of Operation, and the NAV Receiver Troubleshooting Flowchart,
Figure 5-9.
MMOOO3 Page 5-48

KING
KN 53
NAVIGATION RECEIVER
500 OHM AUDtO

OUTPUT
START lOOOHz MOD.3Œ/4
SIGÑAL,IDENT
OFF
NO
NAV VOL
YES TROUBLESHOOT
AUDIO AMP
PIN 6 1302
NO
TROUBLESHOOT
NAV VOL HI YES LINE FROM
NAV VOL. HI
J 302
PIN 14 TO NAV.VOL
NO
COMPOSITE YES TROUBLESHOOT

TP 303 FILTER
NO
DETECTOR INPUT YES TROUBLESHOOT

DETECTOR
BASE Q305
NO
O 303 OUTPUT YES TROUBLESHOOT

COLLECTOR0303 Q 304
NO
Q303 INPUT YES TROUBLESHOOT
BASE Q303 0303
NO
I 301 OUTPUT YES TROUBLESHOOT

PIN I 1301 T303
NO
FIGURE 5-9 NAV RECEIVER TROUBLESHOOTINGFLOWCHART

(Dwg. No. 696-7610-00, R-0)
{Sheet 1 of 2)
MMOOO3 Page 5-49

KING
KN 53
NAVIGATION RECEIVER
CONTENTS
SECTION
VI
ILLUSTRATED
PARTS
LIST
Item Page
6-1 Final Assembly 6-1

6-2 Power Supply 6-7
6-3 Switch Board 6-11
6-4 NAV Receiver 6-15
6-5 GLidestope Receiver 6-25
6-6 Digital Board 6-33
LISTOFILLUSTRATIONS
Figure Page
6-1 KN 53 Final Assembly 6-5

6-2 Power Supply Assembly and Schematic 6-9
6-3 Switch Board Assembly 6-13
6-4 NAV Receiver Assembly 6-21
6-5 NAV Receiver Board Schematic 6-23
6-6 GLidestope Receiver Board Assembly and Schematic 6-31
6-9 Digitat Board Schematic 6-45
6-i
MMOO40-9
7/14/81 KING RADIO CORPORATION
PARTS LISTING
NAME: FINAL ASSY UNIT: KN 0053 ASSY NO: 066•1067-00/99
REV NO: 21 21 21 21
LAST ECO:
ECO DATF:
- • • • • • • • 0 U A NT
SYMBUL PART NUMBFR DESCRIPTION CDDE UM -00 -01
' •02 -03
066-1067-00 FINAL ASSY X

066-1067•01 FINAL ASSV X
066.3067-99 COMMUN BOM
012-1022·00 TAPE ALUM FOIL FT - - - -
012-112T-00 TAG CVR En . . . -
012-1137-00 INSUL CTP TRAY 66 . - . .
012-1138-00 INSUL STM CVR EA - • • •
012-1144-00 INSUL RCVR/GS EA - • - •
012•1157-00 INSUL SCKl FA - • • -
016-1131-00 CNTCf CMT BND 1055 AR - - - -
035-1363-02 PRDTECTIVE LVR EA - • - -
037-0060-01 DISPLAY EA - - - -
047-4371-01 S RDR H 0 En - - - -
47-4527-0) (VR A EA - - - -
047-4688-02 CHAS A BA - - - -
047-4689-02 TOP COVER EA • - - -
047-4690-01 RTM CYR A EA - - - -
047-4750-01 Cve 95 A EA - - - -
047-4753-04 MTG RACK A EA - - - -
047-4926-0) 5000R HD FA - - - -
047-5633•D2 SHLO PC BD EA - - - ·
057-1540-00 WARN HV En - - - -
057-2131-00 NAMETAG (W/GS) EA - -

1 -
057-2131•01 NAMFTAG (W/O GS) FA I 1 · 1

057•2139-00 MOD TAG EA - - - -
066-1067-99 COMMUN BOM A Eh I ) 1 1
073-0379-0) HOLD DOWN UNIT A EA - w w -
073-0387-20 FRONT PANEL Eh - - - •
076-0171•07 STANDOFF En - - - -
076-0171-08 STANDOFF EA - - w -
REV. 1, AUGUST 1981 PAGE 6-1

PARTS LISTING
NAME: FINAL ASSY UNITI KN 0053 ASSY NO: 066-1067-00/99
REY NO: 21 21 21 21
LAST ECO:
ECO DATE:
- - - - - - w - • - OU A NT I TY
SYMBOL PART NUMBER DESCRIPTION CODE UM -00 -01 -02 •O3 -99
076•0171•09 STANDOFF EA
'
- - - •
1
076•0921-00 RETAIN SCREW Eh - - - -
1
088•0832-01 LENS A EA 1 1 · -
088-0832•O3 LENS A FA - - 1 1 -
089-5874-03 SCP PHP 2-56X3/16 Eh - -

3 -
15
089-5874-04 SCR PHP 2-56X1/4 EA - - - -
1
089-5899•03 SCR PHP 2-56×3/16 EA - . . .
2
089-6899•O5 SCR PHP 2-56XS/16 EA - - - • 1
089-5899-10 SCR PHP 2-56XS/8 Eh - - - •
1
089-6004-03 SCR FHP 2-56X3/16 FA - - • • 10
089-6298-03 SCR FMP 3-48 3/16 EA - -
] • 2
089-6303-03 SCREW EA - - • 4
089-6561-00 RETAINING SCREW Eh • - • •
3
089-8231-00 WASHER FLAT Eh - - • •
1
090-0266-00 GRDOVE PIN TYPE 2 EA - • - • 1
187-1164•00 PAD EA - - - -
1
200-5971•01 B/M NAV RCVR A EA - - - -

1
200•6074.00 8/M PWR SPLY A Eh - • • • 1
200-6075•00 B/M GS A to - - 1 • -
200-6077-00 DIGITAL BOARD A 64 • •

1 • •
200-6077-01 DIGITAL BOARD A En 1 1 - 1 •

PARTS LISTING
NAMEl B/M PWR SPLY UNIT: KN 0053 ASSY NOI 200-6074•00
REY NO: 9
LAST ECOs
.ECO DATE:
• - - - - - • • wm • 0 U A NT
SYMBOL PART NUMBER DESCRIPTION CODE UM -00
200•6074•00 B/M PWR SPLY X
009-6074•00 PC BD PWR SPLY EA 1
016•1040-00 PC101 COATING . AR AR
047-3142-01 HEAT SINK REG A EA 1
089•2140=00 NUT HEX ESNA 4•40 EA 1

089-5436-05 SCR FHP 4•40X5/16 EA 1
089-5436-08 5CR FHP 4•40X1/2 EA 1
090-0349-00 FUSE CLIP EA 2
091•0051.03 RTNR TOROID EA 1

091-0095•00 WSHR EA 1
091-0156-00 WSHR STEP NYL En 1
091•0286•02 INSUL XSTR .687 EA 1
C101 097-0074•02 CAP AL 4700F 50V EA 1

C102 118•0026•00 CAP DC .1UF 16v EA 1
C103 118-0026•00 CAP DC .lUF 16V EA 1
ClO4 097•0068•11 CAP AL 4.7UF 25V EA 1
C105 118-0026•00 CAP DC .lUF 16v EA 1
C106 113-5681-00 CAP DC 680PF 500V EA 1
C107 108.5028•03 CAP PC .1UF 100V EA 1
C109 097-0074.03 CAP AL 2UF 350V EA 1
Cl10 097-0074-04 CAP AL 680UF 25V EA 1
C111 097•0074-01 CAP AL 1KUF 16V EA 1
Cll2 097-0056•65 CAP AL 47UF 63V EA 1
C113 097-0068•12 CAP AL ,47UF 63V EA 1
C114 118-0046-00 *CAP DC EA 1
CR103 007.6105•OO DIO HV FDH444 EA 1

CR104 007.6016-00 DIO 5 1N4154 EA 1
CR105 007•6091•O4 DIODE MRS18 EA 1
CR106 007-6091-02 DIODE MRB11 EA 1
CR107 007-6088-01 DIO HC V5Kl40 EA 1
CR108 007-6025•00 DIO 5 1N4003 EA 1
CR109 007-6016•00 DIG S 1N4154 EA 1
CR110 007•6016•00 DIO 5 1N4154 EA 1
CRlll 007-6091-04 0100E MRS18 EA 1
Rev. 1, August 1981 Page 6-7

PARTS LISTING
NAME: 8/M PWR SPLY UNIT: KN 0053 ASSY NO: 200•6074•OO
REY NO: 9
LAST ECO:
ECO DATE:
' • • • • • • • • • 0 U A NT I TY
SYMBOL PART NUMBER DESCRIPTION CODE UM •00
F101 036•OOS8-02 FUSE AGA 32V 2A EA 1
Il01 120•3094•32 IC 340LA 5.0 EA 1

1102 120-3048-01 IC LM239J EA 1
J101 030-2322-05 HEADER SP EA 1

J102 030•2322•01 HEADER 1P EA 1
J103 030•2322-01 NEADER 1P EA 1
L101 019•2281-00 CHOKE FLTR EA 1
0101 007•0348•00 x5TR S NPN 92PUOS EA 1

Q102 007•0381•02 XSTR HF D44E3 EA 1
0103 007-0254-00 XSTR S PNP MPSA92 EA 1
R101 136-2001w72 RES PF 2K EW 1% EA 1

Rl02 136•2491•72 RES PF 2.49K EW 1% EA 1
R103 130-0105•23 RES FC 1M OW 5% EA 1
R106 130•0104•23 RES FC 100K OW 5% EA 1
R107 130•0392•23 RES FC 3.9K Ow 55 EA 1
R108 130-0333-23 RES FC 33K Ow 5% EA 1
R109 130-0513•23 RES FC 51K QW 5: En 1
R110 130-0473•23 RES FC 47K Ow 5% EA 1
R111 130-0514•23 RES FC 510K QW 5% EA 1
R112 130-0513-23 RES FC 51K QW 5% EA 1
R113 130-0562•23 RES FC 5,6K OW 5% EA 1
R115 130•0104•23 RES FC 100K QW 5% EA 1
R117 130•O563•23 RES FC 56K OW 5% EA 1
R118 130-0104-23 RES FC 100K QW 5% EA 1
R119 130•0562-23 RE5 FC 5.6K QW 54 EA 1
R120 130-0121•23 RES FC 120 QW 5% EA 1
R121 130-0680•23 RES FC 68 QW 5% EA 1
R122 130-0102•23 RES FC 1K OW S% EA 1
Rl23 130•0240•23 RES FC 24 QW 5% EA 1
R124 130-0224•23 RES FC
220K QW 5% EA 1
R125 132-5046•00 RES WW .05 2W Si tA 1
R126 130•0101-23 RES FC 100 QW 5% EA 1
R127 131-0225•23 RES CF 2.2M QW 5% EA 1
T101 019•7081•OO XFMR PWR EA 1
Rev. 1 August 1981 Page 6-8

7/14/81 K [NG RADIO CORPORATION
PARTS LISTING
NAMEs B/M SWITCH UNIT: KN 0053 ASSY ND: 200•6076•00
RFV NO: 5
LA5f ECOI
ECO DATE:
- · · - - - - · • - OU A NT
SYMSOL PART NUMB6R DESCRIPTION CODE UM -00
200-6076-00 B/M SWITCH X
009•6076•00 PC 80 SWITCH FA 1
016-1013-00 VAC GREA5E DC 976 AR AR

016•1122-00 EPOXY DEVCON 14250 AR AR
026-0002•00 WIRE COP flN 24G FT ,1
047-5018-00 SPR SW En 1
076•1045-00 SPCR INC/Déc EA 1
088•0765•00 HOUSING SWITCH EA 1

088-0765•01 SWIfcH HSNG EA 1
088-0766•01 DETENT WHEEL 53/80 EA 2
088•O767.01 KNOB A EA 1
088•0768.02 KNOB & $HAFT A EA 1
088-0769•00 SLEEVE•LOCRING EA 1
088-0773-01 KNOB A EA 1
088-0803•00 HOLDER SWITCH EA 1
089•6292•03 SCR PHP 2-56X3/16 EA 2

0A9-6292-07 5CR PHP 2-56XT/16 EA 2
090-0019-05 RETAINING RING EA 2

090-0036-04 RING RTNR .051 EA 1
150-0003•10 TUBING TFLN 24AWG FT .1
R201 031,0353-00 SWITCH S PUT tA 1
5203 031-0343-û0 SWITCH SPDT EA 1

KING
KN 53
NAVIGATION RECEIVER
-E210
E211
026-0002-00 (2)
150-0003--| 0 (2)
009-6076-00
E 2 l3
-088-0768-02
089-6292-03 (2)
088-0773-01
088-0803-00 088-0767-01
E213
031-0343-00
E212
- -
047-5018-00
088-0765-00
Ill Illlll 0766-01

388 (2)
WIRING CHART
¯oso-ools-os(2)
FROM TO KING PART NO.
E 2]O E 212 026--0002-00 !)H 088--0766-01 REF
E 211 E 213 026-0002-00

088-0765-01
NOTES: 388-0769-00
R 201
l. INSTALL SPRING (047--50l8-00) ON HOUSING (088-0765--00)
AFTER SWITCH IS ASSEMBLED ON THE P.C. BOARD.
089-6292-07 (21
2. AFTER ASSEMBLY, APPLY A SMALL AMOUNT OF EPOXY (016-1122-00)
TO THE RETAINING RING (090-0036-04) TO SECURE IT TO THE
SHAFT (088-0768-02)
3. APPLY SMALL AMOUNT OF LUBRICANT, KPN 016-1013-00 WHERE 376-1045-00
KNOB (088-0773-01) SLIDES ON SHAFT.
090-0036-04
SEE NOTE 2
FIGURE 6-3 SWITCH BOARD ASSEMBLY

(Dwg. No. 300-6076-00, R-3)
Rev. 1, August 1981

MMOO40-9 Page 6-13
KING
KN 53
NAVIGATION RECEIVER
E2102H
026-0002--00 (2)
150-0003-1 0 (2)
009-6076-00
E 2l3
088-0768-02
089-6292-03 (2)
088-0773-01
088-0803-00 088-0767-01
E213
031-0343-00
047-50l8-OO I - - -
088-0765-00
088-0766-0! (2)
°°°¯!076-050 R2EF.
088 -0766-01
REF.
WIRING CHART
088-0765-01
FROM TO KING PART NO.
E 2|O E 2\2 026-0002-00
E 211 E 213 026--0002-00 088-0769-00
R 201
089-6292-07 (2)
076-1045-00
NOTES:
1. INSTALL SPRING (047-5018-00) ON HOUSING (088-0765--00) ogo-oose-o4
AFTER SWITCH IS ASSEMBLED ON THE P.C. BOARD.
FIGURE 6-3 SWITCH BOARD ASSEMBLY

(Dwg. No. 300-6076-00, R-1)
MMOO40-9 Page 6-13

7/14/81 KING RADio CORPORATION
PARTS LISTING
NAME: 6/M NAV RCVR UNIT: KN 0053 ASSY NO: 200-5971-01
REY NO: 15
LAST ECO:
ECO DATE:
• - · w • • • - • 0 U A NT I TY
SYMBOL PART NUMBER DESÇRIPTION CODE UM -01
200-5971-01 B/M NAV RCVR X
008•0038-01 TERM BlFUR 4084L EA 2
009•5971•10 PC RO NAV RCVR EA 1
012•1135-00 INSULATUR EA 1
012-1174-00 INSUL EA 4
016•1040-00 PC101 COAT1NG AR AR
047-4526•01 FENCF A EA 1
047-4552.00 CAN SHLD En 1
047-4753-01 SHLO CV A EA 1
C300 113-5102•00 CAP OC ,00]UF 500V EA 1

C301 109•0012-01 CAP OC 4.7UF 100V EA 1
C302 113•5331-00 ÇAP OC 330PF 500V FA 1
C303 113-5560-00 CAÞ DC 56PF 500V En 1
C304 114•5102•00 CAP OC 1KPF 500V EA 1
C305 113•5101-00 CAP DC 100PF 500V EA 1
C306 113•5331•00 CAP OC 310PF 500V En 1
C307 113-5331•00 CAP OC 330PF 500V EA 1
C308 113.3082-00 CAP DC 8.2PF 500V EA 1
C309 113-5560•OO CAP DC 56PF 500V En 1
C310 114-5102-00 CAP DC 1KPF 500V EA 1
C311 113-5022•00 CAP DC 2.2PF 500V EA 1
C312 113-5560•00 CAP DC 56PF 500V EA 1
C313 114-5102•OO CAP DC 1KPF SOOV EA 1
C314 113•3082-00 CAR OC 8.2?F 500V EA 1
C315 113-5331•00 CAP DC 330PF 500V EA 1
C316 113-5331-00 CAP DC 330PF 500V EA 1
C317 109•0007•00 CAP DC .010F 25V EA 1
C318 109-0007•00 CAP OC .01UF 25V EA 1
C319 113•3027-00 CAP DC 2,7PF 500V EA 1
0320 113•$022-00 CAP 00 2.2PF 500V EA 1
C321 113-3027-00 CAP DC 2,7PF 500V EA 1
C322 097-0068-00 CAP AL 10UF 16V EA 1
0323 109-0007.03 CAP DC .05UF 25V EA 1
C324 109-0007-03 CAP OG .05UF 25V EA 1
0325 109•0007•03 CAP DC .05UF 25V EA 1
C326 109-0007-03 CAP DC .05UF 25V En 1
C327 109-0007-00 CAP DC .01UF 25V EA 1
C328 113•5221-01 CAP DC 220PF 500V EA 1

7/1/+/81 kJNG RADIO CORPORATION
PARTS LISTING
NAME: B/M NAV ROVR UNITs KN 0053 ASSY NO! 20095971*01
REV NOI 15
LAST ECOs
ECO DATE:
- - - - - - · · - • - QU A NT I TY
SYMBOL PART NUMBER OFSCRIPTION CODE 11M 901
C329 097-1082•05 CAP AL 100F 20V EA 1

C330 113-5821-00 CAP DC 820PF 500V EA 1
C331 114-7104•00 CAP DC 410F 16V EA 1
C332 109-0007·03 CAP DC ,05UF 25V EA 1
C333 097-0068•03 CAP AL 47UF lov FA 1
C334 113-5821-00 CAP DC 820PF 500V EA J
C335 108-5028-02 CAP PC .01UF 3% SO EA 1
C336 10S-0031=51 CAP MY .033UF SOY E^ 1
0337 108•5028-01 CAP PC .12UF 3% 50 EA 1
C338 097-0068-11 CAP AL 4.7UF 25V EA 1
C339 097-0068-21 CAP AL 33DF 25V EA 1
C340 097-0068-15 CAP AL 100F 25V EA 1
C34) 097-0068•21 CAP AL 33UF 25v EA 1
C342 097-0068-21 CAP AL 33DF 25v EA 1
C343 108-5028-00 CAP PC ,1UF 14 SOY EA 1
C344 113-5201-00 CAP DC 200PF SCOV En 1
0345 108-5028-00 CAP PC .10F 1% 50V EA 1
C346 113-5331•00 CAP DC 330PF 500V EA 1
C347 118-0015-00 CAP DC 27PF 500V E^ 1
0348 097-0068-11 CAP AL 4,7UF 25V EA 1
C349 113-3068-00 CAP DC 6,8PF 500v EA 1
C350 113-3120-02 CAP DC 12PF 500v EA 1
C351 113-5331-00 CAP DC 330PF 500v EA 1
C352 102-0029-01 CAP VAI,7-6PF 500V EA 1
C353 113-3100-01 CAP DC 10PF 500V EA 1
0354 113-5331-00 CAP DC 3300F 500V EA L
C355 113-5022.00 CAP DC 2.2PF 500V E^ 1
C356 118-0017.00 CAP DC 22PE 500V EA )
C357 118-0017•00 CAP DC 22PF 500V EA 1
C358 113•5331-00 CAP DC 330PF 500V E^ 1
C359 118-0017•00 CAP DC 22PF 500V FA )
C360 096-1018-00 CAP IN 3,3UF 159 E^ 1
0361 096-1030-07 CAP TN 68UF 20%20V EA 1
C362 113-5022-00 CAP DC 2.2PF 500v En 1
C363 113-5560•00 CAP DC 569F 500V EA 1
C364 114-5102-00 CAP DC 1KPF 500V EA 1
C365 113-3010-00 CAP DC 1PF 500v EA 1
C366 097-0066-00 CAP AL 10UF 16v EA 1
0367 097-0068-09 CAP AL 2.2UF 25v EA 1
C368 109-0007•03 CAP DC .05UF 25V EA 1
0369 097-0068•00 CAP AL JOUE láv EA 1
C370 118•0026-00 CAP DC ,10F 16V EA 1
C371 108•5028-02 CAP PC .0)UF 3% Sn EA 1
C372 108.5028-02 CAP PC .01UF 3% 50 EA 1
0373 113-3047•00 CAP DC 4.7PF 500V EA 1
C374 104-0001•l4 CAP SM 33PF 100V EA 1
C375 096-1006-00 CAP IN 1,0UF SOY EA 1
CJ301 026•0018-00 WIRE CKTJMPR 22AWG EA 1

7/14/81 KING RADID CORPORATION
PARTS LISTING
NAME3 6/M NAV RÇVR UNITI KN 0053 ASSY NO: 200-5971-01
REV NOt 15
LAST ECO:
ECD DATE:
- - - - • • • - - - QU A NT I TY
SYMBOL PART NUMBER DESCRIÞTION ({)DE UV -01
CJ302 026-0018•00 wiRE CKlJMPR 22AWG En 1

CJ303 026-0018-00 wlkE CKTJMPR 22AWG EA 1
CJ304 026•0018-00 wlRE CKTJMPR 22AWG EA 1
CR301 007•4012-00 DIO V SMV626 EA 1

CR302 007.4012-00 010 V SMV626 EA 1
CR303 007.4012•00 010 V SMV626 EA 1
CR304 007-6016•00 DID S IN4154 EA 1
CR305 001-4012-00 010 V SMV626 EA 1
CR306 007•4012•00 DIO V SMV626 EA 1
FL301 017.0071•00 FLTR 11.1MHZ BP EA 1
1301 120•3020•00 IC EC13509 EA 1

1302 120•3080•00 IC SL60827 EA 1
J301 030.2322•07 HEADER 7P EA 1

J302 030-2322•07 HEADER 7P EA 1
J303 030-2322•01 HEADER 1P EA 1
J304 030-2322-01 HEADER IP Fa 1
J305 030•2322•02 HEADER 2P EA 1
J531 030-0059-00 CONN COAX PNL MTD EA 1
L301 019•22/8•00 COIL RF 3,75T EA 1

L302 019-2057-15 CH RF 1.8UH 5% EA 1
L303 019-2278-00 COIL RF 3.75T En 1
L304 019•2278•00 COIL RF 3.757 EA 1
L305 019•2275-02 INDUCTOR En 1
L306 019-8071•00 COIL TUN BLK En 1
L.307 019-2054•22 CH RF 3.3UH 5% EA 1
L308 019-2274-00 COIL NAV VCO EA 1
L309 019-2054-10 CH RF .33UH 5% EA 1
L310 019•2054•10 CH RF .33UH 5% EA 1
L311 019-2278•OG COIL RF 3.75T En 1
0301 007-0317•01 50306DE EA 1

0302 007•0452•00 XSTR 3N212 En 1
0303 007-0195•00 XSTR S MPSHIO EA 1
0304 007•0238•00 XSTR S PNP FPN4917 EA 1
0305 007.0238•00 XSTP 5 PNP FPN4917 EA 1
0306 007-0078-00 XSTR 5 NPN 2N3415 EA 1
0307 007-0078•00 XSTP S NPN 2N3415 Eh 1
0308 007.0078•00 XSTA $ NPN 2N3415 EA 1
0309 007•0078•00 XSTR S NPN 2N3415 EA 1

PARTS LISTING
NAME: 8/M NAV RCVR UNITt KN 0053 ASSY NO: 200•5971-01
REV NOi 15
LAST ECO:
ECO DATE:
• • - - • • 0 U A NT I TY
0310 007•0238•00 XSTR S PNP FPN4917 EA 1

0311 007•0078•00 XSTR S NPN 2N3415 .EA 1
0312 007•0195•00 XSTR S MPSW10 EA 1
0313 007-0195-00 XSTR S MPSHIO En 1
0314 007-0195-00 XSTR S MPSW10 EA 1
0315 007•0187-00 XSTR S NPN 2NSOS9 EA 1
R300 130-0101-23 RES FC 100 OW 53 . EA 1

R301 130w0103-23 RES FC IOK Ow 5% En 1
R302 130•0433•23 RES FC 43K QW $% EA 1
R303 130-0563•23 RES FC 56K OW 5% BA 1
R304 130.0513•23 RES FC 51K QW 5% EA 1
R305 130-0470•23 RES FC 47 Ow 54 EA 1
R306 130•0103•23 RES FC 10K QW 5% EA 1
R307 130•0103-23 RES FC 10K QW 5% EA 1
R308 130-0510•23 RES FC 51 QW 5% EA 1
R309 130-0563•23 RES FC 56K QW 5% EA 1
R310 131-0563•13 RES CE 56K EW 5% EA 1
R311 130•0302•23 RES FC 3K QW 55 EA 1.
R312 130•010T•23 RES FC 100 QW 5% EA 1
R313 130.0513•23 RES FC SIK Gw 5% EA 1
R314 130-0220m23 RES FC 22 QW $1 EA 1
R315 130•Ol00•23 RES FC 10 QW 5% EA 1
R316 130-0272•23 RES FC 2.7K QW 5% EA 1
R317 130•0100•23 RES FC 10 Ow 5% EA 1
R318 130-0333•23 RES PC 33K QW 5% EA 1
R319 130-0822•23 RES FC 8.2K Ow 5% EA 1
R320 130•0027•23 RES PC 2.7 QW 54 EA 1
R321 130-0301•23 RES FC 300 QW 5% EA I
R322 130•0470•23 RES FC 47 Of 5% E^ 1
P323 130-0181*23 RES FC 180 QW 5% En 1
R324 130•0222-23 RES FC 2.2K QW 5% EA 1
R325 130•0242•23 RES FC 2,4K QW 51 EA 1
R326 130-0473•23 RES FC 47K OW 5% EA 1
R327 130•0823•23 RES FC 82K Qw 5% EA 1
R328 130•0123•23 RES FC 12K OW 5% EA 1
R329 130.0682-23 RES FC 6,8K QW 5% EA 1
R330 130-OS12•23 RES FC 5.1K Ow 57 EA 1
R331 130-0563•23 RES FC 56K OW 5% EA 1
R332 130,0122923 RES FC 1.2K Ow St EA 1
R333 130.0203•23 RES FC 20K Ow 5% EA 1
R334 130•0473-23 RES FC 47K QW 54 EA 1
R335 130•0123•23 RES FC 12K OW 5% EA 1
R336 130-0470•23 RES FC 47 QW 5% EA 1
R337 130•0123·23 RES FC 12K OW 5% EA I
R338 130-0103•23 RES FC IOK QW 5% EA 1
R339 130-0103•23 RES FC 10K QW 52 EA 1
R340 130-0103•23 RES FC 10K OW 5% EA 1
R341 133-0110•22 RES VA SK 1W 20% EA 1

PARTS LISTING
NAME: 8/M NAV RCYR UNIT: KN 0053 ASSY N0s 200-5971.01
REY NOI 15
LAST ECOs
ECU DATEs
- - - - - - • - - -
QU A NT I TY
SYMBOL PART NUMBER DESCRIPTION CODE UN 901
R342 131•OS22923 RES OF 8.2K OW 55 EA 1

R343 130•0104•23 RES FC 100K QW 5% EA 1
R344 130•0331•23 RES FC 330 QW 5% EA 1
R345 130•0332•25 RE5 FC 3.3K QW 10% EA 1
R346 130-0272•25 RES FC 2.7K OW 10% EA 1
R347 130•0511•23 RES FC 510 QW 5% EA 1
R348 130-0102•23 RES FC 1K QW 5% EA 1
R349 130-0392•23 RES FC 3.9K QW 5% EA 1
R350 130•0471•23 RES FC 470 QW 5% EA 1
R351 130•0101•23 RES FC 100 Ow 5% EA 1
R352 130•0101-23 RES FC 100 OW 54 EA 1
R353 130•0682-23 RES FC 6.8K QW 5% FA 1
R354 130•0472•23 RES FC 4,7K QW 5% EA 1
R355 130-0821•23 RES FC 820 OW 5% EA 1
R356 130•0221-25 RES FC 220 QW 10% EA 1
R357 130•0221.25 PES FC 220 QW 10% EA 1
R358 130•0472•23 RES FC 4,7K QW 5% EA 1
R359 130•0821•23 RES FC 820 Qw 5% EA 1
R360 130-0101-23 RES FC 100 QW S% EA 1
R361 130-0103•23 RES FC 10K OW 5% EA 1
R362 130•0333•23 RES FC 33K QW S% EA 1
R363 136•1652•72 RES PF 16.5K EW 1% EA 1
R364 130•0154•23 RES FC 150K QW 5% EA 1
R365 130-0154•23 RES FC 150K QW 5% EA 1
R366 130•0472•23 RES FC 4.7K QW 5% EA 1
R367 130-0470•13 RES FC 47 EW 5% EA 1
R368 133-0110•27 RES VA 100K IW 20% En 1
R369 130-0102•23 RES FC 1K QW 5X EA 1
T301 019•8068•01 XFMR IF EA 1

T302 019•8067-00 XFMR IF EA 1
T303 019•8076•00 XFMR IF EA 1
T304 019-8070-00 XFMR IF EA 1
T305 019•¾078•01 XFMR OUT 500 EA 1
TP301 008•0096-01 TERM TST PT EA 1

TP302 008-0096•01 TERM TST PT En 1
TP303 008-0096•01 TERM TST PT EA 1
TP304 008-0096-01 TERM TST PT EA 1
TP305 008•0096•01 TERM TST PT EA 1
TP306 008-0048-00 SLDRLS TERM EA 1
TP307 008-0048-00 SLORLS TERM EA 1
REV. 1, AUGUST 1981 PATE 6-19

PARTS LISTING
NAM68 8/M GS UNITI KN 0053 ASSY NOt 200.6075•00
REV NO: 16
LAST ECO: 35112
ECD DATE: 6/10/1
· · - · - - · - • • • QU A NT
200•6075•00 B/M GS
008•0038-01 TERM BlFUP .084L EA 3
009•ó075•10 GLIDESLOPE BD EA 1
012-1134-00 INSULATOR EA 1
012•1136•00 INSUL VCO #3 EA 1
016•1040•00 PC101 COATING AR AR
026-0002-00 WIRF COP TIN 24G FT .1
047•3547-00 CAN CHOKE EA 2

047•4334•02 MixFR COVER EA 1
047-4537•01 FNCF GS A En 1
047•4538-01 DVOR FENCE A EA 2
047.4639•O1 FENCE VCO -
A EA 1
047•4546•01 FENCE GS A EA 1
047•4547•01 CVR PRES A EA 1
047•4548•01 CVR VCO EA 1
047•4752•02 SHLD PRES 2 A EA 1
047-4754-01 SHLD VCO 3 A EA 1
C401 109•OOl2•00 CAP DC 1.5UF 100V EA 1

C402 113-3680-00 CAP DC 68PF 500V EA 1
CAO3 113-3680-00 CAP DC 68PF 500V En 1
CA04 113-5022-00 CAP DC 2.2PF 500V En 1
CAOS 113-3121-00 CAP DC 120PF 500V EA 1
CAO6 113•3680-00 CAP DC 68PF 500V EA 1
C407 113-5019-01 CAP DC 1.9PF 500V EA 1
CAOS 113-3680-00 CAP DC 68PF 500V EA 1
C409 113-3680•00 ÇAP DC 68PF 500V EA 1
0410 113•3121•00 CAP DC 12OPF 500V EA 1
CA11 113-3680•00 CAP OC 68PF 500V EA 1
C412 113-5033-00 CAP DC 3.3PF 500V EA 1
C413 113•5019•01 CAP DC 1.9PF 500V EA 1
C414 113-3680-00 ÇAP DC 68PF 500V EA 1
0415 111-0001·08 CAP CR 100PF 200V EA 1
C416 097.0068•10 CAP AL lUF 25V EA 1
CA17 096•1082•05 CAP TN 10UF 20V EA 1
CA18 114-7104-00 CAP DC .1UF 16V EA 1
0419 114-5152-00 CAP DC 1500PF 500V EA 1

PARTS LISTING
NAME: 8/M GS UNIT: KN 0053 ASSY NOI 200-6075•00
REY NOI 16
LAST ECO:
ECO DATE: 6/10/1
--••-- ••-00ANTITY
SYMBOL PART NUMBER DESCRIPTION CODE UM •OO
Ç420 113-3121•00 CAP DC 120PF 500V EA 1

0421 105-0031•11 CAP MY .0027UF SOY EA 1
C422 113-5561•00 CAP DC 560PF 500V EA 1
C423 105•0031-11 CAP MY ,0027UF 80V EA 1
C424 113-5391•00 CAP DC 390PF 500V En 1
C425 114•5152-00 CAP DC 1500PF 500V EA 1
C426 113-7503•00 CAP DC ,05PF 12V EA 1
C427 114-7104•00 CAP DC .10F 16V EA 1
C428 114-5222•01 CAP OC 2200PF 500V FA 1
C429 109-0007•01 CAP OC ,022UF 25V EA 1
0430 097-0068•ll CAP AL 4,7UF 25V En 1
C431 114-5222•01 CAP DC 2200PF 500V EA 1
0432 109-0007•03 CAP DC .05UF 25v EA 1
C433 109-0007•03 CAP DC .0SUF 25V EA 1
C434 097.0068•00 CAP AL 10UF 16V En 1
C435 097-0068•09 CAP AL 2.2UF 25V EA 1
C436 097-0068-09 CAP AL 2.2UF 25V EA 1
C437 113.5331-00 CAP DC 330PF 500V EA 1
C438 097-0068•O1 CAP AL 220F 16V En 1
C439 097 0068•ll CAP AL A,7UF 25V EA 1
0440 096•1082-00 CAP IN 68UF 20V EA 1
0441 114-7502•00 CAP DC 5KPF 100V EA 1
C442 113-3120•02 CAP DC 12PF 500V EA )
0443 113•3270•00 CAP DC 27PF 500V EA 1
C444 113•3390•00 CAP DC 39PF 500V EA 1
0445 113-3390•00 CAP DC 39PF 500V EA 1
C446 113-5331•00 CAP DC 330PF 500V EA 1
C447 113-3220-00 CAP DC 22PF 500V EA 1
C449 097-0068•24 CAP AL 100UF 16V EA 1
CABO 113-3150-00 CAP DC ISPF 500V EA 1
0451 113-5101•01 ÇAP DC 100PF SOOV EA 1
C452 11395331•00 CAP DC 330PF 500V EA 1
C453 109•0007•03 CAP DC .05UF 25v En 1
CASA 109.0007•00 ÇAP DC .01UF 25V En 1
C455 113«3270•00 CAP DC 27PF 500V EA 1
0456 109-0007•03 CAP DC .05UF 25V EA 1
C457 114-7104•00 CAP DC .1UF 16V EA 1
0458 104-0007-03 CAP DC ,05UF 2SV EA 1
C459 096-1082•05 ÇAP TN 10UF 20V EA 1
C460 096•1082•05 CAP TN 10UF 20V EA )
C461 111•0001•08 CAP CR 100PF 200V EA 1
C462 111•0001•08 CAP CR 100PF 200V EA 1
C463 113•3680•00 CAP DC 68PF 500V EA 1
CR401 007-4012•00 010 V SMV626 EA 1

CR402 007•6016•00 DIO S 1N4154 EA 1
CR403 007.5045•09 010 Z 1/4MS,1AZS EA 1
1401 120 302O•00 IC MC1350P EA 1

PARTS LISTING
NAME: 6/M GS UNIT: KN 0053 ASSY NO: 20096075-00
REY NO! 16
LAST ECO:
ECO DATE:
• • • • w . . . - - • 0 U A N 1
SYMBOL PART NUMBER DESCRIPTION CODE UN -00
J533 030-0059•00 CONN COAX PNL MTD ËA 1
L401 019•2276•00 001L RFF 1.5T EA 1

L402 019.2276.00 COIL RFF 1.5T EA 1
L403 019•2276.00 COIL RFF 1.5T EA 1
L404 019•2266•OO COIL ADJ 7MH EA 1
L405 019-2265•00 COIL ADJ 6MH EA 1
L406 019-2265•00 COIL ADJ 6MH EA 1
L407 Ol9-2084•31 CH 2.70H 10% EA 1
L408 019-2084-01 CH .15UH 10% EA 1
L409 019-2050•00 CH RF 4.7UH 10% EA 1
L410 013-0006•03 FERR BEAD EA 1
P401 030•2322•O6 HEADER 6Þ EA 1
0401 007•0310•00 XSTR MFES21 6A 1

0402 007-0310•00 XSTR MFE521 EA 1
0403 007•0452•00 XSTA 3N212 EA 1
Q404 007-0187•00 XSTR S NPN 2NSOS9 EA 1
0405 007-0078•00 XSTR S NPN 2N3415 EA 1
0406 007-0078•00 XSTR S NPN 2N3415 EA 1
0407 007•0078•00 XSTR S NÞN 2N3415 En 1
0408 007-0238•00 XSTR S PNP FPN4917 EA 1
0409 007-0238•00 XSTR 5 PNP FPN4917 EA 1
0410 007•0078•00 XSTR S NPN 2N3415 En 1
0411 007•0078•OO XSTR 5 NPN 2N3415 En 1
0412 007-0238•00 XSTR S PNP FPNA917 EA 1
0413 007•0195•00 XSTR S MPSH10 EA 1
0414 007•Ol95•00 XSTR S MPSHIO EA 1
0415 007·0195-00 XSTR 5 MPSN10 EA 1
0416 007-0452•00 XSTR 3N212 EA 1
0417 007-0238•00 XSTR S PNP FPN4917 EA 1
0418 007-0195•00 XSTR S MPSH10 En 1
RA01 130-0103-23 RES FC 10K Ow St EA 1

R402 130•0101•23 RE$ FC 100 Ow 55 EA 1
R403 130•0101•23 RES FC 100 QW 5% EA 1
R404 130-0103•23 RES FC IOK QW 5% En 1
R405 130-0123•23 RES FC 12K ON 5% En 1
R406 130-0223•23 RES FC 22K OW 5% EA 1
R407 130•Ol33-23 RES FC 13K OW 5% EA 1
R408 130•0683•23 RES FC 68K QW 5% EA 1
R409 130•0684-23 RES FC 680K OW 5% En 1
R410 130-0393-23 RES FC 39K OW 5% EA 1
R411 130-0563•23 RES FC 56K QW 5% EA 1
R412 130•0270•23 RES FC 27 Ow St EA 1

PARTS LISTING
NAME: 8/M GS UNITI KN 0053 ASSY ND* 200•6075-00
REY NO: lA
LAST ECOI
ECO DATE:
=•••*•-• ••QUANTITY
SYMBOL PART NUMBER DESCRIPTION CODE UN •00
R413 130-0101•23 RES FC 100 qw 5% EA 1

R414 130-0101•23 RES FC 100 Ow 5% EA 1
R415 130•0471-23 RES FC 470 QW 5% EA 1
R417 130-0102•23 RES FC 1K OW 5% EA 1
RAIS 130•0822.23 RES FC 8.2K QW 5% EA 1
R419 130-0472.23 RES FC 4,7K QW 5% EA 1
R420 130-0681.23 RES FC 680 QW 5% EA 1
R421 130.0102-23 RFS FC 1K QW 55 EA 1
R422 130.0473-23 RES FC 47K QW 5% EA 1
R423 130-0103•23 RES FC 10K OW 5% fo 1
R424 130-0101•23 RES FC 100 OW 5% EA 1
RA25 133-0113-16 RES VA SK 20% A EA 1
R426 130-0823•23 RES FC 82K QW 5% EA 1
R427 130-0202.23 RES FC 2K OW 5% En 1
R428 130-0163•23 RES FC 16K QW S% EA 1
R429 130-0683-23 RES FC 68K Ow 5% EA 1
R430 130-0333•23 RES FC 33K QW S% EA 1
R431 130-0123•23 RES FC 12K Ow 5% EA 1
R432 130-0103•23 RES FC 10K OW 5% EA 1
R433 130-0104•23 RES FC 100K QW 5% EA 1
R434 130•0103•23 RES FC 10K OW 5% EA 1
R435 133-0113•16 RES VA 5K 20% A EA 1
R436 130•0103-23 RES FC 10K QW 5: Eh 1
R437 130•0472•23 RES FC 4.7K QW 5% EA 1
R438 130.0153•23 RES FC 15K OW 5% EA 1
R439 130•0243•23 RES FC 24K QW 5% EA 1
R440 130•0822-23 RES FC 8.2K QW 55 En 1
R441 130•O472w23 RES FC 4.7K OW 54 E^ 1
R442 130•0821•23 RES FC 820 QW 5% EA 1
R443 130•0101•23 RES FC 100 QW 5% EA 1
R444 130-0472-23 RES FC 4.7K QW 5% EA 1
R445 130-0472=23 RES FC 4,7K QW 5% EA 1
R446 130.0101•23 RES FC 100 QW 5% EA 1
R447 999•9999-98 NOT USED EA •
R448 130-0393-23 RES FC 39K OW 5% EA 1

8449 130-0563•23 RES FC 56K QW 5% EA 1
R460 130,0563•23 RES FC 56K Qw 5% EA 1
R451 130-0101-23 RES FC 100 Qw 5% EA 1
R452 130•0471•23 RES FC 470 QW 5% EA 1
R453 130•0152•23 RES FC 1.5K OW 5% EA 1
RASA 130-0302•23 RES FC 3K QW 55 EA 1
R455 130.0331-23 RES FC 330 OW 5% EA 1
R456 130•0201-23 RES FC 200 OW 5% EA 1
8457 130-0820•23 RES FC 82 QW 5% EA 1
R458 130•0241•23 RES FC 240 QW 5% EA 1
R459 130•O200·23 RES FC 20 QW 5% EA 1
R460 130-0161•23 RES FC 160 Qw 5% EA 1
R461 130-0102-23 RES FC 1K QW 5% EA 1
R462 130=0152•23 RES FC 1.5K OW 5% EA 1
T401 019•2227•00 CGIL VCO 2.5T EA 1

PARTS LISTING
NAME: 6/M GS UNIT: KN 0053 ASSY NO: 200w6075-00
REY NO: 16
LAST ECOs
ECO DATE:
• • • • • • • 0 U A N 1
SYMBUL PART NUMBER DESCRIPTION CODE UM •00
TP401 008•0096•01 TERM TST PT EA 1

TP402 008•0096•01 TERM TST PT EA 1
TP403 008•0096•01 TERM TST PT 6A 1
TP404 008•0096•01 TERM TST PT EA 1
TP405 008-0096•01 TERM TST PT EA 1
TP407 008-0096•01 TERM TST PT EA 1

PARTS LISTING
NAMEs DIGITAL BOARD UNITI KN 0053 AS$Y NO! 200•6077•00/01
REV NOs 32 31
LAST ECOs
ECO DATE*
• • • • • • • • • • • 0 U A NT I TY
SYMBOL PART NUMBER DESCRIPTION . CODE UM •00 •01
200•6077•00 DIGITAL BOARD X

200•6077·01 DIGITAL BOARD X
008-0038•01 TERM BIFUR .084L EA 11 11
009•6077•01 PC BD DIGITAL EA 1 1
015•0041•01 RES MODULE 220K AR • AR
016•1040•00 PC101 CDATING AR AR AR

016•1082•00 DC RTV 3145 AR AR AR
025•0003•00 WIRE 22G BLK EA 1 1

025•0018•22 WIRE 26G RED EA 1 1
025•0018•29 WIRE 26G REDWHT FT 1,5 1,5
025•0018•55 WIRE 26G GRN FT .1 .1
025•5013•02 CA 3C WHT EA 1 1
026•0002•00 WIRE COP TIN 24G FT 1 49
030•1117•00 RECEPTACLE EA 23 18
030•2316-00 CONN OSPLY EA 1 1
030•2323•09 RT ANG HOR 9 PIN EA 1 1
033•0057•20 SCKT INDV PLG 20P EA 2 2
088•0830•01 PUSHBUTTON A EA 1 1
088.0831•00 SW HLOR EA 1 1
089•2140•00 NUT HEX ESNA 4•40 EA 2 1

089.5436•04 SCR FHP 4•40X1/4 EA 2 1
120•0095•00 IC UDN6184A AR AR AR
120•3083•00 IC 01512 AR AR AR
150•0003•10 TUBING TFLN 24AWG FT .3 .3
150•0049•10 TUBING SHNK ,062 FT .1 ,1

150•OO72-00 SLOR SLEEVE 462 EA 1 1

PARTS LISTING
NAME: DIGITAL 80ARD UNITI KN 0053 A55Y NOS 200•6077•00/01
REV NDI 32 31
LAST ECO:
ECO OATEt
• • • - • • • - • • • 0 0 A NT I TY
SYMBOL PART NUMBER DESCRIPTION CODE UM •OO •01
200•6076-00 B/M SWITCH A EA 1 1
C501 096•1006•00 CAP TN 1.0UF 50V EA 1 1

C502 113•3150•00 CAP DC 15PF 500V EA 1 1
CSO3 102•0040•00 CAP VA3.5•lePF250V EA 1 1
CSO4 113•5331•00 CAP DC 330PF 500V EA 1 1
CSOS 113•5331•00 CAP DC 330ÞF 500V EA 1 1
C506 097•0056•59 CAP AL 10UF 63V EA 1 1
C507 113-5331•00 CAP DC 330PF 500V EA 1 1
C508 111•0001•13 CAP CR .1UF SOV EA 1 1
C509 111•0001•13 CAP CR .1UF 50V EA 1 1
C510 111•0001•63 CAP CR .022UF 200V EA 1 1
CS11 111•0001-63 CAP CR .022UF 200V EA 1 I
CB12 096•1006•00 CAP TN 1.0UF 50V EA 1 1
CB13 111.0001•00 CAP CR .01UF 50V EA 1 1
C514 111•0001•00 CAP CR .01UP 50V EA 1 1
C515 111•0001-00 CAP CR .01UF 50V EA 1 1
C516 111•0001•00 CAP CR .01UF SOY EA 1 1
C517 111•OOOl•00 CAP CR .01UF 50V EA 1 1
CB18 111•0001•00 CAP CR .010F 50V EA 1 1
0519 111•0001·00 CAP CR .01UF 50V EA 1 1
C520 111.0001•00 CAP CR ,01UF 50V EA 1 1
C521 111•0001•00 CAP CR .01UF SOY EA 1 1
0522 111•0001•00 CAP CR .010F SOY EA 1 1
C523 111•0001.00 CAP CR ,01UF SOY EA 1 1
C524 111•0001-00 CAP CR .01UF 50V EA 1 1
C525 111.0001•00 CAP CR .01UF 50V EA 1 1
C526 111•0001•00 CAP CR .01UF 50V EA 1 1
C527 111•0001•00 CAÞ CR .010F 50V EA 1 1
C529 113•5221•01 CAP DC 220PF 500V En 1 1
0530 113.7503•00 CAP DC .05PF 12V EA 1 1
C531 106•5028•03 CAP PC .1UF 100V EA 1 1
C532 118•0026-00 CAP DC .1UF 16V EA 1 1
C533 111.0001•00 CAÞ CR .01UF 50V EA 1 1
C534 096-1014•00 CAP TN 40UF 10V EA 1 1
C535 096.1009•00 CAP TN 220F 15V EA 1 1
C537 111•0001-13 CAP CR .10F SOV EA 1 1
C603 113•5102•00 CAP DC ,001UF 500V EA 1 -
C604 096•1009•00 CAP TN 22UF 15V EA 1 •
0605 113•7503•00 CAP DC .OSPF 12V EA 1 •
C606 113-7503•00 CAP DC .05PF 12V EA 1 •
C607 096•1007•00 CAP TN 2.2UF 20V EA 1 m

C608 097•0056-59 CAP AL 10UF 63V EA 1 •
0609 108•5028•00 CAP PC .1UF 1% 50V EA 1 •
C610 108.5028•00 CAP PC .1UF 18 50V EA 1 •
0611 108-5028•00 CAP PC .1UF 1% 50V EA 1 •
C612 108.502B•00 CAP GC .1UG 1% 50V EA 1 •
C613 097•0056•59 CAP AL 10UF 63V EA 1 •
C614 097•0056•60 CAP AL 22UF 25V EA 1 •

PARTS LISTING
NAMEs OIGITAL BOARD UNITs KN 0053 ASSY NOI 200•6077•00/01
REY NO: 32 31
LAST ECO:
ECO DATEI
• • • • • - - • • - • 0 U A NT I TY
SYMBOL PART NUMBER DESCRIPTION CODE UM •00 •01
C615 113·5221•01 CAP DC 220PF 500V EA 1 •
0616 113•S221•01 CAÞ OC 220PF 500V EA 1 •
C617 113•5221•01 CAP DC 220PF 500V EA 1 •
C618 111•0001•13 CAP CR .10F 50V EA 1 •
C619 111-0001•13 CAP CR .1UF 50V EA 1 •
CJSO1 026•0018•00 WIRE CKTJMPR 22AWG EA 1 1

CJ601 026•0018•00 WIRE CKTJMPR 22AWG EA 1 •
CR501 007•6046•05 DIO 5 1N916A EA 1 1

CRSO2 007.6016.00 DID S 1N4154 EA 1 1
CRSO3 007•6016•00 DIO 5 1N4154 EA 1 1
CR504 007.6016•00 DIO S 1N4154 EA 1 1
CRSO5 007•6023•00 DIO G IN277 EA 1 1
CRSO6 007•6023•00 DIO G 1N277 EA 1 1
CR507 007•6023•00 DIO G 1N277 EA 1 1
CR508 007•6023•00 DIO G IN277 EA 1 1
CRSO9 007•6016•00 DIO S 1N4154 EA 1 1
CRSIO 007•6016•00 DIO S IN4154 EA 1 1
CRS11 007.5011•04 DIO Z 13V 1W 53 EA 1 1
CR$12 007•5011.14 DIO I Z3616 EA 1 1
CRS13 007.5011•23 DIO Z 30Y 1W St EA 1 1
CR514 007•6016•00 DIO S 1N4154 EA 1 1
CR515 007•6033•00 DIO G IN270 EA 1 1
CR516 007•6033-00 DIO G 1N270 EA 1 1
CR517 007.6033·00 DIO G 1N270 EA 1 1
CR518 007.5049•11 DIO Z MZ4625 EA 1 1
CR601 007•6025-00 DIO S IN4003 EA 1 •
CR603 007•6016•00 DIO 5 1N4154 EA 1 ·
CR604 007.6016•00 DIO 5 1N4154 EA 1 •
CR605 007•6016•00 DIO S 1N4154 EA 1 .
CR606 007•6016•00 DIO 5 1N4154 EA 1 -
CR607 007•6016•00 DIO 5 1N4154 EA 1 •
CR608 007•6016-00 DIO 5 1N4154 EA 1 •
CR609 007-6016•00 DIO 5 1N4154 EA 1 -
CR610 007-6016•00 DIO S 1N4154 EA 1 •
CR611 007•6033•00 DIO G 1N270 EA 1 1

CR612 007•6033•00 DIO G 1N270 EA 1 1
CR613 007-6033•00 DIO G IN270 EA 1 1
CR614 007•6033•00 DIO G 1N270 EA 1 1
CR615 007-6033-00 DIO G 1N270 EA 1 1
CR616 007•6033·00 DIO G IN270 EA 1 1
CR617 007-6033•00 DIO G 1N270 EA 1 1
CR618 007•6033•00 DIO G 1N270 EA 1 1
F501 036•oC57•05 FUSE 275 125V lA EA 1 1

FSO2 036-0057•05 FUSE 275 125V 1A EA 1 1

PARTS Ll$TING
NAMEI DIGITAL BOARD UNITI KN 0053 ASSY NO: 200-6077.00/01
REY NOl 32 31
LAST ECO:
ECO DATEs
• • • • • • • - - • •
QU A NT I TY
SYMBOL PART NUMBER DESCRIPTION CODE UM •On •01
F503 036.0057-02 FUSE 275 125V .38A EA 1 1
1901 120•2026•00 IC PSO48 EA 1 1

1502 120•2030•00 IC PS243 EA 1 1
1506 120•3026•06 IC UGH7812UC EA 1 1
1507 120•6025•01 IC SCL4049ABC+ EA 1 1
1508 120-0089-00 IC DS8884AN+ EA 1 1
1509 120•6055-01 IC SCL4060ABC+ EA 1 1
1510 120•6038•01 IC CMOS SCL40468C EA 1 1
1511 120•0085-00 IC SN74LS76N EA 1 1
1512 120.4006-01 IC SPS6478 EA 1 1
1513 120•6045•01 IC SCL4022ABC+ EA 1 1
1514 XXX.xXXX•XX EA 1 •
1514 120•0095•00 IC UDN6184A AR - AR

1515 120•3040•00 IC SA555P AR 1 AR
1515 120-3083•00 IC DI512 AR • AR
1516 120-3053•00 IC LM358N En 1 1
1517 12O•0117•00 IC SN74LS26N EA 1 1
1518 120•0131•00 IC SN74500N EA 1 1
1519 120-2028•OO IC ER1400T EA 1 1
1520 120•0088-00 IC SN74LS163N EA 1 1
1521 120.0087•00 IC SN74LS162N EA 1 1
1522 12O•0122•00 IC 93L24PC EA 1 1
1601 120-6056•01 IC SCL4094ABC+ EA 1 •
1602 120-6027-01 IC SCL4017ABC EA 1 •
1603 120-6038-01 IC CMOS SCLA0468C EA 1 -
1605 120•0088•00 IC SN74LS163N EA 1 .
1606 120•0088•00 IC SN74LS163N EA 1 •
1607 120.0088•00 It SNTAL5163N EA 1 ·
1608 120•3052•00 IC LM324N EA 1 •
L501 013.0006•03 FERR BEAD EA 1 1

L502 013•0006•03 FERR BEAD EA 1 1
L503 013•0006•03 FERR BEAD EA 1 1
L504 013•0006-03 FERR BEAD EA 1 1
LSO5 013-0006•03 FERR BEAD EA 1 1
LSO6 013•0006-03 FERR BEAD EA 1 1
L507 013-0006•03 FERR BEAD EA 1 1
LSOS 013•0006-03 FERR BEAD EA 1 1
LSO9 013•0006•03 WERR BEAD EA 1 1
L510 013•0006•03 FERR BEAD EA 1 1
LS11 013•0006•O3 FERR BEAD EA 1 1
L512 013•0006•O3 FERR BEAD EA 1 1
L513 013•0006•03 FERR BEAD EA 1 1
L514 013-0006-03 FERR BEAD EA 1 1
L515 013.0006•03 FERR BEAD EA 1 1
L516 013.0006•03 FERR BEAD EA 1 1
LSIT 013•0006•03 FERR BEAD EA 1 1

7/30/81 KING RADID CORPORATION
PARTS LISTING
NAMEI DIGITAL BOARD UNIT: KN 0053 ASSY NO! 200•6077•00/01
REY NO: 32 31
LAST ECOt
ECD DATE*
• • • • • • • • • • • 0 U A NT I TY
SYMBOL GART NUMBER DE5CRIPTION CODE UM •00 •01
L518 019•2084•43 CH 8.2UH 10% EA 1 1

L519 019-2084•63 CH 56UM 10% EA 1 1
0520 019•2084•43 CH 8.2UH 10% EA 1 1
LS21 019•2084•43 CH 8.2UH 10% EA 1 1
LS22 019•2084•43 CH 8.2UW 10% EA 1 1
L601 019•2082•65 CH 1500H 51 EA 1 •
L602 013•0006•03 FERR BEAD EA 1 •
L603 013•0006-03 FERR BEAD EA 1 -
L604 013•0006•03 FERR BEAD EA 1 •
0501 007•0238•00 XSTR S PNP FPNA917 EA 1 1

0502 007•0257•00 MSTR S NPN MPSA42 EA 1 1
0503 007•0254•OO XSTR S PNP MPSA92 EA 1 1
0504 007•0238•00 XSTR S PNÞ
FPN4917 EA 1 1
0506 007•0238•00 XSTR S PNP FPN4917 EA 1 1
0507 007.0078•00 X5TR S NPN 2N3415 EA 1 1
0508 007•0211•02 XSTR S X38D5559 EA 1 1
0509 007•0243-00 XSTA 5 NPN MPSA06 EA 1 1
0510 007•0243•00 XSTR S NDN MPSA06 EA 1 1
0511 007•0243•00 XSTR 5 NPN MPSA06 EA 1 1
0512 007•0243•00 XSTR S NPN MPSA06 EA 1 1
0513 007•0243•00 XSTR S NPN MPSA06 EA 1 1
0514 007•0243•00 XSTR 5 NPN MPSA06 EA 1 1
0515 007•0243•00 XSTR S NPN MPSA06 EA 1 1
0516 007•0243•00 XSTR S NPN MPSA06 EA 1 1
0517 007•0243•00 XSTR S NPN MPSA06 EA 1 1
0518 007•0243•00 XSTR S NPN MPSA06 EA 1 1
0519 007•0243-00 X5TR S NPN MPSA06 EA 1 1
0520 007•0243•00 XSTR S NPN MPSA06 EA 1 1
0521 007•0243•00 XSTR S NPN MPSA06 EA 1 1
0604 007•0292•00 XSTR S PNP 2N6109 EA 1 •
R501 130•0102•23 RES FC 1K OW 55 EA 1 1

R502 130-0432•23 RES FC 4.3K QW 53 EA 1 1
RSO3 130•0202•23 RES FC 2K QW 53 EA 1 1
R504 130•0102•23 RES FC 1K OW 5% EA 1 1
R505 130•0332•23 RES FC 3.3K QW 55 EA 1 1
R506 130•0332•23 RES FC 3.3K QW 5% EA 1 1
R507 130•0332•23 RES FC 3.3K QW 55 EA 1 1
R508 130-0332•23 RES FC 3.3K OW S% EA 1 1
R509 130•0332•23 RES FC 3.3K QW 55 EA 1 1
R510 130•O332•23 RES FC 3,3K OW 55 EA 1 1
R511 130•0332•23 RE5 FC 3.3K OW 55 EA 1 1
R512 130•0332•23 RE5 FC 3.3K OW 5% EA 1 1
R515 130•0472•23 RES FC 4,7K Ow 5% EA 1 1
R516 130•0101•23 RES FC 100 OW 5% EA 1 1
RB20 132.5024•00 RES WW .82 2W 5% EA 1 1
R522 130•0823-23 RES FC 82K QW 5% EA 1 1

7/30/81 USER ID•JODELL MING RADIO CORPORATION
PARTS LISTING
NAMEs DIGITAL BOARD UNITs KN 0053 ASSY N0s 200•6077•00/01
REY NOi 32 31
LAST ECO:
ECO DATE:
• • • • • • • • • • • 0 Q A NT I TY
SYMBOL PART NUMBER DESCRIPTION CODE UM •00 •01
RS23 130•0182•23 RES FC 1.8K OW 58 EA 1 1

R525 130-0104•23 RES FC 100K QW 5% EA 1 1
RS26 130•0104•23 RES FC 100K QW 53 EA 1 1
RS27 130-0156•23 RES FC 15M OW 52 EA 1 1
RS28 130.0471•23 RES FC 470 OW 5% EA 1 1
R529 130•0821•23 RES FC 820 OW 55 EA 1 1
R530 130•0221•23 RES FC 220 QW 5% EA 1 1
RS31 130•0821•23 RES FC 820 OW 55 EA 1 1
RS32 130-0331•23 RES FC 330 OW 5% EA 1 1
RS33 130•0331•23 RES FC 330 QW 5% EA 1 1
R534 130•0271•23 RES FC 270 QW 55 EA 1 1
R536 130•0821•23 RES FC 820 QW 5% EA 1 1
RS36 136•8062•72 RES PF 80.6K EW 18 EA 1 1
RS37 136•8062•72 RES PF 80,6K EW 15 EA 1 1
RS38 130•0513•23 RES FC 51K QW 55 EA 1 1
RS39 130•0184•23 RES FC 180K OW 5% EA 1 1
RS40 130•0133•23 RES FC 13K QW 5% EA 1 1
RS41 130•0394•23 RES FC 390K QW 55 EA 1 1
R542 134·5005•02 PHOTOCELL100V MAX EA 1 1
R543 130•0394•23 RES FC 390K QW 5% EA 1 1
RS44 130.0104•23 RES FC 100K OW 55 EA 1 1
R545 130.0202•23 RES PC 2K QW 53 EA 1 1
R546 133.0113•14 RES VA 2K 20% A EA 1 1
RS47 130•0104•23 RES FC 100K QW 55 EA 1 1
R548 130•0273•23 RES FC 27K QW 53 En 1 1
R549 130•0823•23 RES FC 82K OW 5% EA 1 1
R550 130•0204•23 RES FC 200K QW 5% EA 1 1
R551 130•0683•23 RES FC 68K OW 5% EA 1 1
RSS2 130•0392•23 RES FC 3.9K QW 55 EA 1 1
R553 130•0683•23 RES FC 68K OW 54 EA 1 1
RS54 130•0204•23 RES FC 200K OW 51 EA 1 1
R555 130•0332•23 RES FC 3.3K OW 5% EA 1 1
R556 130•0332•23 RES FC 3.3K OW 55 EA 1 1
RSST 130•0103-23 RES FC 10K QW 54 EA 1 1
RS58 131•0103•13 RES CF 10K EW 55 EA -
1 1
R569 130•0104•23 RES FC 100K Ow 5% EA 1 1
R560 130•0104•23 RES FC 100K QW 55 En 1 1
RS61 130•0104•23 RES FC 100K OW 55 EA 1 1
RS62 130•0104•23 RES FC 100K QW 55 EA 1 1
RS63 130•0272•23 RES FC 2,7K OW 55 EA 1 1
R564 130.0332•23 RES FC 3.3K QW 55 EA 1 1
RS65 130-0103•23 RES PC 10K QW $5 BA 1 1
RS66 130•0103•23 RES FC 10K OW 5% EA 1 1
RS67 130•0101•23 RES FC 100 OW 5% EA 1 1
RS68 130•0562•23 RES FC 5.6K QW 55 EA 1 1
R569 130•0202•23 RES FC 2K OW 5% EA 1 1
RSTO 130•0511•23 RES FC 510 QW 5% EA 1 1
RS73 130•0104•23 RES FC 100K OW 5% EA 1 1
RSTA 130•0104•23 RES FC 100K QW 5% EA 1 1
RB75 130•0334•23 RES FC 330K OW 5% EA 1 1

PARTS LISTING
NAMEI DIGITAL BOARD UNITI KN 0053 ASSY NDI 200•6077•00/01
REV NOf 32 31
LAST ECOs
ECO DATE:
• • • • • • • • • • • 0 U A NT I TY
SYMBOL PART NUMBER DESCRIPTION CODE UM -00 -01
RS76 130.0334•23 RES FC QW 55

330K EA 1 1
R577 130•0334•23 RES PC 330K
OW 53 EA 1 1
R$78 130-0334•23 RES FC 330K Ow 55 EA 1 1
R601 130-0133•23 RES FC 13K QW 5% EA 1 •
R602 130•0223•23 RE$ FC 22K OW 51 EA 1 •
R603 130-0152+23 RES FC 1.5K QW 55 EA 1 •
R604 130-0125-23 RES FC 1.2M Ow 5% EA 1 -
A607 130•0332•23 RES FC 3.3K QW 5% EA 1 -
R609 130.0102•23 RES FC 1K OW 55 EA 1 •
R614 130-0183•23 RES FC 18K QW 55 EA 1 •
R615 136•1961•72 RES PF 1.96K EW 12 EA 1 •
R616 136•1181•72 RES ÞF 1.18K EW 15 EA 1 •
R617 136•1073-72 RES PF 107K EW 18 EA 1 •
R618 130=0114•23 RES FC 110K OW 55 EA 1 •
R619 136•1783•72 RES PF 178K EW lt EA 1 •
R620 130.0184•23 RES FC 180K OW 5% EA 1 •
R621 130•0153•23 RES FC 15K OW 5% EA 1 •
R622 130.0153•23 RES FC 15K OW 55 EA 1 •
R623 130•0561•23 RES FC 560 OW 5% EA 1 m

R624 130•0561•23 RES FC 560 QW 55 EA 1 •
R625 130•0153•23 RES FC 15K OW 5% EA 1 •
R626 133•0113•16 RES VA 5K 20% A EA 1 •
R627 130•0153•23 RES FC 15K OW 5% EA 1 •
R628 130•0562•23 RES FC 5.6K OW 55 EA 1 •
R629 130-0274•23 RES FC 270K QW 55 EA 1 •
R630 130-0682-23 RES FC 6.8K QW 5t EA 1 •
R631 130•0133•23 RES FC 13K OW 5% EA 1 ·
R632 130.0102•23 RES FC 1K OW 5% EA 1 •
R633 130•0912-23 RES FC 9.lK OW 55 EA 1 •
R634 130•0102•23 RES FC 1K OW 55 EA 1 •
R635 130-0113•23 RES FC 11K OW 52 EA 1 •
R636 133-0113•18 RES VA 10K 20% A EA 1 •
5501 031-0370•00 MOMENTARYSW EA 1 1
0501 015•0046•01 NTWK RES/DIO EA 1 1

0502 XXX•xXXX-XX AR 1 1
YSO1 044•0053•04 XTAL 3.2000MHZ EA 1 1

APPENDIX"A"
TABLEOF CONTENTS
SEMICONDUCTOR CIRCUIT DATA

ANDINTEGRATED
Paragraph Pa
1.1 General 1-
1.1.1 Semiconductor Test Equipment 1-
1.1.2 Semiconductor Voltage and Resistance Measurements 1-
1.1.3 Testing of Transistors 1-
1.1.4 Replacing Semiconductors 1-
1.2 Integrated Circuit Maintenance 1-

1.2.1 General 1-
1.2.2 Terminology 1-
1.2.3 Integrated Circuit Test Equipment 1-
1.2.4 voltage Measurements 1-
1.2.5 Testing Integrated Circuits 1-
1.2.6 Replacing Integrated Circuits 1-2
1-i
APPENDIX"A"
1.1 GENERAL
Due to the wide utilization of semiconductors in this electronic equipment, somewhat different
techniques are necessary in maintenance procedures. In solid state circuits the impedances and
resistances encountered are of much lower values than those encountered in vacuum-tube circuits.
Therefore, a few ohms discrepancy can greatly affect the performance of the equipment. Also, coupling
and filter capacitors are of larger values and usually are of the tantalum type. Hence, when measuring
values of capacitors, an instrument accurate in the high ranges must be employed. Capacitor polarity
must be observed when measuring resistance. Usually more accurate measurements can be obtained if
the semiconductors are removed or disconnected from the circuits.
1.1.1 TEST EQUIPMENT

SEMICONDUCTOR
Damage to semiconductors by test equipment is usually the result of accidentally applying too much
voltage to the elements. Commoncauses of damage from test equipment are discussed in the following
paragraph.
A. Transformerless Power Supplies
Test equipment with transformerless power supplies is one source of high current. However,
this type of test equipment can be used by employing an isolation transformer in the AC
power line.
B. Line Filter
It is still possible to damage semiconductors from line current, even though the test
equipment has a power transfonner in the power supply, if the test equipment is provided
with a line filter. This filter may function as a voltage divider and apply half voltage
to the semiconductor. To eliminate this condition, connect a ground wire from the chassis
to the test equipment to the chassis of the equipment under test before making any other
connections.
C. Low-Sensitivity Multimeters
Another cause of semiconductor damage is a multimeter that requires excessive current to

provide adequate indications. Multimeters with sensitivities of less than 20,000 ohms-
per-volt should not be used on semiconductors. When in doubt as to the amount of current
supplied by a multimeter, check the multimeter circuits on all scales with an external,
low-resistance multimeter connected in series with the multimeter leads. If more than
one milliampere is drawn on any range, this range cannot be safely used on small
semiconductors.
D. Power Supply
When using a battery-type power supply, always use fresh batteries of the proper value.
Make certain that the polarity of the power supply is correct for the equipment under test.
Do not use power supplies having poor voltage regulation.
1.1.2 SEMICONDUCTOR
VOLTAGEANDRESISTANCEMEASUREMENTS
When measuring voltage or resistance in circuits containing semiconductor devices, remember that these
components are polarity and voltage conscious. Since the values of capacitors used in semiconductor
circuits are usually large, time is required to charge these capacitors when they appear. Thus, any
reading obtained is subject to error if sufficient time is not allowed for the capacitor to fully
charge. When in doubt it may be best in some cases to isolate the components in question and measure
them individually.
1.1.3 TESTING OF TRANSISTORS
A transistor checker should be used to properly evaluate transistors. If a transistor tester is not
available, a good multimeter may be used. Make sure that the multimeter meets the requirements out-
lined in the preceding paragraph.
Page 1-1
APPENDIX"A"
A. PNP Transistor
To check a PNP transistor, connect the positive lead of the multimeter to the base of the
transistor and the negative lead to the emitter or collector. Generally, a resistance
reading of 50,000 ohms or more should be obtained. Reconnect the multimeter with the
negative lead to the base. With the positive lead connected to the emitter or collector
a resistance value of 500 ohms or less should be obtained.
B. NPN Transistor
Similar tests made on an NPN transistor should produce the following results:
With the negative lead of the multimeter connected to the base of the transistor the value
of resistance between the base and the collector or emitter should be high. With the
positive lead of the multimeter connected to the base, the value of resistance between
the base and the collector or emitter should be low. If these results are not obtained,
the transistor is probably defective and should be replaced.
CAUTION
IF A TRANSISTORIS FOUNDTO BE DEFECTIVE, MAKECERTAIN

THATTHE CIRCUIT IS IN GOODOPERATINGORDERBEFORE
INSTALLINGA REPLACEMENT TRANSISTOR. IF A SHORTCIRCUIT
EXISTS IN THE CIRCUIT, PUTTINGIN ANOTHERTRANSISTOR
WILL MOSTLIKELYRESULTIN BURNINGOUTTHE NEWCOMPONENT.
DO NOTDEPENDUPONFUSES TO PROTECTTRANSISTORS.
C. Always check the value of the bias resistors in series with the various elements. A
transistor is very sensitive to improper bias voltage; therefore, a short or open circuit
in the bias resistors may damage the transistor.
1.1.4 REPLACINGSEMICONDUCTORS
Never remove or replace a semiconductor with the supply voltage turned on. Transients thus produced
may damage the semiconductor or others remaining in the.circuit. If a semiconductor is to be evaluated
in an external test circuit, be sure that no more voltage is applied to the semiconductor than nonnally
is used in the circuit from which it came.
A. Use only a low heat soldering iron when installing or removing soldered-in semiconductors.
Grasp the lead to which heat is applied between the solder joint and the semiconductor
with long nosed pliers.
This will dissipate some of the heat that would otherwise be conducted into the semi-
conductor from the soldering iron. Make certain that all wires soldered to semiconductor
terminals have first been properly tinned so that the necessary connection can be made
quickly. Excessive heat will permanently damage a semiconductor.
B. In some cases, power transistors are mounted on heat-sinks that are designed to dissipate
heat away from them. In some power circuits, the transistor must also be insulated from
ground. This insulating is accomplished by means of an insulating washer made of mica.
When replacing transistors mounted in this manner, be sure that the insulating washers
are replaced in proper order. After the transistor is mounted, and before making any
connections, check from the case of the transistor to ground with a multimeter to see
that the insulation is effective.
1.2 INTEGRATED
CIRCUITMAINTENANCE
1.2.1 GENERAL
A knowledge of integrated circuit fundamentals is as necessary in testing digital logic circuits

involving IC's as a knowledge of rectification fundamentals is needed to test a power supply.
Page 1-2
APPENDIX"A"
1.2.2 TERMINOLOGY
Several terms are used whenever logic circuits are discussed:
A. A logic state is defined as a high or low level voltage applied to the input or seen at
the output of a device. A high level voltage is called a logic "1". A low level voltage
is called a logic "0". Logic threshold voltage of a device is the input voltage required
at an input to change the output state.
B. A truth table is a list of input logic states that will yield certain output logic states.
A digital logic element should be thoughtof as a circuit element with its output level
being either HI or LO as programmed by the levels present on its inputs.
A logic element may be tested by verifying that it is performing per the Truth Table of
that logic element.
C. Logic elements which have multiple inputs and a single output are known as gates. The OR
gate produces a HI output when one or more of the inputs are HI. With all inputs LO, the
output is LO. The ANDgate produces a HI output only when all inputs are HI. When any
input is LO the output is LO. A small circle at the output of a gate on the schematics
indicates "negation", which means that the sense of the gate logic is reversed. An OR
gate with negation is called a NORgate and an ANDgate with negation is.called a NAND
gate. A NORgate produces a LO output when one or more of the inputs are HI and a NAND
gate produces a LO output only when all inputs are HI.
D. The Flip-Flop logic element is the basic data storage element of digital logic. It has
two outputs that are always at opposite logic levels. That is, when one output is HI the
other is LO. The Flip-Flop will remain in a particular state until that state is changed
by an input signal.
The operation of these Flip-Flops is controlled by the signals on their inputs, and is
best understood by a careful study of their Truth Tables. It should be kept in mind
that a small circle on either the input or the output indicates negation. Also, a
circle on a clock input indicates that a HI to LO transition causes the Flip-Flop to function.
E. Besides the gates and Flip-Flops, two other commonly used logic elements are inverters and
expanders. Inverters are merely switching transistors such that if a logic "1" is the input
to a device, a logic "0" will be the output and vice-versa. An expander is a set of
parallel switching transistors that depends upon another resistor to provide their supply
voltage. Generally, these devices are used to expand the number of inputs available to
a standard gate.
1.2.3 INTEGRATED CIRCUIT TEST EQUIPMENT
As with semiconductors, damage to integrated circuits by test equipment is usually the result of
applying too much current or voltage to the elements. The same precautions as discussed in Paragraph
1.1.1 apply here.
1.2.4 VOLTAGEMEASUREMENTS
Precise voltage measurements are not needed in testing digital IC's other than to see that the voltage
is a HI or a L0 level. An oscilloscope is needed where the input levels are of short duration,
either HI or LO. For instance, if a 10 microsecond pulse going from L0 to HI was applied to one input
of a NORgate, while the other input stayed LO, the output would go LO for 10 microseconds and then
return HI. This, of course, could not be seen without an oscilloscope.
1.2.5 TESTING INTEGRATED CIRCUITS
The fully loaded guaranteed minimum high and maximum low for the digital logic output levels are:
TTL (Vcc =
+5V) ECL (Vcc =
+5.2V)
High Low High Low
2.4 0.5 4.25 3.48

Page 1-3
KING
APPENDIX"A"
The minimum high and maximum low input levels which are guaranteed to be correctly interpreted are:
TTL (Vcc =
+5V) ECL (Vcc =
+5.2V)
High Low High Low
2.0 0.8 4.06 3.75
When checking input and output levels of a logic element under question it should be remembered that an
input or output may not agree with its truth table not because it has malfunctioned but because some
other component connected to the same point has shorted to ground or to the supply voltage (Vcc). This
is not common when an output on one element is connected to an input of another. A majority of digital
IC failures can be grouped into threee categories:
A. Input(s) or output shorted to ground pin of IC.

B. Input(s) or output shorted to Vcc pin of IC.
C. Open input(s) or output.
An input or output shorted to ground would be a constant LO and an input or output shorted to Vcc
would be a constant HI.
Other failures common in digital IC's are:
A. Ground pin open.
B. Vcc pin open.
C. Inputs shorted together.

An open ground pin would not allow a LO on the output. An open Vcc pin would not allow a HI on the
output. (Remember to isolate the device from other components connected to it). Two or more inputs
shorted together can be checked by grounding one of the inputs under question. If the other input also
goes to ground they are probably shorted.
CAUTION
IF AN IC IS FOUNDTO BE DEFECTIVE, VERIFY THATPROPER

POWERSUPPLYVOLTAGESARE PRESENTBEFOREINSTALLINGA
REPLACEMENT IC.
1.2.6 REPLACINGINTEGRATED
CIRCUITS
If an IC is known to be defective, the easiest way to remove it is to cut off each of its pins, remove
the case, and then unsolder the remaining pins from the integrated circuit card one by one. This is
preferrable over removing the IC intact because attempts to remove the IC intact may result in
damage to the printed circuit board.
Page 1-4
FlGIJRE l. BUFFER
A Z Z=A
I I
FIGURE 2. INVERTER
A Z Z=Ã
10
FIGURE 3. NOR GATE
Z Z= A+B+C
I OOO
O I OO
0 0 I O
I I OO
O 1 I O
I I I O
FIGURE 4. NAND GATE

A A BCZ
B Z .Z=ABC 0 0 0 I
C I OO I
OO I i
l 1 0 I
f Ol I
O I I I
i I I O
FIGURE 5. EXCLUSIVE OR GATE
Z Z=A B O
I I O
FIGURE 6. TTL TO CMOS VOLTAGELEVEL TRANSLATORS

BUFFER INVERTER
Voo=l4V Voo=14V
Vcc = SV Vcc = SV
VIN OV 14V VIN OV 14V
VIN VOUT VOUT OV SV VIN VOUT VOUT SV OV
Vss=GND Vss=GND
Page 1-5
KING
FIGURE 7. NOR GATE FLIP-FLOP
S -
Q SR Next Q Q
I i O O
O I I O
O O NC NC NC = NO CHANGE
--
I O O I
Q
R
FIGURE 8. MONOSTABLE MULTIVIBRATOR (ONE-SHOT)
TRIGGER
INPUT 4
C
THRESHOLD
o l
FIGURE 9. (FREE-RUNNING)
ASTABLE MULTIVlBRATOR
VDD
4
Rss
CTc
2
FREQUENCY OF OPERATION IS DETERMINED BY RTC AND CTC.

A NOR OR NAND GATE MAY BE USED IN PLACE OF THE FIRST
INVERTER TO PERMIT GATING OF THE MULTIVIBRATOR.
FIGURE 10. DIFNF A
PUT
OFTEN USED TO CHANGEA STEP SIGNAL

TO A SHORT PULSE SIGNAL,
Page 1-6
KING
LOCATION DIAGRAMS
INTEGRATED CIRCUIT PIN
viewedHom TOP of 10 )
i 12
2 10
3 *
45
6
9
2 8
3 Y
4 6
5
2 I 10
3 9
4 8
5 6
8
1 y
2 6
3 5
4
Page 1-7
KING
1204LOO865-00
CLR PR
>CK -c>CK
ICK IPR I IJ VCC 2CK 2 PR 2

CLR CLR
'LS76
FUNCTION TABLE
IMPUTS OUTPUTS
PRESET CLEAR CLOCK J K Q Ö
L H X XX HL
H L X XX LH
L L X X X HA HA
H H I L L QO O
H H I HL HL
H H I LH LH
H N I H H TOGGLE
H H H X X QO O
THIS CONFIGURATIONIS NONSTABLE', THATIS

IT WILL NOT PERSIST WHEN PRESET ANDCLEAR
INPUTS RETURNTO THEIR INACTIVE (HIGH)LEVEL.
DUALJ-K FLIP-FLOPS WITH PRESET & CLEAR
Page 1-8
74LS162
120-0087-00
74LS183 74LS162 74LS163
120-0088-00
0 I 2 3 4 O I 2 3 4
15 5 15 5
\4 6 14 6
IS 7 15 7
12 9 8 12 11 10 9 8
LOGIC EQLLATIONS
COUNT ENABLE= CEP·CET·PE
TC FOR 74LSI62 = CET-00 2 3
I
TC FOR 74LSI63 = CET•QO I 2 3
PRESET= PE·CP+ (RISING CLOCK EDGE)
RESET= hÏR
PIN NAMES
PË Parallel Enable (Active LOW) Input
PO, 1, 2, 3
Parallel Inputs
CEP Count Enable Parallel Input
CET Count Enable Trickle Input
CP Clock (Active HIGH Going Edge) Input
Ñž Master Reset (Active LOW) Input
Q1' 2' 3' 4 Parallel Outputs
TC Terminal Count Outputs
Page 1-9
KING
74LS162
OUTPUTS
120-0087-00 35
VCC TC 'O 2 CET PE
74LS163
120-0088-00
COER 00 01 03 CET
2
CP PO PI 2 E3 CEP
igi CP I P P2 E3; CEP GND

DATÄ
INPUTS
BCD DECADE COUNTER/4-BITBINARY COUNTER
FUNCTIONAL DESCRIPTION
The 74LS162 is a high speed BCDdecade counter, and the 74LS163 is a high speed
binary counter. Both counters are fully synchrounous will the clock pulse
driving four master/slave flip-flops in parallel through a clock buffer.
The three control inputs, Parallel Enable (FE), Count Enable Parallel (CEP),
and Count Enable Trickle (CET), select the mode of operation as shown in the .
tables below. When the conditions for counting are satisfied, the rising edge
of a clock pulse will change the counters to the next state of the count
sequence shown in the State Diagram og the previous page. The Count Mode is
enabled when CEP and CET inputs and PE are HIGH.
The 74LS162 and 74LS163 can be synchronously preset from the four Parallel
inputs, (PO-3) when PE is LOW. When the Parallel Enable and Clock are LOW,
each master of the flip-flops is connected to the appropriate parallel input
(PO-3) and the slaves (outputs) are steady in their previous state. When the
clock goes HIGH, the masters are inhibited and this information is transferred
to the slaves and reflected at the outputs. The parallel enable input overrides
both count enable inputs, presetting the counter when LOW.
Terminal count is HIGH when the counter is at terminal count (state 9 for
74LS162, and state 15 for 74LS163), and Count Enable Trickle is HIGH, as is
shown in the logic equations. When LOW, the asynchronous master reset overrides
all other inputs resetting the four outputs LOW.
Page 1-10
KING
088884 d. pt.
120-0089-00 CC a b c d e f OUTPUT
la 17 16 Í5 14 13 12 II 10
12 3456789
PROG. A B C D D.PI comma comma GND
INPUT INPUT OUTPUT
TOP VIEW
FUNCTION DPT. COMMA D C B A a b c d e f g DISPLAY

O I I 000000 0000 I 13
l... I
I I I 0001!OOl li l
2 I I 001000 10010 -
3 I I 00110000110 -
-t
4 I I 01001001100 I-
5 I I OIOIOIOOlOO -
6 I I OII00I00000
Il
7 I I 01110001111
I¯¯I
8 I I 1000 0000000 -
9 I I 10010000 100
10 I I 1010110001I
Il l I 10111100010 -
12 I I \ 10000 I I 100
f b
13 1 I I I O I O I I O O O O ; I
c
14 I I IllOllllllO -
d
15 I I IIIIIIIIIII
D.PT. O I XXXXXXXXXXX O
O DECIMAL POINT
COMMA
Comma O O XXXXXXXXXXX Ip
DECIMAL POINT AND COMMA CAN BE DISPLAYED WITH OR WITHOUT ANY NUMERAL.
Page 1-11
Vcc LOGIC DIAGRAM
0$8884
120-0089-00 ouTeuTs
c
Vcc
INPUATS
e ): d
vec
7SEGMENT
)e DECODER
e
cc
C
D.PT.
Vcc comma
COMMA
PROGRAMMABLE REFERENCE
CURRENT
I CIRCUIT
BLANKING
GND
HIGH VOLTAGECATHODEDECODER/DRIVER
GENERALDESCRIPTION
The DS8884A is designed to decode

four lines of BCD input and drive
seven-segment digits of gas-filled
readout displays. Two separate
inputs are provided for driving
the decimal point and comma cathodes.
All outputs consists of switchable
and programmable current sinks
which provide constant current to
the tube cathodes, even with high
tube anode supply tolerance.
Output currents may be varied over
the 0.2 to 1.2ma range for multi-
plex operation. The output cur-
rent is adjusted by connecting
an external program resistor (Rp)
from Vcc to the program input in
accordance with the programming
curve.
Page 1-12
KING
UDN-6184
120-0095-00
IB
2 17
3 16
[4 15
7 12
8 II
9 GND BB 10
GAS DISPLAYDIGIT DRIVER
The UDN-6184 is designed for interfacing between MOS, or other low-voltage

circuitry, and the anodes of gas discharge displays driven in a multiplexed
fashion. The UDN-6184 contains eight drivers. Each driver contains appropriate
level shifting, signal amplification, output off state voltage bias, and 70ma
output current sourcing for the sequential addressing of display anodes. The
inputs include pull-down resistors for direct connection to open drain PMOSlogic.
Page 1-13
KING
74LS26
120-0117-00
CC 4B 4A 4Y 3B 3A 3Y
IA IB IY 2A 2B 2Y GND
POSITIVE LOGIC Y=ÃŠ
QUADRUPLE-INPUT HIGH VOLTAGE INTERFACE POSITIVE-NAND GATES
Page 1-14
KING
93L24PC
TOP VIEW
120-0122-00
vec3
13\2IllO9 34567
AB
A=8
AQ A A2 A3 A4 O SI 2 63 84 80
LOADING
1--< E 9324 B¡ Ao HIGH LOW
A>B A<B A=B 0.5 U.L.
1.0 U.L.
82 Al 0.5 U.L.
I.0 U.L.
| \ l.O U.L. 0.5 U. L .
15 2 i4 83 A2 9 U.L. 2.25 U.L.

9 U.L. 2.25 U.L.
VCC PIN16
=
A3 10 U.L. 2.5U.L.
B4
GND= PIN 8
GND A4
PIN NAMES
Ë ENABLE (ACTIVE LOW)1NPUT
AO,Ai Ag A3,A4 WORD A PARALLEL INPUTS.
BO WORD B PARALLEL INPUTS
1, 2 3, 4
A B A GREATER THAN B OUTPUT
A= 8 A EQUALS TO B OUTPUT
I UNIT LOAD (40µA HIGH/ l.6 mA LOW
TRUTH TABLE
E A B AB A=B

H X X L L L
L WORD A WORD B =
L L H
L WORDA> WORD B L H L
L WORD A<WORD B H L L
L = LOW VOLTAGE LEVEL

H =
HIGH VOLTAGE LEVEL
X =
EITHER HIGH OR LOW VOLTAGE LEVEL
Page 1-15
KING
74800
120-0131-00
IA IB \Y 2A 2B 2Y GND
POSITIVE LOGIC Y= M
QUADRUPLE2-INPUT
Page 1-16
P8048
120-2026-00
I TO VCC 40
TI 39 >PORT#1
2 KTALi KTAL
3 KTAL 2 P27 39
4 RESËT P26 37
5 36 PORT&2
7 P25 RESET
6 ÏÑ P24 35
7 EA P17 34 SINGLE----r
STEP
RÖ Pf6 33 READ
G
9 PiiÑ PIB 32 EKTERNAL ---+
MEM
10 SET PI4 31
11 PI3 30
¯
ITE
ALE
12 DBO Pl2 29 TEST ---
13 DB Pil 28 ---+
-
PROGRAM
STORE
4 DB2 PIO 27 ENABLE
IS DB3 YDD 26 INTERRUPT
16 DB4 PROG 25
ADDRESS
-
>LATCH
y DBS P23 24 BUS < JE ENABLE
19 DBg P22 23
19 DB7 P21 22 PORT

EKPANDER
20 VSS P20 21 STROBE
8-BIT MICROCOMPUTER
SINGLE COMPONENT
DESCRIPTION
The Intel 8048/8035 is a totally self-sufficient 8-bit parallel computer fabricated

on a single silicon ship using Intel's N-channel silicon gate MOSprocess.
The 8048 contains a 1K x 8 program memory, a 64 x 8 RAM data memory, 27I/0 lines,
and an 8-bit timer/counter in addition to onboard oscillator and clock circuits.
The 8048 has a factory-programmed mask ROMprogram memory for low cost and high
volume production.
This microprocessor is designed to be an efficient controller as well as an arith-

metic processor. The 8048 has e×tensive bit handling capability as well as
facilities for both binary and BCD arithmetic. Efficient use of program memory
results from an instruction set consisting mostly of single byte instructions
and no instructions over 2 bytes in length.
Page 1-17
KING
PIN DESCRIPTION
P8048
120-2026-00
Designation Pin # Function Designation Pin # Function
Vgg 20 Circuit GND potential FÏÕ 8 Output strobe activated during a
VDD 26 Programming power supply; +25V BUS read. Can be used to enable
during program, +5V during oper. data onto the BUSfrom an external
ation for both ROM and PROM, device.
Low power standby pin in 8048 Used as a Read Strobe to External
ROM version. Data Memory. (Active low)
VCC 40 Main power supply; +5V during RN 4 input which is used to initialize the
operation and programming· processor.Also used during PROM
PROG 25 Program pulse (+25V) input pin programming verification, and
during 8748 programming, power down, (Active low)
Output strobe for 8243 I/O M 10 Output strobe during a BUS write.
expander. (Active low)(Non TTL VIH
P10-P17 27-34 &bit quasi-bidirectional port. Used as write strobe to External
Port 1 Data Memory.
P20-P27 21-24 &bit quasi-bidirectional port.
Port 2 35-38 ALE 11 Address Latch Enable. This signal
P20-P23 contain the four high
occurs once during each cycle and
order program counter bits during is useful as a clock output.
an external program memory fetch
and serve as a 4-bit I/O expander The negative edge of ALE strobes
bus for 8243 address into external data and pro-
12-19 gram memory.
DO-D7 True bidirectional port which can
-
---
BUS be written or read synchronously PSEN 9 Program Store Enable. This output
using the RD, WR strobes. The occurs only during a fetch to exter-
port can also be statically latched. nal program memory. (Active low)
Contains the 8 low order program SS 5 Single step input can be used in con-
Counter bits during an externet junction with ALE to "single step"
program memory fetch, and receives the processor through each in-
the addressed instruction under the struction. (Active low)
control of PSEN. Also contains the EA 7 External Access input which forœs
address and data during an external aN program memory fetches to re-
RAM data store instructiongnder ference external memory. Useful
control of ALE, RD, and WR. for emulation and debug, and
TO 1 Input pin testable using the con- essential for testing and program
ditional transfer instructions JTO
verification. (Active high)
and JNTO. TO can be designated as XTALI 2 One side of crystal input for inter-
a clock output using ENTOCLK nal oscillator. Also input for exter-
instruction. TO is also used during nal source. (Not TTL Compatible)
programming'
XTAL2 2 Other side of crystal input.
T1 39 Input pin testable using the JTT,
and JNT1 instructions. Can be des-
ignated the timer/counter input using
the STRT CNT instruction.
6 Interrupt input. Initiates an inter-
rupt if interrupt is enabled. Inter-
rupt is disabled after a reset. Also
testable.with conditional jump
instruction. (Active low)
CLOCK 1024 WORDS 64WORDS

PROGRAM DATA
MEMORY MEMORY
8-BIT /
CPU N
GBIT
TIMER/ 27
EVENT COUNTER t/O LINES
Page 1-18
ER1400/1400T
120-2028-00
14 BITS DATA REGISTER
AD MODE -------C
lOOXI4
-------
D WRITE DECODE ( ------02
E ERACE LOGIC
( -----
C3
s D / \
s
S DECODE
CLOCK CLOCK
GEN
MSB UNITS ADDRESS LSB ----
10 BITS
BOTTOM VIEW
VSS(GND) I • 14 Vm (NC)
o
Og 4
5
VGG(-35V) NC
C)2 6;C)
TO
o' e I. DATA I/O 5. CLOCK NC DATA \/O
oc2
4.
vs",
Vgg
i NC NC
8.C3
NC NC
8 LEAD TO-99
CLOCK C3
CI i) C2
1400 Bit Electrically Alterable Read Only Memory TOP y|EW

DESCRIPTION
DUAL INL.1NE
The ER1400 is a serial input/output 1400 bit electrically erasable and reprogrammable
ROM, organized as 100 words of 14 bits each. Data and address are communicated
in serial form via a one-pin bidirectional buss.
Addressing is by two consecutive one-of-ten codes.
Mode selection is by a 3 bit code applied to Cl, C2 and C3.

Data is stored by internal negative writing pulses that selectively tunnel charge
into the oxide-nitride interface of the gate insulator of the 1400 MNOSmemory
transistors. When the writing voltage is removed the charge trapped at the
interface is manifested as a negative shift in the threshold voltage of the
selected memory transistors.
Page 1-19
KING
P8243
120-2030-00 P 50 VCC
P40 2 23 P5I
P4 I 3 22 PS2
P42 4 21 P53
P43 5 20 P60
6 19 P61
PROG 7 18 P62
P23 8 17 P63
P22 9 16 P73
P21 10 15 P72
P20 II 14 P71
GND 12 13 P70
-
ADDRESS LATCH 4 PORT4
DECODER
UFFUER
INSTRUC
DECODER LATCH 4 PORTS
PORT 2 MUX pF
TEMP
4 LATCH 4 PORT 6
A 10CR
PROG CONTROL INPUT
O
BUFFER
4
TCH 4 PORT 7
Page 1-20
KIN G
P8243
120-2030-00
8243
PIN DESCRIPTION A high to low transition of the PROG tine indicates that
address is present while a low to high transition indicates
Symbol Pin No. Function
the presence of data. Additional 8243s may be addedto
PROG 7 Clock Input. A high to low the 4-bit bus and chip selected using additional output
transistion on PROG signifies lines from the 8048/8748/8035.
that address and control are
available on P20-P23, and a low Power On initialization
to high transition signifies that initial application of power to the device forces
data is available on P20-23 input/output ports 4, 5, 6.and 7tothetri-stateandport2to
CS 6 Chip Select Input. A highon CS the input mode. The PROG pin may be either high or low
inhibits any changeofoutputor when power is applied. The first high to low transition of
internal status. PROG causes devicetoexit power on mode. The poweron
P20-P23 11-8 Four (4) bit bi-directional port sequence is initiated if Vcc drops below TV.
conta s the addrhe s and co
P21 P20 Address Code P23 P22 Instruction Code
transition of PROG. During a O 0 Port 4 0 0 Read
low to high transition contains 0 1 Port 5 0 1 Write
the data for a selected output 1 0 Port 6 1 0 ORLD
port if a write operation, or the 1 1 Port 7 1 1 ANLD
data from a selected port before
the low to hÍgh transition if a Wdte 191odes
read operation.
The device'has three write modes. MOVD Pi, A directly
GND 12 0 voit supply. writes new data into the selected port and old data is lost.
P40-P43 2-5 Four (4) bit bi-directiorial I/O ORLD Pi,A takes new data, OR's it with theold data and
PSO-P53 1,23-21 ports. May be programmed then writes it to the port. ANLD Pi,A takes new datà AND's
PSO-P63 20-17 to be input (during read), it with the old data and then writes it to the port. Operation
P70-P73 13-16 fow impedance latched output codeandportaddressarelatchedfromtheinputport2on
(after write) or a tri-state (after the high to low transition of the PROG pin. On the lowto
read).DataonpinsP20-23may hightransitionofPROGdataonport2istransferredtothe
be directly written, ANDed or logic block of the specified output port.
ORed with previous data After the logic manipulation is performed, the data is
VCC 24 +5 volt supply. . latched and outputed. The old data remams latched until
new valid outputs are entered.
General Operation Read Mode
The 8243 contains four 4-bit I/O ports which serve as an The device has one read mode. The operation code and
extensiorl of the on-chip 1/O and are addressed asports4. port address are latched from the input port 2 on the high
7. The following operations may be performed on these to low transition of the PROG pin. As soon as the read
ports: operation and port address are decoded, the appropriate
outputs are tri-stated, and the input buffers switched on.
• Accumulator to Port.
Transfer
The read operation is terminated by a low, to high
• Port to Accumulator.
Transfer
transition of the PROG pin. The port (4. 5. 6or 7) that was
• AND Accumulator to Port.
selected is switched to the tri stated mode while port 2is
• OR Accumulator to Port.
returned to the input mode.
All communication between the 8048 and the 8243occurs
over Port 2 (P20-P23) with timing provided by an output Normally, a port will be in artoutput (write mode) or input
pulse on the PROG pin of the processor. Each transfer (read mode). If modes are changed during operation, the
consists of two 4-bit nibbles: firstreadfollowingawriteshouldbergnored:allfollowing
reads are valid. This is to allow the external driver on the
The first containing the "op code" and port addiess and port to settle after the first read instruction removes the
the second containing the actual 4-bits of data low impedance drive from the 8243output.
Page 1-21
MC1350P
120-3020-00
MONOLITHICIF AMPLIFIER
...an integrated circuit featuring wide range AGC for use as an IF amplifier in radio and TV over the
temperature range 0 to +75°C.
Power Gain -
50dB typ. at 45MHz,
-
48dB typ. at 58MHz
AGC Range -
60dB min, DC to 45MHz
Nearly constant input and output admittance over the entire AGC range
Constant (-3.0dB) to 90MHz

Y21
Low Reverse Transfer Admittance -
1.0umho typ.
12-Volt Operation, Single-Polarity Power Supply
7812 OUTPUT ,
120-3026-06 COMMON L
INPUT
12V
THREE-TERMINAL
POSITIVE VOLTAGE REGULATORS
This series of three-terminal positive voltage regulators are monolithic

integrated circuits designed as fixed-voltage regulators for a wide variety
of applications including local, on-card regulation. Available in seven
fixed output voltage options from 5.0 to 24 volts, these regulators employ
internal current limiting, thermal shutdown, and safe area compensation -
making them essentially blow-out proof. With adequate heatsinking they can
deliver output currents in excess of 1.0 ampere. The last two digits of
the part number indicate nominal output voltage.
Page 1-22
NE555V
120-3040-00 OPVIEW)
CONTROL
OIS THRE& VOLT
VCCCHARGEHOLD AGE
GND TRIG OUT RESET

GER PUT
functional block diagram
CONTROL
VCC VOLTAGE RESET
(5) (5) Wi
THRESHOLD
COMP OUTPUT
GND DISCHARGE
TIMING CIRCUIT
This monolithic timing circuit is a high stable controller capable of producing

accurate time delays, or oscillation. Additional terminals are provided for
triggering or resetting if desired. In the time delay mode of operation, the time
is precisely controlled by one external resistor and capacitor. For a stable
operation as an oscillator, the free running frequency and the duty cycle are
both accurately controlled with two external resistors and one capacitor. The
circuit may be triggered and reset on falling waveforms, and the output structure
can source or sink up to 200ma or drive MTTL circuits.
Page 1-23
LM339N
120-3048-00
Dual-In Lneand FlatPackage
OUTPUT1 00TPUT 1 Y INPUT I 1NPUT1· INPUT2- INPUT2+

TOPVIEW
The LM339 consists of four independent

voltage comparators which were designed
specifically to operate from a single power
supply over a wide range of voltages.
Operation from split power supplies is also
possible and the low power supply current
drain is independent of the magnitude of
the power supply voltage. These comparators
also have a unique characteristic in that
the input common-modevoltage range includes
ground, even though operated from a single
power supply voltage.
Page 1-24
KING
LM324
120-3052-00
DUAL-IN-LINE AND FLAT PACKAGE

OUTPUT INPUT 1NPUT GND INPUT INPUT OUTPUT
4 4 3+ 3 3
I 2 3 4 5 6 7
OUTPUT INPUT INPUT

I¯ V INPUT INPUTOUTPUT
2¯
I I* 2* 2
TOP VIEW
GENERALDESCRIPTION
This series consists of four independent, high gain, internally frequency

compensated operational which were designed specifically
.amplifiers to
operate from a single power supply over a wide range of voltages. Operation
from split power supplies is also possible and the low power supply current
drain is independent of the magnitude of the power supply voltage.
Application areas include transducer amplifiers, DC gain blocks and all the
conventional op amp circuits which now can be more easily implemented in
single power systems. For example, this series can be directly operated
off of the standard +5VDC power supply voltage which is used in digital systems
and will easily provide the required interface electronics without requiring
the additional +15VDC power supplies.
Page 1-25
LM358
DUAL-IN-LINE PACKAGE
120-3053-Otl
OUTPUT A -
U y+
7
INVERTING INPUT A i .
OUTPUT B
A B
NON INVERTING 3 6
INPUT A INVERTING
INPUT B
4 5
GND NON INVERTING
INPUT B
The LM358Nconsists of two independent, high

gain, internally frequency compensated opera-
tional amplifiers which were designed specif-
ically to operate from a single power supply
over a wide range of voltages. Operation from
split power supplies is also possible and the
low power supply current drain is independent
of the magnitude of the power supply voltage.
Page 1-26
KING
LM380N
120-3080-00
BYPASS I -- ---
VS
NON-INVERTING INPUT 2 --- --
13 NC
BYPASSVS 3 ¯¯¯ ¯¯
12
2 ' GND ( 4-----

14
----
II >GND
-----
+
LM38
6
---- -
3,4,5 5 --- ---
10
7 10,11,12 % ./
INVERTING INPUT 6 ---· ---
9
GND GND
GND 7---- ---
g yOUT
HEATSINKPINS
TOP VIEW
AUDIO, RADIOANDTV CIRCUITS
GENERALDESCRIPTION
The LM380 is a power audio amplifier for consumer application. In order to hold system
cost to a minimum, gain is internally fixed at 34dB. A unique input stage allows inputs
to be ground referenced. The output is automatically self entering to one half the
supply voltage.
The output is short circuit proof with internal thermal limiting. The package outline
is standard dual-in-l ine. A copper l ead frame is used with the center three pins on
either side comprising a heat sink. This makes the device easy to use in standard PC
layout.
Page 1-27
KING
SUBSTRATTE
CA3146AE
\4 |3 12 II IO 9 8
120-3087-03
Q5 --------
Q4
I 2 3 4 5 6 7
TRANSISTOR ARRAY
GENERAL DESCRIPTION
This device consists of five high voltage general purpose silicon NPN transistors
on a common monolithic substrate. Two of the transistors are internally connected
to form a differentia11y-connected pair. The transistors are well suited to a
wide variety of applications in low power systems in the DC through VHF range.
They may be used as discrete transistors in conventional circuits; however, in
addition, they provide the very significant inherent integrated circuit advantages
of close electrical and thermal matching.
DUTPUT
INPUT
340LAZ-5.0
2 3 I
120-3094-32
SV
3-TERMINALPOSTIVE REGULATORS GND
BOTTOM VIEW
GENERALDESCRIPTION
This series of three terminal positive regulators is available with several

fixed output voltages making them useful in a wide range of applications.
The regulators have +3% VOU specification, 0.04%/V line regulation, and
0.01%/ma load regulation. When used as a zener diode/resistor combination
replacement, the regulator usually results in an effective output impedance
improvement of two orders of magnitude, and lower quiescent current.
These regulators can provide local on card regulation, eliminating the
distribution problems associated with single point regulation.
With adequate heat sinking the regulator can deliver 100ma output current.
Current limiting is included to limit the peak output current to a safe value.
Safe area protection for the output transistor is provided to limit internal
power dissipation. If internal power dissipation becomes too high for the
heat sinking provided, the thermal shutdown circuit takes over, preventing the
IC from overheating.
Page 1-28
KIN G
SPB 6 4 0 B
CLOCK 1/p CLOCK 14
120-4006-01
PT NC
DNC
NC NC
CC EE
NC SPS646/7 TTLo/p
NC NC
o/p (Q4) PÑ
NOTE.
UNUSEDPINS (EXCEPT 8 AND9) MAYBE
CONNECTEDTO VEE. THIS WILL REDUCE
CLOCK BREAKTHROUGHON THE OUTPUTS,
PINS 8 AND 9 SHOULDBE LEFT OPEN-CIRCUIT
WHEN NOT IN USE.
CLOCK TTL
PULSE I 2 3 04
o/p
ILHHHH
DIV 2LLHH H
PE PE
I 2 RAT10 3 L L L H H
---- ---- ----
4 H L L H H
LLII 5HHLHH
HLIO 6LHHLL
LHIO 7LLHLL
HHIO 8LLLLL
9 H L L L L
TRUTHTABLEFOR 10 H H L_ L_ L
_ _ _
CONTROL PUTS -H _H _
_H _
H H
EXTRA STATE
TRUTHTABLEFOR CONTROLINPUTS COUNT SEQUENCE
Page 1-29
KING
NC 6Y 6A NC 5Y 5A 4V 4A
SCL4049
16 15 14 13 12 11 10 9
120-6025-01
SCL4049UB SCL405000
SCL4050ABC
I 2345678
120-6026-01
V IY lA 2Y 2A 3Y 3A VSS
PIN CONNECTIONS
SCL4049 SCL4050
IA -3
2--¡Y lA-3 2-¯\Y
2A-5 4--2Y2A-5 4-2Y
3A-7 e-3Y3A-7 e-3Y
4 A -9 io-4Y4A--9 10-4Y
5A --Il 12-5YSA-li I2-5Y
6A -14 15-6Y6A--i4 is-6Y

N.C.- 13, 16
Y=Ä VCC¯ '
Y=A
VSS -8
LOG1C DIAGRAM
CMOS HEXBUFFERS/CONVERTERS
The SCL4049 is an inverting hex buffer and the SCL4050 is

a non-inverting hex buffer. Both feature logic-level
conversion using only one supply voltage (VCC). The
input-signal high level (V H) can exceed the VCC supply
voltage when these devices are used for logic-Tevel
conversions. These devices are intended for use as
COS/MOSto DTL/TTL converters and can drive directly two
DTL/TTL loads. (VCC 5V, VOL 0.4V, and DN
=
3ma).
Page 1-30
SCL4017AB
120-6027-01
BLOCK DIAGRAM
CLOCK 14 o- 0 ---o
3
' I -----o
2
VDD R CL CE OUT "9" "4" "8 2 ---o
4
I
16
I
15
I
14
I
13
\
12
\I
I
\
10 9
\ =
4
-----o
---o
7
10
CLOCK
ENABLE130- 65 ---o I
SCL4017AB
7 -----o
6
I 2 3 4 5 6 7 8
8 -----o 9
I I I ..
I .. .. ·· ..
\ ..
\ s
eOUT
-----on
RESET 150--
,, ,, ,, ,, ,, ., ,, ,.
I O 2 6 3 VSS --o
12
VDD= PINI6
USS = PINS
CMOS DECADECOUNTER/DIVIDER
DESCRIPTION
The SCL4017AB consists of a 5-stage Johnson Decade Counter and an Output Decoder.
Inputs include Clock, Reset, and Clock Enable signals.
The counter has interchangeable Clock and Clock Enable lines for incrementing on
either a positive-going or negative-going transition, respectively. A high Reset
signal clears the counter to its zero count.
Use of the Johnson decade counter configuration permits high-speed operation,

2-input decode gating, and spike-free decoded outputs. Anti-lock gating is
provided, thus assuring proper counting sequence. The 10 decoded outputs are
normally low and go high only at their respective decoded time slot. Each
decoded output remains high for one full clock cycle. A Carry-out (COUT) signal
completes one cycle every 10 clock input cycles and is used to directly clock
the succeeding counter in multi-stage applications.
This part can be used in frequency division circuits as well as decade counter or
decimal decode display applications.
Page 1-31
SCL4046
120-6038-01
ZENHIR DEMOD OUT
VDD SIG PCIL VCO

IN OUT R2 RI IN
16 15 l=4 13 12 II 10 9
SC L4046B
\ 2 3 4 5 6 7 8
| | \ i l I
PC I VCO INH Cl Cl VSS
OUT OUT (A) (B)
PHASE COMP
PULSES IN
CMOS PHASE-LOCKED
LOOPS
DESCRIPTION
The SCL4046B is a phase-locked loop containing two phase comparators, a voltage-

controlled oscillator (VCO), source follower, and zener diode. The comparators
have two common inputs. The signal input can be used directly coupled to large
voltage signals, or indirectly coupled (with a series capacitor) to small voltage
signals. The self-bias circuit adjusts small voltage signals in the linear
region of the amplifier. Phase comparator I (an exclusive-OR gate) provides a
digital error signal PCIout, and maintains 90° phase shift at the center frequency
between signal and comparator inputs (both at 50% duty cycle). Phase comparator
II (with leading edge sensing logic) provides digital error signals PCIIout and
phase pulses, and maintains a 0° phase shift between input signals (duty cycle is
immaterial). The linear VCO produces an output signal VC0aut whose frequency is
determined by the voltage of input VC0in and the capacitor and resistors connected
to pins C1A, C18, R1, and R2. The source follower output, Demod Out, with an
external resistor is used where the VC0in signal is needed but no loading can be
tolerated. The inhibit input Inh, when high, disables the VCOand source follower
to minimize standby power consumption. The zener diode can be used to assist in
power supply regulation.
Page 1-32
KING
POSITIVE LOGIC
SCL4022AC+ CLOCK
CLOCK ENABLE RESET OUTPUT= n
120 6045-01
0 X O n
X 1 0 n
O O n+1
X O n
1 0 n + il
X O n
X X 1 "O"
"
COUT "4" "7 N.C.
DD C C CARRY = 1, OTHERWISE
X DON'T CARE IF n<4 =0
SCL4022AB
" " " " ' N.C

,, .. ..
SS CLOCK
---o
2
'
ADD SUFFIX FOR PACKAGE 2
C 16 PIN CERDIP CLOCK 3 ---o
7
ENABLEf3 4 II
D 16 PIN CERAMIC
E 16 PIN EPOXY 5 ---o
4
6 --o
5
F 16 PIN FLAT
7 ---o
¡O
H CHIP RESET 15 C OUT ---o 12
CMOS Octal Counter/Divider DD = PIN 16

VSS = PIN 8
DESCRIPTION
This device consists of a 4-stage Johnson Divide-by-8 Counter and an Output Decoder.
either a positive-going or negative-going transition, respectively. A high
Reset signal clears the counter to its zero count.
Use of the Johnson divide-by-eight counter configuration permits high-speed
operation, 2-input decode gating, and spike-free decoded outputs. Anti-lock
gating is provided, thus assuring proper counting sequence. The 8 decoded outputs
are normally low and go high only at their respective decoded time slot. Each
decoded output remains high for one full clock cycle. A Carry-out (C ) signal
completes one cycle every 8 clock input cycles and is used to direct1 lock the
succeeding counter in multi-stage applications.
This part can be used in frequency division circuits as well as octal counter or
octal decode display applications.
Page 1-33
SCL4060ABC
120-6(155-01
YDD 010 08 09 R 0 0
I | \ I I | \
16 . 15 14 13 12 11 10 9
SCL4060AB
\ 2 3 4 5 6 7 8
GIS 013 QI4 06 05 07 04 VSS
CONNECTION DIAGRAM
CLOCK RESET OUTPUTSTATE

O NO CHANGE
O ADVANCETO NEXT
STATE
X \ ALL OUTPUTS ARE LOW
X i DON T CARE
TRUTH TABLE
CMOS14-STAGE BINARYCOUNTER
ANDOSCILLATOR
DESCRIPTION
This device consists of an oscillator section.and 14 ripple-carry binary

counter stages. The oscillator configuratipn allows design of either
R-C or crystal oscillator circuits. A Reset input is provided which
resets the counter to the all O's state. A high level on the Reset line
accomplishes the reset function. The state of the counter is advanced
one step in binary order on the negative transition of the Clock input
0. All inputs and outputs are fully buffered. Outputs are available from
stages 4 through 10 and 12 through 14.
Page 1-34
KING
SERIAL
OOUTPUTS
DATA 2 8-STAGE I glS
SHIFT
CLOCK 3 REGISTER S
004094 S
120-6056-00
SCL4094 g_g y
120-6056-01 STROBE I STORAGE
REGISTER
OUTPUT
ENABLE 15 3-STATE Y DO = 16
OUTPUTS Y SS =
8
PARALLEL OUTPUTS QI-QS
(TERMINALS 4,5,6,7,I4,I3,\2,Il RESPECTIVELY)
FUNCTIONALDIAGRAM
TRUTH TABLE
PARALLEL SERIAL
STROBE DATA OUTPUTS OUTPUTS
CL OUTPUT
ENABLE QI QN QSI Q'S
O X X OC OC Q7 NC
o x x oc oC NC Q7
I O X NC NC Q7 NC
I I O O ON-I Q7 NC
\ \ \ \ QN-I Q7 NC
I \ I NC NC NC Q7
A =
LEVEL CHANGE LOGIC I HIGH=
X DON'T CARE O¯ LOW

LOGIC
NC NOCHARGE=
OC OPEN CIRCUIT
=
AT THE POSITIVE CLOCK EDGE INFORMATION IN THE 7 th SHIFT

REGISTER STAGE IS TRANSFERRED TOTHE 8 th REGISTER STAGE
AND THE QSOUTPUT.
8 STAGE SHIFT-AND-STOREBUS REGISTER
Page 1-35
APPENDIX"A"
TABLE OF CONTENTS
SEMICONDUCTOR
AND INTEGRATED CIRCUIT DATA
Paragraph Page
1.1 General 1-1

1.1.1 Semiconductor Test Equipment 1-1
1.1.2 Semiconductor Voltage and Resistance Measurements 1-1
1.1.3 Testing of Transistors 1-1
1.1.4 Replacing Semiconductors 1-2
1.2 Integrated Circuit Maintenance 1-2

1.2.1 General 1-2
1.2.2 Terminology 1-3
1.2.3 Integrated Circuit Test Equipment 1-3
1.2.4 Voltage Measurements 1-3
1.2.5 Testing Integrated Circuits 1-3
1.2.6 Replacing Integrated Circuits 1-4
1-i
APPENDIX"A"
1.1 GENERAL
Due to the wide utilization of semiconductors in this electronic equipment, somewhat different
techniques are necessary in maintenance procedures. In solid state circuits the impedances and
resistances encountered are of much lower values than those encountered in vacuum-tube circuits.
Therefore, a few ohms discrepancy can greatly affect the performance of the equipment. Also, coupling
and filter capacitors are of larger values and usually are of the tantalum t.ype. Hence, when measuring
values of capacitors, an instrument accurate in the high ranges must be employed. Capacitor polarity
must be observed when measuring resistance. Usually more accurate measurements can be obtained if
the semiconductors are removed or disconnected from the circuits.
1.1.1 TEST EQUIPMENT

SEMICONDUCTOR
Damage to semiconductors by test equipment is usually the result of accidentally applying too much
voltage to the elements. Commoncauses of damage from test equipment are discussed in the following
paragraph.
A. Transformerless Power Supplies
Test equipment with transformerless power supplies is one source of high current. However,
this type of test equipment can be used by employing an isolation transformer in the AC
power line.
B. Line Filter
It is still possible to damage semiconductors from line current, even though the test
equipment has a power transformer in the power supply, if the test equipment is provided
with a line filter. This filter may function as a voltage divider and apply half voltage
to the semiconductor. To eliminate this condition, connect a ground wire from the chassis
to the test equipment to the chassis of the equipment under test before making any other
connections.
C. Low-Sensitivity Multimeters
Another cause of semiconductor damage is a multimeter that requires excessive current to

provide adequate indications. Multimeters with sensitivities of less than 20,000 ohms-
per-volt should not be used on semiconductors. When in doubt as to the amount of current
supplied by a multimeter, check the multimeter circuits on all scales with an external,
low-resistance multimeter connected in series with the multimeter leads. If more than
one milliampere is drawn on any range, this range cannot be safely used on small
semiconductors.
D. Power Supply
When using a battery-type power supply, always use fresh batteries of the proper value.
Make certain that the polarity of the power supply is correct for the equipment under test.
Do not use power supplies having poor voltage regulation.
1.1.2 SEMICONDUCTOR
VOLTAGEANDRESISTANCEMEASUREMENTS
When measuring voltage or resistance in circuits containing semiconductor devices, remember that these
components are polarity and voltage conscious. Since the values of capacitors used in semiconductor >
circuits are usually large, time is required to charge these capacitors when they appear. Thus, any
reading obtained is subject to error if sufficient time is not allowed for the capacitor to fully
charge. When in doubt it may be best in some cases to isolate the components in question and measure
them individually.
1.1.3 TESTING OF TRANSISTORS
A transistor checker should be used to properly evaluate transistors. If a transistor tester is not
available, a good multimeter may be used. Make sure that the multimeter meets the requirements out-
lined in the preceding paragraph.
Page 1-1
KING
APPENDIX"A"
A. PNP Transistor
To check a PNP transistor, connect the positive lead of the multimeter to the base of the
transistor and the negative lead to the emitter or collector. Generally, a resistance
reading of 50,000 ohms or more should be obtained. Reconnect the multimeter with the
negative lead to the base. With the positive lead connected to the emitter or collector
a resistance value of 500 ohms or less should be obtained.
B. NPN Transistor
Similar tests made on an NPN transistor should produce the following results:
With the negative lead of the multimeter connected to the base of the transistor the value
of resistance between the base and the collector or emitter should be high. With the
positive lead of the multimeter connected to the base, the value of resistance between
the base and the collector or emitter should be low. If these results are not obtained,
the transistor is probably defective and should be replaced.
CAUTION
IF A TRANSISTORIS FOUNDTO BE DEFECTIVE, MAKECERTAIN

THATTHE CIRCUIT IS IN GOODOPERATINGORDERBEFORE
INSTALLINGA REPLACEMENT TRANSISTOR. IF A SHORTCIRCUIT
EXISTS IN THE CIRCUIT, PUTTINGIN ANOTHERTRANSISTOR
WILL MOSTLIKELY RESULTIN BURNINGOUTTHE NEWCOMPONENT.
DO NOTDEPENDUPONFUSES TO PROTECTTRANSISTORS.
C. Always check the value of the bias resistors in series with the various elements. A
transistor is ver.y sensitive to improper bias voltage; therefore, a short or open circuit
in the bias resistors may damage the transistor.
1.1.4 REPLACINGSEMICONDUCTORS
Never remove or replace a semiconductor with the supply voltage turned on. Transients thus produced
may damage the semiconductor or others remaining in the.circuit. If a semiconductor is to be evaluated
in an external test circuit, be sure that no more voltage is applied to the semiconductor than normally
is used in the circuit from which it came.
A. Use only a low heat soldering iron when installing or removing soldered-in semiconductors.
Grasp the lead to which heat is applied between the solder joint and the semiconductor
with long nosed pliers.
This will dissipate some of the heat that would otherwise be conducted into the semi-
conductor from the soldering iron. Make certain that all wires soldered to semiconductor
terminals have first been properly tinned so that the necessary connection can be made
quickly. Excessive heat will permanently damage a semiconductor.
B. In some cases, power transistors are mounted on heat-sinks that are designed to dissipate
heat away from them. In some power circuits, the transistor must also be insulated from
ground. This insulating is accomplished by means of an insulating washer made of mica.
When replacing transistors mounted in this manner, be sure that the insulating washers
are replaced in proper order. After the transistor is mounted, and before making any
connections, check from the case of the transistor to ground with a multimeter to see
that the insulation is effective.
1.2 INTEGRATED
CIRCUITMAINTENANCE
1.2.1 GENERAL
A knowledge of integrated circuit fundamentals is as necessary in testing digital logic circuits

involving IC's as a knowledge of rectification fundamentals is needed to test a power supply.
Page 1-2
KING
APPENDIX"A"
1.2.2 TERMINOLOGY
Several terms are used whenever logic circuits are discussed:
A. A logic state is defined as a high or low level voltage applied to the input or seen at
the output of a device. A high level voltage is called a logic "1". A low level voltage
is called a logic "0". Logic threshold voltage of a device is the input voltage required
at an input to change the output state.
B. A truth table is a list of input logic states that will yield certain output logic states.
A digital logic element should be thoughtof as a circuit element with its output level
being either HI or LO as programmed by the levels present on its inputs.
A logic element may be tested by verifying that it is performing per the Truth Table of
that logic element.
C. Logic elements which have multiple inputs and a single output are known as gates. The OR
gate produces a HI output when one or more of the inputs are HI. With all inputs LO, the
output is LO. The ANDgate produces a HI output only when all inputs are HI. When any
input is L0 the output is LO. A small circle at the output of a gate on the schematics
indicates "negation", which means that the sense of the gate logic is reversed. An OR
gate with negation is called a NOR gate and an ANDgate with negation is called a NAND
gate. A NORgate produces a LO output when one or more of the inputs are HI and a NAND
gate produces a LO output only when all inputs are HI.
D. The Flip-Flop logic element is the basic data storage element of digital logic. It has
two outputs that are always at opposite logic levels. That is, when one output is HI the
other is LO. The Flip-Flop will remain in a particular state until that state is changed
by an input signal.
The operation of these Flip-Flops is controlled by the signals on their inputs, and is
best understood by a careful study of their Truth Tables. It should be kept in mind
that a small circle on either the input or the output indicates negation. Also, a
circle on a clock input indicates that a HI to LO transition causes the Flip-Flop to function.
E. Besides the gates and Flip-Flops, two other commonly used logic elements are inverters and
expanders. Inverters are merely switching transistors such that if a logic "1" is the input
to a device, a logic "0" will be the output and vice-versa. An expander is a set of
parallel switching transistors that depends upon another resistor to provide their supply
voltage. Generally, these devices are used to expand the number of inputs available to
a standard gate.
1.2.3 INTEGRATEDCIRCUIT TEST EQUIPMENT
As with semiconductors, damage to integrated circuits by test equipment is usually the result of
applying too much current or voltage to the elements. The same precautions as discussed in Paragraph
1.1.1 apply here.
1.2.4 VOLTAGEMEASUREMENTS
Precise voltage measurements are not needed in testing digital IC's other than to see that the voltage
is a HI or a L0 level. An oscilloscope is needed where the input levels are of short duration,
either HI or LO. For instance, if a 10 microsecond pulse going from LO to HI was applied to one input
of a NORgate, while the other input stayed LO, the output would go LO for 10 microseconds and then
return HI. This, of course, could not be seen without an oscilloscope.
1.2.5 TESTING INTEGRATED CIRCUITS
The fully loaded guaranteed minimum high and maximum low for the digital logic output levels are:
TTL (Vcc =
+5V) ECL (Vcc =
+5.2V)
High Low High Low
2.4 0.5 4.25 3.48
Page 1-3
APPENDIX"A"
The minimum high and maximum low input levels which are guaranteed to be correctly interpreted are:
TTL (Vcc =
+5V) ECL (Vcc =
+5.2V)
High Low High Low
2.0 0.8 4.06 3.75
When checking input and output levels of a logic element under question it should be remembered that an
input or output may not agree with its truth table not because it has malfunctioned but because some
other component connected to the same point has shorted to ground or to the supply voltage (Vcc). This
is not common when an output on one element is connected to an input of another. A majority of digital
IC failures can be grouped into threee categories:
A. Input(s) or output shorted to ground pin of IC.

B. Input(s) or output shorted to Vcc pin of IC.
C. Open input(s) or output.
An input or output shorted to ground would be a constant LO and an input or output shorted to Vcc
would be a constant HI.
Other failures common in digital IC's are:
A. Ground pin open.
B. Vcc pin open.
C. Inputs shorted together.

An open ground pin would not allow a LO on the output. An open Vcc pin would not allow a HI on the
output. (Remember to isolate the device from other components connected to it). Two or more inputs
shorted together can be checked by grounding one of the inputs under question. If the other input also
goes to ground they are probably shorted.
CAUTION
IF AN IC IS FOUND TO BE DEFECTIVE, VERIFYTHAT PROPER

POWER SUPPLYVOLTAGES ARE PRESENTBEFOREINSTALLINGA
REPLACEMENT
IC.
1.2.6 REPLACINGINTEGRATED CIRCUITS
If an IC is known to be defective, the easiest way to remove it is to cut off each of its pins, remove
the case, and then unsolder the remaining pins from the integrated circuit card one by one. This is
preferrable over removing the IC intact because attempts to remove the IC intact may result in
damage to the printed circuit board.
KING
A Z
FLGURE I.
Z=A
A Z
FIGURE 2.
Z Z= A
A
FIGURE 3. N
Z Z=
0 0 i O
FIGURE 4. AC
Z Z=
0 0 I I
\ O I
\ O \ I
O I I I
GA E
FIGURE 5. EXCLUSIVE OR
A Z Z = AG)B
T_RANSLATORS
CMOS VOLTAGE LEVEL
FIGURE 6.
INVERTER
gFFE
Voo=14V
Voo = 14V
Vcc = SV VIN OY
Vcc = 5V VlN OV 14V
VouT VOUT 5V OV
OV 5V yin
VIN VouT VouT
Vss= GND
Vss = GND
Page 1-5
KING
FIGURE 7. NOR GATE FLIP-FLOP
S
Q S R Next Q Õ
I I O O
O 1 I O
0 0 NC NC NC= NO CHANGE
\ O O I
R
FIGURE 8. MONOSTABLE MULTIVlBRATOR (ONE-SHOT)

VDD
TRIGGER
INPUT 4
C
THRESHOLD
o l
FIGURE 9. ASTABLE MULTIVIBRATOR (FREE-RUNNING)
VDD
4
Rss
CTC
2
FREQUENCY OF OPERATION IS DETERMINED BY RTC AND CTC.

A NOR OR NAND GATE MAY BE USED IN PLACE OF THE FIRST
INVERTER TO PERMIT GATING OF THE MULTIVlBRATOR.
FIGURE 10. DIFNF A
U
¯
®
OFTEN USED TO CHANGE A STEP SIGNAL
TO A SHORT PULSE SIGNAL.
Page 1-6
KING
LOCATION OtAGRAMS
INTEGRATED CtRCutT PIN
From TOP 0
( Viewed
2 10
3 *
4 6
5 6
10 g
\
2 8
3 I
4 6
5 9
4 8
5 6
2 6
3 5
4
Page 1-7
KING
12041.080865
-00
CLR PR
K Q - --
J Q --
:>CK >CK
ICK IPR I IJ VCC 2CK 2 PR 2

CLR CLR
'LS76
FUNCTION TABLE
INPUTS OUTPUTS
PRESET CLEAR CLOCK J K Q Q
L H X XX HL
H L X XX LH
L L X X X HN HA
H H I L L QO O
H H \ HL HL
H H I LH LH
H H I H H TOGGLE
H H H X X QO O
THIS CONFIGURATIONIS NONSTABLE', THATIS

IT WILL NOT PERSIST WHEN PRESET ANDCLEAR
INPUTS RETURNTO THEIR INACTIVE (HIGH)LEVEL.
DUALJ-K FLIP-FLOPS WITH PRESET & CLEAR
Page 1-8
f(Inl(I
74LS162
120-0087-00
74LS163 74LS162 74LS163
120-0088-00
0 I 2 3 4 0 I 2 3 4
15 5 15 5
\·4 6 \•4 6
15 7 15 7
12 9 8 12 11 10 9 8
LOGIC EQUltrHDNS
COUNT ENABLE= CEP·CET PE
TC FOR 74LSI62 = CET-00 I 2 3
TC FOR 74LSI63 = CET•OO 2° 3
I
PRESET= PE·CP+ (RISING CLOCK EDGE)
RESET= NUÑ
PIN NAMES
¯Ï
Parallel Enable (Active LOW) Input
PO, 1, 2, 3
Parallel Inputs
CEP Count Enable Parallel Input
CET Count Enable Trickle Input
CP Clock (Active HIGH Going Edge) Input
ÑR Master Reset (Active LOW) Input
Q1' 2' 3' 4 Parallel Outputs
TC Terminal Count Outputs
Page 1-9
74LS162
OUTPUTS
120-0087-00 31
VCC 70 0 i 2 CET PE
0388-00
COUR 0 I 3 CET
2
CP PO I 2 3y CEP GND
DATA INPUTS
BCD DECADE COUNTER/4-BIT BINARY COUNTER
The 74LS162 is a high speed BCD decade counter, and the 74LS163 is a high speed
binary counter. Both counters are fully synchrounous will the clock pulse
driving four master/slave flip-flops in parallel through a clock buffer.
The three control inputs, Parallel Enable (PE), Count Enable Parallel (CEP),
and Count Enable Trickle (CET), select the mode of operation as shown in the
tables below. When the conditions for counting are satisfied, the rising edge
of a clock pulse will change the counters to the next state of the count
sequence shown in the State Diagram on the previous page. The Count Mode is
enabled when CEP and CET inputs and PE are HIGH.
The 74LS162 and 74LS163 can be synchronously preset from the four Parallel
inputs, (PO-3) when PE is LOW. When the Parallel Enable and Clock are LOW,
each master of the flip-flops is connected to the appropriate parallel input
(PO-3) and the slaves (outputs) are steady in their previous state. When the
clock goes HIGH, the masters are inhibited and this information is transferred
to the slaves and reflected at the outputs. The parallel enable input overrides
both count enable inputs, presetting the counter when LOW.
Terminal count is HIGH when the counter is at terminal count (state 9 for
74LS162, and state 15 for 74LS163), and Count Enable Trickle is HIGH, as is
shown in the logic equations. When LOW, the asynchronous master reset overrides
all other inputs resetting the four outputs LOW.
Page 1-10
KING
088884 d. pt.
120-0089-00 CC a b c d e f OUTPUT
18 17 16 15 14 13 12 II 10
1234567
PROG. A B C D D.PI comma comma GND
INPUT INPUTOUTPUT
TOP VlEW
FUNCTION DPT. COMMA D C B A a b c d e f g DISPLAY

O I l 000000 0000 l II
I-I
I l I 000I I00111 I I
I
2 I I 00 1000 100 10 y
3 I I 00 I 10000 1 1 0 O
4 I I 01001001100 I-I
I
5 I I 0 10 10 100 100 --
6 I I O I I 00 I 00000
7 I I 01110001111
8 i I 1000 0000000
9 I I 10010000100
10 I I 1010110001I
Il I I IOllllOOOIO j-
12 I I I 10000 I I 100
f b
13 I I I I O I O I I O O O O '-
I-
I
e c
l4 I I !!!01111110 : d
15 I I I I I I I I I l I I I
CDmma 00
O DECIMAL POINT
COMMA
DECIMAL POINT AND COMMACAN BE DISPLAYED WITH OR WITHOUT ANY NUMERAL.
Page 1-11
Vcc LOGIC DIAGRAM
058884
r- -- ¯¯ -- -- -- ¯- -- -- ¯l
120-0089-00 ouTPUTs
c
Vcc
INPUATS
c d
cc
7SEGMENT
DECODER
e
Vcc
C
Vcc
D
Vcc comma
COMMA
PROGRAMMABLE REFERENCE
CURRENT4 ClRCUIT
BLANKING \
L - - - -
GND
HIGH VOLTAGECATHODEDECODER/DRIVER
GENERALDESCRIPTION
The DS8884A is designed to decode

four of BCDinput and drive
lines
seven-segment digits of gas-filled
readout displays. Two separate
inputs are provided for driving
the decimal point and comma cathodes.
All outputs consists of switchable

and programmable current sinks
which provide constant current to
the tube cathodes, even with high
tube anode supply tolerance.
Output currents may be varied over
the 0.2 to 1.2ma range for multi-
plex operation. The output cur-
rent is adjusted by connecting
an external program resistor (Rp)
from Vcc to the program input in
accordance with the programming
curve.
Page 1-12
KING
UDN-6184
120-0095-00
I IB
2 -
17
3 16
4 15
5 14
6 13
7 -
12
8 --
II
9 GND BB 10
GAS DISPLAYDIGIT DRIVER
The UDN-6184 is designed for interfacing between MOS, or other low-voltage

circuitry, and the anodes of gas discharge displays driven in a multiplexed
fashion. The UDN-6184 contains eight drivers. Each driver contains appropriate
level shifting, signal amplification, output off state voltage bias, and 70ma
output current sourcing for the sequential addressing of display anodes. The
inputs include pull-down resistors for direct connection to open drain PMOSlogic.
Page 1-13
KING
74LS26
120-0117-00
VCC 48 4A 4Y 3B 3A 3Y
\4 13 12 II 10 9 8
IA 18 \Y 2A 28 2Y GND
POSITIVE LOGIC Y=ÃB
QUADRUPLE-INPUT HIGH VOLTAGE INTERFACE POSITIVE-NAND GATES
Page 1-14
93L24PC TOP VIEW
120-0122-00
u
AO A A2 A3 A4 60 SI 62 63 64 80 A=B
LOADING
I -<
E 9324
4 Bi Ao 13 HIGH LOW
A>B A<B A=B
LO U.L. O,5 U.L.
5 82 A¡ 12
1.0 U.L. 0.5 U.L.
I.0 U.L. 0.5 U. L .
15 2 l4
83 A2 9 U.L. 2.25 U.L.
VCC PlN 16
= 9 U.L. 2.25 U.L.
84 A3 10 U.L. 2.5U.L.
GND= PIN S
GND A4
PIN NAMES
Ë ENABLE (ACTIVE LOW) INPUT
Ag A A2,A3,A4 WORD A PARALLEL INPUTS.
B B B2 WORD B PARALLEL INPUTS
3, 4
A B A GREATER THAN B OUTPUT
A=B A EQUALSTO B OUTPUT
I UNIT LOAD(40µA HIGH/ I.6 mA LOW
TRUTH TABLE
E A B AB A=8

H X X L L L
L WORDA WORDB=
L L H
L WORDA>WORDB L H L
L WORDA<WORDB H L L
L = LOW VOLTAGE LEVEL

H =
HIGH VOLTAGE LEVEL
X =
EITHER HIGH OR LOW VOLTAGE LEVEL
Paae 1-15
KING
74800
120-0131-00
lA IB IY 2A 2B 2Y GND
POSITIVE LOGIC Y= M
2-INPUT
QUADRUPLE
Page 1-16
PBD48
120-2026-00 - ---
e
i TO VCC 40
2 Ti 39 >PORTAhl
XTALi XTAL __
3 XTAL 2 P27 39
4 RËšËT P26 37
IS¯ PORT#2
5 P25 36 RESET
6 MT P24 35
7 EA PI7 54 SINGLE----a
STEP
RD PI6 ---**READ
8 35
9 PiËN PIB 32 EXTERNAL ---a.
MEM
10 y¶¶ PI4 31
II 30 --->WRITE
ALE Pl3
12 DBO PI2 29 TEST...
I:5 DB¡ PII 28 ----a
PROGRAM
I.4 DB2 STORE
~¯¯
PIO 27
ENABLE
15 DB3 YDD 26 INTERRUPT ----a
16 DB4 PROG 25
ADDRESS
---a
LATCH
ly DBS P23 24 BUS< JE ) ENABLE
18 DB6 P22 gg
19 DB7 P21 22 PORT

-¯**EXPANDER
20 YSS P20 21 STROBE
8-BIT MICROCOMPUTER
SINGLE COMPONENT
DESCRIPTION
The Intel 8048/8035 is a totally self-sufficient 8-bit parallel computer fabricated

on a single silicon ship using Intel's N-channel silicon gate MOS process.
The 8048 contains a 1K x 8 program memory, a 64 x 8 RAMdata memory, 27I/0 lines,

and an 8-bit timer/counter in addition to onboard oscillator and clock circuits.
The 8048 has a factory-programmed mask ROMprogram memory for low cost and high
volume production.
This microprocessor is designed to be an efficient controller as well as an arith-

metic processor. The 8048 has extensive bit handling capability as well as
facilities for both binary and BCD arithmetic. Efficient use of program memory
results from an instruction set consisting mostly of single byte instructions
and no instructions over 2 bytes in length.
Page 1-17
KING
PIN DESCRIPTION
P8048
120-2026-00
Designation Pin * Function Dedgnation Pin # Function
VSS 20 Circuit GND potential IÕ 8 Output strobe activated during a
VDD 26 Programming +25V
power supply; BUS read. Can be used to enable
during program, +5V duringoper. data onto the BUS from an external
ation for both ROMand PROM. device.
Low power standby pin in 8048 Used as a Read Strobe to External
ROM version' Data Memory. (Active low)
VCC 40 Main power supply; +5V during R 4 Input which is used to initialize the
operation and programming processor. Also used during PROM
PROG 25 Program pulse (¥25V) input pin programming verification, and
during 8748 programming. power down. (Active low)
Output strobe for 8243 1/O T 10 Output strobe during a BUS write.
expander. (Active low)(Non TTL Vis)
P10 PT7 27-34 8-bit quasi-bidirectional port. Used as write strobe to External
Port 1 Data Memory.
P20-P27 21-24 &bit quasi-bidirectional port.
Port 2 35-38 ALE 11 Address Latch Enable. This signal
P20-P23 contain the four high occurs once during each cycle and
order program counter bits during is useful asa clock output,
an external program memory fetch
and serve as a 4-bit I/O expander The negative edge of ALE strobes
bus for 8243 address into external data and pro-
12-19
gram memory.
DO-D7 True bidirectional port which an -
BUS be written or read synchronously PSEN 9 Program Store Enable. This output
using the RD, WR strobes. The occurs only during a fetch to exter-
port can also be statically latched. nal program memory. (Active low)
Contains the 8 low order program ŠS 5 Single step input can be used in con-
counter bits during an external junction with ALE to "single step"
program memory fetch, and receives the processor through each in-
the addressed instruction under the struction. (Active low)
control of PSEN. Also contains the EA 7 External Access input which forces
address and data during an external all program memory fetches to re-
RAM data store instruction, under ference external memory. Useful
control of ALE, RD. and for emulation and debug, and
TO 1 Input pin testable using the con-
essential for testing and program
ditional transfer instructions verification. (Active high)
JTO
and JNTO. TO can be designated as XTALI 2 One side of crystal input for inter-
a clock output using ENTO CLK nat oscillator. Also input for exter-
instruction. TO is also used during nal source. (Not TTL Compatible)
programming XTAL2 2 Other side of crystal input.
T1 39 Input pin testable using the JT1,
and JNT1 instructions. Can be des-
ignated the timer/counter input using
the STRT CNT instruction.
6 Interrupt input. Initiates an inter-
rupt if interrupt is enabled. Inter-
rupt is disabled after a reset. Also
testable.with conditional jump
instruction. (Active low)
CLOCK IO24WORDS 64WORDS

PROGRAM DATA
MENORY MEMORY
B-BIT /
CPU p
SBIT
TIMER/ 27
EVENT COUNTER 1/O LINES
Page 1-18
ER1400/1400T
120-2028-00
14 BITS DATA REGISTER
DT
BU
N MEMORY DATA FLOW
S ARRAY
,7 READ MODE -----C¡
100X14
,/ WRITE DECODE C2
,- ERACE LOGIC
A ( -----
C3
S
S DECODE
CLOCK ,/ CLOCK
GEN N
MSB UNITS ADDRESS LSB /
10 BITS
BOTTOM VIEW U
VSS(GND) • Vm (NC)
O
Og 4 O VGG(-35v) NC
02 6(3
O' s 'O 1. DATA \/0 5. CLOCK NC DATA I/O

M LC
NC NC
---
SS
4. VGG 8.C3
NC NC
8 LEAD TT)-99
CLOCK C3
ci [ i] ce
1400 Bit Electrically Alterable Read Only Memory TOP VIEVV
DESCRIPTION
DUAL INLINE
The ER1400 is a serial input/output 1400 bit electrically erasable and reprogrammable
ROM, organized as 100 words of 14 bits each. Data and address are communicated
in serial form via a one-pin bidirectional buss.
Addressing is by two consecutive one-of-ten codes.
Mode selection is by a 3 bit code applied to C1, C2 and C3.

Data is stored by internal negative writing pulses that selectively tunnel charge
into the oxide-nitride interface of the gate insulator of the 1400 MNOSmemory
transistors. When the writing voltage is removed the charge trapped at the
interface is manifested as a negative shift in the threshold voltage of the
selected memory transistors.
Page 1-19
KING
P8243
120-2030-00 P 50 I 24 VCC
P40 2 23 P51
P4 I 3 22 P52
P42 4 21 P53
P4 3 5 20 P60
6 19 P61
PROG 7 18 P62
P23 8 17 P63
P22 9 16 P73
P2 I 10 15 P72
P20 II 14 P71
GND 12 13 P70
ADDRESS LATCH 4 PORT4

DECODER
UN
INSTRUC
DECODER LATCH PORTS
4
PORT 2 U
U
TEMP
J LATC 4 PORT 6
ALNOD/OCR
PROG CONTROL
LATCH 4 PORT 7
EUT
CR
Page 1-20
P8243
120-2030-00
8243
PIN DESCRIPTION A high to low transition of the PROG line indicates that
address is present while a low to high transition indicates
Symbol Pin No. Function
the presence of data. Additional 8243s may be added to
PROG 7 Clock Input. A high to low the 4-bit bus and chip selected using additional output
transistion on PROG signifies lines from the 8048/8748/8035.
that address and control are
available on P20-P23, and a low Power On initialization
to high transition signifies that initial application of power to the device forces
data is available on P20-23 input/output ports 4, 5. 6. and 7 to the tri-state and port 2 to
CS 6 Chip Select Input. Ahighon CS the input mode. The PROG pin may be either high or low
inhibits any changeof output or when power is applied. The first high to low transition of
internalstatus. PROGcausesdevicetoexitpoweronmode.Thepoweron
P20-P23 11-8 sequence is initiated if Vcc drops below TV.
Four (4) bit bi-directional port
contains the address and con-
P21 P20 Address Code P23 P22 Instruction Code
trol bits on a high to low
transition of PROG. During a O 0 Port 4 0 0 Read
low to high transition contains 0 1 Port 5 0 1 Write
the data for a selected output 1 0 Port 6 1 0 ORLD
port if a write operation, or the 1 1 Port 7 1 1 ANLD
data from a selected port before
the low to high transition if a Write Modes
read operation.
The device has three write modes. MOVD Pi, A directly
GND 12 0 voit supply- writes new data into the selected port and old data is lost.
P40-P43 2-5 Four (4) bit bi-directional I/O ORLD Pi,A takes new dafa, OR's it with the old data and
P50-P53 1,23-21 ports. May be programmed then writes it to the port. ANLD Pi,A takes new datà AND's
P60-P63 20-17 to be input (during read), it with the old data and thèn writes it to the port. Operation
P70-P73 13-16 low impedance latched output code and port address are latched from the input port 2on
(after write) or a tri-state (after the high to low transition of the PROG pin. On the lowto
read). Data on pins P20-23 may high transition of PROG data on port 2 is transferred to the
be directly written, ANDed or logic block of the specified output port,
ORed with previous data After the logic manipulation is performed. the data is
VCC 24 +5 volt supply. latched and outputed. The old data remains latched until
new valid outputs are entered,
General Operation Read Mode
The 8243 contains four I/O ports which serve as an
4-bit The device has one read mode. The operation code and
port address are latched from the input port 2 on the high
extension of the on-chip I/O and are addressed as ports4-
to low transition of the PROG pin. As soon as the read
7. The followmg operations may be performed on these
ports. operation and port address are decoded, the appropriate
outputs are tri-stated, and the input buffers switched on.
• Transfer Accumulator to Port The read operation is terminated by a low, to high
• Transfer Port to Accumulator transition of the PROG pin. The port (4. 5, 6or 7) that was
• AND Accumulator to Port selected is switched to the tri.stated mode while port 2 is
• OR Accumulator to Port returned to the input mode,
Allcommunication between the 8048and theS243occurs Normally, a port will be in artoutput (write mode) or input
over Port 2 (P20-P23) with timing provided by an output (read mode). If modes are changed during operation, the
pulse on the PROG pin of the processor. Each transfer first read following a write should be ignored; all following
consists of two 4-bit nibbles: reads are valid. This is to allow the external drtver on the
The first containing the "op code" and port address and port to settle after the first read instructron removes the
the second containing the actual 4-bits of data. Iow impedance drive from the 8243 output.
Page 1-21
MC1350P
120-3020-00
MONOLITHICIF AMPLIFIER
...an integrated circuit featuring wide range AGC for use as an IF amplifier in radio and TV over the
temperature range 0 to +75°C.
Power Gain -
50dB typ. at 45MHz,
-
48dB typ. at 58MHz
AGCRange -
60dB min, DC to 45MHz
Nearly constant input and output admittance over the entire AGCrange
Constant (-3.0dB) to 90MHz

Y21
Low Reverse Transfer Admittance -
1.0umho typ.
12-Volt Operation, Single-Polarity Power Supply
7812 OUTPUT /
COMMON 4> .
120-3026-06
INPUT
12V
THREE-TERMINAL
POSITIVE VOLTAGE REGULATORS
This series of three-terminal positive voltage regulators are monolithic

integrated circuits designed as fixed-voltage regulators for a wide variety
of applications including local, on-card regulation. Available in seven
fixed output voltage options from 5.0 to 24 volts, these regulators employ
internal current limiting, thermal shutdown, and safe area compensation -
making them essentially blow-out proof. With adequate heatsinking they can
deliver output currents in excess of 1.0 ampere. The last two digits of
the part number indicate nominal output voltage.
Page 1-22
NE555V
120-3040-00 worvsm
CONTROL
DIS THRE&VOLT
VCCCHARGEHOLD AGE
GNO TRIG OUT AESET

GER PUT
functional block diagram
CONTROL
vcc VOLTAGE RESET
THRESHOLD
COMP OUTPUT
TIMING CIRCUIT
This monolithic timing circuit is a high stable controller capable of producing

accurate time delays, or oscillation. Additional terminals are provided for
triggering or resetting if desired. In the time delay mode of operation, the time
is precisely controlled by one external resistor and capacitor. For a stable
operation as an oscillator, the free running frequency and the duty cycle are
both accurately controlled with two external resistors and one capacitor. The
circuit may be triggered and reset on falling waveforms, and the output structure
can source or sink up to 200ma or drive MTTL circuits.
Page 1-23
LM339N
120-3048-00
Dualln Lineand FlatPackage
OUTPUT 2 OUTPUT 1 Y INPUT 1 INPUT1• INPUT 2 INPUT 2•
TOPviEW
The LM339 consists of four independent

voltage comparators which were designed
specifically to operate from a single power
supply over a wide range of voltages.
Operation from split power supplies is also
possible and the low power supply current
drain is independent of the magnitude of
the power supply voltage. These comparators
also have a unique characteristic in that
the input common-mode voltage range includes
ground, even though operated from a single
power supply voltage.
Page 1-24
LM324
120-3052-00
DUAL-IN-LINE AND FLAT PACKAGE

OUTPUT INPUT INPUT GND INPUT INPUTOUTPUT
414 4 4 + -
3+ 39- 3
+ +
12 3 567
OUTPUT INPUT INPUT V INPUT INPUTOUTPUT

2¯
V¯ \* 2*
I 2
TOP VIEW
GENERAL DESCRIPTION
This series consists of four independent, high gain, internally frequency

compensated operational .amplifiers which were designed specifically to
operate from a single power supply over a wide range of voltages. Operation
from split power supplies is also possible and the low power supply current
drain is independent of the magnitude of the power supply voltage.
Application areas include transducer amplifiers, DC gain blocks and all the
conventional op amp circuits which now can be more easily implemented in
single power systems. For example, this series can be directly operated
off of the standard +5VDC power supply voltage which is used in digital systems
and will easily provide the required interface electronics without requiring
the additional +15VDC power supplies.
Page 1-25
LM358
DUAL-IN-LINE R4CKAGE
120-3053-00
OUTPUT A -
8 y,
7
2 OUTPUT 8
INVERTING INPUT A -
A
NONINVERTING 3 6
INPUT A INVERTING
INPUT B
4 5
GND NON INVERTING
INPUTB
The LM358Nconsists of two independent, high

gain, internally frequency compensated opera-
tional amplifiers which were designed specif-
ically to operate from a single power supply
over a wide range of voltages. Operation from
split power supplies is also possible and the
low power supply current drain is independent
of the magnitude of the power supply voltage.
Page 1-26
KING
LM380N
120 -3080 -00
BYPASS I --- ----
VS
NON-INVERTING INPUT 2-- ---I3NC
BYPASS VS
2 GND ( 4 ----- ---
II GND
---
14
LM38
6 5
-
3,4,5
--- ~~
10
INVERTING INPUT 6 ---- ---
9
GNDGND
GND 7 ¯
8 V OUT
HEATSINKPINS
TOP VIEW
AUDIO, RADIOAND TV CIRCUITS
GENERAL DESCRIPTION
The LM380 is a power audio amplifier for consumer application. In order to hold system
cost to a minimum, gain is internally fixed at 34dB. A unique input stage allows inputs
to be ground referenced. The output is automatically self entering to one half the
supply voltage.
The output is short circuit proof with internal thermal limiting. The package outline
is standard dual-in-line. A copper lead frame is used with the center three pins on
either side comprising a heat sink. This makes the device easy to use in standard PC
layout.
Page 1-27
SUBSTRATE
CA3146AE
\4 |3 I2 Il IO 9 8
120-3087-03
I 2 3 4 5 6 7
TRANSISTOR ARRAY
GENERAL DESCRIPTION
This device consists of five high voltage general purpose silicon NPN transistors
on a common monolithic substrate. Two of the transistors are internally connected
to form a differentia11y-connected pair. The transistors are well suited to a
wide variety of applications in low power systems in the DC through VHF range.
They may be used as discrete transistors in conventional circuits; however, in
addition, they provide the very significant inherent integrated circuit advantages
of close electrical and thermal matching.
OUTPUT
340LAZ-5.0
INPUT
2 3 I
120-3094-32
SV
3-lERMINAL POSTIVE REGULATORS GND
BOTTOM VIEW
GENERAL DESCRIPTION
This series of three terminal positive regulators is available with several

fixed output voltages making them useful in a wide range of applications.
The regulators have +3% VOUI specification, 0.04%/V line regulation, and
0.01%/ma load regulation. When used as a zener diode/resistor combination
replacement, the regulator usually results in an effective output impedance
improvement of two orders of magnitude, and lower quiescent curreht.
These regulators can provide local on card regulation, eliminating the
distribution problems associated with single point regulation.
With adequate heat sinking the regulator can deliver 100ma output current.
Current limiting is included to limit the peak output current to a safe value.
Safe area protection for the output transistor is provided to limit internal
power dissipation. If internal power dissipation becomes too high for the
heat sinking provided, the thermal shutdown circuit takes over, preventing the
IC from overheating.
Page 1-28
KING
SP8640B
CLOCK I/p CLOCK 14
120-4006-01
PT NC
NC
NC NC
CC EE
NC SP8646/7 TTLo/p
NC NC
o/p (Q4)
NOTE:
UNUSED PINS (EXCEPT 8 AND9) MAY BE
CONNECTEDTO VEE. THIS WILL REDUCE
CLOCK BREAKTHROUGHON THE OUTPUTS,
PINS 8 AND 9 SHOULDBE LEFT OPEN-CIRCUIT
WHEN NOT IN USE.
CLOCK TTL
PULSE I 2 3 4 o/p
I L H H H H
DIV 2LLHHH
PE PE
I 2 RAT10 3 L L L H H
---- ----- -----
4 H L L H H
LLII 5HHLHH
HLIO 6LHHLL
LHIO 7LLHLL
HHIO 8LLLLL
9 H L L L L
TRUTH TABLE FOR 10 H H L L L
CONTROL PUTS -H H _ _
_H _
H _ _
_H
EXTRA STATE
TRUTH TABLE FOR CONTROL INPUTS COUNT SEQUENCE
Page 1-29
KING
NC 6Y 6A NC 5Y 5A 4V 4A
SCL4049
16 15 14 !3 12 Il 10 9
120-6025-01
SCL4049UB SCL40500B
SCL4050ABC
\ 2345678
120-6026-01
V \Y lA 2Y 2A 3Y 3A VSS
PIN CONNECTIONS
SCL4049 SCL4050
IA
-3
2-lY lA-3 2-¡y
2A -
5 4 -2Y 2A - 5- 4- 2Y
3A -7 6-3YSA-7 6-3Y
4A-9 10-4Y4A-9 lo-4Y
5A --il I2-5Y5A-li 12-5Y
6A -14 15-6Y6A-l4 15-6Y

N.C.-13,16
Y=Ä VCC¯ l
Y=A
V -8
SS
LOGIC D1AGRAM
CMOS HEX BUFFERS/CONVERTERS
The SCL4049 is an inverting hex buffer and the SCL4050 is

a non-inverting hex buffer. Both feature logic-level
conversion using only one supply voltage (VCC). The
input-signal high level (v H) can exceed the VCC SUPPly
voltage when these devices are used for logic-level
conversions. These devices are intended for use as
COS/MOS to DTL/TTL converters and can drive directly two
DTL/TTL loads. (VCC SV, VOL 0.4V, and DN
=
3ma).
Page 1-30
SCL4017AB
120-6027-01
BLOCK DIAGRAM
CLOCK 14 o- o ---o 3
VDD R CL CE OUT "9" "4" "8" 2 ...-o

4
16 15 14 13 12 11 10 9 4 10
CLOCK
SCL4017AB ENABLE
6
7 --o
IS
I 2 3 4 5 6 7 8
8 -----o 9
I O 2 6 3 VSS RESET 15 e- OUT --o

12
VDD= PIN16
VSS = PlN 8
CMOS DECADECOUNTER/DIVIDER
DESCRIPTION
The SCL4017AB consists of a 5-stage Johnson Decade Counter and an Output Decoder.
either a positive-going or negative-going transition, respectively. A high Reset
signal clears the counter to its zero count.
Use of the Johnson decade counter configuration permits high-speed operation,

2-input decode gating, and spike-free decoded outputs. Anti-lock gating is
provided, thus assuring proper counting sequence. The 10 decoded outputs are
normally low and go high only at their respective decoded time slot. Each
decoded output remains high for one full clock cycle. A Carry-out (COUT) signal
completes one cycle every 10 clock input cycles and is used to directly clock
the succeeding counter in multi-stage applications.
This part can be used in frequency division circuits as well as decade counter or
decimal decode display applications.
Page 1-31
SCL4046
12D-6038-01
ZENER DEhãOD OUT
VDD SIG PCII VCO

IN OUT R2 RI IN
16 15 Id4 13 12 II 10 9
SC L4046B
\ 2 3 4 5 6 7 8
\ \ \ \ \
PC I VCO INH CI CI Vgs
OUT OUT (A) (B)
PHASE COMP
PULSES IN
CMOSPHASE-LOCKED LOOPS
DESCRIPTION
The SCL4046B is a phase-locked loop containing two phase comparators, a voltage-

controlled oscillator (VCO), source follower, and zener diode. The comparators
have two common inputs. The signal input can be used directly coupled to large
voltage signals, or indirectly coupled (with a series capacitor) to small voltage
signals. The self-bias circuit adjusts small voltage signals in the linear
region of the amplifier. Phase comparator I (an exclusive-OR gate) provides a
digital error signal PCIout, and maintains 90° phase shift at the center frequency
between signal and comparator inputs (both at 50% duty cycle). Phase comparator
. II (with leading edge sensing logic) provides digital error signals PCIIout and
phase pulses, and maintains a Oo phase shift between input signals (duty cycle is
immaterial). The linear VCO produces an output signal VC0out whose frequency is
determined by the voltage of input VC0in and the capacitor and resistors connected
to pins C14, C1g, R1, and R2. The source follower output, Demod Out, with an
external resistor is used where the VC0in signal is needed but no loading can be
tolerated. The inhibit input Inh, when high, disables the VCOand source follower
to minimize standby power consumption. The zener diode can be used to assist in
power supply regulation.
Page 1-32
POSITIVE LOGIC
SCL4022AC+ CLOCK
CLOCK RESET GUTPUT= n
ENABLE
120 6045 01
0 X O n
X 1 O n
O O n+1
X O n
1 0 n+1
X O n
X X 1 "O"
'
COUT "4" "7 N.C.
DD R C C
X DON'T CARE If n<4 CARRYs I, OTMERWISE =0
SCL4022AS
BLOCK DIAGRAM
It N2"
..'. M
"5" "6" N.C. "3" VSS
CLOCK 14 > 0 ---o
2
ADD SUFFIX FOR PACKAGE : 2

C 16 P1N CERDIP CLOCK 3 ---0
7
ENABLEl3" 4 li
O 16 PIN CERAMIC -.....o
E 16 PIN EPOXY 5 --o

4
F 16 PIN FLAT
7 --o
10
H CHIP RESET 15 C OUT ---o 12
VDO = PIN 16
CT"OSOctal Counter/Divider
VSS = PIN 8
DESCRIPTION
This device consists of a 4-stage Johnson Divide-by-8 Counter and an Output Decoder.
either a positive-going or negative-going transition, respectively. A high
Reset signal clears the counter to its zero count.
Use of the Johnson divide-by-eight counter configuration permits high-speed

operation, 2-input decode gating, and spike-free decoded outputs. Anti-lock
gating is provided, thus assuring proper counting sequence. The 8 decoded outputs
are normally low and go high only at their respective decoded time slot. Each
decoded output high for one full clock cycle. A Carry-out (C signal
direct10Uilock )
remains
completes one cycle every 8 clock input cycles and is used to the
succeeding counter in multi-stage applications.
This part can be used in frequency division circuits as well as octal counter or
octal decode display applications.
Page 1-33
KlNG
SCL4060ABC
120-6055-01
DD 010
!!!!!!i
08 09 R ø 0 if
18 15 14 13 12 11 10 9
SCL4060 AB
1 2 345 67 8
11illll!
Q12 Qi3 014 Q6 05 Q7 04 VSS
CONNECTION DlAGRAM
CLOCK RESET OUTPUT STATE

O NO CHANGE
O ADVANCETO NEXT
STATE
X i ALL OUTPUTS ARELOW
X = DON'T CARE
TRUTH TABLE
CMOS 14-STAGE BINARYCOUNTER

ANDOSCILLATOR
DESCRIPTION
This device consists of an oscillator section and 14 ripple-carry binary

counter stages. The oscillator configuration allows design of either
R-C or crystal oscillator circuits. A Reset input is provided which
resets the counter to the all O's state. A high level on the Reset line
accomplishes the reset function. The state of the counter is advanced
one step in binary order on the negative transition of the Clock input
0. All inputs and outputs are fully buffered. Outputs are available from
stages 4 through 10 and 12 through 14.
Page 1-34
KING
SER1ÀL
OOUTRUTS
DATA 2 8-STAGE I
S
SHIFT
CLOCK 3 REGISTER S
CD4094 OS
120-6056-00
SCL4094 g_g y
120-6056-01 STROBE I STORAGE
REGISTER
OUTPUT
ENABLE 15 3-STATE Y DO = f6
OUTPUTS Y SS =
8
PARALLEL OUTPUTS QI-Q8
(TERMINALS 4,5,6,7,14,I3,I2,II RESPECTlVELY)
FUNCTIONALDIAGRAM
TRUTH TABLE
PARALLEL SERIAL
OUTPUTS OUTPUTS
CL OUTPUT STROBE DATA
ENABLE QI QN QSI O'S
O X X OC OC Q7 NC
o x x oc oC NC Q7
I O X NC NC Q7 NC
I I O O ON-I Q7 NC
I I \ \ ON-I Q7 NC
I I I NC NC NC Q7
A= LEVEL CHANGE LOGIC I HIGH
¯
X DON'T CARE 0- LOW

LOGIC
NC NO CHARGE
=
OC OPEN C1RCUIT
=
AT THE POSITIVE CLOCK EDGE INFORMATION IN THE 7 th SHIFT

REGISTER STAGE IS TRANSFERRED TOTHE 8 th REGISTER STAGE
AND THE QS OUTPUT.
8 STAGESHIFT-AND-STOREBUS REGISTER
Page 1-35
El
KING.
KN
NAVIGATION
RECEIV
INSTALLATION
MANU
006-0174-
RtV 0, APRIL, 19
-
KING
KN 53
NAVIGATION RECEIVER
TABLE
OFCONTENTS
I
SECTION
INFORMATION
GENERAL
Paragraph Page
1.1 Introduction 1-1
1.2 Equipment Description 1-1
1.3 Technical Characteristics 1-1

1.3.1 KN 53 General Information 1-1
1.3.2 VOR/LOC Characteristics 1-2
1.3.3 Glideslope Characteristics 1-2
1.4 Units and Accessories 1-3

1.4.1 Units and Accessories Supplied 1-3
1.4.2 Optional Accessories 1-3
1.5 Accessories Required but not Supplied 1-4
1.6 License Requirements 1-4
1.7 Requirements for TSO'd VOR/ILS Glideslope Systems 1-4

1.7.1 Glideslope Indicator Requirements 1-4
1.7.2 Localizer Converter and Indicator Requirements 1-5
l.7.3 VOR Converter and Indicator Requirements 1-5
1.7.4 King TSO'd Systems 1-6
SECTION
ll
1NSTALLATION
2.1 General Information 2-1
2.2 Unpacking and Inspecting Equipment 2-1
2.3 Equipment Installation 2-1

2.3.1 KN 53 Installation 2-1
2.3.2 Molex Connector Assembly 2-1
2.3.3 NAV and Glideslope Antenna Installation 2-2
2.4 Post Installation Adjustments 2-2
III
SECTION
OPERATION
3.1 General 3-1
3.2 Post-Installation Checkout 3-1
i
KING
KN 53
NAVIGATION RECEIVER
OFCONTENTS
TABLE
LISTOFILLUSTRATIONS
Figure Page
2-1 Molex Information (3 sheets) 2-3

2-2 030-0005-00 Connector Assembly 2-6
2-3 Antenna Connector 2-7
2-4 Outline and Mounting Drawing 2-9
2-5 KN 53 Installation Drawing 2-11
2-6 KN 53 Install Kit with Optional Diplexer Unit 2-13

2-7 KN 53 to KI 203/KI 204 Interconnect Diagram 2-15
2-8 KN 53 to KN 72/KI 206 or KNI 520 Interconnect 2-17
2-9 KN 53 to KN 72/RI 525 or KI 525A Interconnect 2-19
2-10 KN 53 to KI 208/KI 209 Interconnect 2-21
3-1 KN 53 Control Functions 3-3
ii
KING
KN 53
NAVIGATION RECEIVER
SECTION
I
INFORMATION
GENERAL
1.1 INTRODUCTION
This manual contains information relative to the physical, mechanical, and electrical
characteristics and installatio.n procedures of the King Radio Corporation Silver Crown
KN 53 Navigation Receiver.
1.2 EllUIPMENTDESCRIPTION
The King KN 53 is a TSO'd panel mounted 200 channel VHF YOR/LOC Receiver with a 40
channel Glideslope Receiver/Converter option. The NAV receiver supplies VOR/LOC
information to navigation converters and provides two out of five frequency selection
for remote mounted Distance Measuring Equipment.
1.3 CHARACTERISTICS
TECHN1CAL
Minimum performance requirements under standard conditions (ambient room temperature
and humidity):
1.3.1 KN 53 GENERAL INFORMATION
TSO CATEGORIES: NAV C40a DO-153:

LOC C36c, Class D, Cat II DO-131
GS C34c, Class D, Cat II DO-132
ENVIRONMENTAL CATEGORIES: 00-160

/AlDl/A/PS/XXXXXXABABA
PHYSICAL DIMENSIONS: Width: 6.31 inches (16.0 cm)

(including mounting rack Height: 1.30 inches (3.30 cm)
and connectors) Depth: 9.75 inches (24.77 cm)
WEIGHT:
With GS 2.6 lbs (1.18 Kg)
Without GS 2.3 lbs (1.04 Kg)
With GS, Rack and Conn. 3.0 lbs (1.36 Kg)
Without GS, with Rack and Conn. 2.7 lbs (1.23 Kg)
POWER REQUIREMENTS: 11 to 33VDC input

With GS @ 13.75VDC .75 AMP
With GS @ 27.5VDC .25 AMP
Without GS @ 13.75VDC .60 AMP
Without GS @ 27.5VDC .20 AMP
DME CHANNELING: 5 wire 2 x 5 code MHz lines

5 wire 2 x 5 code KHz lines
1 wire 50KHz line
1 DME common line
ILS ENABLE OUTPUT: Ground on ILS channels, open otherwise
Page 1-1
KING
KN 53
NAVIGATION RECEIVER
1.3.2 VOR/LOC CHARACTERISTICS (KPN 0ßß-1067-00/01)
FREQUENCY DISPLAY: Gas discharge display of one active and

one stored frequency. The stored
frequency is updated by the incre-
ment/decrement switch. The transfer
button trades the active frequency with
the stored frequency.
FREQUENCY MEMORY: Frequency data stored with no standby

power required.
FREQUENCY STABILITY: +0.0015%
SENSITIVITY: 2.0uv (hard) max. will provide a

half-flag navigation indication.
Typical 1.0uv (hard).
SELECTIVITY: Typical 6dB at +17KHz, 80dB at +42KHz
SPURIOUS RESPONSES: Down at least 60dB
IDENT FILTER: 15dB minimum tone rejection
AGC CHARACTERISTICS: From 5uv to 20,000uv (hard) audio

output will not vary more than 3dB.
AGC active from half flag to +6dBm
(hard).
+1.5°
NAV RECEIVER ACCURACY: maximum error/95% probability
NAV OUTPUT: Adjustable 0.35VRMS LOC, 0.5VRMS VOR

output into 20,000 ohms or greater
AUDIO OUTPUT: 50mw @ 500 ohms
NUMBER OF CHANNELS: 200 (50KHz spacing)
FREQUENCY RANGE: 108.00MHz to 117.95MHz
1.3.3 GLIDESLOPE CHARACTERISTICS (KPN 066-1067-00 only)
NUMBER OF CHANNELS: 40 (150KHz spacing)
FREQUENCY RANGE: 329.15MHz to 335.00MHz
SELECTIVITY: 6dB max at +21KHz, 50da min. at +129KHz
SENSITIVITY: Typically 12uv (hard) for half flag

20uv (hard) maximum
INDICATOR OUTPUT: No load resistors or wiring changes are

necessary for any combination of
deviation or alarm flag loads.
Deviation: Three 1000 ohm loads max
Flag: Three 1000 ohm loads max
COURSE DEVIATION RESPONSE: 0.6 seconds maximan
Page 1-2
KING
KN 53
NAVIGATION RECEIVER
CENTERING ACCURACY: Less than +10ua under all service

conditions
DEFLECTION CHARACTERISTICS: A difference in depth of modulation of

0.09/ddm, or 2dB tone ratio shall
produce a deflection of +78ua (+30a
typical).
1.4 UNITSANDACCESSORIES
l.4.1 UNITS AND ACCESSORIES SUPPLIED
A. King KN 53 with Glideslope (KPN 066-1067-00)
B. King KN 53 without Glideslope (KPN 066-1067-01)
C. King KN 53 Installation Kit (KPN 050-1712-00) consists of:
KPN DESCRIPTION Q_TY
030-0101-02 Ant. Conn. 2
(1 spare when used with 066-1067-01)
030-1094-53 Card Edge Connector w/Polarizer 1
030-1107-30 ,
Connector Pins 30
(5 spares when used with 066-1067-00)
(7 spares when used with 06ß-1067-01)
089-2353-01 Clip Nut, 6-32 4
089-5903-07 Scc PHP 4-40 x 7/16 2
089-6012-08 Scr FHP 6-32 x 1/2 4
089-8003-34 Washer, Split #4 2

089-8252-30 Washer, Shim 4
090-0019-07 Retaining Ring 2
1.4.2 OPTIONAL ACCESSORIES
A. KA 139 Diplexer (071-1185-00)
NOTE
1. This diplexer may be used with 066-1067-00. This permits the glideslope
receiver to use the aircraft's navigation antenna.
2. The two antenna connectors, 030-0101-02, furnished in the installation

kit, 050-1712-00, will be spaces when this diplexer is used.
Page 1-3
KING
KN 53
NAVIGATION RECEIVER
RI°QUIRED
1.5 ACCESSORIES BUT NOTSUPPLIED
A. Navigation Antenna and Cables
B. Glideslope Antenna and Cables

KA 22 (KPN 071-1008-00) or equivalent
C. 300 to 1000 ohm Headphones
D. VOR/LOC Converter and Indicator, Glideslope Indicator.

Various King Options include:
1. KN 53 (066-1067-01), KI 203 VOR/LOC Converter with VOR/LOC Indicator
3. KN 53 (066-1067-00), KN 72 VOR/LOC Converter, KI 206 VOR/LOC/GS

Indicator
4. KN 53 (066-1067-00), KN 72 VOR/LOC Converter, KI 525A Pictorial

Navigation Indicator
6. KN 53 (066-1067-01), KI 208 VOR/LOC Convertet and Indicator
1.8 LICENSEREQUIREMENTS
No special federal communications license is required to operate the KN 53.
1.7 FOR TSO'O YOR/\LS GLIDESLOPE

REQUIREMENTS SYSTEMS
The additional units used in conjunction with the KN 53 must meet the specifications
listed below to comprise a completely TSO'd navigation system.
1.7.1 GLIDESLOPE INDICATOR REQUIREMENTS
A. The indicator shall meet all applicable requirements of TSO C34c.
B. Centering curent to be O ± 6ua with a 95% probability under all

environmental conditions listed in RTCA Paper DO-132, Minimum Performance
Standards--Airborne ILS Glideslope Receiving Equipment, Paragraph 2.1
sub-paragraph b, Centering Accuracy.
C. The course deviation pointer shall visibly deflect at least +5/8 inch along
its scale when the input current is changed from zero to +150ua.
D. Deflection linearity over the deflection range from zero to 150ua shall be
within 10% of being proportional to the input current. Additionally, as the
current is increased beyond that producing full scale deflection to a value
of +685.7ua, the indicator deflection shall not decrease.
E. When the input current is abruptly changed from any value from zero to
+l50ua, the pointer shall reach 67% of its ultimate deflection within 2
seconds and pointer overshoot shall not exceed 5%.
F. The input impedance shall be 1K ohms +5% for both the deviation indicator
and warning signal.
G. A warning signal input current of 150ua or .less shall produce a fully

visible warning flag. A warning signal input current of 260ua or greater
shall produce a fully concealed warning flag.
Page 1-4
KING
KN 53
NAVIGATION RECEIVER
l.7.2 LOCALIZER CONVERTER AND INDICATOR REQUIREMENTS
A. The converter and indicator shall meet all applicable requirements of C36c.
B. The localizer centering current to be O ± 6ua with a 95% probability under

all environmental conditions listed in RTCA Paper DO-131, Minimum
Performance Standards--Airborne ILS Localizer Receiving Equipment, Paragraph
2.1 sub-paragraph b, Centering Accuracy.
C. The course deviation pointer shall visibly deflect at least +3/8 inch along
its scale when the input current is changed from zero to ±90ua.
D. Deflection linearity over the range from zero to ±90ua shall be within 10%
of being proportional to the difference in depth of modulation of the 90 and
150Hz signals, or the deflection shall be within 5% of standard deflection
(+90ua) of being proportional to the difference in depth of modulation,
whichever is greater. Additionally, as the difference in depth of
modulation is increased beyond that producing full scale deflection (±150ua)
to a value of 0.4ddm, the course deviation pointer deflection shall not
decrease.
E. When the input current is abruptly changed from zero to ±l50ua, the pointer
shall reach 67% of its ultimate deflection within 2 seconds and pointer
overshoot shall not exceed 5%.
F. The input impedance of the indicator for both the deviation indicator and
warning signal shall be 1K + 5%.
G. A warning signal input current of 125ua or less shall produce a fully

1.7.3 VOR CONVERTER AND INDICATOR REQUIREMENTS
A. The converter and indicator shall meet all applicable requirements of TSO
C40a.
3°
B. The bearing error shall
be less than with a 95% probability under all
environmental conditions listed in RTCA Paper DO-153, Minimum Performance
Standards--Airborne VOR Receiving Equipment, Paragaraph 2.1, sub-paragraph
2.1.2, Bearing Accuracy.
NOTE
For oldercequipment the bearing error shall be less

than 2.7 with a 95% probability under all
environmental conditions listed in RTCA Paper
DO-ll4, Minimum Performance Standards--Airborne VOR
Receiving Equipment, Paragraph 2.1, sub-paragraph
b, Bearing Accuracy.
C. The course deviation pointer shall visibly deflect at least 1/2 inch (for
DO-153) or 3/8 inch (for DO-114) along its scale when the input current is
changed from zero to +150ua.
D. Deflection Linearity
The deflection shall be proportional to the change in phase between the two
components of tge standard VOR test signal, within 20% of the deflection
produced by a 10 (+150ua) change in phase. This requirement shall be met
at all deflectigns produced when the phase difference is varied from plus
10 to minus 10 of that producing an "on course" indication. The pointer
deflection shall not decrease as the phase difference is increased from that
producing an "on ourse" indication to that producing an indication which is
equivalent to +80 from "on course".
Page 1-5
KING
KN 53
NAVIGATION RECEIVER
E. Deflection Response
When the difference in phase between the two components of an "on course"
standard VOR test signal is abruptly changed, the pointer shall reach 70% of
its ultimate position within 3 seconds and the pointer overshoot shall not
exceed 20%.
F. The input impedance of the indicator for both the bearing error and warning
signal shall be 1K + 5%.
G. A warning signal input current of 125ua or less shall produce a fully

H. The input impedance of the TO/FROM indicator shall be 200 ohms +200ua
sensitivity.
1.7.4 RING TSO'D SYSTEMS
A. The following systems when used in conjunction with the KN 53, KPN
066-1067-00 (with or without the KA 139 diplexer accessory) will meet all
SO system requirements.
1. KI 204
2. KN 72, KI 206
3. KN 72, KI 525A
4. KI 209
B. The following systems when used in conjunction with the KN 53, KPN
066-1067-01, will meet all TSO system requirements.
1. KI 203
2. KI 208
Page 1-6
KING
KN 53
NAVIGATION RECEIVER
11
SECTION
INSTALLATIION
2.1 GENERALINFORMATION
This section contains information relative to the installation and wiring of the KN 53.
A close adherence to methods and procedures discussed herein is required.
2.2 UNPACKING
ANDINSPECTlNGEûUIPMENT
Exercise extreme care
when unpacking the equipment. Make a visual inspection of the
unit for evidence damage
of incurred during shipment. If a claim for damage is to be
made, save the shipping container to substantiate the claim. The claim should be
promptly filed with the transportation company. It would be advisable to retain the
container and packaging material after all equipment has been removed in the event that
equipment storage or reshipment should become necessary.
2.3 EQUIPMENT1NSTALLATION
2.3.1 KN 53 INSTALLATION (Figures 2-1 through 2-9)
A. Plan a location on the aircraft panel that is clearly visible and within
easy access of the pilot.
B. Avoid mounting the KN 53 close to heater vents or other high heat sources.
C. Compass safe distance is 8 inches for worst case deflection of one degree.
D. Install the mounting rack in the aircraft using 6-32 x 1/2 flat head
phillips screws (KPN 089-6012-08) and 6-32 clip nuts (KPN 089-2353-01). The
screws are inserted from the inside through the holes in the sides of the
mounting rack.
E. Connect the harness wires to the connector pins and insert the connector
pins into the rear of the Molex connector. See Section 2.3.2 and Figure
2-1.
F. Mount the Molex connector in the two holes at the rear of the mounting rack.
Use two 4-40 x 7/16 pan head, phillips screws (KPN 089-5903-07) and two #4
split lock washers (KPN 089-8003-34). Orient the connector so the polarizer
key is shown in Figure 2-4.
G. Connect the antenna cables to the antenna connectors (Figure 2-2).
H. Insert the antenna connectors through the hole in the rear of the mounting
rack from the outside. Secure with a spacer (KPN 089-8252-30) and retaining
ring (KPN 090-0019-07) installed from the inside of the rack.
I. Install the KN 53 into the mounting rack and secure by turning the hold down
adjustment screw (accessible through a hole in the front panel) clockwise
with an allen hex wrench until it is locked into place (Figure 2-4).
2.3.2 MOLEX CONNECTOR ASSEMBLY (Figure 2-1)
A. Solderless Contact Terminal Assembly using Molex Crimper
Refer to instructions in Figure 2-1.
B. Solderless Contact Terminal Assembly using Pliers
1. Strip each wire 5/32" for contact terminal (KPN 030-1107-30). (The last
two digits of the contact terminal part number indicate the number of
terminals furnished).
2. Tin the exposed conductor.
Page 2-1
KING
KN 53
NAVIGATION RECEIVER
3. Using needle nose pliers, fold over each conductor tab in turn, onto the
exposed conductor. When both tabs have been folded, firmly press the
tabs against the conductor.
4. Repeat step 3 for insulator tabs.
5. Apply a small amount of solder (using minimum heat) to the conductor/tab

connection to assure a good electromechanical joint.
C. Contact Insertion into Molex Connector Housing
1. After the contact terminals have been installed on the wiring harness,
the contact terminals can be inserted into the proper location in the
connector housing (KPN 030-1094-53). The terminal cannot be inserted
upside down. Se sure to push the terminal all the way in, until a click
can be felt or heard.
2. The self-locking feature can be tested by gently pulling on the wire.
D. Extraction of Contact from Molex Connector
1. Slip the flat narrow blade of a Molex contact ejector tool, HT-1884 (KPN
005-2012-11), under the contact on the mating side of the connector. By
turning the connector upside down one can see the blade slide into the
stop.
2. When the ejector is slid into place, the locking key of the contact is
raised, allowing the contact to be removed by pulling moderately on the
lead.
3. Neither the contact or position is damaged by removing a contact;

however, the contact should be checked visually before reinstalling in
connector, to be certain that retaining tab "A" extends as shown (see
Figure 2-1) for retention in connector.
2.3.3 NAV AND GLIDESLOPE ANTENNA INSTALLATION
A. Antenna should be installed as per Advisory Circular 43.13-2 Methods and

Guidelines.
B. When applicable, the KA 139 diplexer may be used; so that the glideslope
receiver will use the NAV antenna.
2.4 POST INSTALLATION

ADJUSTMENTS
The KN 53 has been calibrated to operate with the standard King systems noted in
Section I. Adjustments are accessible through the top and bottom covers to fine tune
the navigation system if required. The physical location of the adjustments are noted
in Figure 2-4 and their electrical functions are explained in Sections IV and VI of the
KN 53 maintenance manual (KPN 006-5168-00). When adjustments are required, the
self-stick covers should be replaced.
A. Composite level set, R368, has been pre-set at the factory for standard
0.35RMS LOC, 0.50RMS VOR output.
B. Display dimmer, R546, has been preset to the King standard. R546 may be
adjusted to light balance the aircraft panel.
C. Glideslope adjustments (KPN 066-1067-00 only):
1. Glideslope course width, R425
2. Glideslope centering, R626
3. Glideslope flag, R636
Page 2-2
KING
KN 53
NAVIGATION RECEIVER
SOLDERLESSCONTACTTERMINAL
KPN 030-1107-30
TAB A
HAND EJECTOR
KPN 005-2012-11
MOLEX PN HT-1884

(Dwg. No. 696-6333-00, R-0)
(Sheet 1 of 3)
Page 2-3
KING
KN 53
NAVIGATION RECEIVER
Holding the hand crimpers as shown, release the crimper's ratchet pawl and open by squeezing tightly
on the handles, and then releasing pressure.
HAND CRIMPER
KPN 071-6041-00
VIOLEX P/N 6115
Close crimpers until ratchet begins to engage. Then insert the terminal into the jaws from the back
side. (See Figures at bottom of page) For 24 to 30AWGwire, it will be necessary to start the crimp
in jaw A and then complete it in jaw B.
JAW TERMINAL WIRE SIZE INSULATIONRANGE
A 030-1107-30 18 to 24AWG .110 to .055
B 030-1107-30 24 to 30AWG .065 to .030
,..- WIRE ST0p INSULATION TABS-
Terminal is in correct position when insulation tabs are flush with outside face of crimp jaws.

(Sheet 2 of 3)
Page 2-4
KING
KN 53
NAVIGATION RECEIVER
Once the terminal is in the correct position, close the jaws gently until the terminal is held loosely
in place. Push wire stop down so that it rests snugly behind the contact portion of the terminal.
Strip the wire insulation back 1/8 inch and insert the wire through the insulation tabs into the
conductor tabs until the insulation hits the conductor jaw face or until the conductor touches the
wire stop.
WIRE STOP
INSULATION
JA\YS
CONDUCTORJAW FACE
Squeeze the handles until the crimp jaws close and the ratchet releases.
Straighten the terminal if necessary, then release the plier grips and remove the crimped terminal.
CRIMPINGPRESSUREADJUSTMENT
If too much or too little pressure is needed to release the crimper's ratchet pawl at the end of
the crimp stroke, the ratchet can be easily adjusted. A spanner wrench provided with the tool can
be used to loosen the lock nut, and rotate the keyed stud clockwise for increased pressure and
counter-clockwise for decreased pressure. Once the desired pressure has been set, the lock nut
must be tightened again. Newer models may have a screwdriver adjustment.
KEYED STUD
SPANNER WRENCH
->
LOCK NUT
(OPPOSITE SIDE)

(Sheet 3 of 3)
Page 2-5
KING
KN 53
NAVIGATION RECEIVER
1
TRIM OUTER JACXET TO DIMENSION
SHOWN.
COMB OUT BRAID AND TR1M DIELEC-

TRIC TO DIMENSION SNOWN,
2
TAPER BRAID OVER DIELECTRIC AND
SLIP CABLENUT, WASH£R(WHEN FUR-
NISHED)ANO V-GROOVEGASKET
OVER CAOLE. POSlTION SAAID CLAMP
WITH SNOULDERTIGHT AGAINST GUT-
ER JACK€T. FDLD GRAls BACK OVER
BRAID CLAMP.
3
TRIM OFF EXCESS BRAID. POSIT-
ION WASHER AND GASKET AS SHOWN
AND soLDER PIN TO CENTER CON-
y
-
DUCTOR. PLACE INSULATOR OVER
PIN, (lF FURNISHED).
INSERT CABLE AND HARDWARE INTO

CONNECTDR HOUSING AND TIGHTEN
CABLENUT.
FIGURE 2-2 030-0005-00 CONNECTOR ASSEMBLY

(Dwg. No. 155-5267-00, R-0)
Page 2-6
KING
KN 53
NAVIGATION RECEIVER
RF AGC
RF AGC AMP AGC AMP

ATTACK Q4]O Q SII I
Q408
-
R435
Q4I2
Q409
Q 402
ANTENNA
329.15 COURSE
3 POLE 33.3KHz IF 1F WlDTH
TO ADJ
PRE- MIXER BANDPASS IF AMPS DETECTOR BUFFER
J533 335.OMHz
SELECTOR Q403 FILTER I401
' Q405 Q407 G.S.AUDIO
329.15 TO 335.0MHz R425
Q401 Q402 Q404 Q406 J401
L404,L405,L406
PIN 8
L40I L402 C4l9,C420,C42l
L403 C422,C423,C424,
329.117 TO 334.967
C425
109.706 TO Ill.656 MHz
VCO
Q413 Q4la
VCO CONTROL VOLTAGE
Q415CR401 J40I
L407 T4OI Pl N I
IIOMHz
BANDPASS
L408
C450
LOOP 455566
COUNTER
MIXER
BANDPASS BUFFER I COUNTER INJ.
Q4l6
L409 Q4\7 Q4l8 J40I
C455 CR403 PIN 4
GLIDESLOPE 97.0 TO 100.85 MHz

INJECTION
(NAV VCO) E407
FIGURE 4-7 GLIDESLOPE BLOCK DIAGRAM

(Dug. No. 696-7605-00, R-0)
MMOOO3 Page 4-15

KING
KN 53
NAVIGATION RECEIVER
P532
030-1094-53
GD
A 22AWG
C3 A+ INPUT +l40R28VDC
--
d 22 AWG IN OUT
POWER GROUND 12VREGUlATOR DME OUTPUTCODES
A GND 120-3026-06
NAVFREQUENCY MA MB MC MD ME
IN OUT MHz
4 SWITCHEDA+ 108 I O O I O
GND
B )COMPOSITE
RI 109 I O O O I
20K
!/4½' 110 O 1 0 0 1
15 )COMPOSITECOMMON
Ill I I O O O
2 )5002-AUDIO
\\2 1 O I O O
GLIDESLOPE DEVIATION 113 0 I \ 0 0
P -
RIS 114 0 1 O I O
510*
14 115 O O I \ O
KN53 GLIDESLOPE FLAG 117 O O O 1 1

R 15 -5000 a Mz
510" 023-0114-00 KA KB KC KD KE 50KHz
R
KHz
8 00 0 1 0 0 I O
)RFAGC
.05 O 1 0 0 I 1
7 )IF AGC .IO I 1 O O O O
2K
130-0202-23 .20 1 0 1 0 0 0
CRI
12PLACES ILS 0 I 1 0 0 0
12 .30
MA 007-7004-00 .40 0 1 0 1 0 O
R3 CR2 12PLACES
D .50 0 0 I 1 0 0
CMR3
R4 .60 0 0 I O 1 0
H ,vs
MC .70 0 0 O I I O
R5 CR4 I O O I O O
5 .80
R6
gy MD .90 ¡ Q O O I O
CR5
MR6 ILS CHANNEL= \
R7
F
NOTES, I.SIMUSTBECLOSED TO GROUNDTO
CKRAy VERIFY THE DMEOUTPUTCODES.
6
2. I = LED EMITTINNGLDARHTNESS
M
RC 3.THE FOLLOWING CONNECTORS
RIO CRS
IC ARE INCLUDED INTHE KN53
KCDRIO
Rll INSTALLATION KIT 050-1712-00.
L V. a.030-OfDI-02 (20TY)
KE
CRII b.030-lO94-53 (IOTY)
CRil2 c.030-IIO7-30(P1NS FOR ITEMb ABOVE)
RI3 50KHz
E
N
DME CHANNELING LINES ENABLE
P533 -
030-0101-02
PB3I030-0101-02-
TOGLIDESCOPE GENERATOR
TO VOR/LOC GENERATOR
FIGURE 5-1 KN 53 TEST FIXTURE

(Dwg. No. 002-0506-00, R-0)
Page 5-3
MMOOO3
KING
KN 53
NAVIGATION RECEIVER
DME CODE NAVCODE GLIDESLOPE DATA CATHODE DRIVER MAX CLOCK

YES CLROECSMANDSTROBE INPUTS YES
START OK 9 OK OK OK
J532 PINS F,il,5, IS22,PINS3,4,5,6,7 PINI,2,30FI6Oi PINS2,3,4,5,6,7 PIN5 ISO7
H,D,J,L,IO,M,6 I521,PINS 3,4,5,6 OF I508
1520,PINS3,4
NO NO NO NO
NO
PROCESSOR 1503,504,505 VCC (PIN24)OF CHECK lJNES FOR CHECK lJNES FOR CHECK LINES FOR
OUTPUTS YES SHOATS SHORTS SHORTS
. I/O EXPANDER AT
OK +5,PINI2AND
OK
PIN6 ATGROUND
NO NO
NO s,
TROUBLESHOOT TROUBLESHOOT
I503,I504,I505 I/O EXPANDER
SUPPLY LINES
AREPROCESSOR PROCESSOR RESET

YES
SUPPLY LJNES PIN AT+5
OKP
NO NO
TROUBLESHOOT
CHECKRESET LINE
SPROCLESSL
NRES FOR SHORT
DO USE FREQUENCY DOES INCREMENT/ DOES UNITSTORE

ANDSTANDBY USE ANDSTANDBY
' FREQUENCYEXCHANGE
YES DECREMENTSWlTCH YES
APPROPRIATLY FREQUENCIES
PLACESWHEN CHANGESTANDBY DURINGPOWEROR
TRANSFERIS FREQUENCY
PUSHED
NO NO NO
CHECK CONTINUITY CHECK FOR BAD CHECK I5I7,I5I9

OFTRANSFER SWITCH CONTACTS ISO7ABB,AND
SWITCH AND ASSOCIATED
SHORTS ON LINE CIRCUITRY
FIGURE 5-8 PROCESSOR TROUBLESHOOTINGFLOWCHART

(Dwg. No. 696-7618-00, R-0)
MMOOO3 Page 5-45

KING
KN 53
NAVIGATION RECEIVER
DISPLAY KEEP
YES
INTENSITY a ALIVC3
OK OK
NO NO
VARIABLE DUTY CATHODE TROUBLESHOOT R575, R576 TROUBLESHOOT

YES
YES PROGRAMING R577, R578 DISPLAY AND
CATHODE DRIVERS
-
CYCLE RAMP YES

OK PIN 7 CURRENT PIN \ ISOS OK CONNECTOR
I5l5 OK ISOS
NO NO
ISI6A & I5\6B &
ASSOCIATED ASSOCIATED
CIRCUITY CIRCUITY
FIGURE 5-7 DISPLAY TROUBLESHOOTINGFLOWCHART

(Sheet 2 of 2)
MMOOO3 Page 5-41

KING
KN 53
NAVIGATION RECEIVER
ARE ALL DISPLAY

YES YES
START - ANODES DATA
OK CORRECT
NO NO
MUX HIGH VOLTAGE

JOHNSON ANODE TROUBLESHOOT DISPLAY DATA CATHODE
CLOCK YES YES LEVEL YES YES YES
COUNTER DRIVERS DISPLAY & OK PINS2,3,4, ORIVERS
AT PIN4, ISO7 SHIFTER
OK I513NO OK I514 CONNECTOR 5,6,7 NO508 OK I5NOO
OK OK Q502NOQ503
NO
TROUBLESHOOT TROUBLESHOOT TROUBLESHOOT TROUBLESHOOT SEE SECTION TROUBLESHOOT

LINES TO JOHNSON HIGH VOLTAGE ANODE PROCESSOR CATHODE
PROCESSOR COUNTER LEVEL SHIFTER DRIVERS TRBLSHOOTING DRIVERS

(Dwg. No. 696-7617-00, R-0)
(Sheet 1 of 2)
MMOOO3 Page 5-39

KING
KN 53
NAVIGATION RECEIVER
al90
SWITCHED
A1RCRAFT POWER(Il-33V)
HIGH
VOLTAGE
LINE CURRENT
FILTER LlMIT
LIOl C101 Ol03
RECIFICATION FILTERING
LOW TRANSFORMER CRIOS CICS
RESET
SWITCHED r CIIC
TIOl CRIO6
A/C POWER CRID7 Cill
SEINO BR CRIOB (:11
TRANSISTOR
SWITCH SWITCH 3 5
CONTROL 0101
IIO2(C) Q102
PRECISION ERROR OVER CURRENT

VOLTAGE a SENSE LIMPr *
REFERENCE IIO2(D) RI25 IIO2(A)
FI6URE 4-6 KN 53 POWER SUPPLY BLOCK DIA6RAM

(Dwg. No. 696-7604-00, R-0)
MMOOO3 Page 4-13

3
3
Q
Pas
o'
10
B-
o
-m
oso 24
-i -i --i
or -I oo o e o >
o-zzoo a o > To o
Co OO
o cocr er o or
rog
O
o isa o oÑgo? »e
r- -
o> , 20
in
o No no
,T mm OgQ
cg: om --
¯U °
A 8
5 5°¾ (° 908¯
r P
KING
KN 53
NAVIGATION RECEIVER
RF AGC
RF AGC AMP AGC AMP

ATTACK Q410 Q411 Q408
R435
Q4l2 ges
Q402
ANTENNA
329.15 COURSE
3 POLE 33.3KHz IF IF WIDTH
PRE- MIXER BANDPASS IF AMPS ADJ
d533 3M.OMHz DETECTOR BUFFER
SELECTOR *
Q403 FILTER I40\
' Q405 " Q407 G.S. AUDIO
329.15 TO 335.OMHz
0401 Q402 R425 d40I
L404,L405,L406 Q404 Q406
PlN6
L40\ L402 C419,C420,C42\
L403 C422,C423,C424,
329.117 TO 334.967
C425
109.706 TO lit.656 MHz
VCO
Q4l3 4M , VCD C NTDCLVOLTAGE
Q4l5 CR40¡ J40 I
PIN I
L407 T40\
BANDPASS
L408
C450
LOOP 55566TO
COUNTER
MIXER I
BANDPASS BUFFER I COUNTER INJ,
Q416
L409 Q4l7 Q418 J40I
C455 CR403 PIN 4
GLIDESLOPE 97.0 TO 100.85 MHz

INJECTION
(NAV VCO) E407
FIGURE 4-7 GLIDESLOPE BLOCK DIAGRAM

(Dwg. No. 696-7605-00, R-0)
MMOOO3 Page 4-15

KING
KN 53
NAVIGATION RECEIVER
P532
330-1094-53
#22AWG
C3 A+ INPUT+t4 OR28VDC
--
# 22 AWG IN OUT
POWER GROUND 12VREGULATOR DME OUTPUTCODES
A --
GND 120-3026-06
NAVFREQUENCY MA MB MC MD ME
IN OUT MHz
4 ) SWITCHEDA+
GND
108 I O O I O
B )COMPOSITE
RI
109 i O O O I
0 110 0 1 0 0 I
15 )COMPOSITECOMMON
111 I I O O O
2 )5002-AUDIO
\\2 1 0 1 0 0
GLIDESLOPE DEVlATION 113 0 I I O O
P
RIS !!4 O \ O \ O
510'
!!5 0 O I I O
116 0 0 i O I
KN53 GLlDESLOPE FLAG ll7 O O O I I
R [5 O-500-µa
5|Ol' O2030-OÏl4-OO
R KA KB KC KD KE 50KHz
KHz
8 0 1 0 0 1 0
)RFAGC
.00
.05 0 I O O I I
7 )IFAGC .IO I i O O O O
2K
130-0202-23 .20 I O I O O O
CRI
R2 12PLACES ILS .30 0 I I O O O
MA OOT-TOO4-OO .40 0 1 0 i O O
R3 CR2 12PLACES
D v^ .50 0 0 I I O 0
CMR3
R4 60 0 O I O 1 0
H
MC .70 O O O I 1 O
R5 CR4 I O O \ O O
5 .80
CMRD5 90 I O O 0 I O
R6
ER6 ILS CHANNEL= I
R7
F
NOTES. I.SIMUSTBECLOSED TO GROUND TO
CRAy
RS VERIFY THE DMEOUTPUTCODES.
6
2. RHKNESS
=LLEEDDEEMMITTINN6
RB
M
KC 3.THE FOLLOWING CONNECTORS
RI CR9
10 ARE INCLUDEDINTHEKN53
CDRIO
RII INSTALLATION K1T 050-1712-00.
L 0.030-0101-02
(20TY)
KE
CRll b.030-1094-53 (IOTY)
CRil2 c.030-IIO7-30 (PINS FOR ITEMb ABOVE)
50KHz
E
N
DME CHANNELlNG LINES ENABLE
P533 -
¯]O30-Ol01-02,
P53I
030-0101-02 TO 3LIDESCOPE GENERATOR
TO VOR/LOC GENERATOR
FIGURE 5-1 KN 53 TEST FIXTURE

(Dwg. No. .002-0506-00, R-0)
Page 5-3
MMOOO3
KING
KN 53
NAVIGATION RECEIVER
DME CODE NAVCODE GLIDESLOPE DATA CATHODE DRIVER MAX CLOCK

YES AND STROBE
CLROECSE INPUTS YES
OK & OK OK OK
START
d532 PINS F, 1,5, I522.PINS3,4,5,6,7 PIN I, 2,3 OFI60\ P1NS 2,3,4,5,6,7 PIN 5 ISO7
H,D,J,L,IO,Ms I521,PINS 3,4,5,6 OF I508
1520,PINS3,4
NO NO NO NO
NO
PROCESSOR 1503,504,505 VCC (PIN24)OF CHECK 1JNES FOR CHECK LINES FOR CHECK LINES FOR
OUTPUTS YES SHORTS SHORTS SHORTS
I/O EXPANDER AT
+5,PINI2AND
OK OK
PIN6ATGROUND
NO NO
NO
I503,I504,I505 I/O EXPANDER
SUPPLY LINES
AREPROCESSOR PROCESSOR RESET

YES
-----Ma
SUPPLY LINES PINAT+5
OKP
NO NO
TROUBLESHOOT
CHECK RESET LINE
SROCLESSL NRES FOR SHORT
DOUSE FREQUENCY DOES INCREMENT/ DOESUNITSTORE

ANDSTANDBY YES DECREMENTSWITCH YES USE ANDSTANDBY
FREQUENCY EXCHANGE APPROPRIATLY FREQUENCIES
PLACESWHEN CHANGESTANDBY DURINGPOWEROR
TRANSFERIS FREQUENCY
PUSHED
NO NO NO
CHECK CONTINUITY CHECK FOR BAD CHECK I5I7,I519

SWITCH CONTACTS I507ASB,AND
OFTRANSFER
SWITCH AND ASSOCIATED
SHORTS (iN LINE CIRCUITRY
FIGURE 5-8 PROCESSOR TROUBLESHOOTINGFLOWCHART

(Dwg. No. 696-7618-00, R-0)
MMOOO3 Page 5-45

KING
KN 53
NAVIGATION RECEIVER
DISPLAY KEEP
YES
INTENSITY a AL1VES
OK OK
NO NO
VARIABLE DUTY CATHODE TROUBLESHOOT RS75, R576 TROUBLESHOOT

-YES
YES PROGRAMING R577, R578
CYCLE RAMP YES CATHODE DRIVERS DISPLAY AND
OK PIN 7 CURRENT PIN I I506 OK CONNECTOR
I515
OK 1508
NO NO
I5\6A & I516B &
CIRCUITY CIRCUITY

(Sheet 2 of 2)
MMOOO3 Page 5-41

KING
KN 53
NAVIGATION RECEIVER
ARE ALL DISPLAY

YES YES
START ANODES DATA
OK CORR
NO NO
MUX HIGH VOLTAGE

JOHNSON ANODE TROUBLESHOOT DISPLAY DATA CATHODE
CLOCK YES YES LEVEL YES YES YES
COUNTER DRIVERS DISPLAY B OK PINS2,3,4, DRIVERS
AT PIN4, ISO7 SHIFTER
OK I 3NO OK I514 CONNECTOR 5,6,7 NOSOS OK 5NOO8
OK OK Q5 2N,Q503
NO
TROUBLESHOOT TROUBLESHOOT TROUBLESHOOT TROUBLESHOOT SEE SECTION TROUBLESHOOT

LINES TO JOHNSON HIGH VOLTAGE ANODE PROCESSOR CATHODE
PROCESSOR COUNTER LEVEL SHIFTER DRIVERS TRBLSHOOT1NG DR1VERS

(Dwg. No. 696-7617-00, R-0)
(Sheet 1 of 2)
MMOOO3 Page 5-39

KING
KN 53
NAVIGATION RECEIVER
SWITCHED
AIRCRAFT POWER(II-33V)
HIGH
VOLTAGE
LINE CURRENT
FILTER LIMlT
LIOI CIOI QlO3
RECIFICKTION FILTER1NG
LOW TRANSFORMER CRID5 CIOS
RESET
' SWITCHED T101 I
CRIO6 CilO
A/C POWER CRIO7 Cil)
SEIN R CRIOB Cil
-26
TRANSISTOR
SWITCH SWITCH 3 5
CONTROL QIOI
IlO2(C) QIO2
PRECIS10N ERROR OVER CURRENT

VOLTAGE SENSE LlMIT *
REFERENCE IIO2(D) RI25 IlO2(A)
FIGURE 4-6 KN 53 POWER SUPPLY BLOCK DIAGRAM

(Dwg. No. 696-7604-00, R-0)
MMOOO3 Page 4-13

KING
KN 53
NAVIGATION RECEIVER
E NOTE "8
SEE NOTE'7 088-OO66-OO(4)

SEE NOTE"7" 030-2322-02
MATCHING SET
030-2322-50EE
OTE"9. ( MATCHCOLOR DOTS) TP301
047-4526-0 TP303
NOTES
as 3 TRANS, Q 306, 7, 8 9, 0, SEE DETAlL "C"

,
4. ADD THE SUFFlX

-01
TO THE 200-5971 NUMBER OF THE FARSLDE OF
+ ca43 THE BOARD. RUBBER STAMP OR LABLE METHODS ARE ACCEPTABLE,
P306
C367 5.PRIOR TO POST COATING BOTH SIDES OF ASSEMBLY WITH CLEAR
L306 URETHANE COATlNG (OI6-iO40-00),MASK OFF THE FOLLOWING:
Loyo-cow / \ TP30)THRUTP307,L305, d30),THRU,J305,E319,E32O,T302,T303,T304.J53I,
ta .507 TP305 L306, R 34l,R368, ALL MOUNTING SURFACES. ALL COMPONENTS lNSIDE AND ON THE BOARD
'047-4763-01 FARSIDE OF 047-4526-01 AND 047-4552-00
/ MUST ALSO BE FREE OF COATlNG.
Lol2 -il35-oo c - -
6.COAX CONNECTOR IS TO BE TlGHTENED,THEN SOLDERED TO FENCE ,

(SEE NOTE"lO") PRIOR TO INSTALLING FENCE ON BOARD.
TP302 7 BOTTOM SHIELD AND RECElVER FENCE,lNCLUDING PARTITIONS, ARE TO BE SOLDERED TO

.30
BOARD EVERY PLACE POSSIBLE.LEADS UNDER 047-4753-01 MUST NOT EXCEED.035MAX..
8.THE CASES OF Q 30), AND Q 302 ARE TO BE FLUSH WITH FAR SIDE OF BOARD.
TP304 \
- 030-2322-OH2) THE SOURCE.LEAD OF Q30I SHOULD ALSO BE SOLDERED TO THE CASE TAB ALONG
I 4 WITH C3OO. THE DRAIN LEAD OF Q301 JS WRAPPED AND SOLDERED AROUND THE
¯¯^¯' TOP LEAD OF R367 ALONG WITH C373.
9.PINS WITH ASTRISK ARE TO BE CUT OFF FLUSH WITH CARRJER.(FARSIDE ONLY),
008-0038-OH2
047-4552-00 FO.REMOVE THE PROTECTIVE BACKING FROM Ot2-il35-OO,\NSULATOR, AND INSTALL
009-597)-lo
sEE NOTE"ll" THE INSULATOR ON THE INSIDE OF 047-4753-01,SHIELD, BEFORE INSTALLING
THE SHIELD.
C C E
il. L305 MUST BE 1NSERTED FULLY 1NTO BOARD SO THAT ITS HEIGHT ABOVE THE
BOARD DOES NOT EXCEED .600 MAX..
B B B
E E C
DETAIL"A" DETAIL "B" DETAIL "C"
FIGURE 6-4 NAV RECEIVER ASSEMBLY

(Dwg. No. 300-5971-01, R-0)
MMOO40-9 Page 6-21

KING
KN 53
NAVIGATION RECEIVER
DIGITAL BOARO
J532 200-6077-OD/01
002-6077-00 P305 J305
RF AGC -
8
---
RF AGC
J531
FOR TEST ONLY
IF AGC -
7 2 -
IF AGC
P3Dl J301
OPEN --
9 l -
VOL i NAVIGATION
ANTENNA
DPEN --- K 2 -
NC NC --
2
S 3 --
+12 3 NAVIGATION RECEIVER
-L 4 -NC NC---- 4 200-5971-01
COMPOSITE ---
B 5 --
COMPOSITE 5 002 5971-00
6 ---NC NC--- 6
COMPOSITE COMUN ---15
5000 AUOTOOUT --
2 7 --
5000 AUDIO 7
ILS ENABLE ---

12
3 J2 J30
8 -
NC NC- 8
DME SW COMMON -
N 9 -
NC NC-- 9
E 10 NC NC--- 10
50KHz - ---
MA -
D 11 ----
IDENT 11
MB - H ES20 12 - +9 12
MC -
5 BLACK 13 NC
---- NC-- 13
E519 Op E52l
MD-11 RED 14-VOLHI 14
WH1TE
ME --
F
P303
KA -
6
KB M NAV PHASE DET GS INJECTION
-
E319 ----
KC- 10 4 J304 E320 GROUNO

L SHlELDED TWlSTED NAVCOUNTER
KD --
#2RSTHREECONDUC
KE- J
I ...I
THE OUTPUTSARE ONLY
VALÏD WITH GLIDESLOPE +FLAG - 13
E408
E407
OPTION 066-1067-00 -FLAG -
R
P401 J401
+DOWN -14
6 ----
GS AUDIO 6 GLIOESLOPE RECEIVER
5 -
+9 SW 5 200-6075-00
4 ---
COUNTERINJ. 4 002-6075-00
3 ----
NC NC- 3
E514 #26 RED/WHITE
SWITCHEDA+ -
4 2 -
GROUND 2
1 -
VCD CONTROL l J533
26 RED
GL ESLOPE
E214 _ ON/OFF
SWITCH THE GLIDESLOPE RECEIVER AND ASSOCIATED CONNECTIONSARE ONLY USEO WITH 066-1067-00 (GLIDESLOPE OPTION)
E510
SWITCH BOARD E215
200-6076-00 Pl03 JlO3 NOTE:
#22 BLACK +190
THE GLIOESLOPE RECEIVER AND
ASSOCIATEO CONNECTIONSARE
#26 P102 JlO2 NOT USED WITH
POWERSUPPLY
-066-1067-01.
E201 P24 E501

RED/WHITE E513 SWA+
IDENT 200-6074-00
E202 P23 E502
PlOi J101 002-6074-00
P20 EE 3
E2 E213
4
E21 E2ll 1
E205 P22 E505 1 -26
E206 VOL COMMON E506 2 RESET 2
VOL E507-o- E515 RED 3 +9 3

E207
E208 VOL HI 508+E516 WHITE 4 --
+5 4
E511
E209 IDENT 509 E517 BLK 5 GROUND 5
E518
RIGHT ANGŒ HEADERCONNECTIONS
FIGURE 5-10 KN 53 INTERNAL INTERCONNECT

(Dwg. No. 002-0448-00, R-0)
Rev.1, August 1981

MMOO40-8 Page 5-53
KING
KN 53
NAVIGATION RECEIVER
SEE NOTE 8" -SEE NOTE"12"
SEE SEE NOTE"7" 012-1174-00 (4)

NOTE 7"
MMAA COSLETR
DOTS)
SEE OTE"9
47-4526-0\ TP303
SEE NOTE
NOTES'
L TRANS. Q 303, |2 , 13,14, SEE DETAIL "A".
-{iEli 2 TRANS. Q 304,5,IO,l5, SEE DETAIL"B".
L304
3 TRANS.0306,7,8,9,0,SEE DETAIL"C".
4 ADD THE -Ol SUFFlX TO THE 200-597\ NUMBER OF THE FARSlDE OF
| | - -
TP306 THE BOARD. RUBBER STAMP OR LABLE METHODS ARE ACCEPTABLE.
5.PRlOR TO POST COAT1NG BOTH SIDES OF ASSEMBLYWlTH CLEAR
URETHANE COATjNG (016-1040-00), MASK OFF THE FOLLOW1NG:
Om<w o TP30\THRUTP307,L305, J3Oi,THRU,J305,E319,E320,T302,T303,T304,d531,
UT 6 TP305 L 306, R 34l,R368, ALL MOUNTING SURFACES. ALL COMPONENTS INSlDE AND ON THE BOARD
e-17 3-0i
/ -
FARSIDE OF 047-4526-01 AND 047-4552-00 MUST ALSO BE FREE OF COAT1NG.

0 2-455- 6.COAX CONNECTOR [S TO BE TIGHTENED,THEN SOLDERED TO FENCE,
EE 33TE O -- --
PRIOR TO INSTALLING FENCE ON BOARD.

TP302 BOTTOM SHIELD AND RECEIVER FENCE,1NCLUDING PARTITIONS, ARE TO BE SOLDERED TO
age
BOARD EVERY PLACE POSSlBLE.LEADSUNDER 047-4753-01 MUST NOT EXCEED.035MAX.
TP¾O4 8.THE CASES OF Q 301, AND Q 302 ARE TO BE FLUSH WITH FAR SIDE OF BOARD.
Oso-2322-CH2) THE SOURCE LEAD OF 0301 SHOULD ALSO BE SOLDERED TO THE CASE TAB ALONG
WITH C300. THE DRAIN LEAD OF Q30\ IS WRAPPED AND SOLDERED AROUND THE
TOP LEAD OF R367 ALONG WITH C373.
9.PINS W1TH ASTRlŠK ARE TO BE CUT OFF FLUSH WITH CARRIER.(.FARSIDE ONLY),
Oce-e U-OH2)
047-4552-00 597\-lO
lO.REMOVE THE PROTECTIVE BACKlNG FROM Ol2-1135-OO,iNSULATOR, AND INSTALL
NOTE il" 009
SEE THE INSULATUR ON THE INSIDE OF 047-4753-0! ,SHIELD, BEFORE JNSTALLJNG
THE SHIELD.
11. L305 MUST BE 1NSERTED FULLY INTO BOARD SO THAT ITS HEIGHT ABOVE THE
BOARD DOES NOT EXCEED MAX.. .600
12. LEAD LENGTHS IN VACINITY OF Q30\ SHOULD BE AS SHORT AS POSSIBLE.

B B B
E E C
DETAIL "Ñ DETAIL "B" DETAIL "C"
FIGURE 6-4 NAV RECEIVER ASSEMBLY

(Dwg. No. 300-5971-01, R-6)
Rev. 1. August 1981

MMOO40-9 Page 6-21
RF OSC HA EL - - sov
os
. vr
r
-- c r
KN 53 Digital Board Schematic

580006-45 KPN 600-1162-40 Page: 5 of 5
KING
KN 53
NAVIGATION RECEIVER
P/D 030-1094-53 P/0 030-1094-53 P/O 030-2070-00

P532 P621 P521
0 MA 12 ----55-- -------
N
H m NC ---
, M
5 MC 9 ----------------
W K
11 se a N P 7------------- x N I
F UE ll r- S I N
6
· --- ------------
e a 7 | y R
M -KB NC ---------‡
c 5
10 KC 4 --------47
O
L
N N
L KO 6 Q _ -ci
F 0 0 A
J KE H r- E
M
-----
E
E 50 0-: 5 ------Ci e 5 O
OME SW COMI.cu c E ----W- 6 2
N A R
r------- P I
L
1 r--·--' u
r--
- --
i V
030-1094-03 \ | r- R
P/ ---
N 12 ILS ENABLE S 10 +LEFT

" N 2
5 15 $" COMPOSITE
COMPDSITE COMMON
6
Î 3
rioi:T
+TO
i
e
3 2 11 raal.I
2 500 OHM AUDIO OUT 12 +VOR FLAG N
5 AUDIO COMMON 7 ADROFLAG LF
y
R (sEE NOTE D ,,,
O STA E P N
(SEE NOTE I)
13 +FLAG 4 STA F T O 2 Q
C ,
(SEE NOTE 1)
-FLAG Ë 9 STA G w I
O I
(SEE NOTE Il
V 14 su L 1 RoT c z 6 C
R
Plom 0 13 ROT H a / A
C
#22 AWG SEE NOTE2
--
8
4 STITCHED A.
3 -A+ IN (13 74/27.5VOC)

S
(TWO22 AWG)
C A+ IN
15
1 PWR GND A/C GND -- -- - -
(TWO 22 AWG) 22 Awe

A PM GNO
J
PS31 030-0101-02
TO NAV ANTENNA
P533 030-0101-02
(SEENOTEI)TD GLICESLOPE ANTENNA
NOTES:
1. THE5E INPUTS/0UTPUT5 ARE ONLY VALID WITH KN 53 GLIDESLOPE OPTION (066-1067-00)
2. PIN 8 IS 13.75VOC INPUT, 27.5VOC INPUT IS PIN R.
3, WIRE SIZES: A+, SWITCHEDA+, AND PWRGNO ARE 22AWG. ALL OTHERS ARE 24AWG.
4. KN 53 PIN DESIGNATORS NOT 5HOWN ARE N.C.
5. DASHED UNES TO INDICATORS ARE FOR REFERENCE ONLY AND IT IS NOT INTENDED TO
HAVE TWO INDICATORS WITH RESOLVERS TO ONE VOR/LOC CONVERTER,
6. THESE FUNCTIONS ARE NOT AVAlLABLE IN Kl 207 OR KNI S2\.
BOTH KNI 520 AND Ki 206 HAVE COURSE DATUM OPTlON A/P COUPLING.
FIGURE 2-8 KN 53 TO KN 72/KI 206 OR KNI 520 INTERCONNECT

(Dwg. No. 155-1329-00, R-1)
Rev. 1, July 1981

IMOO20-8 Page 2-19
KING
KN 53
NAVIGATION RECEIVER
030-1094-53 /0 03 -1 4 53 P/O 030-2178-00

P532 P621 P2 BOTTOM PLUG
D MA 12 y
H MB NC y
5 HC -
9 O
b
11 M 8 N P
F ME 11 T
6 KA 7 | X
5
M KB NC
10 KC 4 E
L -
KD 6 D N 5
J KE H
M L
E 50MIIl 5
E 5
N DMESW COMMON C ---
L _____J 5
A
P/O 030-1094-03 P/C 030-2153-00
P/O P721 P/O P721 Pl TOP PLUG
K
12 ILS ENABLE S 10 +LEFT V I
N B COMPOSITE 6 2 RIG||T
N N
5 15 COMPOSITECOMMON 3 +TO Z
11 i ROM T D
2 500 OHM AUDIO OUT 12 +VOR FLAG K
¡
S AUDIO COMMON 7 -VOR FLAG F
5 STA O
C
(SEE NOTE I) ,
, O K STA E A
R (SEE NOTE l)
13 -+FLA- ; R 4 STA F
R
(SEE NOTE I) -FLAG '
C (SEE NOTEI)
/ 9 STA G
14
L 1 RoT c O
13 RoT il
O R
R Pio P721
C
---
8
SEE NOTE 2
#22AWG SWITCHED A'
4 ON
(13.75/27.5VDc)
A+ IN
3 A/C GND
(TWO22 AWGA+IN #22AWG 15
C A
^
W
PWR GND
1
(TWO22AWG)PWR
GND
P531 030-0101-02
TO NAV ANTENNA
P533 030-0101-02 NOTES:

1. THESE INPUTS/OUTPUTS ARE ONLY VALIO WITH KN 53 GLIGESLOPE OPTION (066-1067-00)
2. PIN 8 IS 13.75VOC INPUT, 27.5VOC INPUT IS PIN R.
3. WIRE ŠIZES: A+, SWITCHED A+, AND PWR GNO ARE 22AWG. ALL OTHERSARE 24AWG.
4. KN 53 PIN DESIGNATORS NOT SHOWNARE N.C.
FIGURE 2-9 KN 53 TO KN 72/KI 525 OR KI 525A INTERCONNECT

(Dwg. No. 155-1330-00, R-0)
IMOO20-8 Page 2-21

32.5ms
- - -
OV
C4l7
1 PRESELECTOR C405 C410 MIXER lovt

i
I 120 t2 > R4I4 20V I
)I IL '°° * IS IF 2ndfF DETECTOR
RS40K9
R402 R403 C4I4 SV
C6488 100 100 64II
R34 OK C459 R459

R422
L402
i i
L403 - R4l5
IF BANDPASS FILTER P/O
1 I .
6
4
JS33 -
- C4 5
240
R46I
L4 C24
37
R404 35 25 R427
I2K
C402
68 68
R407 412 -- R4
4 9
R428
16K
R437 R434 795V 408

47K IOK
C434
6Vf R 9
RS435 [432
04 i 04lO TP404
G.S. VCO CONTROL

+9V
R458
15K
|AGC
RF
R436
I
CR402
3.89V 428V
R430
-
R433
J40\ l
CR40I VCO R446 --
SET IOOK
R439 I I F AGC AMP

TP405
- C4 C443 4
R44 C446 L407 C449 C43 3
005 330 .I 00µf 3 247pf 262pi
C4
2 6
35 RE
T401
C 5 3 R4257 8 C46
R44 R4 C 03
444 47K RS447 R45 13Vp-p 32.5ms-
4 7
RS649 0416 5.7V
26
44
68463
COUNTER INJECTION
0415 R R
l.55V
8
451
E407 GL1DESgE INJECTION LOOP MIXER COUNTER BUFFER
E408
NOTES IV pp 35Vp-p
I. UNLESS NOTED; ALL RESISTANCE VALUES ARE IN OHMS,CW,5%

ALL CAFACITANCE VALUES ARE IN PICOFARADS(pf!
2. NO SYMBOL RF LEVEL DDES NOT MATTER.

NO RF SIGNAL.
700yv RF SIGNAL
RECEIVER FREQUENCY=332mHz.
KN53 GLIDESLOPE BOARD AFTER MOD 1

FIGURE 2
DATE: July, 27, 1979 KN 53-1
880004-38 KPN 600-1162-10 Addendum

KING
KN 53
NAVIGATION RECEIVER
089-8252-30(4)
090-0019-07(2)
REFERENCE INSTALLATION DRAWING

f55-53I4-00
FOR OPTIONAL DIPLEXER UNIT
(KAI39)
030-OlO3I-02(2)
GLIDESLOPE
ANTENNA
047-4751-04 (066-1067-00 ONLY)
083-5903-07 (2)
NAV A TENNA
POLARIZINGKEY-
POLARIZING KEY
FRONT VIEW -
CONNECTOR
(LOOKING IN FROM FRONT
030-1094 -53
OF RACK )
P532
089-6012-08 .
SCREW, FHP 6-32 x I/2

(4 PLACES)
089-2353-01
CLIP NUTS, 6-32

(4 PLACES)
FIGURE 2-5 KN 53 INSTALLATION DRAWING

(Dwg. No. 155-5312-00, R-0)
IMOO20-8 Page 2-13

KING
KN 53
NAVIGATION RECEIVER
8.000 .437
(20.320) ( l.IIO)
.600
(1.524)
4.900 __
350
(l2. 446 ) (.889) LOCK1NG SCREW
6.250
(!5.875)
230606
(2 )
CUTOUT DIMENSlONS FOR BEH1ND

1.300
G.S.
L GCOSÙRSE (3.302) AIRCRAFT PANEL MOUNT
R626 (15.72)
6.312
(16.032) (SEE NOTE6)
R34l NAV
OPTIONAL RFAGC
R368 NAV 350 CUTOUT DIMENSIONS FOR FRONT
DIPLEXER UNIT
C (3429)
D
E 3.200 AIRCRAFT PANEL MOUNT
R546 28)
SEE NOTE 3
| I 6 320
(\6.052)
.700
(1.778)
NOTES:
1. DIMENSIONS IN ( ) ARE IN CENTIMETERS.
2. WEIGHT: 066-IO67-OO = 3.OLBS. (I.36Kg)
066-1067-01 = 2.7 LBS.
(l.23Kg)
3. DASHED CIRCLES INDICATE TUNING ADJUSTMENT
ACCESS HOLES LOCATED ON TOP OF KN 53.
4. TOLERANCES FOR PANEL CUTOUTS: 00
0
5. WHEN INSTALLINGTWO OR MORE PANEL MOUNTEDUNITS IN A STACK,
THE MOUNTINGTRAYS SHALL BE SPACED INCHES (.127cm) APART.
.050
NEWER STYLE MOUNTINGTRAYS HAVE HAD.025|NCH (.0635cm) D1MPLES

BUILT IN, TOP AND BOTTOM, BOTH SIDES, SO THAT TWO NEW STYLE
TRAYS WILL AUTOMATICALLY BE SPACED PROPERLY.
6. TO DETERM1NE STACKHEIGHT, USE THE HE1GHTDIMENSION FOR A FRONT
AIRCRAFT PANEL MOUNT.
FIGURE 2-4 KN 53 OUTLINE AND MOUNTINGDRAWING

(Dwg. No. 155-5313-000, R-3)
Rev. 1, July 1981

IMOO20-8 Page 2-11
32.5ms
OV
C417
PRESELECTOR c40s c4io MIXER Iov
it I IF 2nd fF DETECTOR
R5
R40002 4003 SV
C4 K C64 4
C408
c 59 8459
IF BANDPASS FILTER
L402 L403 . R4 +9v
COURSE
.400
R4tl o
56K C O C 02 C WIDTH AD
C403 C40 6.2VC4l8 .5V-
R40 R64525
5 R462 0426 RIO AUDIO
3.6V
0403 I.5 K R42l
TOV-7 CW Tyy
C4 3 .ipt
L404 L405 L406 C428 C432 04 5
R412K IK P402 .059
C 7 Q4 2 4 2200 R417
C401 Q40I D TP401
C4062 C
J533 I O 4150 242300
33
S
R
R423404
2
54 R
Q4
02
GS VCO CONTROL RF
pg
- - - - SV
R438
15K AGC
6
437V 3.89V 4,28V
R430
d401 33K
c VCO R44o
SET
4,9 IF AGC AMP
4K
T" OE
- C4 C443
C42
R440 C446 L407
27µh
C449 C439 C438
005µf 2BV2K 330 00µf 4 f
¯
344
OBµs
R46600
OV
2 C40553
3 SMRE
T40I
5 R 4É .-R475 3. 4IBV R4257 CO458 C4060 C 03
R4470 R 5 32.5ms-
4 7 13Vp-p
L409
5 9V
- R443
C4 R24450
C343502 TP407
C463 R4 C42
CCJNTER
68 _ Q415 R43
6K 376V4
4 i
INJECTION
L55V
Q4|8
L
C45 I C450 330

E4 oaps
GLlDESLOPE INJECTION LOOP MIXER COUNTER BUFFER
E408
IOV 30V5V
NOTES p-p
l. UNLESS NOTED; ALL RESISTANCE VALUES ARE IN OHMS,QW,5%

ALL CANCITANCE VALUES ARE IN PICOFARADS(pf)
2 NO SYMBOL= RF LEVEL DOES NOT MATTER.

NO RF SIGNAL.
700µv RF SIGNAL.
RECEIVER FREQUENCY 332 mHz.
=
KN53 GLIDESLOPE BOARD AFTER MOD 1

FIGURE 2
DATE: July, 27, 1979 KN 53-1
SBOGO4-38 KPN 600-1162-10 PAGE: 4 of 4

KING
KN 53
NAVIGATION RECEIVER
CHECK FIOI,F50I
SYSTEM DEAD F502,F503,iF BLOWN
YES
START CHECK FOR SHORT
DIRCUITS OR
EXCESSIVE LOADS
NO
NO
3lJDESLOPE
DISPLAY YES DISPLAY NAVRECEIVER DME
YES YES RECEIVER YES
PROPERLY DATA
------
OPERATION y UTFUT3
OPERATION
1LLUMINATED CORRECT OK OK
OK
NO NO NO
NO
NO
POWER
SEE DISPLAY NAV PHASE SEE NAV GS.PHASE G.S.RCVR SEEG.S. SEE
SUPPLY YES YES YES YES
SECTION COMPARATOR R RECEIVER COMPARATOR R BOARD M CONVERTER MICROPROCESSOR
VOLTAGES
TROUBLESHOOTING LOCKED LOCKED OPERATIONAL SECTION TROUBLESHOOTING
CORRECT
SECTION
NO NO NO NO
SEESECTION ON
SEENAV SEEG.S. SEEG.S.
POWER SUPPLY
SYNTHESIZER S SYNTHESIZER a RECEIVER
TROUBLESHOOTING
MICROPROCESSOR MICROPROCESSOR SECTION
TROUBLESHOOTING TROUBLESHOOTING
SECTION SECTION
FIGURE 5-3 KN 53 SYSTEM TROUBLESHOOTINGFLOWCHART

(Dwg. No. 696-7614-00, R-0)
MMOOO3 Page 5-19

KING
KN 53
NAVIGATION RECEIVER
LE AGC. YES I30I INPUT YES TROUBLESHOOT

TP30l PINS465130I 1301
NO NO
1801 INPUT TROUBLESHOOT

TROUBLESHOOT YES
FILTEROMATCHING
IE AGC DRAIN 0302
TRANSFORMERS
NO
DC VOLTAGES DC VOLTAGES CHECK

LO INJECT YES 0302 YES Q30l YES PRESELECTOR y CONNECTlON
GATE 2 Q302 GATE I,2,DRAIN GATE I,2,DRAIN ALLIGNED FROM SIGNAL
SOURCE, Q3 02 SOURCE O 30! GENERATOR
TO ANTENNA
NO NO NO
CONNECTION
TROUBLESHOOT
TROUBLESHOOT
0 DET. OUTPUT YES TROUBLESHOOT 0302 AND
TP305 C356,C316
CIRCUITRY CIRCUITRY
NO
O DET OUTPUT
TP 305
FROM SECTION NO
SYNTHESIZER
TROLSHOOTING
CHECK FOR CHECK FOR

VOLTAGE DROP YES
ACROSS R345 SHORTS ON DISCONTINUITY
TUNING LINES IN 0 DET LINE
NO
RECEIVER COUNTER SEE SECTION

VCO OUTPUT YES YES YES
BUFFER OUTPUT BUFFER OUTPUT SYNTHESIZER
EXTERNAL T.V.
EXTERNAL T.V. EXTERNAL Ty TRBLSHOOTING
NO NO NO
TROUBLESHOOT
RECEIVER COUNTER
VCO
BUFFER BUFFER
FIGURE 5-9 NAV RECEIVER TROUBLESHOOTINGFLOWCHART

(Sheet 2 of 2)
MMOOO3 Page 5-51

KING
KN 53
NAVIGATION RECEIVER
0 DETECTOR
YES
START LOCKUP ---
PINI,I510
NO
50 KHz REF 50 KHz TROUBLESHOOT

PIN 4 ISOS FROM DIVIDER O DETECTOR
PIN 3 I510
NO NO
3.2mHz NAv COUNTER PROGRAMABLE TROUBLESHOOT

YES YES
OSCILLATOR INJECT DIVIDER t TTLTO CMOS
PlN II, T509 PIN I, I5l2 PIN 11 I520 INTERFACE
NO NO NO
BINARY COUNTER
TROUBLESHOOT SEE SECTION DIVIDE BY 20/21 Q OUTPUTS
YES
REFERENCE NAV RECE1VER OUTPUT
PINS II,12,l3,\4
OSCILLATOR TRBLSHOOTING PIN6 I511
I520
DECADE COUNTER
NO NO OUTPUTS
NO
PINS 11,12,13,14
1521
TROUBLESHOOT BINARY COUNTER

DIVIDE BY 20/21 PROGRAM PINS
I5II, I512 PINS 3,4,5,61520
NO NO
CHECK LINES
BINARY COUNTER
TO PROCESSOR
PROGRAM PINS
FOR SHORTS
PINS 3,4,5,6
1521
FIGURE 5-5 NAV SYNTHESIZER TROUBLESHOOTINGFLOWCHART

(Dwg. No. 696-7616-00, R-0)
MMOOO3 Page 5-25

KING
KN 53
NAVIGATION RECEIVER
+9 SW GLIDESLOPE
VOLTAGE YES FREQUENCY YES
START CORRECT(AFTER 3YWTIIE3 ER
SWITCHO604) OPERATING
NO NO
CHECKTHEINPUTS IS VCO CONTROL

VCO OUTPUT ADJUST VCO
YES YES VOLTAGETRYING YES
AMPLITUDE GLIDESLOPE INJ TO CORRECT? CONTROLVOLTAGE
PIN 13, I603
GOOD(TP406) ANDt09KHZ REF. (T40l )
NO NO NO
AKREESURE CSO PASREATOR ,\KOZ HNEN4 CCHOEMCKARAHAOSRE

CHECK VCO 15160\OUTPUT CAN VCO BE COUNTERBUFFER
YES ' YES YES YES
Q4l3,4l4,415 CHANNELIS CORRECTŸ MANUALLY OUTPUTCORRECT RECElVING VCOMANUALLY BLOOPFILTER
(FVCO-FNAVVCO) li.lKHZ REEP CONTROLLEDTO I603,R601,
CR401 SELECTED CONTROLEDP
1603 PIN 3 CORRECT R602
NO NO NO FREQUENCY
NO
NO
REL E CHECK CHE ISOI CC CKROL CCHO ' CHECK DIVIDE

BY CHECKCOUNTERS
O YES YES YES LINE NTE FE
---er
IS I LOW Q604 SEE DETAILED
-----•
160\ BAD FOR SHORTS a IlomHZ BANDPASS, NINE COUNTER
BEFORESWITCHP CRSO¡ THEORY CHECK VCO 12mHZ BANDP SS' 1605,606,607
0413,414,4150 Q4l6,417,41 1602
NO CR40\ L408,C450
L409, C456
CHECKTHAT A
LOCALIZER
CHANNELHAS
BEEN SELECTED
FIGURE 5-6 GLIDESLOPE TROUBLESHOOTINGFLOWCHART

(Dwg. No. 696-7611-00, R-0)
(Sheet 1 of 3)
MMOOO3 Page 5-31

KING
KN 53
NAVIGATION RECEIVER
RECIEVERSECTION CONVERTER
YES YES
OPERATING SECTION
(TP402) OPERATING?
NO NO
DETECTOR CENTERING CSHUE9CKRACTIVE

YES FLAG VOLTAGE YES CHECK D-BAR
OUTPUT GOOD? YES YE YES
ADJUSTED DETECTOR DRIVER
COLLECTORO40f GOOD?
R626 CR605, 606 16088
NO NO
CHECK CHECK FREQUENCY

FLAG CURRENT CHECK FLAG
CHECK DETECTOR D-BAR VOLTAGE YES YES ADDITIVE YES YES RESPONSE OF 90 a
ADJUSTED DETECTOR DRIVER 150HZ FILTERS
0405, Q406 GOODP
R636 CR603, 604 1608A CHECK C609,10,II,SI2
NO
COURSE WIDTH CHECK CHECK

YES YES REFERENCE YES YES
ADJUSTED AUD10BUFFER CHECK ISOS
VOLTAGEB
R 425 0407 ACTIVE FILTERS A BB
1608 CSD
IS DITH :R ON
VCO Ct·NTROL YES
lim C
VOLTAGE f.T
78l.25HZ
NO
CHECK DITHER
GENERATOR 1509
LOOP FILTER.

(Sheet 2 of 3)
MMOOO3 Page 5-33

KING
KN 53
NAVIGATION RECEIVER
.250
-
.125
RG-58A/U KPN 026-0015-00

USED ON NAV,COM,DME,XPONDER
AND RADIO TELEPHONE.
.125
SOLDER SHIELD NSIDE.

SEE NOTE L
COAXI RG-124B/U KPN 024-0002-00
/ CUT,STRIP AND SOLDER DME LOW LOSS AND T5-50
AS SHOWN, SAME AS ABOVE. TIMES AA24l3PN KPN 024-0013-00
TRANSPONDER LOW LOSS.
(USE CAUTION WHEN SOLDERING SHIELD,
SOLDER SHIELD OUTSIDE. EXCESS HEAT WILL MELT CENTER
SEE NOTE I- CONDUCTOR INSULATOR.)
INSTALL .375
50 OHM MATCH. .!25 SLIDE FERRULE 076-1042-01

OVER SHIELD.
RG- 316U 026-0011-00

GLIDE SLOPE ANTENA.
AVOID EXCESS SOLDER
ON CENTER CONDUCTOR SOLDER .125
FOLD BRAID BACK
SHIELD AND OVER FERRULE
FERRUL.
SEE NOTE I.
AFTER lNSTALLING CAR
TACK SOLDER-2 PLACES.
NOTES:
L AVOlD APPLYlNG EXCESSlVE HEAT TO CONNECTOR BODY.
HEAT SINK SPRING CONTACTS DURING SOLDERING.
WARNING
CLOSE ADHERANCE TO THIS PROCEDURE IS NECESSARY FOR AN

INTERFERENCE-FREE INSTALLATION.
FIGURE 2-3 ANTENNACONNECTOR

Rev. 1, JuLy 1981 (Dwg. No. 030-0101-02, R-4)
IMOO20-8
Page 2-9
KING
KN 53
NAVIGATION RECEIVER
047¯4689-OI
NOTES: 089-5674-03 076-Ol7PO9-,

REE
I. BEFORE INSTALLING FRONT PANEL 089-5899-03(2)
(073-0367-20),POSITION LENS
047-4750-017
047¯4527-Ol
(068-0832-0\) 1N FRONT PANEL
AND CEMENT WITH (016-1131-00) 057-2l39¯OO
047-475! 04
076-018 007 (
4
(\5 FOR ASSY -Ol)
069-6298-03 057-2131-00 (FOR ASSY -OO)
057-2131-0) (FOR ASSY -01)
II44-O
047 4688-02
43-00
012-037 00 -
'
089-5899-05 -
Ol2 |138-00
47-4
FIGURE 6-1 KN 53 FINAL ASSEMBLY

(Dwg. No. 300-2320-00/01, R-0)
MMOO40-9 Page 6-5

KING
KN 53
NAVIGATION RECEIVER
--047-4689-02
NOTES: 089-5874-03 076-0171-09

REE
I. BEFORE 1NSTALLING FRONT PANEL 047-4750-0\- 089-5899-O3(2)
(073-0387-20), POSITION LENS
047-4527¯Ol
(088-0832-01) IN FRONT PANEL --
AND CEMENT WITH (016-113\ 00). 057-2l39-00

2. WHEN BUILDING300-2320-ÔO
(GLlDESLOPE OPTION), CONNECT THE
GLIDESLOPEINJECTION WIRES,
026-0002-00, AS NOTED.
SEE NOTE 2 I
E320
3.-X DESIGNATES LENS OR FRONT PANEL i E319
ASSY WITH SHINY LENS.
4 (ORPT ANNEA SE Wl2OH E2N850

ON U D
N3-0
047-475l-04
(15 FOR ASSY -OI) 012-1022-00 (2)-/

' c
-
089-6298 03 --
057-213\ OO(FOR ASSY-OOS-02)
(3 FOR ASSY ¯00) 057-2\3l-Ol(FOR ASSY-OIS-03)
(2 FOR ASSY OI) 012-1 44-00
047-4688-02
088-0832-01
(FOR -OO a Ol ASSY) - .
X-088-0832-03
(FOR -02 a -03 ASSY)
OR 2OO-2805-OO (FOR -OO 8 ASSYS) -01
X-2OO-2805-Ol(FOR-O2 8-03ASSY )
Ol2-II57-00
NOE 2E
7-46 O
SE
090-0265-00
3008 823\-00
89-6561-00
l87- Il64¯OO 089-6004-03(IO)
089-6303-03(4) Ol2-Il27-OO(61
057-l540-OO
FIGURE 6-1 KN 53 FINAL ASSEMBLY

(Dwg. No. 300-2320-00/01, R-11)
Rev. 1, August 1981

MMOO40-9 Page 6-5
KING
KN 53
NAVIGATION RECEIVER
N]TES:
150-0003-10
(2PLCS)
1. .(016-1040-00),
PRIOR TO POST CDATING
OFF THE
MASK
SIDES
BOTH OF -SSY nÏ I C-EAR URETHANECOATING
FOLLOWTN 552'. OfJ 23?3-09. C503,
RMS. M.L SIFURCATED TERM1N 01) .'.LL 91NTIN. USFACES*,
-SEE NOTE 7" P.E Mits. INSIDE OF OASHER I 2 (5 (OM O 7-23) WN 1501,
70 R21*, PIT*, P302·, PS 9101". Gér,
ELE PIER. , n'.
SEE NOTE 9 P103 PSDI",R620,ANDR636.
,
033 0057 (2)-\ 088-0830-01- *OENOTES THAT MASKINGIS REQUIRED ON BOTH SIDES OF BOARD.
oss-oasi-oo
(SEE NOTES384) 2. ADO THE ilx 10 M EDI m/7
-935
NUMBER.ONTHE FAR SIDE OF THE
BOARO. RUBetR STAMP OR LABEL METHJDS ARE ACCEPTABLE.
Si FUCP -R542 3. 088-0831-00, 088-0830-01, 5501, AND 200-5076-00 MUST BE INSTALLED
AFTER PDM CIT-TIN TM C,c3r]PRAY CONTAMINATIONWILL DESTRG¥ THE
SWITCHIA. 00R TEMST) 5 Q ALL SWITCHES.
Le 7
18 4. INSERT 3501 INTO BOARDUNTIL THE SWITCH BODYBOTTOMSOUT DN 90ARO,
R63 TO ASSURE PERFECT ALIGNFFNT TC'DER THE TWOOUTSIDE TERMINAL5flRST
TO PREVENT DAMAGINGTHE nOOL (CNTACTS. SNAP 088-0830-01 IMO
a n 088-0831-00 BEFORE HEAT M:/N £ 38-0831-00 INTO THE BOARD. TŒ
1514
+ + BODYOF 088-0831-00 MUST BE FLUSH WITH THE PC BOARDAND OBB-C:50 01
606 DI I 603 I 605 MUST WORKSMOOTHLY.
R ·
MFC Cl40¿. 2CJ-tB6-00 TO THE RIGHT ANGLE HEADER, 03G-2323-09,

5.
.1
i P40l T 5 %.T E rB4JRED TO GUARANTEEALIGNMENTIN THE CHASSIS.

9 O Oi
6. APPLY ADHESIVE, 016-1082-00, UNDERY501, USING CARE NOT TO
I 608 CONTAMINATEC503.
626 7. CLIP LEAD 10 FROMUSO2 BEFORE INSTALLING ON PC E :.RD. U502
(015 043·013 IS ONLY USED WITH ANODEDRIVER, IBM, 120-3083-00.
L. 2 1. Celluu MEN AM3DEDRIVER, I514, 120 0095 00 IS USED
8. Ti 5, 05.5 0057-20, FOR I50l MUST BE INSERTED FOR MAXIMUM
026-0002-00 Os cei2 bcARD ENGAGEMENT THESE LEADS CANNOT BE TRIMMED.
9. IS , F50b F500 F503, RS42,030-2316-OO, ARE TO BE INSTALLED

L C
L5 C
950
L5 10. AFTER INSTALLtNG 050-2316-00, POST COATIT'S RESPECTIVE PADS ON
C THE NEAR SIDE OF THE BOARD.
4
SEE NOTE"9"
C .
LSO C .
C
L5 Ogg_ g-QQ
SEE NOTE"[O"
J532
0/
I502 E 2 14
E 215
506
009-6077 -01 -
089-2140-OO(2
SEE NOTE"9 SEE NOTE"6 O26 0002-00(5) 030 2323-09
089-5436-D4(2
(3PLCS) (LOOP USED TOSECURE WIRE)
200-6076-00
(SEE NOTE385)
9.0¾
WIRING CHART
E
FROM TO DESCRIPTION KING PART NO. LENGTH E52
55
ESIO E5|I 22 BLACK 025-0003--00 11.500 E515
E B E C
426 025-0018-22 E518
E214 E512 RED 10.250
E514 E215 26 RED/WHITE 025-0018-29 9,750 so-co49-ogi) e WlRE SOLDERED TO

0507 05 I THRU 0504
E5l3 E215 26 RED/WHITE 025-0018-29 1.750 SHIELD,
150-OOT2-OO(i)
EE55220
EE55176 288 WLH
DETAJL "A"
T SEE DETAIL "A"
E519 E515 28 RED
SHIELEE518 26 GREEN 025-0018-55 .000

E E
Q506 Q5|O, Q509, Q5Il THRU Q5l5,
Q5l6 THRU Q5|8 Q5l9 THRU QS2]
FIGURE 6-7 DIGITAL BOARD ASSEMBLY

(Dwg. No. 300-6077-00, R-20)
Rev. 1, August 1981

MMOO40-9 Page 6-41
KING
KN 53
NAVIGATION RECEIVER
J532
PIN N DME CHANNELING ... P304
DME COMMON .
12 DME CHANNELING NAV CTR
BUFFERS
Q5ll-2\
CMOS/
TTL
BUFFER
10 2
TTL/5CMOS EA5ROM
| 4
I/O
3 MICROPROCESSOR 4 4 COMPARÁTOR
5 TTL / ECL
ISOI EXPANDER IS22 ,
ISO2 RS31 R532
PRESETTABLE SLIP-STOP SLIP-STOP TTL/ECL -

IOlil ECL/TTL -
2
/\ COUNTER DECODE SLIP-START RS33 I512A Q501 I51\A
5 j
4 IO I52I I5HB R529
PRESETTABLE
CATHODE INC / DEC
SWITCHES COUNTER
DRlVER
-16
I52O PHASE
I 506 P303
NAV LOCATED ON COMP i NAV PHASE
DISPLAY SWITCH BOARD 1510 NAV SYNTHESIZER DECTECTOR
TTL/CMOS
50KH
1NTERFACE
DIMMING Q504
ISIS ¯-------- 3.2MHz REC
J2,5KHz
I516 OSC 8 D1VIDER
78(.25Hz
RS42 3.2MHz YSOI I509
9V
OOKHz
2
9
S 9VOLT 1602
DIGIT ANODE P40i
FILTER
DRIVER POWERSWITCH PIN5
COUNTER +9 SW1TCHED
C603, C604 Q604 TO G.S.
1513 1514
L60\ CR60I 11.1 KH RECEIVER
I DISPLAY DRIVER
L _ _ _ _ _ _ _ _ _
PROGRAM- PHASE LOOP P40I
SER1AL TO MABLE PIN I
COMPARATOR FILTER
1 3 PARALLEL CONY 6 VCO CONTROL
COUNTER 1603 R601 R603
VOLTAGE
I601
1 I606 1607 R602 C607
P401
PlN4 9/÷14
COUNTER INJECTICP) FLAG ADJ
1605 R636
FROM G.S. RCVR
P401 JS32
PlN6 90HZ FILTER ADDITIVE FLAG
PIN13
G.S. AUDIO * AUDIODECTECTOR DRIVER : +FLAG
--
I608C
C609 C610 I608A
CR603,604
R6IS,IS, 20 CENTERING ADJ.
R626
J532
50HZ F1LTER SUBTRACTIVE D-BAR
p p
I608D AUDIO DECTECTOR DRIVER r +UP
FIGURE 4-4 KN 53 DIGITAL BOARDBLOCK DIAGRAM
C6II C6I2 CR605,606 I608B
(Dwg. No. 696-7602-00, R-1) OPTIONAL GS DIGITAL
R6I6, 17, 18
v. 1, August 1981 |
1040-7 Page 4-7 --- -- ------ ------- ----
KING
KN 53
NAVIGATION RECEIVER
NOTES;
150-0003-10
1. . PRIOR TO POST COATING BOTH SIOES OF ASSY WITH CLEAR URETHANECOATIIB
(2PLCS) (016-1040-00), MASKOFF THE FOLLOWING: J532*, 030-2323-09, C503,
R546, ALL BIFURCATEDTERI¢INALS (008-0038-01), ALL MOUNTINGSURFACES*,
-SEE NOTE"†' ALL AREAS INSIDE OF DASHEDLINES*, SOCKETS (033-0057-20) FOR I501,
E515 TO E521*, P30l*, P302*. P303*. P30P. P305*, P101*, PlO2*,
r-SEE NOTE"9 PlO3*, P40I",R 626,AND R636,
(2) 088-0830-0\- *0ENOTES THAT MASMINGÏS REQUIRED ON BOTH SIDES OF BDARO.
088-0831 00
SEE NOTES384) 2. A00 THE -00 SUFFIX TO THE 200-6077- NUMBERON THE FAR SIDE OF THE
BOARO. RUBBERSTAMP OR LABEL METEDDSARE ACCEPTABLE.
El F RS42 088-0831-00, 088-0830-01. 5501. AND 200-6076-00 MUST BE INSTALLEO
' "" 3.
AFTER POST COATING. ANY OVERSPRAY CONTAMINATION WILL DESTROYTHE
SWITCHING CHARACTERISTICS OF ALL SWITCHES.
L (.07 I 402 I r
I
-
4. INSERT 5501 INTO BOARDUNTIL THE SWITCH BODYBOTTOMSOUT ON BOARO,
6L3 TO ASSURE PERFECT ALIGNMENT. SOLDER THE TWOOUTSIDE TERMINALSFIRST
I 1.. TO PREVENT OAMAGINGTHE SWITCH CONTACTS. SNAP 088-0830-01 INTO
n\n
n a n a a n 9 a n ^ =
154
088-0831-00 BEFORE HEAT STAKING 088-0831-00 INTO THE 80ARO. THE
BODYOF 088-0831-00 MUST BE FLUSH WITH THE PC BOARDAND 088-0830-01
6:3 6 MUETWORKSMOOTHLY.
REwoR NOTES 5. BEFORE SOLDERING 200-6076-00 TO THE RIGHT ANGLE HEADER, 030-2323-09,
Eck v4ot THE BOARDSMUST BE FIXTURED TO GUARANTEEALIGNMENTIN THE CHASSIS.
i i e 4.
EC a o e 2[] 6. APPLY ADHESIVE, 016-1082-00, UNOER Y501, -USING CARE NOT TO
10 CONTAMINATEC503.
8624 7 CLIP LEAD 10 FROMU502 SEFORE INSTALLING ON PC BOARD. U502
0 504 (015 0041-01) IS ONLY USED WITH ANODEDRIVER, 1514. 120-3083-00.
LEG4
U502 IS OMITTED WHEMAMX3EORIVER, 1514, 120-0095-00 15 USED.
8 t CRKETSNMO3E3 00N57- FEORLE MAXIMUM
MUSTNBEINSERTMEDEFOR
026-0003-00 ca c611 S
9. I501, F501, F502, F503, R542,O30-23l6-OO, ARE To SE INSTALLED

AFTER Post coATING.
eeeeee emeeeeeeeeee uma
SEE NOTE "9"
J532
r:D 214
ri
003 1378-Ol(1)
-
089-2l40-OO(2
SEE NOTE"9 5EE NOTE"6 026- CT -OO(5) 030-2323-09
089-5436-04(2
(3 PLC S) (LOOP USE YO SECURE RE
200-6076-00
(SEE NOTE 3 8 5)
9 000 - --- -
WIRlNG CHART co'
E517
ES2
FROM TO DESCRIPTION KING PART NO. LENGTH E516
ES
E510 E5|| 22 BLACK 025-0003-00 II.500 E5i5
E C
E2l4 E512 26 RED 025-0018-22 10250 ESIS
E514 E215 26 RED/WHITE O25-OOle-29 9 750 025-5013-02

SOLDERED TO
E513 E2i5 26 RED/WHITE 025-0018-29 I 750 60
03/2-CO(i)
C C
E520 E5l7 28 BLACK
DETAtL "A"
E521 E516 28 WHITE SEE DETAIL"A
E5l9 E515 28 RED
SHIELCE518 26 GREEN 025-00!8-55 1.000 E E

Q506, OSIO, 0509, 05il THRU 05!5,
05l6 THRU 05!8 0519 THRU Q52]

(Dwg. No. 300-6077-00, R-19)
Rev. 1, August 1981

MMOO40-9 Page 6-41
KING
KN 53
NAVIGATION RECEIVER
C POTES:
B 150-0003-10
1, PRIDR TO POST COATING BOTH SIDES OF ASSY WITH CLEAR URETHANECOATING
E
(2PLCS) (016-1040-00). MASKOFF THE FOLLOWING J532*. 030-2323-09, 0503,
Q5I2,0520,Q5l7 R546, ALL BIFURCATEDTERMINALS (008-0038-01), ALL MOUNTINGSURFACES*
SEE NOTE"7" ALL AREAS INSICE ET CASA.D LDIES*, SOCWTS (033-0057-20) FOR I501.
E515 TO E521*,.?¾1•, PICT P303*, P302*, P305*, PlOl*, PlO2*,
/cSEE NOTE"9" P103*, P40l",R626.AND ¾636.
E 033 EOOS7 EO (2) 088-0830-0 - *0ENOTES THAT MASKINGIS REQUIRED ON BOTH SIDES OF BOARD.
8 088-0831-00
SEE NOTES384) 2. ADDTHE -00 SUFFIX TO THE 200-6077- NUMBERON THE FAR SIDE OF-THE
C BOARO. RUBBERSTAMP OR LABLE METEDDSARE ACCEPTABLE.
Q5I4,0521,0519 --
al
n c R542 3. 088-0831-00, 088-0830-01, 5501, AND 200-0076-00 MUST BE INSTALLED
. . . . . . . .
9 -
+ 1 1 n
AFTER POST COATING. ANY OVERSPRAYCONTAMINATIONWILL DESTROYTHE
- l50·ooo3-IO
1607 1502
| ;
Igu
LSu T¯¯
SWITCHING CHARACTERISTICS OF ALL SWITCHES.
4, INSERT S501 INTO BOARDUNTIL THE SWITCH BODYBOTTOMSOUT ON BOARD,
S C 14 6 / TO ASSURE PERFECT ALIGNMFNT. SOLDER THE TWOOUTSIDE TERMINALSFIRST
a A s = • ^ ^ n TO PREVENT DAMAGINGTHE-SWITCH CONTACTS. SNAP 088-0830-01 INTD
E , ^
* 088-0831-00 BEFORE HEAT STAKING 088-0831-00 INTO THE BOARO. THE
/
-
0511,05lS,0518 4.
IBt3 Y ROSS 083 0 HUST BE FLUSH WITH THE PC BOAROAND 088-0830-01
Isol + ,
Isos/
1509003 C 40 5. BEFORE SOLDERING 200-6076-00 TO THE RIGHT ANGLEHEADER, 030-2323-09,

10 .
ECB
nn .
. . THE BDARDSMUST BE FIXTURED TO GUARANTEEALIGNMENTIN THE CHASSIS,
e c 6. APPLY ADHESIVE, 016-1082-00. UNDERY501. USING CARE NOT TO

10 CDNTAMINATEC503.
E
4626
"" -
7. CLIP LEAO 10 FROMU502 BEFORE INSTALLING ON PC BOARD. U502
0509,Q5l3,05IO,0516 LGO4 4507 (015-0041-01) IS ONLY USED WITH ANODEDAIVER, 1514, 120-3083-00.
B U502 IS DMITTEDWHENANDDEDRIVER, I514, 120-0095-00 IS USED.
c 8. THE SOCKETS, 033-0057-20, FOR I501 MUST BE INSERTEO FOA MAXIMUM
026-OOO2-OC en
C610 C6 C61 ct,ti PC.BOARD ENGAGEMENT. THESE LEADS CANNOT BE TRIMMEŒ.
9 I Fsop FeoC F503, R542,030-23tG-00, ARE TO BE INSTALLED
es SEE NOTE"9"
noe pa4 030-2316-00
E214
0
E2
7 13
009-6077-0[- -- 1506 J
089-240 002 /
SEE NOTE"B" SEENOTE"6" IO26-C302-C [M 03 -2323-09
089-5436-04(2
(3 PLC S) L C- USED TO 31CUSE W RE)
200-6076-00
SEE NOTE385)
11.000
IPR KCHARART 500
FROM TO DESC ON NO. LI NGTH E520
E510 ESII 22 BLACK 025-0003-00 II.500 E5 5

E 3 E C
E214 E5l2 26 RED 025-0018-22 II,000 '-
E518
E514 E215 26 RED/WHITE 025-0018-29 JO.750 [5C-0049 0 0 025 50\3-02

to' 050\ THRU 0504, 0506 wiRE SOLDERED TO
ES\3 E215 26 RED/WENTE 025-0018-29 2.250 SHIELD.
I50-0072-CO(0
E520 E517 28 BLACK
DETAIL "A'
ES2I E516 28 WHITE SEE DETAIL"A"
E519 E5\.5 28 RED
SHIELEESIS 26 GREEN 025-0018-55 1.000

(Dwg. No. 300-6077-00, R-13)
Rev. 1, August 1981

MMOO40-9 Page 6-41
KING
KN 53
NAVIGATION RECEIVER
NOTES:
150-0093 10 1. PRIOR TO POST COATING 631N LICES Œ ASSY RITH CLEAR URETHANECOATING
(2PLCM (016 1040-00), MASKOFF Ti€ FC LEWII 030-2323-09,
,¾2•,
CSO3,
R546 ALL BIEURCATEO TERMINALS (008-0038-01), ALL MOUNTINGSURFACES*,
SEE
NOTE"7e / ALL AREAS IMIGE Œ DíSAD LINES*, SOCIETS (033-0057-20) FOR 1501.
/ E515 TO ESzl'. PIQ1'. PS:2-, P303*, P304*, FCO*'_ P101". P102•.
SEE NOTE"g" / PlD3*, P4Oi",RS26,AND L36.
033 SEEOSNO 21 088-0830 *OENOTES THAT MASKINGIS REQUIRED ON BOTH SIDES OF 80ARO.
01
088-0831-00,
\ SEE NOTES384) 2. A TR I
T
SJFix2U-6D77-
10 NUMBERON THE FAR SIDE OF THE
EGANO. ELMîR ST.'.W
Œ LM.E METFOD5ARE ACCEPTABLE.
1 088-0831-00, 088-0830-01, 5501, AND 200-6075-00 MUST BE INSTALLED
-
Hy RS42 3.
AFTER POST COATING. ANY OVERSPRAYCONTAMINATIONWILL OESTROYTHE
Iro CE 5 SWITCHING CHARACTERISTICS OF ALL SWITCHES.
1602
-.a
15 . I 4. INSERT S501 INTO BOARD TIL THE SWITCH BODYBOTTOMSQUT ON BOARD,

.
.
.4 6654 1 2 TO ASEURE PERFECT ALICUMNT, SQLDER THE TWODUTSIDE TERMINALSFIRST

A " 9
SI
TO PREVENT DAMAGING M Laffc4 CONTACTS. SNAP 088-0830-01
Cf6 0,51-00 BEFORE >€nf STMI'O
INTO
CA Uf31-OO INTO THE 6.3ARO. THE
1514 088-0831-00
L 9 0 Ft.t a alTN THE PC 80ARO AND D88-DB30-01
Is \ l + 1403 05 ORK SMOOTHLY.
5. E SOLDERING 200-6D76-DO TD THE RIGHT ANGLEHEADER, 030 7523-03,

40 M F. ARDS MUST BE FIXTURED TO GUARANTEEALIGNMENTIN THE E145513
9 IC Oi
6. rif ADHESIVE, 016 109 O UNOER Y501. USING CARE NOT TO
C4 c
O . .
%'TWINATEC503
8626 7. IP LEAD 10 2 i ET RE INSTALLING ON PC ET.23
FRCV UTO2
D15 f 341-01) I C%J L-_EDRITH ANODEDRIVER, 1514, 120-?]¾ U.
0.02 15 OMITTED w€N -WCi ORIVER, I5l4, 120-006 O 15 U:ED
026-0002-00 - 8. THE SOCKETS, 035 DDoreo. POR I501 MUST BE INSURED 53 4D THEY
RUD XIMLNEROM THE FARSIDEBOARO SL41 4 E LEADS
Coc
9. I50I F501. F502, FSC3, R542,030-23f6-OO, ARE TO BE INSTALLED

L ,
AFTER POST COATING.
04 SEE NOTE"9"
030~2316-00
J 532
509
I5 ls
CS
( 503
15 7 1521 52 15
009-6077 -O
089 2140-00(2
SEE NOTE"9 SEE NOTE"6 6026-OOO2-DO(S) 03 2323-09
089-5436-04(2
(3 PLC S) L OP USD TO SECURE WIRE)
200-6076-00
(SEE NOTE385
ii.5OD
WIR)NG CHART oc oo
FROM TO DESCR\PTlON K1NG PART NO. LENGTH ES20
6
ES2l
ESIO E5H 22 BLACK 025-0003-00 11.500 ESIS
E C E5f9
E214 E512 26 RED 025-0018-22 11.000 ESIS
16
E5f4 E2l5 26 RED/WHITE 025-0018-29 10.750 150-OO49-lO(2) 025 5013-02
0501 THRU 0505 iRE SOLDERED TO
E513 E2\5 26 RED/WhilTE 025-0018-29 2.250 SHIELD,
ES20 E5fT 28 BLACK

DETA1L "A"
E521 E516 28 WHlTE SEE DETAIL"A"
E519 ESIS 28 RED

SH1E ESI8 26 GREEN 025-0018-55 1.000

(Dwg. No. 300-6077-00, R-1)
MMOO40-9 Page 6-41

KING
KN 53
NAVIGATION RECEIVER
NOTES:
50-0003-10
/ 1. PRIOR TO POST COATING BOTH SIDES OF LSSY AITH CLEAR UFESL','I COATING
(2PLCS) 016 10 x]). K'SK OFF THE FOLLOW18. -'42*.
030-2325-03. C'.03,
. -,L
Nilt
I ,TED TERMINALS (002-0]¾
GF DASEEDLINES TYL
01). ALL MOUN116-, VRFACES*,
(853-0057-2¾ FC4 16.-'31,
t NOTE"7" L ss
.15 10 t' 1 M31 .

P302*, P303", PIC
, ,
POJ5*, PlOl", PlD26, AND
SEE NOTE "9" PIDI
33-Ce O (2)-
_0830 C OENOTES THAT MASKING IS REQUIREDON BOTH SIDES, OF BOARO.
O
- 088-0851-00
SEE NOTES364) 2 Y' Ut. 01 5. EIx 10 3+ ;.(3-6077- NUMBERON THE FAR SIOE OF THE
ARELMETHODSARE ACCEPTABLE.
o, F501 FSO _RS42 C-9 1 1, :AD G CJ76-00
MUST BE INSTALLED
3 SI
I NE rk. 4:-/ CEN¾v:NATION WILL DESTROY THE
E51
C 1 CM ALL SWITCHES.
4 U.I L THE thITCH E av äri l OUT ON BOARO,
rECT ._DER THE 7w.1 CJTLIL- TLhuTFs&LSFIRST
-HCONTACTS. SVP C DWl-01 17.TO
088-0831-00 lNTO 7HE 80AHO. THE
B WITH THE PC BOARDAND 088-0830-01
502 T .
U THE RIGHT ANGLE 1- -TTR. 050-2323-09,
5 -
JARANTEEALIG ST IN W CHASSIS.
1NG
5 PLA EDB 3XSTR

r A'( ON L J 2 -
7 C 05 0 1]In ANODE DRIVER, IMA, L 0 083-00.

L lEO M e diCR, I514, 120-L Do IS USEO, .
CR
8 05 3. KU RD1 MUST BE INSERTED FOR MAXIMUM
026-0002-0 L --
FC BCARD EhiAGE.YLNT THLSL LEADS CANNCT BE TRIMMED.
FSO9 9 I5 FSOOl, FCSCOA2,

FSO3, RS42,030-2316-OO, ARE TO BE INSTALLED
150e
504
25
_E NOTE"9'
P 05 _23|6-00
15
MIS)
KY 5 0:(ii)-------- - E 2
E513
009-6077-01-
1. --
089-2140-0
SEENOTE"9" SEENOTE"6 026 02-00(5) 030-2323-09-
089-5436-04
(3 PLCS) (LOOP USE TO SECURE W RE
200-6076-00
SEE NOTE385)
----- Rooo -
WIRING CHART soa - 50
E57
FROM TO DESCRIPTION KING PART NO. LENGTH
E521 -- - __ EE55l65
E510 E5ll
*22
BLACK 025-0003-00 IL500
E BE C E5l9
A26 O25-OOIS-22 -ESIB
E214 E5l2 RED 10.250
p0
E514 E2l5 26 RED/WHITE 025-0018-29 9.750 43' 150-0049-l0(0 025 50i3-02
i ni ute 0508 IRE SOLDERED TO
E513 E215 26 RED/WHITE 025-0018-29 l.750 SHIELD,
[50-0072-00 0)
E520 E5l7 28 BLACK C C
DETAIL"A
E52l E516 28 WHITE SEE DETAIL"A"
E519 E5l5 28 RED
SHIELCE5i8 26 GREEN 025-0018-55 l.OOO E E
Q506, Q5|O Q509, Q5II THRU Q5l5,
QSIS THRU QSf6 Q5lS THRU 0521

(Dwg. No. 300-6077-01, R-18)
Rev. 1, August 1981

MMOO40-9 Page 6-43
KING
KN 53
NAVIGATION RECEIVER
C NOTES:
.5-10-
150 C PRIOR TO POST CO^TTNGBOTH SIDES OF ASSY WITH CLEAR URETHANECOATING
1.
B (27103) (Dlt K40 .-O X & THE FDLLOhING: J532*, 030-2323-09, CSO3,
R546 i .
BíFL :-TED TE MINALS (008-0038-01), ALL MOUNTINGSURFACES"
E Q512,0520,0517 -SEE NOTE'7" ALL AREAS INSIOE OF OASHEOLINES*, SDCWTS (033-0057-20) FOR 1501,
/// E515 TO E521*, P3Dl' P3D2*, P303*, P3DA*, P305=, P101
,
P102*, AND
NOTE "9 / PlD3,*
E 033 0057- O (2) 088-0830-01 *OENOTES THAT MASKINGIS REQUIREO ON BOTH SIDES OF BOARD.
088-083|-00
SEE NOTES354) 2. AUD THE -Ol SUFFIX TO THE 200-6077- NUMBERON THE FAA SIDE OF THE
BOARD. RUBBERSTAMP DR LABLE METECDS-AREACCEPTABLE.
C
Q5l4,Q52l,O5l95 r.. . 8542 088-D83D-D1, S5D1, AND 200-6076-00
''' 088-0831-00, HUST BE INSTALLED
,rset
3.
AFTER POST COATING. ANY OVERSPRAY CONTAMINATIONWILL DESTROYTHE
15 SWITCHING CHARACTERISTICS OF ALL SWITCHES.
I50-OOO3-\0 535 0534 - 4. INSERT $501 INTO BDARDUNTIL THE SWITCH BODYBOTTOMSOUT ON BOARD,
TO ASSURE PERFECT ALIGNMENT SOLDER THE TWODUTSIDE TERMINALSFIRST
-
TO PREVENT DAMAGINGTHE. SWITCH CONTACTS. SNAP 088-0830-01 INTD
C OBS-OB31-OO BEFORE HEAT STAKIm 088-0831 00 INTO THE BOARD. THE
E Q5|l,Q5l5, +
BODYOF 088-0831-00 MUST BE FLUSH WITH THE PC BDARDAND 088-0830-01
Q5IB MUST WORK SMOOTHLY.
BEFORE SOLDERING 200-5075-00 TO THE RIGHT ANGLE HEADER, 030-2323-09,
.
C
5.
150-0003-10 ./ THE BOAROSMUST BE FIXTURED TO GUARANTEEALIGNMENT IN THE CHASSIS.
. GI ,
6. APPLY ADHESIVE, 016-1082-00, UNDERY501, USING CARE NOT TO
CONTAMINATEC503.
E Q509,Q513,Q510, 7. CLIP LEAD 10 FROM USO2 BEFORE INSTALLING ON PC BOARD, 1]EO2
(015-0041-01) IS ONLY USED WITH ANDDEDRIVER, I514, 120-3083-00.
05|6 |
U502 IS OMITTED WHENAbDOE ORIVER, I514, 120-0095-00 IS USED.
026 -0002 -00

-- 8, THE StlCKETS, 033-0057-20, FOR I501 MUST BE INSERTED FOR MAXIMUM
PC. BOARD ENGAGEMENT THESE LEADS CANNGT B€ TRIMM€D.
es
9. 150!, F501, F502,F503, R542,030-23\6-00, ARE TO BE INSTALL€D
LS 1 os
AFTER POST COATING.
0500
-SEE NOTE "9"

L
R520
LSI C 7
LSI C
P302
009-6077 - 01-
089-2140-00
SEE NOTE 9 SEE NOTE 6 CD 5) 030-2323-09
089-5436-04
(3PLCS) L ED JRE WIRE)
200-6076-00
(SEE NolE385)
--- -- I 000 - ----
WIRlNG CHART oo
FROM TO E520-
DESCRIPTION KING PART NO. LENGTH
025-0003--00
E521 -
E510 E5|[ 22 BLACK ll.500 ESIS
025-0018-22
E BE C . ESI9 --
E214 E512 26 RED ll.OOO E5IS
E514 E215 26 RED/WHITE 025-OOl8-29 IO.750 33

C B
0507 MRE SOLDERED TO
05OI THRU Q504, ..
E513 E215 26 RED/WHlTE 025-OOlB-29 2.250 SHJELD,

- --- ¡SO-CO72-OO(l)
E520 E5l7 28 BLACK
DETAIL "A"
E521 E516 28 WHlTE SEE DETAIL"A"
E5l9 E515 28 RED

SHIELEESIS 26 GREEN OÑ-00IS-55 l.000

(Dwg. No. 300-6077-01, R-12)
Rev. 1, August 1981

MMOO40-9 Page 6-43
KING
KN 53
NAVIGATION RECEIVER
FROM pg
330\ PIN \
NAV VOL *
NAV
ANTENN
IST R.E 2NDR.E R.E AMPL 3RD R.E 4TH R.E MIXER FILTER MPLAUD J301,PINT
J531 POI E
L Q30I
L300 Lœ30L4E
Q302 FL30l
IST LE
133002
2ND IF
Q303
DETECTOR
Q304 FILTER
NT
e
AUDIO
FI5LTCER
AUDIO
OUTPOU27 OUODÉ
CR306 CR30) L302 CR302 CR303 T30I T303 T304 0305 0306,3L7305 OUTPUT
C372,R363 T305
R.F AGC L,0. INJECTION IF AGC IDENT J301,PIN2
TUNING NAV VOL
COMMON
J302,PIN 14
R.FAGCAMPL * NAV VOL Hi
INTEGRATOR I.E AGC J302.PINil
03 a
,03]
AMPL * IDENT SW
Q3|l,R34I 0307,0308 J30I,PIN 5
C341,C342 R337,C333 * COMPOSITE
OUTPUT
RCVR DC REF
BUFFER
Q313 R 334
L309 R333
NAV NAV. CTR.
COUNTER
PHASE J304
, BUFFER
DETECTOR LOOP VCO Q3l4
FILTER G.S. INJECTION
J 30 3 i e CR305 L3tO
L306,C343 0312,C308 E319
C344,C345 C352
J305,PIN2
I.F. AGC
J305,PINI
e R.F. AGC
FIGURE 4-5 NAV RECEIVER BOARD BLOCK DIAGRAM

(Dwg. No. 696-7603-00, R-0)
MMOOO3
Page 4-11
-
o
--
con
RA
es e ..au m•œ os na reir
KN 53 DIGITAL BOARD SCHEMATIC
SBOOO7-56 KPN 600-1162-70 Page: 4 of 4
|
KING
KN 53
NAVIGATION RECEIVER
MAX BRIGHTNESS FREQUENCY 109.30 110.55 Bl BRIGHTNESS
2µs
MUX LOCK
+5V-
2µs
MUX RESET
5C
DIMMER OCK
+ISOV-
50ms U U U U U U U U \
ANODE I
+95V-
ANODE 5
ANODE 2
ANODE 6
ANODE 3 .
ANODE 7
ANODE4
ANODE8
A+5V -
CODED INPUT
CODED INPUT B
CODED INPUT C
CODED lNPUT D
INPUT h
INPUT i
950µs
80 ps
50ps
CURRENT
PROGARGAEMMlNG
SE7GOo
SUSTAINING
OION
SEG b
ZA ION VOLTA
SEGc
SEGd
SEGe
SEG f
SEG g
SEG h
SEG i
FIGURE 4-11 DISPLAY TIMING DIAGRAM

(Dwg. No. 696-7609-00, R-0)
Rev. 1, August 1981
MMOO40-7 Page 4-29
KING
KN 53
NAVIGATION RECEIVER
a a ab
b b f b b f b f
e9 h
de h e c e
ANODE ----->
l 2 3 4 5 6 7 8
FIGURE 4-10 PAIRINGS

Rev.1, August 1981 (Dwg. No. 696-7608-00, R-0)
MMOO40-7 Page 4-27
KING
KN 53
NAVIGATION RECEIVER
NOTES:
150 (2 0-7 l. PRIOR TO POST C TIN L I SIDTS C .WY WITH CLEAR ET EG-TNG
/ (016-1040-00) < LSE Tu-£ FF..tralt,3 >!T .2 f.0) C is. .i3
RT-:G ALL BIFUR TED L INALS [C t 01L -J.. 'A '1% NATE
SEE NOTE 7 -L :REAS INSIO C : O LI?.C .115 (033 E 07
t'.*
BE 4 :191. .)
EA', TO E521*, 3 2 JI ,
P101 F1C¿ AND , , ,
SEE NOTE'S Pib5

033-0E (2) -0830- *DENOTES THAT MASKINGIS REQUIRED ON BOTH SIDES OF BOARD.
088
088-083 00,
SEE NOTESSM) 2. ADO THE -01 SUFFIX TO THE 200-6077- MNBER ON THE FAR SIDE OF THE
ROARD. RUBBER STAMP OR LABLE METHJDS -'e CEPTABLE.
RS42 3. O i ¾ CJ Q 9-0830-01. $501, ANO 202 E075-00 MUST BE INSTALLED
I ER M 001NG. ANY OVERSPRAY CONTAMINATION WILL DE..* THE
I
LTERISTICS OF ALL SWITCHES.
LE 04 I 4 I . i INTO E I LSTIL THE SWITCH BODY BOTTOMSOUT ON BOARD,
10 : .wNT S EN TH Tr-D OUTSIDE TERMIK 5 I Øs'AT
TO P . I C.'v D E 5.1 D< Crin: Ta TNAP 088-0830-01 INTO
15i4
(Ub e ir c.y..ya. CM 31 60 INTO THE BOA 1:£
BEST E Jul r34,r r_. t ._.1-lMS PC 80ARO ANO L
-:
10 DI
5 ,FC ING 200-6076-00 TO THE RIGHT ANGLEHEADER, US 2321 L.L.

ST BE FIXTURED TO GUARANTEEALIGNMENT IN THF Mó51S
6. APPLY ADHESIVE, 016 1082-00. UNDER Y501, USING CARE NOT TO
CONTAMINATEC503.
- 7. CL10 LE : 1 02 BEFORE INSTALLuss Nr E wa L.
ct / 015 E. 1 01 C _Y USED WITH ANODE:C Ifla 120 3 $ 00.

ANDOEORIVER, I511. r;3 15 d.
026-0002 -OC
-, . 7-20. FOR 1501 MUST BED 17 TNEY
FROMTHE FARSIDF b ..E D LEADS
9, 2 3, R542,O30-23|6-OO, ARE TO BE INSTALLED

.' 1508 ,
SEE NOTE"9'
I sol 304
050-2316-00
J 532
O O
4 "'
,
1502
07
2
0 6 i i E 2|5
Ste
usi -
1517 15
009-6077 -Oi
089-2|40-OO
L-SEE NOTE"9" SEE N TE 6 020 002 OO 5) O3 -2323-09-
089-5436-04
(3 PLC S) LOC «Sin TO SECURE W RE)
200-6076 -OO
(SEE NOTE385
\[.500 -
WiRING CHART oo
FRCM TO DESCRIPTION KING PART NO. LENGTH E520
cd
ESIO E5|! 22 BLACK 025-0003-00 ||.500 ESI5
E C E519
E2\4 E5l2 26 RED 025-0018-22 ||.000 -•--ESIS
E5t4 E245 26 REDI HE O25-O 8-29 10.750 50-0049-IO(2 025-50|3-02

050 THRU Q505 RE SCLDERED TO
E5\3 E215 26 RED/WH TE 025-0018- 29 2.250 SHiELD.
ES2O E5l7 28 BLACK

DETAIL "A"
E52l E5t6 26 WH SEE DETAIL"A"
E519 ESIS 28 RED
SHJEL ESIS 26 GREEN 025-0018-55 f.OOO

(Dwg. No. 300-6077-01, R-1)
MMOO40-9 Page 6-43

Replace these iso-ooo
(2 PLC S
or
/
resistors
SEE NOTE"7
-SEE NOTE "9"
- .i(2),
88-0830 OI
OB8-OB3I-OO
(SEE NOTES384)
FSDI FSO2 6 Ploi i r I -RS42
253 0534
613 /
1814
515
HOLOil TUOniG (150-000390 4

2A4&)Oi TÔ P401
026-0002 -OO
C 505
I SEE NOTE"9"
ISO 4
21 40
1512
eeeeeeeeeeeeeeese as4 oso_29is_oo
d 552- --
L
E54
-RSI7 520 - -
c509
L52
c
so4 en 1522 1507
1502 E 214
15i
030-Ill7~OO(18)- --- -- CR56 C 3

OOS--OO38-Ol(II) E519 E 2|
dRSIS E5 3 PIO2
13
CO37 P 303 C 63
12
-
s -
a
E609
1519 I i CSO3 517
506
1517 1521 1520
I5D3
Y ) ISOS $@l0
009-6077 -OI 1808
089-2140-00(2
-SEE NOTE 9 i SEE NOTE 026-OOO2-00(S) 030-2323-09-
089-5436-O4(2
43PLCS (LOOP USED TOSECURE WIRE)
200-6076-00-
(SEE NOTE385)
FIGURE l
KN 53 Digital Board Parts Layout
590006-4E KPS 600-1162-40 Page: 3 of 5

JIO3
0103 +l90V
TIOl CRIO5 CRIO9 CRIIO
I 8
CIO7
Rll9 .I 3250V R2423 _ 22OK
- 5.6K --
Rll7
56 K CRIO4
JiO2
LIO! 3 ::RIl3 CR 06
F101 gy
I101 e5.6K 3
1-IN OUT-2 E-+ RI26 RII5
SW 2A lOO lOOK CIIO
4COI C 3 CIO3 I 2 14
A+ 22
2
04DC 13-0 CRIO7
-8-
+5V
2-
O
33K
RM C3 C 08
| K 20 -26V
CIO2
K -
CIO6 QO CII2
R 6437V
680pf
RIO2
2.49K RII2
i% gRIOI 5tK
- >2K
R 07 CIO
gRIO6
>lOOK
RI25
.05
2W
RESET
NOTES:
1. UNLESS NOTED, ALL. RESISTANCE VALUES ARE IN OHMS,QW,5%.
ALL CAPACITANCE VALUES ARE IN MICROFARADSlµfl.
3. VOLTAGE READlNGS TAKEN WITH 13.75 VDC SW.A+ [NPUT.
KN 53 POWER SUPPLY BOARD
SBOOO6-15 KPN 600-1162-20 PAGE: 5 of 5

KING
KN 53
NAVIGATION RECEIVER
YES SENSITIVITY YES SELECTIVITY

B ]" A GC GOOD?
GOOD? GOÓDP
NO NO NO
CHECK RF AGC CHECK DITHER

CHECK RF AGC CHECK DITHER CHECK LOWPASS
YES I5EONERATOR YES
ADJUSTMENT ADJUSTMENT
ADJUSTMENT IF FlLTER
(R4351 (R435)
NO NO
RF AGC VOLTAGE TP404 DOES TP405 CHECK VOLTAGES

CHECK DOES
CO R
CURLTRAEGE REK40 Q404 CMXEER QH403
1 CO TROELLAEDBY
PRESELECTOR
YES
VOLTAGECONTROL |
H
COLLECTOR Q405 ALIGNMENT I.E AMP GAIN? R402 SR403 Ÿ L405 8406
NO NO NO
IF AGC VOLTAGE CHECKRFAGC CHECKIFAMPS CHECK RFAMPS

CONTROLLED BY YES
VOLTAGE AT AMP Q410,411,412
COLLECTORQ405 1401 AND Q404 Q40]ANDQ402
CR402
NO
CHECKAGC AMPS
Q40BAND 0405

(Sheet 3 of 3)
KING
KN 53
NAVIGATION RECEIVER
32.5ms
c4
PRESELECTOR c405 c4io MIXER
-SEE [2 20
SEE NOTE "l O" NOTE "7 O + s IF 2nd fF DETECTOR
R409
R4002 R403 9V
C6 680K C 4
026-OOO2-OO(.500 LONG)
047-3547-00 2) 047-4538-01 (2)
R410 C459 R459
TP40I 008-0038-01(3) 39 0 20 R422
TP406 47K
NOTES: L402 L403 -R415 IF BANDPASS FILTER P/O
I. PRIOR TO POST COATING BOTH SIDES OF ASSEMBLY WITH CLEAR R411 -
47o SV COURSE .r4oi
URETHANE COATING (016-1040-00)

C 200 CS46202 C34204 WIDTH AD
--
-g
/ R443 44 MASK OFF THE FOLLOWING: c4oß c409
56K
.5V- 0406 Q4O7
R402
R401 41 R442 44 416 ALL MOUNTING AREAS, 4533, TP 401 THRU TP 407, J 401, R 425, R435, 68 se . R412 .
R425
5K
-
TP403
G.S'
R44I C445 E 407,E408, ALL COMPONENTS INSIDE FENCED AREAS, AND BOARD AREA : 2¾ C418 R462 C426 R423 6
C4II
.
3.6V AUDIO
403 440 C444 T401
UNDERNEATHSHIELDS 047-4752-01 & 047-4754-01 (FARSIDE). c413 0403 191 L5K L404 L405 L406 .05pf C42B
R4IS
R421
TP402
C432 IOKQ4
5
TOV CW yyy
D 64 2200 R417 IK
8.2K
.05µ
2. TRANSISTORS Q401,Q402,Q403,Q416,SEE DETAIL"A'I c i 0401

L4tO G2 D TP40 6mb 6mh ,.6V
SEE NOTE "9" C402 L409 3. TRANSISTORS 0413., Q414,04IS,Q4IS,SEE DETAIL"B" d533
- C4323 C416
C4062 C
5 O IV
433
CO5pf
T1
d533 ,,
c4o 57 Q 04 C431
R41 4. TRANSISTORS Q 404,0408 , Q 409, Q 412, Q 417, SEE DETAIL"C C427 C429 '3.36V 2.6V 2200 R 204
c44 46 C435
R461
-
5. TRANSISTORS Q 405,Q 406, O 407, Q 4lO, Q 41I , SEE DETAIL"D . IK R405 -IPI 2.2pf .02291 R419
I2K R 8 C461 50V 47K +C430
SEE NOTE "6" 6. CUT OFF PIN 3 FLUSH WITH CARRIER, FARSIDE. L401 33V
.
-
2o 47
R22
+
4
7. BOTTOM SHIELDS,FENCES & PARTITIONS, ARE TO BE SOLDERED EVERY L J
OSSNim.E LEADS UNDFERBOTTOM
.
DLS c
041 R427
P4 c4 2 c46B R4307 R428
C 449 0412 4
TP405 4 HIE R RF AGC AMP 0409
R 5 045
+ FROM OI2-Il34-00
SHACELDNSG & 012-1136-00 AND INSTALL INSIDE
R 2 R437 R434 795V 408
c4 R425 40039 47K
-6075- 10 N5S33AL NGO BEE FENHTEEND
THEN SOLDERED TO THE FENCE, PRIOR TO
C
TP404 RS435 R4032
Q411 410 TP404
R 424
405 0406 10. Q 401 SQ 402 MUST HAVE THE COATING AND MARKING BUFFED FROM THE
... .
G.S. VCO CONTROL *6>
TOP SURFACE.THEN CASE TOP MUST BE TINNED WITHALOW TEMP. IRON R436
047-4334-02 047-4546-01
TP402 WITH A HEATSINK CLAMPED TO THE BOTTOM OF THE TRANSISTOR. Î4401 +9V 15K AGC og v \4.28V
R43o
047-4547-01 I I 047-4548-01 POSITION TRANSISTORS AS SHOWN,SO THAT THE LEADS HOLD THE TOPOF CR401 R446 SET
I i / i i oo
__
IF AGC AMP
THE CASE FLUSH WITH THE BENT PARTITION TABS. THEN SOLDER. APPLY
-
_
047-4537-01
HEAT TO TABS ONLY TO MAKE SOLDER CONNECTION.
040 C42C44244
047-4539-01 C 43 C47 C2 f8
µ1 00 f .3vp-p
+gy 6 5V
415
3 25V 16V
0239 60765-10 REF OSµs
R
3564 010 C4 OV
0414 4
0 2 I -00
O2 3 -SPARE
DI
SEE NOTE"7" SEE NOTE"8" C39 SR2404 3. 4.18V R4257 4LB C O
J 401 R44 Sv 4444 R4752 C 03
47 R4
L409 4 7 I.3Vp-p 32.5ms
5 a+9V
057V
C
6C463 C R4 C4 R3454 TP407
B B B COUNTER INJECTION
Gi G2 1
Q415
I.55V
041 B
C E C E C E L RV R4
451 C
D 100 Is
S E407 GLlDESLOPE INJECTION LOOP MIXER COUNTER BUFFER
DETAIL "Ñ DETAIL"B" DETAIL"C" DETAIL"D" E408
OV ! - OV
NOTES .IV p-p 3.5V p-p
.08ps
I. UNLESS NOTED ALL RESISTANCE VALUES ARE IN OHMS,QW,5%

ALL CAPACITANCE VALUES ARE IN PICOFARADS(pfl.
2. NO SYMBOL= RF LEVEL DOES NOT MATTER.

× NO RF SIGNAL.
=
700µv RF SIGNAL.
RECEIVER FREQUENCY=332mHz.
FIGURE 6-6 GLIDESLOPE RECEIVER BOARD AND SCHEMATIC

(Dwg. No. 300-6075-00, R-10)
(Dwg. No. 002-6075-00, R-6)
Rev. 1, August 1981

MMOO40-9 Page 6-31
KING
KN 53
NAVIGATION RECEIVER
9V
NOTES:
R322 I. UNLESS NOTED,ALL RESISTANCE VALUES ARE IN OHMS,
8.96V 47 QW. 5% ALL CAPACITANCEVALUESARE IN PICOFARADS(pfl.
,
R S R317
10 2. DC VOLTAGE CONDITIONS. VOLTMETER WITH IOM INPUT
R323 + C329 FREQ -II2MHz
C326 BSIV gg 10uf INPUT LEVEL -ICOOuV
C325 882V
8.65V
.05uf
05uf 16V MOD.FREO -1000Hz at 30%
AUDIOCUTPUT 50mw + 5V
RF AMPLIFIER - - + I' 3°6 /I.asv m -NOSIGNAL
|st IF AMPLIFIER
_case
R314 / N 10uf
400V R304 858V R 5
MIXER s.sav 22 16 ç¡---i-- --ces
44
+SV CRYSTAL FIL E
R316
I30 2.7K
FL301 3 DETECTOR
NAV ANT 67
-- - C327
JS31 C I Ist POLE cas 2 POLE c 47 83028 rd POLE c i 4th POLE ce
la
C 4 L. a.36v
1.32 C319 -Lcs2: 3.65V 302
L30I 2.7 2.7 304
01 L303 02 os
V 06
P FI R
C363-L RS61 C303 I 330 C309 R306 C312 :R307 R313 CJ301 5.17V 2 IF AGC
I 56 IOK 56 56 10K 56 -
IOK SIK
COMPOSITE
"3°3
I RF AGC
C364 -L cao4- cais - -c
'°°°
T '°°° '°°° '°'
L F AGC 20MFC3TE
'4.12V R33362
C360 R347 CJ302 CJ303 CJao4 AUDO FILTER +sv
+ 9V 12 +9V 3.3uf 5|O . . . ME +SV 8.90V 4.45V
15V 92V I.76V R3227 R306K5
R353 8. IV R35I 829V R30502 R 6 R32KB
NC 8 R342 R
T 02 0307 R331
*_]_ 56 0306 0315
NC 9 LOOP FILTER C348 CISI
33o c
RF GC
+
cas4-- 685V
65 53064
NC 10
.92V
NC 13 R34K5 TP305 C3 309 311 1 22V
4.12V 07h 2.99V 0310 R329
4.12v CR304
C3423 RL48 C2347 R349 C348
0- 2.28V OOO5mh
43- L308
4 3 3
0.tuf 0.luf R303K
R3 2 C3 4. V
C350
I casos IDENT FILTER
VCO
IDENT II
NAV PHASE DETECTOR
NAVVOL. M 11
P/ J30I
NAV500 CilM DUTPUT
+9V *SV
PO JSCI 5.49V R357 5.29V C359

RCVR BUFFER 8366 d3 4
\ 220
\ 22
NAV COUNTER
NC 6 _Lesse
C354 330 L3IO
330 L3O9 C356 .33ub
- -C357
NC 4 TIONAL GL1DESLOPE CONNECTIONS
AUDIO AMPIFIER N R354
4.7K Q313
cass TP304 0314 GLIDESLOPE INJECTION
5 15V CO R3250 GND

E320
C339
330
3
NAV VOL. I 6
I302 583 COUNTER BUFFER
T305
(PINS 3,4,5,118
12 ALSO GROUNDED)
FIGURE 6-5 NAV RECEIVER BOARD SCHEMATIC

(Dwg. No. 002-5971-00, R-0)
MMOO40-9 Page 6-23

KING
KN 53
NAVIGATION RECIEVER
192V JIO3
ISIV
TIOI +190V
CRIO5 CRIO9 CRIl
091-0095-00 CIO7 CIO9 RI2

089-5436-08 -RII9 .I 2 RI23 _220K
091-0051-03 -5.6K 350V 2
NOTES: REFERENE CRIO4 192V

VOLTAGE 5.0v PELRy
R 125 C107
I. TRANSISTORS Q101 a Q103,SEE DETAIL "B". LIOl -:R113
SEE DETAIL"C"
- -
2 Flol 3 CRIO6
3 t
106 2. PRSS URNETHAONEHDAET
CLECAOR NOGF ouT-2
TOR 5.6KRI26
-
I ' l'
YW TH C RII5 PY
E- SCILLATOR
4 4. (016-1040-00), MASK OFF THE FOLLOWING: cioi clI3 i cio3 - IOOK CIlo
047-3142-01 Riol .I 102 RI22
e 102 -•--C T 101 Llo! ALL MOUNTING AREAS, J IOI , J 102, J103 , 450 3 4- 680
.47
-
D 2
, o 5 HEAT SINK FOR QIO2 , F IOI,AND FUSE CLIPS. 50V 63V C4704
13- 25V
I 102 QiOI CRIO7
--e
_ _
I.25V +5V
6 3. I 101, SEE DETAIL "A UO2 2 ---
CRiis
091-0286-02 e loi 25v DC
07
__
090-0349-00 CIII GND

R
RIO9 C
cil SIK 8.IV RESET C3RIO3 c os
5 4R 1
009-6074-00
R Qlo
RIGI
+ + 5.0 Y
O
030-2322-05 030-2322-01(2)
I I RI25 <2 58µs --
.05
089-2140-00
091-0156-00
OUT IN E ½ † C
Q 102 REF.
COM. B e .091-0286-02
REF. ÑË5ÏT
DETAIL A". DETAIL "B','
047-3142-01 REF.
I 009-6074-00 REF.
I
NOTES:
089-5436-05 1. UNLESS NOTED; ALL RESISTANCE VALUES ARE IN OHMS,QW,5%.
ALL CAPACITANCE VALUES ARE IN MICROFARADSfµf).
2. UNLESS NOTED, ALL VOLTAGES ARE ± 20%.
DETAIL"C" 3. VOLTAGE READINGS TAKEN WITH 13.75 VDC SW.A+ INPUT.
FIGURE 6-2 POWER SUPPLY ASSEMBLY& SCHEMATIC

(Dwg. No. 300-6074-00, R-3)
(Dwg. No. 002-6074-00, R-5)
Rev. 1, August 1981

MMOO40-11 Page 6-9
KING
KN 53
NAVIGATION RECEIVER
JIO3
QlO3 ig y
TIOI CRIO5 CRIO9 CRIIO
091-0095-00 C107 CIO9 RI

089-5436-08 RII9 .I 2 RI23 _220K
091-0051-03 - 5.6K 350v 2
Rii7
NOTES: 56K CRio4
I. TRANSISTORS Q iOl 8 QiO3,SEE DETAlL LjO) Rll3
SEE DETAIL"C" R 125 2 Clo7 FIOI CR
1101 5.6K
ARSS CLECAORURNETHAONEH
CS AETNOGF 1 ouT-2 m7 þ s 3
YW TH RII5
SW +
E
4 (016-1040-00), MASK OFF THE FOLLOWING: 2A
cloi cit3 cio3 cito
047-3142-0\ R101 / A+ I02 -+
680
102 T 101 ALL MOUNTING AREAS, J 10\ J 102, J 103
, 450 .47
3 -1
4- - 2
,
OATSSINI FDORQMILO2 F IOI,AND FUSE CL1PS. 50V 63R 4DC

-I Qloi
- -
, 2 13
6 3 2 -
091-0286-02 C 101 10-

CIIO -090-0349-00
8
32
009-6074-00
- R 2 -RIOM3
.i 47K -
CIO6 RI20
18
CII2
IIO2 I 680pf 6437V
RIO2
oi si
C I12
103
03 -
7 i
CIO5
C 112
030-2322-05- 030-2322-01(2) .IOOK
RI25
.05
2W
089-2140-00
09I-0156-00
OUT *† IN E - C
Q 102 REF.
COM. B - 09I-0286-02 REE RESET

2
DETAIL "A". DETAIL "B'.
047-3142-0\ REF.
009-6074-00 REF.
NOTES:
089- 5436-05
I. UNLESS NOTED, ALL RESISTANCE VALUES ARE IN OHMS, QW,5%.
ALL CAPACITANCEVALUES ARE IN MICROFARADS(µf)
DETAIL"C
3. VOLTAGE READINGS TAKEN WITH [3.75 VDC SW.A+ 1NPUT.
FIGURE 6-2 POWER SUPPLY ASSEMBLY AND SCHEMATIC

(Dwg. No. 300-6074-00, R-1)
(Dwg. No. 002-6074-00, R-1)
MMOO40-9 Page 6-9
KING
KN 53
NAVIGATION RECEIVER
88V
4VP-P
NOTES:
R322 l. UNLESS NOTED,ALL RESlSTANCE VALUES ARE IN OHMS,
R315 R317 8.96V 47 QW, 5% , ALL CAPACITANCEVALUESARE lN PICOFARADS(pfL
10
2. R3IO INSTALLED IN THIS POSITION WHEN Q302 IS KPN 007-0317-00.
R323 C329
C32 C326 gey 180 IOuf DC VOLTAGE CONDITIONS: VOLTMETER WITH IOM INPUT
- _
8 V
ose out B.82V 16V F UT-II2MHL
RF AMP R NO W
c3es Al 0305 I.83V F D FREQ 0500Hz at 3Œ/o
4.OOV R53 4 8.58v R 5 IF AMPLIFIER
49y
XER -- --
T3O4 R325--C330 -:R344 A -NOSlGNAL
CRYS AL FIL E
NAV ANT.
OL cao r DE O
E L
0303 304
C2 3 8 36V
L301 01 3
L303 2 L3 4 6
3 3
IV 6 J305
R3 I 3 368V
C3 3 C3 3- 301 AMPLIFIER
F 05506 06 C 2 4llV C375
IF Acc
0364 6 i RF AGC
3 4 C313-L R31I
COM SITE
C3IO C3IS
1000 1000 330 30K
30 ---
---- P/O J 301
C360 R347 4 12V R362 COME DITE
+9V 3uf c 2
12 i +gy SIC CJ303 CJ304 AUD ) FILTER +sv
C367 SET 690v
NCC sg 2OV RF AGC
R43% 82K R328 50K5
T 02
LOOP FILTER 0348
NC 10
06
5 330 4OSV-*CW _Lca24 316
RF AGC 4 av Toser + cass
NC 13 465V 4 f 5064
82
6 392V
4.l2V
C
C63 C3
05mb
R3500 R339 54 064V I llV
C350 342 C
5V 25V Q308
CR305 66
6 IDENT FILTER
J303
--
NAV PHASE DETECTOR
rT1
PNJ301
NAV500 OllM CUTPUT

PO J301
R357 529V C3259
RCVR BUFFER R356 549V
NC 6 566V 220
IO%,
\ 10% J304
C33358 NAV COUNTER
NC 4 C3504 L3IO
LSO9
AUDIO AMPIFlER orv \ 33ub - E C356
22 R358 "h C357
6 Div R354 4.7K
C33 47K OPTlONAL GLIDESLOPE CONNECTIONS
+\2V 3 4.7u TP304 Q313 3|
- C368 40 25V 9
C3 5 R359
Q314
R360
E319
GLIDESLOPE 1NJECT10N
NC 2 -05uf
25V R355
5 ISV
2.2 820 __ 100
3 GND
R330 14 - E320
NAV VOL. i I 1302 583 3
e
COUNTER BUFFER
c335 2
(PINS 3,4,5 li a C370

12 ALSO GROUNDED) - luf
FIGURE 6-5 NAV RECEIVER BOARD SCHEMATIC

(Dwg. No. 002-5971-00, R-5)
Rev. 1, August 1981

MMOO40-9 Page 6-23

Manual KN53 Pago

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KIN G.

REVISION 1 JULY, 1981

1.1 Introduction 1-1

1.4 Units and Accessories 1-3

1.5 Accessories Required but not Supplied 1-4

2.1 Generat Information 2-1

2.4 Post Installation Adjustments 2-3

2-1 Molex Information (3 Sheets) 2-5

3-1 KN 53 Control Functions 3-2

PAG_E REASON FOR CHANGE

TABLE OF CONTENTS UPDATED

1.3.1 KN 53 GENERAL INFORMATION

TSO CATEGORIES: NAV C40a DO-153

ENVIRONMENTALCATEGORIES: DO-160 /A1D1/A/PS/XXXXXXABABA

PHYSICAL DIMENSIONS: Width: 6.31 inches (16.0 cm)

POWER REQUIREMENTS: 11 to 33VDC input

DME CHANNELING: 5 wire 2 x 5 code MHz Lines

ILS ENABLE OUTPUT: Ground on ILS channets, open otherwise

Rev. 1, July 1981 Page 1-1

1.3.2 VOR/LOC CHARACTERISTICS (KPN 066-1067-00/01)

FREQUENCYDISPLAY: Gas discharge display of one active and one

FREQUENCYMEMORY: Frequency data stored with no standby power

SENSITIVITY: 2.0uV (hard) max. will provide a half-flag

SELECTIVITY: Typicat 6de at +17KHz, 80dB at +42KHz

SPURIOUS RESPONSES: Down at least 60dB

IDENT FILTERS: 15dB minimum tone rejection

AGC CHARACTERISTICS: From 5uV to 20,000uV (hard) audio output will

NAV OUTPUT: Adjustable O.35VRMS Loc, 0.5VRMS VOR output

AUDIO QUTPUT: 50mw a 500 ohms

NUMBEROF CHANNELS: 200 (50KHz spacing)

FREQUENCYRANGE: 108.00MHz to 117.95MHz

1.3.3 GLIDESLOPE CHARACTERISTICS (KPN 066-1067-00 onty)

NUMBEROF CHANNELS: 40 (150KHz spacing)

FREQUENCYRANGE: 329.15MHz to 335.00MHz

SELECTIVITY: 6dB max at +21KHz, 508 min. at +129KHz

SENSITIVITY: Typicatty 12uV (hard) for half flag 2Ouv

INDICATOR OUTPUT: No Load resistors or wiring changes are

Deviation: Three 1000 ohm Loads max

Flag: Three 1000 ohm Loads max

COURSE DEVIATION RESPONSE: 0.6 seconds maximum

Rev. 1, July 1981

CENTERING ACCURACY: Less than +10uA under aLL service conditions

DEFLECTION CHARACTERISTICS: A difference in depth of modulation of

B. King KN 53 without Glidestope (KPN 066-1067-01)

C. King KN 53 Installation Kit (KPN 050-1712-00) consists of:

PART NUMBER DESCRIPTION QUANTITY

030-1107-30 CONN PINS (30) 1

057-2193-03 DECAL, NAV 1 1

089-2353-01 CLIP NUTS 6-32 4

090-0019-07 RETAINING RING 2

030-0101-02 CONN ANT 2

D. KA 139 Diplexer (071-1185-00, Optional Accessories)

Rev. 1, JuLy 1981

B. GLidestope Antenna and Cables

C. 300 to 1000 ohm Headphones

D. VOR/LOC Converter and Indicator, GLidestope Indicator.

1. KN 53 (066-1067-01), KI 203 VOR/LOC Converter with VOR/LOC Indicator

2. KN 53 (066-1067-00), KI 204 VOR/LOC Converter with VOR/LOC/GS Indicator

3. KN 53 (066-1067-00), KN 72 VOR/LOC Converter, KI 206 VOR/LOC/GS Indicator