Skill Lab Report Group-B (HK)
Skill Lab Report Group-B (HK)
Submitted by,
Bachelor of Engineering in
Electronics and Communication Engineering
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2023-24
CONTENTS
INTRODUCTION
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INTRODUCTION
Phase-1 of the Second year Skill Lab was organized in the department between March 4th – 9th. In
the first day morning session Dr. Ravish Aradhya H V Prof. and Head address the students by
highlighting importance of skill lab followed by an expert talk on PCB materials and
Terminologies By Mr. Raghavendra Rao, Principal Engineer, Intel Technology India Pvt Ltd and
Mr. Shashidhar K R, Engineering Manager, Intel Technology India Pvt Ltd. From the afternoon
session onwards the topics were divided into Four components and were conducted in three
exclusive labs (Venues): Skill building through EasyEDA with Prototype Development and
Testing, Hands on using STM32F407VG MCU, Application development using Simulink and
CPU design using Logisim.
In every lab there were teaching faculty and technical staff to help the students to understand the
basic concepts. First elaborate theoretical concepts were discussed by the teaching faculty and then
technical staff were there to clear any doubts to realize these theoretical concepts into actual
realization.
On the last day, the student’s understanding was evaluated by the Quizzes in all the four domains.
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CHAPTER-I
Skill Building Through EasyEDA with Prototype
Development and Testing
2nd step involves setting the dimension of area of PCB in ‘mm’ and
implement a compact sized design. Upcoming process is wire
connection in top layer (Vcc) and bottom layer (Ground) for Through
Hole Connection (THC). Wire connection rearrangement has to be
done in order to avoid any intersection of wire within a layer, for this
auto-routing can also be deployed instead of manual operation.
3rd step involves the DRC (Design Rule Check) which confirms
whether the PCB design conforms to all the basic requirements and is
ready to be viewed in 2D and 3D along with the creation and
download of ‘Gerber file’ as ZIP format.
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CHAPTER-II
Hands on using STM32F407VG MCU
The board selected as target was ATMEL with ID: AT89C51ED2. Code
execution, code build and code debugging was deployed in order to
correct any errors or bugs.
Bit pattern of serial control (SCON) register of 8051 MCU and bit
pattern of timer mode control (TMOD) register of 8051 MCU was
introduced along with practice of questions based on the 8 bits, such as,
SM0, SM1, SM2, REN, TB8, RB8, TI, RI – SCON & GATE, C/T’,
M1, M0 (for Timer 0 & Timer 1) – TMOD.
Setting of stop time (=0.1 sec) was involved to view the graph
generated.
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CHAPTER-IV
CPU Design using Logisim
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