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Static Timing Analysis Part 2

The document discusses static timing analysis. It defines the clock as a periodic synchronization signal used as a time reference. It describes slew as the amount of time for a signal transition and accounts for rise and fall time uncertainty. It discusses different types of clocks including gated clocks, which reduce power by switching off clocks when values don't change, virtual clocks which have no source, and generated clocks.

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Soutik Dey
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55 views20 pages

Static Timing Analysis Part 2

The document discusses static timing analysis. It defines the clock as a periodic synchronization signal used as a time reference. It describes slew as the amount of time for a signal transition and accounts for rise and fall time uncertainty. It discusses different types of clocks including gated clocks, which reduce power by switching off clocks when values don't change, virtual clocks which have no source, and generated clocks.

Uploaded by

Soutik Dey
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Static Timing Analysis

Clock
The clock is a periodic synchronization signal used as a time reference for data
transfers in synchronous digital systems.

T(Clk Period)

Prepared by : Abinash Kumar Bharati


Static Timing Analysis
Slew
• Amount of time it takes for a signal transition to occur
• Accounts for uncertainty in Rise and fall times of the signal
• Slew rate is measured in volts/sec

Rise Time Fall Time


Prepared by : Abinash Kumar Bharati
Static Timing Analysis
Types of Clocks
• Gated Clock
Clock Gated Clock
• Virtual Clock
• Generated (Derived) Clock Clk_enb

Gated clock
• Clock gating reduces power consumption by switching off the clock to
flipflops when the value of those flipflops does not change.
• It is mainly used in Low Power Applications.
Prepared by : Abinash Kumar Bharati
Static Timing Analysis

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

Virtual clock
• Virtual clock has no sources.
• Not connected to any port or pin within the current design
• Mainly used to model the I/O timing specification
• Serves as a reference for input or output delays

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

100M 98M
Hz Hz

100 100
MHz MHz

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

Prepared by : Abinash Kumar Bharati


Static Timing Analysis

Prepared by : Abinash Kumar Bharati

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