Universiti

Malaysia
PAHANG
FACULTY OF COMPUTER SYSTEMS & SOFTWARE ENGINEERING
FINAL EXAMINATION

COURSE COMPUTER ARCHITECTURE &

ORGANIZATION

COURSE CODE BCN1043

LECTURER SYAFIQ FAUZI KAM[ARULZAMAN

MD SAIFUL AZAD
RAMDAN RAZALI
DATE 6 JANUARY 2019

DURATION 3 HOURS

SESSION/SEMESTER SESSION 2018/2019 SEMESTER I

PROGRAMME CODE BCS/BCN/BCG

INSTRUCTIONS TO CANDIDATE:
1. This question paper consists ofFIVE(5) questions. Answer ALL questions.
2. All answers to a new question should start on new page.
3. All the calculations and assumptions must be clearly stated.
4. Candidates are not allowed to bring any material other than those allowed by the
invigilator into the examination room.
5. The question should be answered in English

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

This examination paper consists of SIX(6) printed pages including the front page.
CONFIDENTIAL BCS/BCN/BCG/1819I/BCN1043

QUESTION 1 [20 MARKS]

**- *I * •

a) The following questions are based on the assembly language code below:
LOAD D
ADD E
DIV C
STORY
LOAD A
SUB B
DIV Y
STOR Y
i) Formulate the mathematical equation, which the above codes are based on.
(4 Marks)
ii) Convert the above equation into assembly language that utilizes two-address.
instruction.
(6 Marks)

b) The following questions are based on the equation below.

Y =(A+B)/(C -(D — E))

Construct the assembly language code for the above equation according to the type of
instructions below.

i) Three-address instruction

(4 Marks)

ii) One-address instruction

(6 Marks)

2
CONFIDENTIAL BCS/BCN/BCG/1819UBCN1043

QUESTION 2[20 MARKS]

a) Usually, two of the design choices in a cache arellie rOw'size and whether each row is
organized as a single block of data or as more than one block (2-way or 4-way set
associative). The goal ofa cache is to reduce overall memory access time. Suppose that we
are designing a cache and we have a choice between a direct-mapped cache where each
row has a single 64-byte blocks of data, and a 2-way set associative cache where each row
has two 32-byte blocks of data. In this circumstance, what would be your choice? Justify
your answer with adequate reasoning.
(4 Marks)

b) Explain the advantages and disadvantages of using a direct mapped cache instead of a 4-
way set associative cache(at least ONE(1)for each).

(3 Marks)

c) Assume you have a 2-way set associative cache, where words are 4 bytes, addresses are
assigned to the byte, each block holds 512 bytes, and there are 1024 blocks in the cache. If
you reference a 32-bit physical address — and the cache is initially empty — how many data
words could be brought into the cache with this reference?
(3 Marks)

d) If the physical address F A B 1 2 3 8 9(in hex)is supplied to the cache, in which set (i.e.,
set id)does the data would be placed(cache and other specifications are same as in Question
2.c)?
(5 Marks)

e) As we know that different processes have different multiprocessing requirements. Let us

consider that we have several processes with following specifications: i) all are unrelated
processes,ii) processes are related to each other and share common threads,and iii)threads
in different processes can be grouped together. Explain the multiprocessor scheduling
techniques that would be suitable for those cases.

(3 Marks)

f) Compare volatile and non-volatile memory with specific examples (at least ONE (I))(an
example for each memory type).

(2 Marks)

3
 CONFIDENTIAL BCS/BCN/BCG/1819I/BCN1043

QUESTION 3[20 MARKS]

a)Explain one function ofthe I/O module.

(2 Marks)

b)What are the common problems in using single bus what is the best solution nowadays?

,
1 -
(4 Marks),

c)What is interrupt and the use ofit? Explain the interrupt cycle with the help ofa flowchart.

(10 Marks)

d)When we have large blocks of data to be transferred, DMA is usually used. Why DMA is

recommended compared to Programmed and Interrupt-Driven I/O? Justify your answer.

(4 Marks)

4
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QUESTION 4[20 MARKS]

a) The computer com:ponents are listed as below. Draw the block diagrani and label properly
how these components are arranged to form a computer.
Arithmetic and Logic Unit
Status flags
Shifter
Complementor ct.41

Arithmetic and Boolean logic

Control unit
Registers
Control path
(5 Marks)

b)Figure 4.1 below shows one ofthe data flow cycles in a computer.

Address Data Control

bus bus bus
MBR ---- Memory buffer register
MAR = Memory address register
IR = Instruction register
PC = Program counter

Figure 4.1

)
i Name the type of data flow cycle shown in the figure.
ii) Explain the procedures during the cycle in (i), as an instruction is read from
memory.
(4 Marks)

c) Answer the following questions:

i) Write the definition ofpipelining

(2 Marks)
ii) One strategy ofpipelining is known as instruction prefetch orfetch overlap.
Explain the strategy and sketch the related figure to help your explanation.
(5 Marks)
iii) Write TWO (2)pipelining advantages and TWO(2) pipelining disadvantages.
(4 Marks)

5
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QUESTION 5[20 MARKS]

a) The CPU'time-Of a program is defined as the product of the CPU clock cycle and clock
cycle time. Explain how performance could be improved considering these two factors.
(2 Marks)

b) Suppose we have two implementations ofthe same instruction set architecture (ISA). For
some program, machine A has a clock cycle time of 10 ns. and a CPI of 2.0 and machine
B has a clock cycle time of20 ns. and a CPI of 1.2. Explain which machine is faster for this
program, and by how much.
(4 Marks)

c) Mr. A needs to run a simulation for his thesis and his supervisor wants him to run it for a
fixed problem size. Mr. A can make 90% of the program parallel, with 10% of it being
sequential.
i What speedup can Mr. A expect on 10 processors?
)
(4 Marks)

ii) What would be the maximum speed up on an infinite number of processors?

(2 Marks)

d) Two different compilers are being tested for a 500 MHz machine with three different
classes of instructions: Class A, Class B, and Class C, which require one, two, and three
cycles(respectively). Both compilers are used to produce code for a large piece ofsoftware.
The first compiler's code uses 5 billion Class A instructions, 1 billion Class B instructions,
and 1 billion Class C instructions. The second compiler's code uses 10 billion Class A
instructions, 1 billion Class B instructions,and 1 billion Class C instructions.Explain which
sequence will be faster according to MIPS and execution time.
(6 Marks)

e) Let us consider that as a person-in-charge, you are asked to suggest a specific computer
among several options. In this circumstance, explain what are the metrics you would
consider coming to your decision.

(2 Marks)

END OF-QUESTION PAPER