Chapter3: Gate-Level Minimization

Lecture2- Five-Variables Function Simplification using Map

Method, Product-of-Sum (POS)Simplification using Map Method
Engr. Arshad Nazir, Asst Prof
Dept of Electrical Engineering
SEECS
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 Objectives
• Functions Simplification in Sum-of-Products (SOP) using
Five-Variables Map
• Product of Sums Minimization
• Don’t Care Conditions
• NAND and NOR Implementations

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5-Variable Map Patterns

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5-Variable Map Patterns

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 5-Variable Map Patterns
• The number of adjacent squares that may be combined always represent a
number that is a power of 2 such as 1, 2, 4, 8, 16, and 32.
➢ One square represents one minterm with five literals.
➢ Two adjacent squares represents a term of four literals.
➢ Four adjacent squares represents a term of three literals.
➢ Eight adjacent squares represents a term of two literals.
➢ Sixteen adjacent squares represents a term of one literal.
➢ Thirty-two adjacent squares represents the entire map and produces a
function that is always equal to 1.
Note that the squares on map can be combined horizontally or
vertically but not diagonally since these differ by more than one
variable.

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 Minimization Example of 5-Variable Map
Example 3-7: Simplify the Boolean function
F(V,W,X,Y,Z) = ∑(0,2,4,6,9,13,21,23,25,29,31)

EE-223 Digital Logic Design Spring 2024

F = v′w′z′ + wy′z + vxz 7

Minimization Example of 5-Variable Map

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 Product of Sums Minimization
• By definition, all the squares in a map that are not marked
with a 1 represent the complement of the function.
➢ If we mark the empty squares with 0s and then
combine the zeros into valid adjacent squares, we
obtain a simplified expression of the complement of the
function i.e., F′
➢ The complement of F′ [as (F′)′ = F] by DeMorgan’s
theorem (by taking the dual and complementing each
literal, section 2-4), gives us the product of sums form

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 POS Minimization Example
xz yz

0
W′x 0 0 0 0 xy
0 0 0
0

12)

F′ = w′x + yz + xz + xy
F = (F′)′=(w′x + yz + xz + xy)′ = (w + x′)(y′ + z′)(x′ + z′)(x′ + y′)

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 Example 3-8
• F = S(0,1,2,5,8,9,10)
Simplify the function in
➢sum of products (SOP)
➢Product of sums (POS)
• Solution:
➢ The squares marked with 1’s represents
minterms and are combined to form
simplified function in sum of products
(SOP). F=B′D′+B′C′+A′C′D
➢ If the squares marked with 0’s are are
combined we obtain the simplified
complemented function F′=AB+CD+BD′
➢ Applying DeMorgan’s theorem we
obtain the simplified function in product
of sum form (POS) F=(A′+B′)(C′+D′)(B′+D)
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SOP and POS Gate Implementation
Two-level logic diagrams

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Listing Truth Table using SOP and POS

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 Working With Maxterms
• At times, we may be required to work with maxterms.
➢ The previous process actually worked with minterms. Remember that the
numbers used for minterms are the opposites of the numbers used for
maxterms:
o F(w, x, y, z) = ∑(0, 1, 2, 8, 9, 10, 11), uses minterms
o F(w, x, y, z) = π(3, 4, 5, 6, 7, 12, 13, 14, 15), uses maxterms
➢ If you are given minterms, fill in 1’s for the minterms and then fill the
remaining cells with 0’s
➢ If you are given maxterms, fill in 0’s for the maxterms and then fill the
remaining cells with 1’s
➢ For SOP simplification, solve the map for the 1’s
➢ For POS simplification, solve the map for the 0’s to get complemented
function. Taking the complement of this complemented function we obtain
function in POS form
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 Don’t Care Conditions
• So far, we have always assumed that all combinations of the
input values are necessary in our expressions.
• Sometimes there are unspecified combinations within a
function.
➢ For example, four bit binary coded decimal code has six
combinations that are not used.
• Functions that have unspecified outputs for some input
combinations are called incompletely specified functions.
➢ These are called don’t care conditions because in most
applications, we do not care what the specification of the
combination is and not concerned about the function output
for these combinations..

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 Indicating Don’t Care Conditions
• A don’t care condition cannot be specified with a 1 because it
would require the function to always be 1 for the combination.
• Likewise, a don’t care condition cannot be specified with a 0
because it would require the function to always be 0 for the
combination.
• To specify don’t care conditions in a map, we use the letter ‘x’ or
‘d’.
➢ When we choose adjacent squares to simplify the map, the
don’t care minterms can be assumed to be 0 or 1, whichever
leads to the simplest expression.

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 Simplification with Don’t Care Conditions
• Example 3.9: Simplify the Boolean function: F (w,x,y,z) = ∑ (1,3,5,9,13)+∑ (0,2,7)
m d

F1 = w′x′+y′z = ∑m(0, 1, 2, 3, 5, 9, 13)

F2 = w′z+y′z = ∑m(1, 3, 5, 7, 9, 13)
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 NAND and NOR Implementations
• Digital circuits are frequently constructed with NAND and NOR gates
rather than with AND and OR gates due to following reasons:-
➢ they are easier to fabricate with electronic components
➢ they are used in all IC digital logic families
• NAND and NOR gates are said to be universal gates because they can
perform all three basic functions namely AND, OR, and NOT
operations and hence any logic function can be implemented with
either all NAND or all NOR gates.
• Because of their use, rules have been developed that allow us to
convert Boolean functions using AND, OR and NOT into the
equivalent NAND and NOR logic diagrams.

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 NAND Circuits
• The NAND gate is a universal gate that can be used to construct
any gate, therefore being able to replace all AND and OR gates.

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 NAND Notation
• A convenient method for creating a NAND circuit is to obtain the
simplified Boolean function in terms of Boolean operators and
then convert the function to NAND logic.
• To facilitate the conversion to NAND logic we define equivalent
alternative symbols as shown below for NAND gate

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 Two-Level Implementations
• The implementation of Boolean functions with NAND gates
requires that the function be in sum of products form.
– F = AB + CD
• All three diagrams are equivalent

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 Two-Level Implementations
• F = AB+CD+E
• F = ((AB)' (CD)' E')' =AB+CD+E

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 Example 3-10
• Implement F(x,y,z)= S(1,2,3,4,5,7) with NAND gates

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 Two-Level NAND Rules
• Given a Boolean function, follow these rules to obtain the NAND
logic diagram:
➢ Simplify the function and express it in sum of products
➢ Draw a NAND gate for each product term of the expression
that has at least two literals. This is group of first level gates
➢ Draw a single gate using the AND-invert or the invert-OR
graphic symbol in the second level, with inputs coming from
outputs of first level gates
➢ A term with a single literal requires an inverter in the first
level, unless the single literal is already complemented

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 Multilevel NAND Circuits
• The general procedure for converting a multi-level AND-OR
diagram into an all-NAND diagram is as follows:
➢ Convert all AND gates to NAND gates with AND-invert
graphic symbols
➢ Convert all OR gates to NAND gates with invert-OR graphic
symbols
➢ Check all the bubbles in the diagram
o Every bubble that is not compensated by another along
the same line will require the insertion of an inverter or
complement the input literal

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Multilevel NAND Example

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Multilevel NAND Example

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 NOR Circuits
• The NOR operation is a dual of the NAND operation and
therefore all procedures and rules for NOR logic are the dual of
the corresponding procedures and rules for the NAND logic.

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 NOR Notation
• A convenient method for creating a NOR circuit is to obtain the
simplified Boolean function in terms of Boolean operators and
then convert the function to NOR logic.

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Two-Level NOR Implementations
• The implementation of Boolean functions with NOR gates
requires that the function be in product of sums form.
F = (A + B)(C + D)E

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Multilevel NOR Implementations

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The End

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