Memory Management –

Segmentation and Paging

Dr. Lawrence Cheung

Semester 2, 2023/2024
Introduction
• This chapter
− provides an overview of the Intel family of
microprocessors.
− presents the microprocessor as a programmable
device by first looking at
• (i) its internal programming model and then at
• (ii) how it addresses its memory space.

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Objectives
• Upon completion of this chapter, you will be
able to
− Describe how memory is accessed using real
mode memory-addressing techniques.
− Describe how memory is accessed using protected
mode memory-addressing techniques.
− Detail the operation of the memory paging
mechanism.

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Topics
• Memory Addressing – Real Mode
• Memory Addressing – Protected Mode
• Segmentation Mechanism
• Paging Mechanism

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Topics
• Memory Addressing – Real Mode
• Memory Addressing – Protected Mode
• Segmentation Mechanism
• Paging Mechanism

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Real Mode
• In real mode operation, it allows an Intel CPU
to address only the first 1M byte of memory
space (even the Pentium microprocessor).
• Real mode operation
− Is the default operation mode.
− Allows downward compatibility.

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Real Mode
− Default operation mode: In all cases, each of these
microprocessors begins operation in the real mode
by default whenever power is applied or the
microprocessor is reset.
− Downward compatibility: Real mode operation
allows application software written for the
8088/8086, which contain only 1M byte of memory,
to function in the 80286 and above without
changing the software.

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Real Mode
• The first 1M byte of memory is called either the
real memory or conventional memory system.

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Segments and Offsets
• A combination of a segment address and an
offset address access a memory location in the
real mode.
• The segment address, located within one of the
segment registers, defines the beginning
address of any 64K-byte memory segment.
• The offset address selects any location within
the 64K-byte memory segment.

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Segments and Offsets
• Example: Segment register = 1000H, Offset
register = F000H

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Segments and Offsets

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Topics
• Memory Addressing – Real Mode
• Memory Addressing – Protected Mode
• Segmentation Mechanism
• Paging Mechanism

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Protected Mode
• Protected mode memory addressing (80286
and above) allows access to data and programs
located above the first 1M byte of memory as
well as within the first 1M byte of memory.

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Protected Mode
• Protected mode memory addressing
Logical
Address

Logical
Address Different size!
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Topics
• Memory Addressing – Real Mode
• Memory Addressing – Protected Mode
• Segmentation Mechanism
• Paging Mechanism

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Segmentation Mechanism
• The segment register is interpreted differently
in different modes by the microprocessor to
access the memory segment.
• In real mode, there are four types of
segments: CS (Code Segment), DS (Data
Segment), ES (Extended Segment) and SS
(Stack Segment).

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Segmentation Mechanism
• In protected mode, the segment register
stores more information.

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Segmentation Mechanism
• RPL = Requested Privilege Level

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Segmentation Mechanism
• TI = Table Indicator
There are a number of descriptor
tables in the memory, but at a DT1
particular instant only 2 of them
are active.
DT2
Segment register
selecter TI RPL
Selector
13 bit 1 bitTI 2 bitRPL
13 bits 1 bit 2bits
DT3
Select either LDT or GDT (LDT)

descriptor 8191 DT7

Select one out of the descriptor 8190 (GDT)
8192 descriptors descriptor 8189
DT9 Memory
space
descriptor 2
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Segmentation Mechanism
• The descriptor describes the memory
segment's location, length, and access rights
of the segment of memory.
• There are two descriptor tables.
− Global descriptors contain segment definitions
that apply to all programs,
− Local descriptors are usually unique to an
application.

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Segmentation Mechanism
• Each descriptor table contains 8192
descriptors.

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Descriptors
• Each descriptor is 8 bytes in length.
• The base address portion of the descriptor
(Base) indicates the starting location of the
memory segment.
• The paragraph boundary limitation is removed
in protected mode.

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Descriptors
• The segment limit (Limit) contains the last
offset address found in a segment.
• Example: If a segment begins at memory
location F00000H and ends at location
F000FFH, the base address is F00000H and the
limit is FFH.

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Descriptors
• The 80286 accesses memory segments that
− are of size 1 to 64K bytes.
− begin at any location in its 16M bytes of memory.
• The 80386 and above access memory
segments that
− are of size 1 to 1M bytes or 4K to 4G bytes.
− begin at any location in its 4G bytes of memory .

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Descriptors
• The upper bound is determined by the
number of bits in the corresponding field.
• The value of the limit will be multiplied by 4K
bytes if the granularity bit (G bit) is set to be 1.

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Descriptors

Append FFF to the right

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Descriptors
• The AV bit, in the 80386 and above descriptor,
is used by some operating systems to indicate
that the segment is available (AV = 1) or not
(AV = 0).

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Descriptors
• The D bit indicates how the 80386 through
the Pentium Pro instructions access register
and memory data in the protected mode or
real mode.
− If D = 0, the instructions are 16-bit instructions
compatible with the 8086-80286 microprocessors,
else the instructions are 32-bit instructions.

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Descriptors
− The 32-bit instruction mode is only accessible in a
protected mode system such as Windows NT,
Windows 95, or OS/2.
− The access rights byte controls access to the
protected mode memory segment.

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Descriptors
• Access Rights

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 80286 system
Example

Selector TI RPL
13 bits 1 bit 2bits

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Program-Invisible Registers
• The global and local descriptor tables are
placed in the memory system.
• 80286 and above contain program-invisible
registers to access and specify the address of
these tables.

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Program-Invisible Registers
• The program invisible registers are not
directly addressed by software.
• These registers control the microprocessor
when operated in the protected mode.

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Program-Invisible Registers

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 TR: Task Register

Program-Invisible Registers IDTR: Interrupt Descriptor

Table Register

Segment register Memory

(CS/DS/ES/SS/FS/ space
GS/TR/LDTR)
selecter
selector TI RPL
Selector TI RPL
13 bit 1 bit 2 bit
13 bits 1 bit 2bits

LDT

Starting addr of LDT

point to the
segment
carrying the

Size of GDT
Select a LDT
selecter
selector descriptor in descriptor n
GDT
GDT
Define
the size Starting addr of GDT

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Program-Invisible Registers
• Each of the segment registers contains a
program-invisible portion used in the
protected mode.
• The program-invisible portion of the segment
register is loaded with the base address, limit,
and access rights each time the number in the
segment register is changed.

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Program-Invisible Registers
• This allows the microprocessor to access a
memory segment repeatedly without
referring back to the descriptor table for each
access (using a cache instead).
• The GDTR (global descriptor table register)
and IDTR (interrupt descriptor table register)
contain the base address of the descriptor
table and its limit.

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Program-Invisible Registers
• When protected mode operation is desired,
the address of the global descriptor table and
its limit are loaded into the GDTR.
• Before using protected mode, the interrupt
descriptor table and the IDTR must be
initialized.

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Program-Invisible Registers
• The location of the local descriptor table is
selected from the global descriptor table.
• One of the global descriptors is set up to
address the local descriptor table.
• To access the local descriptor table, the LDTR
is loaded with a selector, just as a segment
register is loaded with a selector.

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Program-Invisible Registers
• The task register (TR) holds a selector that
accesses a descriptor that defines a task.
− A task is most often a procedure or application
program.
− The descriptor in TR is stored in the global
descriptor table.
• Task switching allows multitasking systems to
switch from one task to another in a simple
and orderly fashion.
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Linear Address
• Logical address to linear address

Segment
registers:
CS, DS, ES, SS,
FS, GS, etc.

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Linear Address
• Logical address to linear address

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Topics
• Memory Addressing – Real Mode
• Memory Addressing – Protected Mode
• Segmentation Mechanism
• Paging Mechanism

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Paging Mechanism
• Paging performs linear to physical address
translation.
• Paging allows any program and data
relocatable (even more powerful than the
segment and offset addressing scheme.).

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Memory Paging
• The memory paging mechanism located
within the 80386 and above allows any
physical memory location to be assigned to
any linear address.
• The linear address is defined as the address
generated by a program.
• With the memory paging unit, the linear
address is invisibly translated into any physical
address.
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Paging Mechanism
• Linear address to physical address

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How Paging Works in Intel’s CPU
1. The memory space is divided into a number
of pages.
2. Each page is of size 4 Kbytes.
3. Any data/program is divided into pages of
size 4 Kbytes each and these pages are
individually loaded into the memory space.
4. Any data/program byte is associated with a
logical address.
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How Paging Works in Intel’s CPU
5. The dir:page info tells which page the
requested data is in.
6. The offset tells which byte in the specified
page is the requested data
A 32-bit linear address is divided
into 3 fields: dir, page and offset

dir page offset

10 bits 10 bits 12 bits

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How Paging Works in Intel’s CPU

Example: L. Addr = 00F23000H →

0000,0000,1111,0010,0011,0~0B →
Dir = 3H, page = 323H, offset = 0H
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Paging Registers
• The paging unit is controlled by the contents
of the microprocessor's control registers.

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Paging Registers

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Paging Registers
• The PG bit selects paging when it is set to be
1.
• The linear address, as it is generated by the
software, is broken into three sections that
are used to access the page directory entry,
page table entry, and page offset address.
• A page of memory contains 4K bytes of
memory.

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 The Page Directory and Page Table
• A page directory contains entries that locate
the starting addresses of up to 1024 page
tables.
• Each page table contains 1024 entries that
locate the starting addresses of 1024 pages.
page directory page table

4K bytes
::: :::
4K bytes
1K entries
: 4 bytes/entry :
Template format of a table entry

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The Page Directory and Page Table
• The page directory plus the page tables could
be a big storage overhead to the memory
system.
• Example: A paged memory system of 4G bytes
must allocate 4K bytes of memory for the
page directory and 4K x 1024 bytes for the
1024 page tables.

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The Page Directory and Page Table

pages
page tables

4K bytes
::: :::

4K bytes
Key data ::::
1 Table (P.D./P.T.) : : page directory

4K bytes
1K entries :
4 bytes/entry :::
:::
::: :::
4K bytes :::
: :::
::

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The Page Directory and Page Table
• Time overhead - Repaging a 4K byte section of
memory requires access to the page directory
and a page table, both located in memory.
• Intel has incorporated a cache called TLB
(translation look-aside buffer) to hold the
most recent page translation addresses to
speed up the translation.

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A More Detailed Example

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A More Detailed Example

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The Page Directory and Page Table
• Example: Suppose that the EMM386.exe
program allows access to 16M bytes of
extended and conventional memory through
paging, and locations C8000H-EFFFFH must be
repaged to locations 110000-138000H with all
other areas of memory paged to their normal
locations.

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A More Detailed Example

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The Full Picture

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End