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WWW - Manaresults.co - In: Vlsi Design

This document contains details about a supplementary examination for VLSI Design, including: 1) The exam contains 5 questions from 5 units, with each question worth 15 marks. Questions cover topics like MOSFET fabrication steps, encoding schemes, inverter delay calculation, scaling factors, MOSFET small-signal models, current sources/sinks, NAND/CMOS gate geometry, domino logic, flip-flops, LUTs/CLBs/IOBs in FPGAs, velocity saturation, and FinFETs. 2) Unit I questions cover MOSFET fabrication steps and enhancement vs depletion types. Unit II covers inverter delay calculation and cascaded inverter pair delay. Unit III covers

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34 views2 pages

WWW - Manaresults.co - In: Vlsi Design

This document contains details about a supplementary examination for VLSI Design, including: 1) The exam contains 5 questions from 5 units, with each question worth 15 marks. Questions cover topics like MOSFET fabrication steps, encoding schemes, inverter delay calculation, scaling factors, MOSFET small-signal models, current sources/sinks, NAND/CMOS gate geometry, domino logic, flip-flops, LUTs/CLBs/IOBs in FPGAs, velocity saturation, and FinFETs. 2) Unit I questions cover MOSFET fabrication steps and enhancement vs depletion types. Unit II covers inverter delay calculation and cascaded inverter pair delay. Unit III covers

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jagadeesh
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© © All Rights Reserved
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Code No: R1932042 R19 SET - 1

III B. Tech II Semester Supplementary Examinations, November-2022


VLSI DESIGN
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 75
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****
UNIT-I
1. a) Give the fabrication steps for single metal CMOS n-well process and additional [8M]
steps for bipolar devices.
b) What is the difference between enhancement-type and depletion-type [7M]
MOSFETs? Explain why the enhancement-type MOSFET is preferred?
(OR)
2. a) Tabulate the encoding scheme for a simple single metal nMOS process with [8M]
respect to various MOS layers.
b) Explain the terms figure-of-merit of MOSFET and output conductance using [7M]
necessary equations.
UNIT-II
3. a) What is inverter delay? How delay is calculated for multiple stages. [8M]
b) Two nMOS inverters are cascaded to drive a capacitive load C L =16Cg. [7M]
Calculate pair delay Vin to Vout in terms of τ.
(OR)
4. a) Why scaling is required? Write the scaling factors for different types of device [8M]
parameters.
b) Discuss the limits due to sub threshold currents. [7M]
UNIT-III
5. a) Draw the small-signal model for the MOS transistor. Briefly explain each [8M]
component in that.
b) Choose values of VGS = 1,2,3,4 and 5 V, assume that the channel modulation [7M]
parameter is zero. Sketch to scale the output characteristics of an enhancement
n-channel device if VT = 0.7 V and ID = 500 µA when VGS = 5 Vin saturation.
(OR)
6. a) Derive the voltage gain equation for common source amplifier at high [8M]
frequencies.
b) Write short notes on current sinks and sources? [7M]
UNIT-IV
7. a) In gate logic compare the geometry aspects between two input nMOS NAND [8M]
gate and CMOS NAND gate?
b) Draw the positive latch using transmission gates and explain the operation? [7M]
(OR)
8. a) Explain about Domino CMOS logic. Draw the Domino structure for AND and [8M]
OR gates?
b) Draw the schematic circuit of a SR flip flop with negative edge triggering [7M]
using NAND gates. Give its truth table and explain its operation?
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Code No: R1932042 R19 SET - 1

UNIT-V
9. a) Explain the following terms: [8M]
(i) LUT (ii) CLB (iii) IOB (iv) Switch matrix
b) List out the different FPGA families. Explain how they are differing. [7M]
(OR)
10. a) Briefly discuss about velocity saturation effects in a short channel Si- [8M]
MOSFET?
b) What is a FinFET? What are the differences between FinFET and a multi-gate [7M]
transistor?
*****

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