Thesis B Progress Report

by

Brent Kyle Mitchley

Student ID: z5167868

Thesis submitted as a requirement for the degree Bachelor of Engineering

(Electrical Engineering)

Submitted: March 29th, 2021

Supervisor: Dr David Tsai
Abbreviations

DC Direct Current
FIR Finite Impulse Response
FPGA Field Programmable Gate Array
HPF High Pass Filter
LFP Local Field Potential
LPF Low Pass Filter
PCA Principal Component Analysis

1
Contents

Abbreviations ............................................................................................................................................................... 1

1. Progress Update ....................................................................................................................................................... 3

1.1 Summary of Thesis A ........................................................................................................................................... 3
1.2 Thesis B Progress ................................................................................................................................................. 3
1.2.1 Signal Analysis............................................................................................................................................. 3
1.2.2 Filter Design ................................................................................................................................................ 4
1.2.3 Calculating the Spike Detection Threshold ................................................................................................. 6
1.2.4 Learning to Use Xilinx Software and Verilog............................................................................................... 7
1.2.5 MATLAB’s HDL Coder.................................................................................................................................. 7
1.2.6 Developing the Simulink Model.................................................................................................................. 7

2 Reflection .................................................................................................................................................................. 9

3 Revised Plan ............................................................................................................................................................ 10

Appendices ................................................................................................................................................................. 11
Appendix A – Block Diagram of Verilog Implementation of FIR Filter ............................................................................ 11
Appendix B – Simulink Model ......................................................................................................................................... 11

2
1. Progress Update
1.1 Summary of Thesis A
The aim of this thesis is to implement a real-time neural spike sorting algorithm on an FPGA and
determine the number of recording channels that can be processed simultaneously. During Thesis A,
time was spent learning about neural signals, the methods used to perform spike sorting over the past
20 years, and the difficulties of spike sorting. The knowledge gained in Thesis A was generated through
the literature review, meetings with my supervisor, Dr Tsai, and my preliminary work. The preliminary
work consisted of forming an understanding of PCA and data clustering methods and writing a non-
real-time implementation of spike sorting using PCA and k-means clustering in MATLAB.

1.2 Thesis B Progress

1.2.1 Signal Analysis

I began Thesis B by performing a more thorough analysis of neural data provided by Dr Tsai than I
had done in Thesis A. The neural data came from two sources (shown in Figure 1):
1. Approximately seven seconds of neural activity recorded from 32 channels. During this
recording, the brain is being stimulated by the eyes’ response to light. The first 1.2 – 1.5s are
ignored to avoid the large, non-biological, negative step at t = 0.
2. Approximately 30 seconds of neural activity recorded from 32 channels. During this recording,
there is no deliberate brain stimulation.

Figure 1: Examples of neural data from each source. Stimulated data on the left, unstimulated data on the right.

The stimulated neural data shows a large, slow varying deviation from 0 when compared to the
unstimulated data, possibly due to fluctuations in the LFP. When we examine the frequency spectrum

3
of each data source, we see that both data sets have large frequency content below 5Hz. In the
unstimulated data this difference is near 30dB whilst for the stimulated data it is 50dB, shown in Figure
2 below.

Figure 2: Normalised magnitude spectrums of each data source. Stimulated on the left, unstimulated on the right.

The existence of relatively large low frequency content was not surprising as it can be attributed to the
LFP or the occurrence of electrode drift. However, I was surprised by the existence of a significant
DC component. I discussed this with Dr Tsai, and it was attributed to voltage offsets in the analogue
front-end circuit.

1.2.2 Filter Design

After analysing the data, I started designing a filter for the spike sorting process. There are three factors
that have influenced my design choices:

1. Required passband:
Per the literature reviewed in Thesis A, the lower cut-off frequency can be 100-300Hz and the
upper cut-off frequency should be above 3kHz.

2. Computational cost:
Computational cost was considered in terms of the number of flip-flops required by a given
filter. I also considered the bit representation required for the filter output and the impact this
would have on the rest of the system. Based on the FIR filter design shown in Appendix A, if
the incoming data and filter are represented as 𝐵𝐵𝑜𝑜 -bit and 𝐵𝐵𝑓𝑓 -bit signed integers respectively,
and the filter has 𝑁𝑁 taps (the order of the filter) then the number of flip-flops required is given
by (1),

4
 𝐹𝐹𝐹𝐹 = (𝐵𝐵𝑜𝑜 + 𝐵𝐵𝑓𝑓 ) (𝑁𝑁 − 1) (1)
The neural data is assumed to be represented by 10-bit signed integer and I found that the filters
could be reasonably represented as 8-bit signed integers.

3. How the spike detection threshold is calculated:

A. Calculate the threshold using the first 𝑡𝑡 second window of the signal and hold it constant
throughout the experiment.
B. Periodically update the threshold value.
C. Using a multiple of the mean or the median for the threshold.

Based on the literature review in Thesis A, a median based threshold was reported to be better for spike
detection algorithms. However, the median is difficult to calculate, even in real-time, due to the need
to sort through a large amount of data. Hence, I wanted to be able to calculate the median once at the
beginning of the recording and hold it constant. For this method to be valid, the threshold value must
be relatively independent of the specific time window used. I decided that if the median value from
each window of the data varied by less than ±5% I would consider it to be constant or stable (limited
variation).

To ensure the median is stable, the large low frequency components discussed in Section 1.1.2 must
be removed from the signal. I found that to stabilise the median, these low frequencies needed to be
attenuated by at least 60dB. Achieving this required a bandpass filter with 243 taps. Using equation
(1), this filter requires 4356 flip-flops.

Since the greatest attenuation requirement falls on the lower frequencies, I considered a second
filtering approach, shown in Figure 3, to reduce the filter order.

Figure 3: Block diagram of filtering approach intended to reduce computational cost.

To achieve the required attenuation, a 25-tap LPF and 123-tap HPF were required. Using (1) we can
calculate the cost of using a LPF followed by an HPF; 3604 flip-flops, a reduction by 752. However,
a problem with using two filters is that it requires two instances of multiplying by 8-bit numbers.

5
Hence, to represent the output of the whole filtering stage, we would need 26 bits rather than 18. This
greatly increases the computational cost of all later stages of the algorithm.

I concluded that the cost of a filter that provides enough attenuation for a stable the median is too high
and adopted an approach where the threshold is updated periodically. The low frequency attenuation
was relaxed to 40dB at 0Hz, and a 103-tap bandpass filter was chosen. The cost of this filter is 1836
flip-flops. Its magnitude response (not normalised) is shown in Figure 4.

Figure 4: Magnitude response of the integer based bandpass filter. Note that the normalised frequency corresponds to 10kHz.

1.2.3 Calculating the Spike Detection Threshold

As discussed in Section 1.2.2, the threshold value must be updated periodically. I spent roughly 2
weeks, in parallel with other tasks, trying to develop an algorithm to calculate the median efficiently.
Eventually a mean-based threshold was adopted because it is significantly easier to calculate on an
FPGA. Mean-based thresholds have been used effectively for spike sorting. I performed my own
comparison to support these findings. Figure 7 shows the median and mean-based thresholds differ by
less than 5% over all but the first window.

Figure 5: Comparison of mean and median based thresholds calculated using 0.5s windows.

6
1.2.4 Learning to Use Xilinx Software and Verilog
I spent a little over one week getting familiar with Xilinx’s Vivado software and writing code in
Verilog. I started by writing a simple counter. I then designed and coded a 4-tap FIR filter in Verilog
and verified its output. The design of this filter is shown in Appendix A and can be easily extended.
Writing an FIR filter in Verilog improved my understanding of the computational cost of filtering and
helped me realise equation (1) in Section 1.2.2.

1.2.5 MATLAB’s HDL Coder

During Thesis A I learned that Simulink models and MATLAB scripts can be converted to fixed-point
HDL (Verilog or VHDL) via MATLAB’s HDL Coder tool. I wanted to use these tools to expedite my
progress and because they provide a way to verify Verilog code easily. I started to learn how to use
these tools by following tutorials found on the MathWorks website. Unfortunately, the Verilog code
generated by the HDL Coder is not easy to read or understand and using the tool also makes it more
difficult for me to directly optimise the code. Therefore, it is better if I write the Verilog code myself,
even if my initial progress is slower due to me learning to write complex code in Verilog. I will not be
using MATLAB’s HDL Coder as originally planned.

1.2.6 Developing the Simulink Model

As set out in Thesis A, the first goal of this Thesis is to develop a Simulink model of the spike sorting
algorithm which can be used to verify the Verilog implementation. Currently, the Simulink model
includes filtering, spike detection and spike capturing. The model is shown in Appendix B and a
description is provided here.

Filtering is done using the 103-tap filter discussed in Section 1.2.2. The signal is then down sampled
by two so that the effective sampling rate is 10kHz. Action potential spikes are typically 2ms long and
each sample is 0.1ms apart, so the data is passed through 21 memory blocks (modelling flip-flops).
This means we always have a window of the last 21 samples available. Let these 21 samples be 𝑥𝑥1 to
𝑥𝑥21 , where 𝑥𝑥1 is the most recent sample. When a spike is detected, these samples are stored.

When storing the spikes, it is important that the peak of each spike occurs at the same sample in its
corresponding window. In Thesis A, I found that the start and end of the spikes were 0.5ms before and
1.5ms after the peak, respectively. At 10kHz, this is 5 and 15 samples. Therefore, the spike will be
stored when the peak is at 𝑥𝑥6 .

7
To store or capture the spikes we must first determine that the threshold has been crossed and that the
peak of the spike is at 𝑥𝑥6 . The Simulink models for threshold comparison and peak detection are shown
in Figures 6 and 7. The outputs of these two systems are put through an AND gate.

Figure 6: Threshold comparison system. The output is 1 if the threshold is crossed and 0 otherwise.

Figure 7: Peak detection system. Output is 1 if a peak is found and 0 otherwise.

I have tested the system using one of the stimulated data channels and it captured 409 spikes, a subset
of which are shown in Figure 8. This is a promising result, since it is similar to the number that were
captured by the offline method that I implemented in Thesis A.

Figure 8: Subset of the spikes captured by the Simulink model.

8
2 Reflection
In the past term-and-a-half, I have learnt a lot about processing neural signals, the difficulties of
managing a long-term project, and how I can improve my approach in the future. I have found the
work challenging, enjoyable and at times frustrating and stressful.

Working on a thesis has been very different to my previous experience at university and in industry,
where projects are at most 8-10 weeks long. A thesis is a significantly longer project, and therefore I
have found it more difficult to accurately plan and predict how quickly I will be able to complete tasks
than I have in shorter projects. A second point of difference is that in other university courses and in
industry you can discuss ideas to solve challenging problems with peers and colleagues, whereas this
is very much an individual project. I have enjoyed working on this project, but I have also realised
how much I value working with others.

One of the things I have learnt about myself is that I tend to overthink problems and spend hours trying
to come up with the ‘best’ solution. Though there are beneficial consequences to taking your time, and
not rushing things, I have been a bit extreme. I would estimate that over the course of Thesis B my
progress has been slowed by a week due to this. Although I will not be cavalier going forward, I think
there is some benefit to me implementing an adequate method and then thinking about the ‘best’
solution later. This will give me a sense of progress and will help keep me motivated during the
remainder of Thesis B and in Thesis C.

Something that has frustrated me is that I feel like I have spent more time ‘learning’ rather than ‘doing’.
This causes me to feel like I am not making enough progress. For example, I spent a whole week
learning to use Xilinx software and to write my first piece of Verilog code. Only then could I turn to
designing a filter in Verilog. Further, I have found that online tutorials and forums written for Verilog
are less helpful than those written for other languages that I have learnt during university.

As I get further into the project, and more into the ‘doing’ phase of it I am enjoying it more. I also have
a better grasp of what I can expect to accomplish each week and anticipate that I will be more
productive in the future as I improve upon the issue of overthinking.

9
3 Revised Plan
As mentioned in the reflection, I estimate that I lost about a week due to me spending too long trying
to arrive at the ‘best’ solution. I also misjudged how long tasks would take me when I created my
original plan. For both these reasons, I am not exactly where I had planned to be at this point in Thesis
B. The Gantt chart in Figure 9 show the work to be done in the remaining time. I have been more
conservative in my estimates of how long tasks will take, which I hope will account for unforseen
difficulties.

Completion Term 1 2021 Term 2 2021

Tasks Weeks
(%) 7 8 9 10 1 2 3 4 5 6 7 8 9 10
Complete Simulink implementation 4 15
Implement the FIR filter in Verilog 1 50
Implement spike detection and capture in Verilog 1 0
Implement principal component analysis in Verilog 2 0
Thesis B Executive Summary 1 0
Review of Expected Outcomes 1 0
Implement data clustering in verilog 2 0
Synthesise the spike sorting process in Verilog 2 0
Verification: Compare Simulink and FPGA implementations 1 0
Assess the scalability of the implementation 1 0
Optimise and extend the implementation 4 0
Final Poster 3 0
Final Report 3 0

Figure 9: Gantt chart showing the work to be done in the remaining time.

10
Appendices
Appendix A – Block Diagram of Verilog Implementation of FIR Filter
The variable 𝑥𝑥𝑖𝑖𝑖𝑖 is updated each clock cycle, and ℎ[𝑛𝑛] represents the nth tap of the filter h.

Appendix B – Simulink Model

11