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DLD 05 Decoders

This document provides instructions for implementing a 3-to-8 line decoder using non-hierarchical gates, hierarchical gates, and 2-to-4 line decoders. It describes using a 74139 dual 2-to-4 decoder integrated circuit and connecting it to create a 3-to-8 line decoder. It also describes implementing combinational logic functions using decoders and basic gates, and discusses how to handle the fact that Logisim decoders are active-low rather than active-high.

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18 views8 pages

DLD 05 Decoders

This document provides instructions for implementing a 3-to-8 line decoder using non-hierarchical gates, hierarchical gates, and 2-to-4 line decoders. It describes using a 74139 dual 2-to-4 decoder integrated circuit and connecting it to create a 3-to-8 line decoder. It also describes implementing combinational logic functions using decoders and basic gates, and discusses how to handle the fact that Logisim decoders are active-low rather than active-high.

Uploaded by

zunaedz110
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Objective (skip grayed colored ones)

1. Definition: Study decoders


2. Implementation: Implement 3-to-8 line
decoder using
a) Non-hierarchical - Basic gates, AND gate with more inputs
b) Hierarchical - Decoder and two-input AND gates
c) 2-to-4 line decoders with enable
3. Application: Implement combinational
circuits (functions) using decoder and basic
gates
F = M1 . M3 . M6 . M7

13-Nov-21 CSE 226: Digital Logic Design Lab 2


What To Do (2) (skip grayed colored ones)
2. Implement a 3-to-8 line decoder using
a) Non-hierarchical - Basic gates, AND gate with more inputs
b) Hierarchical - Decoder and two-input AND gates - LS
c) 2-to-4 line decoders with enable (see below) - Both

13-Nov-21 CSE 226: Digital Logic Design Lab 3


IC: 74139 dual 2-to-4 Decoder

13-Nov-21 CSE 226: Digital Logic Design Lab 4


Functional/Pin Diagram

13-Nov-21 CSE 226: Digital Logic Design Lab 5


Implement a 3-to-8 line Decoder
• Following that pattern complete this connection using
74139, note the pin numbers

13-Nov-21 CSE 226: Digital Logic Design Lab 6


What To Do (3)

3. Application: Implement combinational


circuits (functions) using decoder and basic
gates
F = M1 . M3 . M6 . M7

• Active-low decoders generate maxterms.


• If you have a product of maxterms equation for a
function, you can easily use a active-low decoder
and AND gates to implement that function.
• But, in logisim, there is no Active-low decoder. What
can we do?
13-Nov-21 CSE 226: Digital Logic Design Lab 7
Writing Report (skip grayed colored ones)
1. Pin diagram of 74139 (with two 2-to-4 decoders
inside).
2. Logic diagram of 3-to-8 line decoder implementation
a) Basic gates, non-hierarchical (AND gate more inputs)
b) Basic gates, hierarchical (Decoder and AND gate – two
inputs)
c) 2-to-4 line decoders with enable
3. Logic diagram of realizing combinational circuits
using 3-to-8 line decoder
F = M1 . M 3 . M 6 . M 7
4. Answer the question:
a) How to use the 3-to-8 line decoder (the one you have
designed with two 2-to-4 line decoders) for implementing
the following function?

13-Nov-21 F = m0 + m4 + m5 + m7 8
CSE 226: Digital Logic Design Lab

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