STM32L476RG STMicroelectronics

STM32L476xx
Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,

up to 1MB flash, 128 KB SRAM, USB OTG FS, LCD, ext. SMPS
Datasheet - production data
Features
Includes ST state-of-the-art patented LQFP144 (20 × 20)
LQFP100 (14 × 14) UFBGA132 (7 × 7) WLCSP72
technology LQFP64 (10 × 10) UFBGA144 (10 × 10) WLCSP81
WLCSP99
• Ultra-low-power with FlexPowerControl
– Internal multispeed 100 kHz to 48 MHz
– 1.71 V to 3.6 V power supply oscillator, auto-trimmed by LSE (better than
– -40 °C to 85/105/125 °C temperature range ±0.25 % accuracy)
– 300 nA in VBAT mode: supply for RTC and – 3 PLLs for system clock, USB, audio, ADC
32x32-bit backup registers
• Up to 114 fast I/Os, most 5 V-tolerant, up to 14
– 30 nA Shutdown mode (5 wakeup pins) I/Os with independent supply down to 1.08 V
– 120 nA Standby mode (5 wakeup pins)
• RTC with HW calendar, alarms and calibration
– 420 nA Standby mode with RTC
• LCD 8× 40 or 4× 44 with step-up converter
– 1.1 µA Stop 2 mode, 1.4 µA with RTC
– 100 µA/MHz run mode (LDO Mode) • Up to 24 capacitive sensing channels: support
touchkey, linear and rotary touch sensors
– 39 μA/MHz run mode (@3.3 V SMPS
Mode) • 16x timers: 2x 16-bit advanced motor-control,
– Batch acquisition mode (BAM) 2x 32-bit and 5x 16-bit general purpose, 2x 16-
bit basic, 2x low-power 16-bit timers (available
– 4 µs wakeup from Stop mode
in Stop mode), 2x watchdogs, SysTick timer
– Brown out reset (BOR)
• Memories
– Interconnect matrix
– Up to 1 MB flash, 2 banks read-while-write,
• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, proprietary code readout protection
Adaptive real-time accelerator (ART
– Up to 128 KB of SRAM including 32 KB
Accelerator™) allowing 0-wait-state execution
with hardware parity check
from flash memory, frequency up to 80 MHz,
MPU, 100DMIPS and DSP instructions – External memory interface for static
memories supporting SRAM, PSRAM,
• Performance benchmark NOR and NAND memories
– 1.25 DMIPS/MHz (Drystone 2.1) – Quad SPI memory interface
– 273.55 CoreMark® (3.42 CoreMark/MHz @
• 4x digital filters for sigma delta modulator
80 MHz)
• Rich analog peripherals (independent supply)
• Energy benchmark
– 3x 12-bit ADC 5 Msps, up to 16-bit with
– 294 ULPMark™ CP score
hardware oversampling, 200 µA/Msps
– 106 ULPMark™ PP score
– 2x 12-bit DAC output channels, low-power
• Clock Sources sample and hold
– 4 to 48 MHz crystal oscillator – 2x operational amplifiers with built-in PGA
– 32 kHz crystal oscillator for RTC (LSE) – 2x ultra-low-power comparators
– Internal 16 MHz factory-trimmed RC (±1%) • 20x communication interfaces
– Internal low-power 32 kHz RC (±5%) – USB OTG 2.0 full-speed, LPM and BCD
– 2x SAIs (serial audio interface)
March 2024 DS10198 Rev 9 1/271

This is information on a product in full production. www.st.com
STM32L476xx
– 3x I2C FM+(1 Mbit/s), SMBus/PMBus • 14-channel DMA controller

– 5x USARTs (ISO 7816, LIN, IrDA, modem) • True random number generator
– 1x LPUART (Stop 2 wake-up) • CRC calculation unit, 96-bit unique ID
– 3x SPIs (and 1x Quad SPI)
• Development support: serial wire debug
– CAN (2.0B Active) and SDMMC interface (SWD), JTAG, Embedded Trace Macrocell™
– SWPMI single wire protocol master I/F
• All packages are ECOPACK2 compliant
– IRTIM (Infrared interface)
Table 1. Device summary
Reference Part numbers
STM32L476RC, STM32L476VC, STM32L476JE, STM32L476ME, STM32L476QE,

STM32L476xx STM32L476RE, STM32L476VE, STM32L476ZE, STM32L476JG, STM32L476MG,
STM32L476QG, STM32L476RG, STM32L476VG, STM32L476ZG
2/271 DS10198 Rev 9

STM32L476xx Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 18
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 21
3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.9.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.9.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 40
3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 40
3.15 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.16 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Contents STM32L476xx
3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.21 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.22 Digital filter for Sigma-Delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 45
3.23 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.24.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.24.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.24.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.24.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 49
3.24.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.24.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.24.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.24.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.25 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 51
3.26 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.27 Universal synchronous/asynchronous receiver transmitter (USART) . . . 53
3.28 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 54
3.29 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.30 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.31 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 56
3.32 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.33 Secure digital input/output and MultiMediaCards interface (SDMMC) . . . 57
3.34 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 57
3.35 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 58
3.36 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.37 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.37.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.37.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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STM32L476xx Contents
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 115
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 116
6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3.6 Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 171
6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 172
6.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 185
6.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 190
6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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Contents STM32L476xx
6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

6.3.25 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.3.26 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.3.27 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.3.28 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 203
6.3.29 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
6.3.30 SWPMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

7.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
7.2 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
7.3 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
7.4 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
7.5 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
7.6 WLCSP99 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
7.9 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
7.10 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
7.10.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
7.10.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 260
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
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STM32L476xx List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32L476xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 19
Table 4. STM32L476xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. STM32L476xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 7. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 8. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 9. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 10. DFSDM1 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 11. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 12. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 13. STM32L476xx USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 14. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 15. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 16. STM32L476xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 17. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 18. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 19. STM32L476xx memory map and peripheral register boundary addresses . . . . . . . . . . . 104
Table 20. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 21. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 22. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 23. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 24. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 25. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 26. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 27. Current consumption in Run and Low-power run modes, code with data processing
running from flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 121
Table 28. Current consumption in Run modes, code with data processing running from flash,
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
running from flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
ART disable and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . 124
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 32. Current consumption in Run, code with data processing running from
SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . 126
Table 33. Typical current consumption in Run and Low-power run modes, with different codes
running from flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 127
Table 34. Typical current consumption in Run, with different codes running from flash,
(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
(VDD12 = 1.05 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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running from flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 37. Typical current consumption in Run modes, with different codes running from
flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . 129
Table 38. Typical current consumption in Run modes, with different codes running
from flash, ART disable and power supplied by external SMPS (VDD12 = 1.05 V) . . . . . 129
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 40. Typical current consumption in Run mode, with different codes running from
Table 42. Current consumption in Sleep and Low-power sleep modes, flash ON . . . . . . . . . . . . . . 132
Table 43. Current consumption in Sleep, flash ON and power supplied by external SMPS
(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 44. Current consumption in Low-power sleep modes, flash in power-down. . . . . . . . . . . . . . 133
Table 45. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 48. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 49. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 50. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 51. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 52. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 53. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 54. Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 55. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 56. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 57. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 58. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 59. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 60. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Table 61. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 62. PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 63. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 64. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 65. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 66. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 67. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 68. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 69. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 70. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 71. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 72. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 73. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 74. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 75. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 76. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 77. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 78. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
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Table 82. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 83. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 84. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 85. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 86. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 87. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 88. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 89. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 90. LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 91. DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 92. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 93. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 94. WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 95. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 96. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 97. Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 98. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 99. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 100. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 101. eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 102. USB OTG DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 103. USB OTG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 104. USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 105. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 218
Table 106. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 218
Table 107. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 219
Table 108. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 220
Table 109. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 110. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 221
Table 111. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 112. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 223
Table 113. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 114. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 115. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 116. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 117. Switching characteristics for NAND flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 118. Switching characteristics for NAND flash write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 119. SWPMI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 120. LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 121. UFBGA144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 122. UFBGA144 - Recommended PCB design rules (0.80 mm pitch BGA). . . . . . . . . . . . . . . 240
Table 123. UFBGA132 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 124. UFBGA132 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 242
Table 125. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 126. WLCSP99 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 127. WLCSP99 - Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 129. WLCSP81 - Recommended PCB design rules (0.4 mm pitch). . . . . . . . . . . . . . . . . . . . . 251
Table 131. WLCSP72 - Recommended PCB design rules (0.4 mm pitch BGA) . . . . . . . . . . . . . . . . 254
Table 132. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 133. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
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Table 134. STM32L476xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Table 135. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
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STM32L476xx List of figures
List of figures
Figure 1. STM32L476xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 5. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 6. STM32L476Zx LQFP144 pinout(1) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 7. STM32L476Zx, external SMPS device, LQFP144 pinout(1) (2) . . . . . . . . . . . . . . . . . . . . . . 62
Figure 8. STM32L476Zx UFBGA144 ballout(1) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 9. STM32L476Qx UFBGA132 ballout(1) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 10. STM32L476Qx, external SMPS device, UFBGA132 ballout(1) (2). . . . . . . . . . . . . . . . . . . . 64
Figure 11. STM32L476VxT LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 12. STM32L476VxY, external SMPS device, WLCSP99 ballout(1) (2). . . . . . . . . . . . . . . . . . . . 65
Figure 13. STM32L476Mx WLCSP81 ballout(1) (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 14. STM32L476Jx WLCSP72 ballout(1) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 15. STM32L476Jx, external SMPS device, WLCSP72 ballout(1) (2) . . . . . . . . . . . . . . . . . . . . . 66
Figure 16. STM32L476Rx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 17. STM32L476Rx, external SMPS device, LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 18. STM32L476xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 19. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 20. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 21. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 22. Current consumption measurement scheme with and without external
SMPS power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 23. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 24. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 25. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 26. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 27. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 28. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 29. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 30. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 31. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 32. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 33. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 34. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch
function 184
Figure 35. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 36. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 37. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 38. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 39. Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 40. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 41. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 42. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 43. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 44. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 45. USB OTG timings – definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . 214
Figure 46. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 217
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Figure 47. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 219

Figure 48. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 49. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 50. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 51. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 52. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 53. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 54. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 55. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 56. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 231
Figure 57. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 232
Figure 58. LQFP144 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 59. LQFP144 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 60. UFBGA144 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 61. UFBGA144 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 62. UFBGA132 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Figure 63. UFBGA132 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 64. LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 65. LQFP100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 66. WLCSP99 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 67. WLCSP99 – Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 68. WLCSP99 (external SMPS device) marking (package top view) . . . . . . . . . . . . . . . . . . . 249
Figure 69. WLCSP81 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 70. WLCSP81- Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 71. WLCSP81 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 72. WLCSP72 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 73. WLCSP72 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 74. WLCSP72 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 75. LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 76. LQFP64 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 77. LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
12/271 DS10198 Rev 9

STM32L476xx Introduction
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L476xx microcontrollers.
This document must be read in conjunction with the STM32L47x, STM32L48x, STM32L49x
and STM32L4Ax reference manual (RM0351), available from the STMicroelectronics
website www.st.com.
For information on the Arm®(a) Cortex®-M4 core, refer to the Cortex®-M4 Technical
Reference Manual, available from the www.arm.com website.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32L476xx errata sheet (ES0250), available on the STMicroelectronics
website www.st.com.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS10198 Rev 9 13/271

60
Description STM32L476xx
2 Description
The STM32L476xx devices are ultra-low-power microcontrollers based on the

high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to
80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision that
supports all Arm® single-precision data-processing instructions and data types. It also
implements a full set of DSP instructions and a memory protection unit (MPU) which
enhances application security.
The STM32L476xx devices embed high-speed memories (flash memory up to 1 Mbyte, up
to 128 Kbyte of SRAM), a flexible external memory controller (FSMC) for static memories
(for devices with packages of 100 pins and more), a Quad SPI flash memories interface
(available on all packages) and an extensive range of enhanced I/Os and peripherals
connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
The STM32L476xx devices embed several protection mechanisms for embedded flash
memory and SRAM: readout protection, write protection, proprietary code readout
protection and Firewall.
The devices offer up to three fast 12-bit ADCs (5 Msps), two comparators, two operational
amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two
general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven
general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four
digital filters for external sigma delta modulators (DFSDM).
In addition, up to 24 capacitive sensing channels are available. The devices also embed an
integrated LCD driver 8x40 or 4x44, with internal step-up converter.
They also feature standard and advanced communication interfaces, namely three I2Cs,
three SPIs, three USARTs, two UARTs and one Low-Power UART, two SAIs, one SDMMC,
one CAN, one USB OTG full-speed, one SWPMI (single wire protocol master interface).
The STM32L476xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C
(+125 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to
3.6 V VDD power supply when using internal LDO regulator and a 1.05 to 1.32V VDD12
power supply when using external SMPS supply. A comprehensive set of power-saving
modes makes possible the design of low-power applications.
Some independent power supplies are supported: analog independent supply input for
ADC, DAC, OPAMPs and comparators, 3.3 V dedicated supply input for USB and up to 14
I/Os can be supplied independently down to 1.08 V. A VBAT input makes it possible to
backup the RTC and backup registers. Dedicated VDD12 power supplies can be used to
bypass the internal LDO regulator when connected to an external SMPS.
The STM32L476xx family offers seven packages from 64-pin to 144-pin packages.
14/271 DS10198 Rev 9

STM32L476xx Description
Table 2. STM32L476xx family device features and peripheral counts

STM32 STM32 STM32 STM32 STM32 STM32 STM32
Peripheral
L476Zx L476Qx L476VxT L476VxY L476Mx L476Jx L476Rx
512 1 512 1 256 512 1 1 512 1 512 1 256 512 1

Flash memory
KB MB KB MB KB KB MB MB KB MB KB MB KB KB MB
SRAM 128KB
External memory
controller for static Yes Yes Yes(1) No No No No
memories
Quad SPI Yes
Advanced
2 (16-bit)
control
General 5 (16-bit)
purpose 2 (32-bit)
Basic 2 (16-bit)
Low -power 2 (16-bit)
Timers
SysTick
1
timer
Watchdog
timers
(indepen- 2
dent,
window)
SPI 3
2C
I 3
USART 3
UART 2
LPUART 1
Comm. SAI 2
interfaces
CAN 1
USB OTG
Yes
FS
SDMMC Yes
SWPMI Yes
Digital filters for sigma-
Yes (4 filters)
delta modulators
Number of channels 8
RTC Yes
Tamper pins 3 2 2 2 2
Yes Yes Yes Yes Yes
LCD Yes Yes
8x40 or 8x40 or 7x28 or 8x30 or 8x28 or
COM x SEG 8x40 or 4x44 8x28 or 4x32
4x44 4x44 4x31 4x32 4x32
DS10198 Rev 9 15/271

60
Description STM32L476xx
Table 2. STM32L476xx family device features and peripheral counts (continued)

STM32 STM32 STM32 STM32 STM32 STM32 STM32
Peripheral
L476Zx L476Qx L476VxT L476VxY L476Mx L476Jx L476Rx
Random generator Yes

(3) 109(3) 82(3) 65(3) 57(3) 51(3)
GPIOs 114 68
Wakeup pins 5 5 5 3 4 4 4
Nb of I/Os down to 14 14 0 14 6 6 0
1.08 V(2)
Capacitive sensing
24 24 21 12 12 12 12
Number of channels
12-bit ADCs 3 3 3 3 3 3 3
Number of channels 24 19 16 15 16 16 16
12-bit DAC channels 2
Internal voltage
Yes No
reference buffer
Analog comparator 2
Operational amplifiers 2
Max. CPU frequency 80 MHz
Operating voltage (VDD) 1.71 to 3.6 V
Operating voltage
1.05 to 1.32 V
(VDD12)
Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C
Operating temperature
Junction temperature: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C
LQFP144
UFBGA WLCSP WLCSP WLCSP
Packages UFBGA LQFP100 LQFP64
132 99 81 72
144
1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory
using the NE1 Chip Select.
2. These GPIOs are supplied by VDDIO2.
3. In case external SMPS package type is used, 2 GPIOs are replaced by VDD12 pins to connect the SMPS power supplies
hence reducing the number of available GPIOs by 2.
16/271 DS10198 Rev 9

STM32L476xx Description
Figure 1. STM32L476xx block diagram
CLK, NE[4:1], NL, NBL[1:0],

Flexible static memory controller (FSMC):
NJTRST, JTDI, A[25:0], D[15:0], NOE, NWE,
SRAM, PSRAM, NOR flash,
NWAIT, NCE3, INT3 as AF
JTCK/SWCLK JTAG & SW MPU NAND flash
JTDO/SWD, JTDO
ETM NVIC
TRACECLK BK1_IO[3:0]
TRACED[3:0] D-BUS Quad SPI memory interface CLK
ARM Cortex-M4 NCS
80 MHz
I-BUS
FPU RNG
ACCEL/
CACHE
Flash
ART
S-BUS up to
1 MB @ VDDUSB
DP
FIFO
USB
PHY
DM
OTG
AHB bus-matrix
SCL, SDA, INTN, ID, VBUS, SOF
SRAM 96 KB
SRAM 32 KB
VDD Power management

AHB2 80 MHz VDD = 1.71 to 3.6 V
DMA2
Voltage VDD12 = 1.05 to 1.32 V(1)
regulator
VDD12 3.3 to 1.2 V VSS
DMA1
@ VDD @ VDD
Supply
MSI reset
supervision
8 Groups of VDDIO2, VDDUSB
Touch sensing controller RC HSI Int
3 channels max as AF BOR
VDDA, VSSA
RC LSI VDD, VSS, NRST
PA[15:0] GPIO PORT A PVD, PVM
PLL 1&2&3
AHB1 80 MHz
PB[15:0] GPIO PORT B @VDD
XTAL OSC OSC_IN

PC[15:0] GPIO PORT C 4- 16MHz OSC_OUT
IWDG
VBAT = 1.55 to 3.6 V
PD[15:0] GPIO PORT D
Standby
PE[15:0] GPIO PORT E interface
Reset & clock
M AN AGT
control @VBAT
PF[15:0] GPIO PORT F OSC32_IN
XTAL 32 kHz
OSC32_OUT
PG[15:0] GPIO PORT G RTC
RTC_TS
FCLK
PCLKx
AWU
HCLKx
RTC_TAMPx
Backup register
PH[1:0] GPIO PORT H RTC_OUT
@ VDD
U STemperature
AR T 2 M sensor
Bps TIM2 32b 4 channels, ETR as AF
CRC
@ VDDA TIM3 4 channels, ETR as AF
16b
8 analog inputs common
to the 3 ADCs ADC1
TIM4 16b 4 channels, ETR as AF
8 analog inputs common
to the ADC1 & 2 ADC2
IF
ITF TIM5 32b 4 channels, ETR as AF
8 analog inputs for ADC3 ADC3
smcard
USART2 RX, TX, CK, CTS, RTS as AF
IrDA
@ VDDA
VREF+ smcard RX, TX, CK, CTS, RTS as AF
VREF Buffer AHB/APB2 USART3
AHB/APB1 IrDA
UART4 RX, TX, CTS, RTS as AF

114 AF EXT IT. WKUP
UART5 RX, TX, CTS, RTS as AF

D[7:0]
FIFO
CMD, CK as AF SDIO / MMC

SP2 MOSI, MISO, SCK, NSS as AF
3 compl. channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]), TIM1 / PWM 16b SP3 MOSI, MISO, SCK, NSS as AF
ETR, BKIN, BKIN2 as AF
3 compl. channels (TIM1_CH[1:3]N), I2C1/SMBUS SCL, SDA, SMBA as AF
4 channels (TIM1_CH[1:4]), TIM8 / PWM 16b
WWDG
ETR, BKIN, BKIN2 as AF
I2C2/SMBUS SCL, SDA, SMBA as AF
2 channels, 16b
TIM15
1 compl. channel, BKIN as AF I2C3/SMBUS SCL, SDA, SMBA as AF
APB2 80MHz
1 channel,
FIFO
TIM16 16b
1 compl. channel, BKIN as AF bxCAN1 TX, RX as AF
1 channel, @VDDA
16b
1 3 0 M Hz
1 compl. channel, BKIN as AF TIM17

OpAmp1 VOUT, VINM, VINP
smcard
A P B(max)
RX, TX, CK,CTS, USART1

RTS as AF IrDA TIM6 16b OpAmp2 VOUT, VINM, VINP
APB1 80 MHz
MOSI, MISO,
SPI1
SCK, NSS as AF TIM7 16b
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK LCD Booster
VLCD
SAI1 VLCD = 2.5V to 3.6V

MCLK_B, SD_B, FS_B, SCK_B as AF
B Hz
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

2
SAI2
60PM
MCLK_B, SD_B, FS_B, SCK_B as AF

LCD 8x40 SEGx, COMx as AF
SDCKIN[7:0], SDDATIN[7:0],
A
DFSDM
SDCKOUT,SDTRIG as AF
@ VDDA @ VDDA LPUART1 RX, TX, CTS, RTS as AF
INP, INM, OUT COMP1 IO

ITF SWPMI1
DAC1 RX, TX, SUSPEND as AF
INP, INM, OUT COMP2
LPTIM1 IN1, IN2, OUT, ETR as AF
Firewall
LPTIM2 IN1, OUT, ETR as AF
1. Only available when using external SMPS supply mode.

DAC1_OUT1 DAC1_OUT2 MS31263V8
Note: AF: alternate function on I/O pins.
DS10198 Rev 9 17/271

60
Functional overview STM32L476xx
3 Functional overview
3.1 Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for
embedded systems, developed to provide a low-cost platform that meets the needs of MCU
implementation with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code-
efficiency, delivering the high-performance expected from an Arm® core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions enabling efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded Arm® core, the STM32L476xx family is compatible with all Arm® tools
and software.
Figure 1 shows the general block diagram of the STM32L476xx family devices.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard
Arm® Cortex®-M4 processors. It balances the inherent performance advantage of the Arm®
Cortex®-M4 over flash memory technologies, which normally requires the processor to wait
for the flash memory at higher frequencies.
To release the processor near 100 DMIPS performance at 80 MHz, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 64-bit flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from flash memory at a CPU frequency up to 80 MHz.
3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole
4 Gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
18/271 DS10198 Rev 9

STM32L476xx Functional overview
3.4 Embedded flash memory

STM32L476xx devices feature up to 1 Mbyte of embedded flash memory available for
storing programs and data. The flash memory is divided into two banks allowing read-while-
write operations. This feature permits to perform a read operation from one bank while an
erase or program operation is performed to the other bank. The dual bank boot is also
supported. Each bank contains 256 pages of 2 Kbyte.
Flexible protections can be configured thanks to option bytes:
• Readout protection (RDP) to protect the whole memory. Three levels are available:
– Level 0: no readout protection
– Level 1: memory readout protection: the flash memory cannot be read from or
written to if either debug features are connected, boot in RAM or bootloader is
selected
– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial
wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
Table 3. Access status versus readout protection level and execution modes
Debug, boot from RAM or boot
User execution
Protection from system memory (loader)
Area
level
Read Write Erase Read Write Erase
Main 1 Yes Yes Yes No No No

memory 2 Yes Yes Yes N/A N/A N/A
System 1 Yes No No Yes No No

memory 2 Yes No No N/A N/A N/A
Option 1 Yes Yes Yes Yes Yes Yes

bytes 2 Yes No No N/A N/A N/A
(1)
Backup 1 Yes Yes N/A No No N/A(1)
registers 2 Yes Yes N/A N/A N/A N/A
1 Yes Yes Yes(1) No No No(1)
SRAM2
2 Yes Yes Yes N/A N/A N/A
1. Erased when RDP change from Level 1 to Level 0.
• Write protection (WRP): the protected area is protected against erasing and
programming. Two areas per bank can be selected, with 2-Kbyte granularity.
• Proprietary code readout protection (PCROP): a part of the flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
One area per bank can be selected, with 64-bit granularity. An additional option bit
(PCROP_RDP) allows the user to select if the PCROP area is erased or not when the
RDP protection is changed from Level 1 to Level 0.
DS10198 Rev 9 19/271

60
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
• single error detection and correction
• double error detection.
The address of the ECC fail can be read in the ECC register.
3.5 Embedded SRAM

STM32L476xx devices feature up to 128 Kbyte of embedded SRAM, split into two blocks:
• 96 Kbyte mapped at address 0x2000 0000 (SRAM1)
• 32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).
This block is accessed through the ICode/DCode buses for maximum performance.
These 32 Kbyte SRAM can also be retained in Standby mode.
The SRAM2 can be write-protected with 1 Kbyte granularity.
The memory can be accessed in read/write at CPU clock speed with 0 wait states.
3.6 Firewall
The device embeds a Firewall which protects code sensitive and secure data from any
access performed by a code executed outside of the protected areas.
Each illegal access generates a reset which kills immediately the detected intrusion.
The Firewall main features are the following:
• Three segments can be protected and defined thanks to the Firewall registers:
– Code segment (located in flash or SRAM1 if defined as executable protected
area)
– Non-volatile data segment (located in flash)
– Volatile data segment (located in SRAM1)
• The start address and the length of each segments are configurable:
– Code segment: up to 1024 Kbyte with granularity of 256 bytes
– Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes
– Volatile data segment: up to 96 Kbyte with a granularity of 64 bytes
• Specific mechanism implemented to open the Firewall to get access to the protected
areas (call gate entry sequence)
• Volatile data segment can be shared or not with the non-protected code
• Volatile data segment can be executed or not depending on the Firewall configuration
The flash readout protection must be set to level 2 in order to reach the expected level of
protection.
3.7 Boot modes

At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:
• Boot from user flash memory
• Boot from system memory
• Boot from embedded SRAM
20/271 DS10198 Rev 9

The boot loader is located in system memory. It is used to reprogram the flash memory by
using USART, I2C, SPI, CAN or USB OTG FS in Device mode through DFU (device
firmware upgrade).
3.8 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.9 Power supply management
3.9.1 Power supply schemes

• VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and
the system analog such as reset, power management and internal clocks. It is provided
externally through VDD pins.
• VDD12 = 1.05 to 1.32 V: external power supply bypassing internal regulator when
connected to an external SMPS. It is provided externally through VDD12 pins and only
available on packages with the external SMPS supply option. VDD12 does not require
any external decoupling capacitance and cannot support any external load.
• VDDA = 1.62 V (ADCs/COMPs) / 1.8 (DAC/OPAMPs) to 3.6 V: external analog power
supply for ADCs, DAC, OPAMPs, Comparators and Voltage reference buffer. The VDDA
voltage level is independent from the VDD voltage.
• VDDUSB = 3.0 to 3.6 V: external independent power supply for USB transceivers. The
VDDUSB voltage level is independent from the VDD voltage.
• VDDIO2 = 1.08 to 3.6 V: external power supply for 14 I/Os (PG[15:2]). The VDDIO2
voltage level is independent from the VDD voltage.
• VLCD = 2.5 to 3.6 V: the LCD controller can be powered either externally through VLCD
pin, or internally from an internal voltage generated by the embedded step-up
converter.
• VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Note: When the functions supplied by VDDA, VDDUSB or VDDIO2 are not used, these supplies
should preferably be shorted to VDD.
Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V
tolerant (refer to Table 20: Voltage characteristics).
Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1 or
VDDIO2, with VDDIO1 = VDD. VDDIO2 supply voltage level is independent from VDDIO1.
DS10198 Rev 9 21/271

60
Figure 2. Power supply overview
VDDA domain
3 x A/D converters
VDDA 2 x comparators
2 x D/A converters
VSSA 2 x operational amplifiers
Voltage reference buffer
VLCD LCD
VDDUSB
USB transceivers
VSS
VDDIO2 domain
VDDIO2 I/O ring

VSS PG[15:2]
VDD domain
VDDIO1
VDD I/O ring
Reset block
Temp. sensor
3 x PLL, HSI, MSI
VSS
Standby circuitry
(Wakeup logic, IWDG) VCORE domain
Core
VCORE SRAM1
Voltage regulator
SRAM2
Digital peripherals
VDD12
Flash memory
Low voltage detector
Backup domain
LSE crystal 32 K osc
BKP registers
VBAT RCC BDCR register
RTC
MSv45700V1
During power-up and power-down phases, the following power sequence requirements
must be respected:
• When VDD is below 1 V, other power supplies (VDDA, VDDUSB, VDDIO2, VLCD) must
remain below VDD + 300 mV.
• When VDD is above 1 V, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the MCU remains below 1 mJ; this allows external decoupling
capacitors to be discharged with different time constants during the power-down transient
phase.
22/271 DS10198 Rev 9

Figure 3. Power-up/down sequence

V
3.6
VDDX(1)
VDD
VBOR0
0.3
Power-on Operating mode Power-down time
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1
1. VDDX refers to any power supply among VDDA, VDDUSB, VDDIO2, VLCD.
3.9.2 Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
except Shutdown and ensuring proper operation after power-on and during power down.
The device remains in reset mode when the monitored supply voltage VDD is below a
specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An
interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the device embeds a Peripheral Voltage Monitor which compares the
independent supply voltages VDDA, VDDUSB, VDDIO2 with a fixed threshold in order to ensure
that the peripheral is in its functional supply range.
DS10198 Rev 9 23/271

60
3.9.3 Voltage regulator

Two embedded linear voltage regulators supply most of the digital circuitries: the main
regulator (MR) and the low-power regulator (LPR).
• The MR is used in the Run and Sleep modes and in the Stop 0 mode.
• The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is
also used to supply the 32 Kbyte SRAM2 in Standby with SRAM2 retention.
• Both regulators are in power-down in Standby and Shutdown modes: the regulator
output is in high impedance, and the kernel circuitry is powered down thus inducing
zero consumption.
The ultralow-power STM32L476xx supports dynamic voltage scaling to optimize its power
consumption in run mode. The voltage from the Main Regulator that supplies the logic
(VCORE) can be adjusted according to the system’s maximum operating frequency.
There are two power consumption ranges:
• Range 1 with the CPU running at up to 80 MHz.
• Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also
limited to 26 MHz.
The VCORE can be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode.
• Low-power run mode with the CPU running at up to 2 MHz. Peripherals with
independent clock can be clocked by HSI16.
When the MR is in use, the STM32L476xx with the external SMPS option permits to force
an external VCORE supply on the VDD12 supply pins.
When VDD12 is forced by an external source and is higher than the output of the internal
LDO, the current is taken from this external supply and the overall power efficiency is
significantly improved if using an external step down DC/DC converter.
3.9.4 Low-power modes

The ultra-low-power STM32L476xx supports seven low-power modes to achieve the best
compromise between low-power consumption, short startup time, available peripherals and
available wakeup sources.
24/271 DS10198 Rev 9

STM32L476xx
Table 4. STM32L476xx modes overview
Regulator
Mode (1) CPU Flash SRAM Clocks DMA and Peripherals(2) Wakeup source Consumption(3) Wakeup time
MR
112 µA/MHz
range 1
SMPS All
range 2 40 µA/MHz(5)
High
Run Yes ON(4) ON Any N/A N/A
MR
100 µA/MHz
range2
SMPS All except OTG_FS, RNG
Low
Any to Range 1: 4 µs
DS10198 Rev 9
LPRun LPR Yes ON(4) ON except All except OTG_FS, RNG N/A 136 µA/MHz
to Range 2: 64 µs
PLL
MR range
37 µA/MHz
1
SMPS All 6 cycles
High Any interrupt or
Sleep No ON(4) ON(7) Any
MR event
35 µA/MHz
range2
SMPS All except OTG_FS, RNG 6 cycles
Low
Any
Functional overview
Any interrupt or
LPSleep LPR No ON(4) ON(7) except All except OTG_FS, RNG 40 µA/MHz 6 cycles
event
PLL
25/271
Table 4. STM32L476xx modes overview (continued)
26/271
Functional overview
Regulator
BOR, PVD, PVM

RTC, LCD, IWDG Reset pin, all I/Os
Range 1(8) COMPx (x=1,2) BOR, PVD, PVM
DAC1 RTC, LCD, IWDG
OPAMPx (x=1,2) COMPx (x=1..2)
LSE USARTx (x=1...5)(9) USARTx (x=1...5)(9) 0.7 µs in SRAM
Stop 0 No Off ON 108 µA
LSI LPUART1(9) LPUART1(9) 4.5 µs in flash
I2Cx (x=1...3)(10) I2Cx (x=1...3)(10)
LPTIMx (x=1,2) LPTIMx (x=1,2)
Range 2(8) *** OTG_FS(11)
All other peripherals are SWPMI1(12)
DS10198 Rev 9
frozen.
BOR, PVD, PVM

COMPx (x=1,2) BOR, PVD, PVM
DAC1 RTC, LCD, IWDG
OPAMPx (x=1,2) COMPx (x=1..2)
LSE USARTx (x=1...5)(9) USARTx (x=1...5)(9) 6.6 µA w/o RTC 4 µs in SRAM
Stop 1 LPR No Off ON
LSI LPUART1(9) LPUART1(9) 6.9 µA w RTC 6 µs in flash
I2Cx (x=1...3)(10) I2Cx (x=1...3)(10)
LPTIMx (x=1,2) LPTIMx (x=1,2)
*** OTG_FS(11)
All other peripherals are SWPMI1(12)
frozen.
STM32L476xx
Table 4. STM32L476xx modes overview (continued)
STM32L476xx
Regulator
BOR, PVD, PVM

COMPx (x=1..2) BOR, PVD, PVM
I2C3(10) RTC, LCD, IWDG 5 µs in SRAM
LSE 1.1 µA w/o RTC
Stop 2 LPR No Off ON LPUART1(9) COMPx (x=1..2)
LSI 1.4 µA w/RTC
LPTIM1 I2C3(10) 7 µs in flash
*** LPUART1(9)
All other peripherals are LPTIM1
frozen.
SRAM2 BOR, RTC, IWDG 0.35 µA w/o RTC

LPR
ON *** 0.65 µA w/ RTC
All other peripherals are Reset pin
Powered LSE
DS10198 Rev 9
Standby Off powered off. 5 I/Os (WKUPx)(13) 14 µs

Off Powered LSI 0.12 µA w/o RTC
OFF *** BOR, RTC, IWDG
Off 0.42 µA w/ RTC
I/O configuration can be
floating, pull-up or pull-down
RTC
***
All other peripherals are Reset pin
Powered Powered powered off. 0.03 µA w/o RTC
Shutdown OFF Off LSE 5 I/Os (WKUPx)(13) 256 µs
Off Off *** 0.33 µA w/ RTC
RTC
I/O configuration can be
floating, pull-up or pull-
down(14)
1. LPR means Main regulator is OFF and Low-power regulator is ON.
Functional overview
2. All peripherals can be active or clock gated to save power consumption.
3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in
LPRun/LPSleep.
4. The flash memory can be put in power-down and its clock can be gated off when executing from SRAM.
5. Theoretical value based on VDD = 3.3 V, DC/DC Efficiency of 85%, VCORE = 1.10 V
27/271
6. Theoretical value based on VDD = 3.3 V, DC/DC Efficiency of 85%, VCORE = 1.05 V
7. The SRAM1 and SRAM2 clocks can be gated on or off independently.
28/271
Functional overview
8. SMPS mode can be used in STOP0 Mode, but no significant power gain can be expected.
9. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.
10. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
11. OTG_FS wakeup by resume from suspend and attach detection protocol event.
12. SWPMI1 wakeup by resume from suspend.
13. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
14. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.
DS10198 Rev 9
STM32L476xx
By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the
user to select one of the low-power modes described below:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Low-power run mode
This mode is achieved with VCORE supplied by the low-power regulator to minimize the
regulator's operating current. The code can be executed from SRAM or from flash, and
the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be
clocked by HSI16.
• Low-power sleep mode
This mode is entered from the low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the low-
power run mode.
• Stop 0, Stop 1 and Stop 2 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI
RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode
to detect their wakeup condition.
Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,
most of the VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, allowing a very fast wakeup time but with much higher consumption.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI
up to 48 MHz or HSI16, depending on software configuration.
• Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL, the
MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The brown-out reset (BOR) always remains active in Standby mode.
The state of each I/O during standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1 and register contents are lost except for registers
in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in
Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention
mode).
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).
The system clock after wakeup is MSI up to 8 MHz.
DS10198 Rev 9 29/271

60
• Shutdown mode
The Shutdown mode permits to achieve the lowest power consumption. The internal
regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16,
the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2 and register contents are lost except for registers in the Backup
domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).
The system clock after wakeup is MSI at 4 MHz.
30/271 DS10198 Rev 9

Table 5. Functionalities depending on the working mode(1)

Stop 0/1 Stop 2 Standby Shutdown
Wakeup capability
Wakeup capability
Wakeup capability
Wakeup capability
Low- Low-
Peripheral Run Sleep power power VBAT
run sleep - - - -
CPU Y - Y - - - - - - - - - -
Flash memory (up to
O(2) O(2) O(2) O(2) - - - - - - - - -
1 MB)
SRAM1 (up to
Y Y(3) Y Y(3) Y - Y - - - - - -
96 KB)
SRAM2 (32 KB) Y Y(3) Y Y(3) Y - Y - O(4) - - - -
FSMC O O O O - - - - - - - - -
Quad SPI O O O O - - - - - - - - -
Backup registers Y Y Y Y Y - Y - Y - Y - Y
Brown-out reset
Y Y Y Y Y Y Y Y Y Y - - -
(BOR)
Programmable
voltage detector O O O O O O O O - - - - -
(PVD)
Peripheral voltage
monitor (PVMx; O O O O O O O O - - - - -
x=1,2,3,4)
DMA O O O O - - - - - - - - -
High speed Internal (5) (5)
O O O O - - - - - - -
(HSI16)
High speed external
O O O O - - - - - - - - -
(HSE)
Low speed internal
O O O O O - O - O - - - -
(LSI)
Low speed external
O O O O O - O - O - O - O
(LSE)
Multi-Speed internal
O O O O - - - - - - - - -
(MSI)
Clock security
O O O O - - - - - - - - -
system (CSS)
Clock security
O O O O O O O O O O - - -
system on LSE
RTC / Auto wakeup O O O O O O O O O O O O O
Number of RTC
3 3 3 3 3 O 3 O 3 O 3 O 3
Tamper pins
DS10198 Rev 9 31/271

60
Table 5. Functionalities depending on the working mode(1) (continued)

Wakeup capability
Wakeup capability
Wakeup capability
Wakeup capability
Low- Low-
run sleep - - - -
LCD O O O O O O O O - - - - -
(8) (8)
USB OTG FS O O - - - O - - - - - - -
USARTx
O O O O O(6) O(6) - - - - - - -
(x=1,2,3,4,5)
Low-power UART
O O O O O(6) O(6) O(6) O(6) - - - - -
(LPUART)
I2Cx (x=1,2) O O O O O(7) O(7) - - - - - - -
(7)
I2C3 O O O O O O(7) O(7) O(7) - - - - -
SPIx (x=1,2,3) O O O O - - - - - - - - -
CAN O O O O - - - - - - - - -
SDMMC1 O O O O - - - - - - - - -
SWPMI1 O O O O - O - - - - - - -
SAIx (x=1,2) O O O O - - - - - - - - -
DFSDM1 O O O O - - - - - - - - -
ADCx (x=1,2,3) O O O O - - - - - - - - -
DAC1 O O O O O - - - - - - - -
VREFBUF O O O O O - - - - - - - -
OPAMPx (x=1,2) O O O O O - - - - - - - -
COMPx (x=1,2) O O O O O O O O - - - - -
Temperature sensor O O O O - - - - - - - - -
Timers (TIMx) O O O O - - - - - - - - -
Low-power timer 1
O O O O O O O O - - - - -
(LPTIM1)
Low-power timer 2
O O O O O O - - - - - - -
(LPTIM2)
Independent
O O O O O O O O O O - - -
watchdog (IWDG)
Window watchdog
O O O O - - - - - - - - -
(WWDG)
SysTick timer O O O O - - - - - - - - -
Touch sensing
O O O O - - - - - - - - -
controller (TSC)
32/271 DS10198 Rev 9

Table 5. Functionalities depending on the working mode(1) (continued)

Wakeup capability
Wakeup capability
Wakeup capability
Wakeup capability
Low- Low-
run sleep - - - -
Random number
O(8) O(8) - - - - - - - - - - -
generator (RNG)
CRC calculation unit O O O O - - - - - - - - -
5 5
GPIOs O O O O O (9) (11)
O O O pins pins -
(10) (10)
1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.
2. The flash can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAM clock can be gated on or off.
4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling Range 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
3.9.5 Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.9.6 VBAT operation

The VBAT pin permits to power the device VBAT domain from an external battery, an
external supercapacitor, or from VDD when no external battery and an external
supercapacitor are present. The VBAT pin supplies the RTC with LSE and the backup
registers. Three anti-tamper detection pins are available in VBAT mode.
VBAT operation is automatically activated when VDD is not present.
An internal VBAT battery charging circuit is embedded and can be activated when VDD is
present.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
DS10198 Rev 9 33/271

60
3.10 Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run
and sleep, Stop 0, Stop 1 and Stop 2 modes.
Table 6. STM32L476xx peripherals interconnect matrix
Low-power sleep
Low-power run
Stop 0 / Stop 1
Stop 2
Sleep
Interconnect
Run
Interconnect source Interconnect action
destination
TIMx Timers synchronization or chaining Y Y Y Y - -

ADCx
DAC1 Conversion triggers Y Y Y Y - -
TIMx
DFSDM1
DMA Memory to memory transfer trigger Y Y Y Y - -
COMPx Comparator output blanking Y Y Y Y - -
TIM16/TIM17 IRTIM Infrared interface output generation Y Y Y Y - -
TIM1, 8 Timer input channel, trigger, break from
Y Y Y Y - -
TIM2, 3 analog signals comparison
COMPx
Low-power timer triggered by analog Y
LPTIMERx Y Y Y Y Y (1)
signals comparison
ADCx TIM1, 8 Timer triggered by analog watchdog Y Y Y Y - -
TIM16 Timer input channel from RTC events Y Y Y Y - -
RTC Low-power timer triggered by RTC alarms Y
LPTIMERx Y Y Y Y Y (1)
or tampers
All clocks sources (internal TIM2 Clock source used as input channel for
Y Y Y Y - -
and external) TIM15, 16, 17 RC measurement and trimming
USB TIM2 Timer triggered by USB SOF Y Y - - - -

CSS
CPU (hard fault)
RAM (parity error)
Flash memory (ECC error)
TIM1,8
COMPx Timer break Y Y Y Y - -
TIM15,16,17
PVD
DFSDM1 (analog
watchdog, short circuit
detection)
34/271 DS10198 Rev 9

Table 6. STM32L476xx peripherals interconnect matrix (continued)
Low-power sleep
Low-power run
Stop 0 / Stop 1
Stop 2
Sleep
Interconnect
Run
Interconnect source Interconnect action
destination
TIMx External trigger Y Y Y Y - -

Y
LPTIMERx External trigger Y Y Y Y Y (1)
GPIO
ADCx
DAC1 Conversion external trigger Y Y Y Y - -
DFSDM1
1. LPTIM1 only.
DS10198 Rev 9 35/271

60
3.11 Clocks and startup

The clock controller (see Figure 4) distributes the clocks coming from different oscillators to
the core and the peripherals. It also manages clock gating for low-power modes and
ensures clock robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
– 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply
a PLL. The HSE can also be configured in bypass mode for an external clock.
– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the
USB device, saving the need of an external high-speed crystal (HSE). The MSI
can supply a PLL.
– System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 80 MHz.
• Auxiliary clock source: two ultralow-power clock sources that can be used to drive
the LCD controller and the real-time clock:
– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy.
• Peripheral clock sources: Several peripherals (USB, SDMMC, RNG, SAI, USARTs,
I2Cs, LPTimers, ADC, SWPMI) have their own independent clock whatever the system
clock. Three PLLs, each having three independent outputs allowing the highest
flexibility, can generate independent clocks for the ADC, the USB/SDMMC/RNG and
the two SAIs.
• Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
• Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI16 and a software
36/271 DS10198 Rev 9

interrupt is generated if enabled. LSE failure can also be detected and generated an
interrupt.
• Clock-out capability:
– MCO: microcontroller clock output: it outputs one of the internal clocks for
external use by the application. Low frequency clocks (LSI, LSE) are available
down to Stop 1 low power state.
– LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes
down to Standby mode. LSE can also be output on LSCO in Shutdown mode.
LSCO is not available in VBAT mode.
Several prescalers permit to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 80 MHz.
DS10198 Rev 9 37/271

60
Figure 4. Clock tree

to IWDG
LSI RC 32 kHz
LSCO
to RTC and LCD

OSC32_OUT
LSE OSC
/32
32.768 kHz
OSC32_IN
LSE
LSI
MSI
MCO HSE
ĺ to PWR
SYSCLK
HSI16 to AHB bus, core, memory and DMA
Clock
PLLCLK source
AHB HCLK FCLK Cortex free running clock
control
OSC_OUT HSE OSC PRESC
4-48 MHz / 1,2,..512
HSE to Cortex system timer
/8
OSC_IN Clock MSI
detector SYSCLK APB1 PCLK1
HSI16 PRESC
/ 1,2,4,8,16 to APB1 peripherals
HSI RC x1 or x2
to TIMx
16 MHz x=2..7
LSE
HSI16 to USARTx
SYSCLK x=2..5
to LPUART1
MSI RC HSI16
SYSCLK to I2Cx
100 kHz – 48 MHz x=1,2,3
LSI
LSE to LPTIMx
HSI16 x=1,2
HSI16
to SWPMI
MSI PCLK2
PLL HSI16 APB2
/M HSE PRESC to APB2 peripherals
VCO FVCO / P PLLSAI3CLK
/ 1,2,4,8,16
/Q PLL48M1CLK x1 or x2
to TIMx
/R PLLCLK
x=1,8,15,16,17
LSE
PLLSAI1 HSI16 to
SYSCLK USART1
/Q PLL48M2CLK
MSI
PLLADC1CLK 48 MHz clock to USB, RNG, SDMMC
/R
SYSCLK to ADC
PLLSAI2
/Q to SAI1
/R PLLADC2CLK
SAI1_EXTCLK
to SAI2
SAI2_EXTCLK
MS32440V3
38/271 DS10198 Rev 9

3.12 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.13 Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features
implementation.
Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory as well as memory to memory. Data can be quickly moved by DMA
without any CPU actions. This keeps CPU resources free for other operations.
The two DMA controllers have 14 channels in total, each dedicated to managing memory
access requests from one or more peripherals. Each has an arbiter for handling the priority
between DMA requests.
The DMA supports:
• 14 independently configurable channels (requests)
• Each channel is connected to dedicated hardware DMA requests, software trigger is
also supported on each channel. This configuration is done by software.
• Priorities between requests from channels of one DMA are software programmable (4
levels consisting of very high, high, medium, low) or hardware in case of equality
(example: request 1 has priority over request 2)
• Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
• Support for circular buffer management
• 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)
logically ORed together in a single interrupt request for each channel
• Memory-to-memory transfer
• Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers
• Access to flash, SRAM, APB and AHB peripherals as source and destination
• Programmable number of data to be transferred: up to 65536.
Table 7. DMA implementation

DMA features DMA1 DMA2
Number of regular channels 7 7
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3.14 Interrupts and events
3.14.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M4.
The NVIC benefits are the following:
• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail chaining
• Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.14.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 40 edge detector lines used to generate
interrupt/event requests and wake-up the system from Stop mode. Each external line can be
independently configured to select the trigger event (rising edge, falling edge, both) and can
be masked independently. A pending register maintains the status of the interrupt requests.
The internal lines are connected to peripherals with wakeup from Stop mode capability. The
EXTI can detect an external line with a pulse width shorter than the internal clock period. Up
to 114 GPIOs can be connected to the 16 external interrupt lines.
40/271 DS10198 Rev 9

3.15 Analog to digital converter (ADC)

The device embeds 3 successive approximation analog-to-digital converters with the
following features:
• 12-bit native resolution, with built-in calibration
• 5.33 Msps maximum conversion rate with full resolution
– Down to 18.75 ns sampling time
– Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit
resolution)
• Up to 24 external channels, some of them shared between ADC1 and ADC2, or ADC1,
ADC2 and ADC3.
• 5 internal channels: internal reference voltage, temperature sensor, VBAT/3,
DAC1_OUT1 and DAC1_OUT2.
• One external reference pin is available on some package, allowing the input voltage
range to be independent from the power supply
• Single-ended and differential mode inputs
• Low-power design
– Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
– Dual clock domain architecture: ADC speed independent from CPU frequency
• Highly versatile digital interface
– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
– Handles two ADC converters for dual mode operation (simultaneous or
interleaved sampling modes)
– Each ADC support multiple trigger inputs for synchronization with on-chip timers
and external signals
– Results stored into 3 data register or in RAM with DMA controller support
– Data pre-processing: left/right alignment and per channel offset compensation
– Built-in oversampling unit for enhanced SNR
– Channel-wise programmable sampling time
– Three analog watchdog for automatic voltage monitoring, generating interrupts
and trigger for selected timers
– Hardware assistant to prepare the context of the injected channels to allow fast
context switching
3.15.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN17 and ADC3_IN17 input
channels which is used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
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To improve the accuracy of the temperature sensor measurement, each device is

individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 8. Temperature sensor calibration values

Calibration value name Description Memory address
TS ADC raw data acquired at a

TS_CAL1 temperature of 30 °C (± 5 °C), 0x1FFF 75A8 - 0x1FFF 75A9
VDDA = VREF+ = 3.0 V (± 10 mV)
TS ADC raw data acquired at a
TS_CAL2 temperature of 110 °C (± 5 °C), 0x1FFF 75CA - 0x1FFF 75CB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.15.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input
channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
Table 9. Internal voltage reference calibration values

Calibration value name Description Memory address
Raw data acquired at a

VREFINT temperature of 30 °C (± 5 °C), 0x1FFF 75AA - 0x1FFF 75AB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.15.3 VBAT battery voltage monitoring

This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC1_IN18 or ADC3_IN18. As the VBAT voltage may be
higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally
connected to a bridge divider by 3. As a consequence, the converted digital value is one
third the VBAT voltage.
3.16 Digital to analog converter (DAC)

Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in inverting configuration.
42/271 DS10198 Rev 9

This digital interface supports the following features:

• Up to two DAC output channels
• 8-bit or 12-bit output mode
• Buffer offset calibration (factory and user trimming)
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• External triggers for conversion
• Sample and hold low-power mode, with internal or external capacitor
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.
3.17 Voltage reference buffer (VREFBUF)

The STM32L476xx devices embed an voltage reference buffer which can be used as
voltage reference for ADCs, DAC and also as voltage reference for external components
through the VREF+ pin.
The internal voltage reference buffer supports two voltages:
• 2.048 V
• 2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.
Figure 5. Voltage reference buffer
VREFBUF
VDDA DAC, ADC
Bandgap + VREF+
Low frequency
100 nF
cut-off capacitor
MSv40197V1
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3.18 Comparators (COMP)

The STM32L476xx devices embed two rail-to-rail comparators with programmable
reference voltage (internal or external), hysteresis and speed (low speed for low-power) and
with selectable output polarity.
The reference voltage can be one of the following:
• External I/O
• DAC output channels
• Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers
and can be also combined into a window comparator.
3.19 Operational amplifier (OPAMP)

The STM32L476xx embeds two operational amplifiers with external or internal follower
routing and PGA capability.
The operational amplifier features:
• Low input bias current
• Low offset voltage
• Low-power mode
• Rail-to-rail input
3.20 Touch sensing controller (TSC)

The touch sensing controller provides a simple solution for adding capacitive sensing
functionality to any application. Capacitive sensing technology is able to detect finger
presence near an electrode which is protected from direct touch by a dielectric (such as
glass or plastic). The capacitive variation introduced by the finger (or any conductive object)
is measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
44/271 DS10198 Rev 9

The main features of the touch sensing controller are the following:
• Proven and robust surface charge transfer acquisition principle
• Supports up to 24 capacitive sensing channels
• Up to 3 capacitive sensing channels can be acquired in parallel offering a very good
response time
• Spread spectrum feature to improve system robustness in noisy environments
• Full hardware management of the charge transfer acquisition sequence
• Programmable charge transfer frequency
• Programmable sampling capacitor I/O pin
• Programmable channel I/O pin
• Programmable max count value to avoid long acquisition when a channel is faulty
• Dedicated end of acquisition and max count error flags with interrupt capability
• One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
components
• Compatible with proximity, touchkey, linear and rotary touch sensor implementation
• Designed to operate with STMTouch touch sensing firmware library
Note: The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.
3.21 Liquid crystal display controller (LCD)

The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320
pixels.
• Internal step-up converter to guarantee functionality and contrast control irrespective of
VDD. This converter can be deactivated, in which case the VLCD pin is used to provide
the voltage to the LCD
• Supports static, 1/2, 1/3, 1/4 and 1/8 duty
• Supports static, 1/2, 1/3 and 1/4 bias
• Phase inversion to reduce power consumption and EMI
• Integrated voltage output buffers for higher LCD driving capability
• Up to 8 pixels can be programmed to blink
• Unneeded segments and common pins can be used as general I/O pins
• LCD RAM can be updated at any time owing to a double-buffer
• The LCD controller can operate in Stop mode
3.22 Digital filter for Sigma-Delta modulators (DFSDM)

The device embeds one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
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hardware. DFSDM features optional parallel data stream inputs from microcontrollers
memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
• 8 multiplexed input digital serial channels:
– configurable SPI interface to connect various SD modulator(s)
– configurable Manchester coded 1 wire interface support
– PDM (Pulse Density Modulation) microphone input support
– maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
– clock output for SD modulator(s): 0..20 MHz
• alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
– internal sources: device memory data streams (DMA)
• 4 digital filter modules with adjustable digital signal processing:
– Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
– integrator: oversampling ratio (1..256)
• up to 24-bit output data resolution, signed output data format
• automatic data offset correction (offset stored in register by user)
• continuous or single conversion
• start-of-conversion triggered by:
– software trigger
– internal timers
– external events
– start-of-conversion synchronously with first digital filter module (DFSDM1_FLT0)
• analog watchdog feature:
– low value and high value data threshold registers
– dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
– input from final output data or from selected input digital serial channels
– continuous monitoring independently from standard conversion
• short circuit detector to detect saturated analog input values (bottom and top range):
– up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
– monitoring continuously each input serial channel
• break signal generation on analog watchdog event or on short circuit detector event
• extremes detector:
– storage of minimum and maximum values of final conversion data
– refreshed by software
• DMA capability to read the final conversion data
• interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
• “regular” or “injected” conversions:
– “regular” conversions can be requested at any time or even in continuous mode
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without having any impact on the timing of “injected” conversions

– “injected” conversions for precise timing and with high conversion priority
Table 10. DFSDM1 implementation

DFSDM features DFSDM1
Number of channels 8
Number of filters 4
Input from internal ADC -
Supported trigger sources 10
Pulses skipper -
ID registers support -
3.23 True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
3.24 Timers and watchdogs

The STM32L476xx includes two advanced control timers, up to nine general-purpose
timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer.
The table below compares the features of the advanced control, general purpose and basic
timers.
Table 11. Timer feature comparison

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels
Any integer
Advanced Up, down,
TIM1, TIM8 16-bit between 1 Yes 4 3
control Up/down
and 65536
Any integer
General- Up, down,
TIM2, TIM5 32-bit between 1 Yes 4 No
purpose Up/down
and 65536
Any integer
General- Up, down,
TIM3, TIM4 16-bit between 1 Yes 4 No
purpose Up/down
and 65536
Any integer
General-
TIM15 16-bit Up between 1 Yes 2 1
purpose
and 65536
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Table 11. Timer feature comparison (continued)

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels
Any integer
General-
TIM16, TIM17 16-bit Up between 1 Yes 1 1
purpose
and 65536
Any integer
Basic TIM6, TIM7 16-bit Up between 1 Yes 0 No
and 65536
3.24.1 Advanced-control timer (TIM1, TIM8)

The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6
channels. They have complementary PWM outputs with programmable inserted dead-
times. They can also be seen as complete general-purpose timers. The 4 independent
channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
• One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.24.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
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3.24.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,

TIM17)
There are up to seven synchronizable general-purpose timers embedded in the
STM32L476xx (see Table 11 for differences). Each general-purpose timer can be used to
generate PWM outputs, or act as a simple time base.
• TIM2, TIM3, TIM4 and TIM5
They are full-featured general-purpose timers:
– TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler
– TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.
These timers feature 4 independent channels for input capture/output compare, PWM
or one-pulse mode output. They can work together, or with the other general-purpose
timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
• TIM15, 16 and 17
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
– TIM15 has 2 channels and 1 complementary channel
– TIM16 and TIM17 have 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.24.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
3.24.4 Low-power timer (LPTIM1 and LPTIM2)

The devices embed two low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to
wakeup the system from Stop mode.
LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 mode.
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This low-power timer supports the following features:

• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous/ one shot mode
• Selectable software/hardware input trigger
• Selectable clock source
– Internal clock sources: LSE, LSI, HSI16 or APB clock
– External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
• Programmable digital glitch filter
• Encoder mode (LPTIM1 only)
3.24.5 Infrared interface (IRTIM)

The STM32L476xx includes one infrared interface (IRTIM), which can be used with an
infrared LED to perform remote control functions. It uses TIM16 and TIM17 output channels
to generate output signal waveforms on IR_OUT pin.
3.24.6 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.24.7 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.24.8 SysTick timer

This timer is dedicated to real-time operating systems, but can also be used as a standard
down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source
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3.25 Real-time clock (RTC) and backup registers

The RTC is an independent BCD timer/counter. It supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
• Two programmable alarms.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
• Three anti-tamper detection pins with programmable filter.
• Timestamp feature, which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby or Shutdown mode.
The RTC clock sources can be:
• A 32.768 kHz external crystal (LSE)
• An external resonator or oscillator (LSE)
• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
• The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wakeup the device from the low-power modes.
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3.26 Inter-integrated circuit interface (I2C)

The device embeds three I2C. Refer to Table 12: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System Management Bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 4: Clock tree.
• Wakeup from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
Table 12. I2C implementation

I2C features(1) I2C1 I2C2 I2C3
Standard-mode (up to 100 kbit/s) X X X

Fast-mode (up to 400 kbit/s) X X X
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X
Programmable analog and digital noise filters X X X
SMBus/PMBus hardware support X X X
Independent clock X X X
Wakeup from Stop 0 / Stop 1 mode on address match X X X
Wakeup from Stop 2 mode on address match - - X
1. X: supported
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3.27 Universal synchronous/asynchronous receiver transmitter

(USART)
The STM32L476xx devices have three embedded universal synchronous receiver
transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver
transmitters (UART4, UART5).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable, and are able to communicate at speeds of up to
10 Mbit/s.
USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and
SPI-like communication capability.
All USART have a clock domain independent from the CPU clock, allowing the USARTx
(x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The
wake up events from Stop mode are programmable and can be:
• Start bit detection
• Any received data frame
• A specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 13. STM32L476xx USART/UART/LPUART features

USART modes/features(1) USART1 USART2 USART3 UART4 UART5 LPUART1
Hardware flow control for modem X X X X X X

Continuous communication using DMA X X X X X X
Multiprocessor communication X X X X X X
Synchronous mode X X X - - -
Smartcard mode X X X - - -
Single-wire half-duplex communication X X X X X X
IrDA SIR ENDEC block X X X X X -
LIN mode X X X X X -
Dual clock domain X X X X X X
Wakeup from Stop 0 / Stop 1 modes X X X X X X
Wakeup from Stop 2 mode - - - - - X
Receiver timeout interrupt X X X X X -
Modbus communication X X X X X -
Auto baud rate detection X (4 modes) -
Driver Enable X X X X X X
LPUART/USART data length 7, 8 and 9 bits
1. X = supported.
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3.28 Low-power universal asynchronous receiver transmitter

(LPUART)
The device embeds one Low-Power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop
mode are programmable and can be:
• Start bit detection
• Any received data frame
• A specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
LPUART interface can be served by the DMA controller.
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3.29 Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to 40 Mbits/s in master and slave modes, in
half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces
support NSS pulse mode, TI mode and Hardware CRC calculation.
All SPI interfaces can be served by the DMA controller.
3.30 Serial audio interfaces (SAI)

The device embeds 2 SAI. Refer to Table 14 for the features implementation. The SAI bus
interface handles communications between the microcontroller and the serial audio
protocol.
The SAI peripheral supports:
• Two independent audio sub-blocks which can be transmitters or receivers with their
respective FIFO.
• 8-word integrated FIFOs for each audio sub-block.
• Synchronous or asynchronous mode between the audio sub-blocks.
• Master or slave configuration independent for both audio sub-blocks.
• Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode.
• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.
• Peripheral with large configurability and flexibility permitting to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out.
• Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame.
• Number of bits by frame may be configurable.
• Frame synchronization active level configurable (offset, bit length, level).
• First active bit position in the slot is configurable.
• LSB first or MSB first for data transfer.
• Mute mode.
• Stereo/Mono audio frame capability.
• Communication clock strobing edge configurable (SCK).
• Error flags with associated interrupts if enabled respectively.
– Overrun and underrun detection.
– Anticipated frame synchronization signal detection in slave mode.
– Late frame synchronization signal detection in slave mode.
– Codec not ready for the AC’97 mode in reception.
• Interruption sources when enabled:
– Errors.
– FIFO requests.
• DMA interface with 2 dedicated channels to handle access to the dedicated integrated
FIFO of each SAI audio sub-block.
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Table 14. SAI implementation

SAI features(1) SAI1 SAI2
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X

Mute mode X X
Stereo/Mono audio frame capability. X X
16 slots X X
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X
FIFO size X (8 words) X (8 words)
SPDIF X X
1. X: supported
3.31 Single wire protocol master interface (SWPMI)

The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
• full-duplex communication mode
• automatic SWP bus state management (active, suspend, resume)
• configurable bitrate up to 2 Mbit/s
• automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
3.32 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bitrate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
56/271 DS10198 Rev 9

The CAN peripheral supports:

• Supports CAN protocol version 2.0 A, B Active
• Bit rates up to 1 Mbit/s
• Transmission
– Three transmit mailboxes
– Configurable transmit priority
• Reception
– Two receive FIFOs with three stages
– 14 Scalable filter banks
– Identifier list feature
– Configurable FIFO overrun
• Time-triggered communication option
– Disable automatic retransmission mode
– 16-bit free running timer
– Time Stamp sent in last two data bytes
• Management
– Maskable interrupts
– Software-efficient mailbox mapping at a unique address space
3.33 Secure digital input/output and MultiMediaCards interface

(SDMMC)
The card host interface (SDMMC) provides an interface between the APB peripheral bus
and MultiMediaCards (MMCs), SD memory cards and SDIO cards.
The SDMMC features include the following:
• Full compliance with MultiMediaCard System Specification Version 4.2. Card support
for three different databus modes: 1-bit (default), 4-bit and 8-bit
• Full compatibility with previous versions of MultiMediaCards (forward compatibility)
• Full compliance with SD Memory Card Specifications Version 2.0
• Full compliance with SD I/O Card Specification Version 2.0: card support for two
different databus modes: 1-bit (default) and 4-bit
• Data transfer up to 48 MHz for the 8 bit mode
• Data write and read with DMA capability
3.34 Universal serial bus on-the-go full-speed (OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that can be
provided by the internal multispeed oscillator (MSI) automatically trimmed by 32.768 kHz
external oscillator (LSE).This permits to use the USB device without external high speed
crystal (HSE).
DS10198 Rev 9 57/271

60
The major features are:

• Combined Rx and Tx FIFO size of 1.25 KB with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
• 12 host channels with periodic OUT support
• HNP/SNP/IP inside (no need for any external resistor)
• USB 2.0 LPM (Link Power Management) support
• Battery Charging Specification Revision 1.2 support
• Internal FS OTG PHY support
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected.
3.35 Flexible static memory controller (FSMC)

The Flexible static memory controller (FSMC) includes two memory controllers:
• The NOR/PSRAM memory controller
• The NAND/memory controller
This memory controller is also named Flexible memory controller (FMC).
The main features of the FMC controller are the following:
• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR flash memory/OneNAND flash memory
– PSRAM (4 memory banks)
– NAND flash memory with ECC hardware to check up to 8 Kbyte of data
• 8-,16- bit data bus width
• Independent Chip Select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO
• The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2.
LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
58/271 DS10198 Rev 9

3.36 Quad SPI memory interface (QUADSPI)

The Quad SPI is a specialized communication interface targeting single, dual or quad SPI
flash memories. It can operate in any of the three following modes:
• Indirect mode: all the operations are performed using the QUADSPI registers
• Status polling mode: the external flash memory status register is periodically read and
an interrupt can be generated in case of flag setting
• Memory-mapped mode: the external flash is memory mapped and is seen by the
system as if it were an internal memory
The Quad SPI interface supports:
• Three functional modes: indirect, status-polling, and memory-mapped
• SDR and DDR support
• Fully programmable opcode for both indirect and memory mapped mode
• Fully programmable frame format for both indirect and memory mapped mode
• Each of the five following phases can be configured independently (enable, length,
single/dual/quad communication)
– Instruction phase
– Address phase
– Alternate bytes phase
– Dummy cycles phase
– Data phase
• Integrated FIFO for reception and transmission
• 8, 16, and 32-bit data accesses are allowed
• DMA channel for indirect mode operations
• Programmable masking for external flash flag management
• Timeout management
• Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
DS10198 Rev 9 59/271

60
3.37 Development support
3.37.1 Serial wire JTAG debug port (SWJ-DP)

The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins
can be reused as GPIO with alternate function): the JTAG TMS and TCK pins are shared
with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.37.2 Embedded Trace Macrocell™

The Arm® Embedded Trace Macrocell™ provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L476xx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell™ operates with third party debugger software tools.
60/271 DS10198 Rev 9

STM32L476xx Pinouts and pin description
4 Pinouts and pin description
Figure 6. STM32L476Zx LQFP144 pinout(1)(2)
PB3 (JTDO-TRACESWO)
PA14 (JTCK-SWCLK)
PB4 (NJTRST)
PA15 (JTDI)
VDDIO2
BOOT0
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PG11
PC11
VDD
VDD
VSS
VSS
PG9
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
109
119
118
117
116
115
114
113
112
110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VDDUSB
PE5 4 105 PA13 (JTMS-SWDIO)
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN (PC14) 8 101 PA9
PC15-OSC32_OUT (PC15) 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDDIO2
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN (PH0) 23 86 PD15
PH1-OSC_OUT (PH1) 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VSSA 30 79 PD10
VREF- 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE12
PE13
PE14
PE15
PB10
VSS
VDD
PA3
PA4
PA5
PA6
PA7
PF11
PE11
PB11
MS31270V6
1. The above figure shows the package top view.

2. The I/O pins supplied by VDDIO2 are shown in gray.
DS10198 Rev 9 61/271

107
Pinouts and pin description STM32L476xx
Figure 7. STM32L476Zx, external SMPS device, LQFP144 pinout(1)(2)
PB3 (JTDO-TRACESWO)
PA14 (JTCK-SWCLK)
PB4 (NJTRST)
PA15 (JTDI)
VDDIO2
BOOT0
VDD12
PG14
PG13
PG12
PG10
PC12
PC10
PG11
PC11
VDD
VDD
VSS
VSS
PG9
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
109
119
118
117
116
115
114
113
112
110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VDDUSB
PE5 4 105 PA13 (JTMS-SWDIO)
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN (PC14) 8 101 PA9
PC15-OSC32_OUT (PC15) 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDDIO2
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN (PH0) 23 86 PD15
PH1-OSC_OUT (PH1) 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VSSA 30 79 PD10
VREF- 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE12
PE13
PE14
PE15
PB10
VDD12
VSS
VDD
PA3
PA4
PA5
PA6
PA7
PF11
PE11
MSv43895V3

62/271 DS10198 Rev 9

Figure 8. STM32L476Zx UFBGA144 ballout(1)(2)

1 2 3 4 5 6 7 8 9 10 11 12
A VSS PE0 PB8 BOOT0 PB7 PG14 PG12 PD7 PD6 PD1 PD0 VSS
B VBAT PE4 PE3 PE1 PB6 PG15 PG11 PD5 PC12 PC10 PA12 PA11
PC15-
C PE5 PE2 PB9 PB5 PB3 PG9 PD4 PC11 PA14 PA13 PA10
OSC32_OUT
PC14-
D PF4 PE6 PC13 PB4 PG13 PG10 PD3 PD2 PA15 PA9 PA8
OSC32_IN
E PF6 PF1 PF0 PF2 VSS VDDIO2 VDD VSS VDDUSB PC6 PC9 PC8
F PF8 PF7 PF5 PF3 VDD VSS VSS VDDIO2 PG7 PG6 PG8 PC7
PH1-
G PH0-OSC_IN PF10 PF9 VDD VSS VSS VDD PG4 PD13 PG3 PG5
OSC_OUT
H PC2 PC0 PC1 NRST VSS VDD VDD VSS PD12 PD11 PD14 PG2
J VSSA VREF- PA0 PC3 PC4 PF11 PG1 PE9 PB13 PB14 PD10 PD15
K VREF+ VDDA PA1 PA6 PB2 PF12 PG0 PE11 PB11 PB12 PD8 PD9
OPAMP1 OPAMP2
L PA2 PA4 PB0 PF13 PE8 PE12 PE13 PE14 PB10 PB15
_VINM _VINM
M VSS PA3 PA5 PA7 PC5 PB1 PF14 PE7 PF15 PE10 PE15 VSS
MSv50902V2

Figure 9. STM32L476Qx UFBGA132 ballout(1)(2)

1 2 3 4 5 6 7 8 9 10 11 12
A PE3 PE1 PB8 BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12
B PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11
C PC13 PE5 PE0 VDD PB5 PG14 PG13 PD2 PD0 PC11 VDDUSB PA10
PC14-
D PE6 VSS PF2 PF1 PF0 PG12 PG10 PG9 PA9 PA8 PC9
OSC32_IN
PC15-
E VBAT VSS PF3 PG5 PC8 PC7 PC6
OSC32_OUT
F PH0-OSC_IN VSS PF4 PF5 VSS VSS PG3 PG4 VSS VSS
PH1-
G VDD PG11 PG6 VDD VDDIO2 PG1 PG2 VDD VDD
OSC_OUT
H PC0 NRST VDD PG7 PG0 PD15 PD14 PD13
J VSSA/VREF- PC1 PC2 PA4 PA7 PG8 PF12 PF14 PF15 PD12 PD11 PD10
K PG15 PC3 PA2 PA5 PC4 PF11 PF13 PD9 PD8 PB15 PB14 PB13
L VREF+ PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 PB11 PB12
OPAMP1_ OPAMP2_
M VDDA PA1 PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15
VINM VINM
MSv35003V8

DS10198 Rev 9 63/271

107
Figure 10. STM32L476Qx, external SMPS device, UFBGA132 ballout(1)(2)

1 2 3 4 5 6 7 8 9 10 11 12
A PE3 PE1 PB8 BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12
B PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11
C PC13 PE5 PE0 VDD PB5 VDD12 PG13 PD2 PD0 PC11 VDDUSB PA10
PC14-
D PE6 VSS PF2 PF1 PF0 PG12 PG10 PG9 PA9 PA8 PC9
OSC32_IN
PC15-
E VBAT VSS PF3 PG5 PC8 PC7 PC6
OSC32_OUT
F PH0-OSC_IN VSS PF4 PF5 VSS VSS PG3 PG4 VSS VSS
PH1-
G VDD PG11 PG6 VDD VDDIO2 PG1 PG2 VDD VDD
OSC_OUT
H PC0 NRST VDD PG7 PG0 PD15 PD14 PD13
J VSSA/VREF- PC1 PC2 PA4 PA7 PG8 PF12 PF14 PF15 PD12 PD11 PD10
K PG15 PC3 PA2 PA5 PC4 PF11 PF13 PD9 PD8 PB15 PB14 PB13
L VREF+ PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 VDD12 PB12
OPAMP1_ OPAMP2_
M VDDA PA1 PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15
VINM VINM
MSv47486V2

Figure 11. STM32L476VxT LQFP100 pinout(1)

BOOT0
PC12
PC10
PC11
PA15
PA14
VDD
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VDDUSB
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT
NRST
13
14
LQFP100 63
62
PC6
PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF- 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB15
PA0 23 53 PB14
PA1 24 52 PB13
PA2 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE12
PE13
PE14
PE15
PB10
VSS
VDD
PA3
PA4
PA5
PA6
PA7
PE11
PB11
MS31271V3
64/271 DS10198 Rev 9

Figure 12. STM32L476VxY, external SMPS device, WLCSP99 ballout(1)(2)

1 2 3 4 5 6 7 8 9 10 11
A VSS VDD PC11 VDD PG11 VSS PB3 PB7 VSS VSS VBAT
PC14-
B PA13 VDDUSB PA15 VSS PG10 VDDIO2 PG15 PB6 VDD12 VDD
OSC32_IN
PC15-
C PA9 PA10 PA12 PC10 PC12 PG12 PG14 PB5 PB9 PC13
OSC32_OUT
D PC7 PC8 PC9 PA11 PA14 PG9 PG13 BOOT0 PB8 VSS VDD
PH1-
E VSS VDDIO2 PC6 PG8 PA8 VSS VSS PB4 NRST PH0-OSC_IN
OSC_OUT
F PG5 PG4 PG6 PG7 VSS VSS PA4 PC3 PC2 PC0 PC1
G PD8 PB15 PG2 PG3 VSS PB0 PA5 PA1 PA0 VREF+ VSSA/VREF-
H PB14 PB13 PB12 PB10 PE7 VSS PC4 PA6 VSS PA3 VDDA
J VDD VSS VDD12 PB11 PE8 VDD PB2 PB1 PA7 VDD PA2
MSv67578V1

Figure 13. STM32L476Mx WLCSP81 ballout(1)(2)

1 2 3 4 5 6 7 8 9
A VDDUSB PA15 PD2 PG9 PG14 PB3 PB7 VSS VDD
B VSS PA14 PC12 PG10 PG13 VDDIO2 PB6 PC13 VBAT
PC15- PC14-
C PA12 PA13 PC11 PG11 PG12 PB4 PB5
OSC32_OUT OSC32_IN
PH1-
D PA11 PA10 PC10 PD5 PD6 PD7 BOOT0 PH0-OSC_IN
OSC_OUT
E PC9 PA8 PA9 VDD PD4 PE7 PB8 PB9 NRST
F PC7 PC8 PC6 PD9 PD8 PE8 PC2 PC1 PC0
G PB15 PB14 PB11 PA1 PA4 PA2 PC3 VREF+ VSSA/VREF-
H PB12 PB13 PB10 PA7 PA6 PA5 PA3 PA0 VDDA
J VDD VSS PB2 PB1 PB0 PC5 PC4 VDD VSS
MSv38020V4

DS10198 Rev 9 65/271

107
Figure 14. STM32L476Jx WLCSP72 ballout(1)(2)

1 2 3 4 5 6 7 8 9
A VDDUSB PA15 PD2 PG9 PG14 PB3 PB7 VSS VDD
B VSS PA14 PC12 PG10 PG13 VDDIO2 PB6 PC13 VBAT
PC15- PC14-
C PA12 PA13 PC11 PG11 PG12 PB4 PB5
OSC32_OUT OSC32_IN
PH1-
D PA11 PA10 PC10 BOOT0 PH0-OSC_IN
OSC_OUT
E PC9 PA8 PA9 WLCSP72 PB8 PB9 NRST
F PC7 PC8 PC6 PC2 PC1 PC0
G PB15 PB14 PB11 PA1 PA4 PA2 PC3 VREF+ VSSA/VREF-
H PB12 PB13 PB10 PA7 PA6 PA5 PA3 PA0 VDDA
J VDD VSS PB2 PB1 PB0 PC5 PC4 VDD VSS
MSv35083V8

Figure 15. STM32L476Jx, external SMPS device, WLCSP72 ballout(1)(2)

1 2 3 4 5 6 7 8 9
A VDDUSB PC10 PD2 PG9 PG14 PB3 BOOT0 VSS VDD
B VSS PA14 PC12 PG10 PG13 VDDIO2 PB7 VDD12 VBAT
PC15- PC14-
C PA12 PA13 PA15 PG12 PB4 PB8 PC13
OSC32_OUT OSC32_IN
PH1-
D PA11 PA10 PC11 PB9 PH0-OSC_IN
OSC_OUT
E PC9 PA8 PA9 WLCSP72 PB5 PB6 NRST
F VDD PC7 PC8 PC2 PC1 PC0
G PB15 PC6 PB14 PA2 PA0 PA1 PC3 VREF+ VSSA/VREF-
H PB12 PB13 PB11 PA7 PA5 PA4 PA3 VDD VDDA
J VDD12 VSS PB10 PB0 PB1 PB2 PC4 PA6 VSS
MSv43896V2

66/271 DS10198 Rev 9

Figure 16. STM32L476Rx LQFP64 pinout(1)
PB3 (JTDO-TRACESWO)
PA14 (JTCK-SWCLK)
PB4 (NJTRST)
PA15 (JTDI)
BOOT0
PC12
PC10
PC11
VDD
VSS
PD2
PB9
PB8
PB7
PB6
PB5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDDUSB
PC13 2 47 VSS
PC14-OSC32_IN (PC14) 3 46 PA13 (JTMS-SWDIO)
PC15-OSC32_OUT (PC15) 4 45 PA12
PH0-OSC_IN (PH0) 5 44 PA11
PH1-OSC_OUT (PH1) 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA/VREF- 12 37 PC6
VDDA/VREF+ 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD
PC4
PC5
PB0
PB1
PB2
VSS
PB10
VDD
PA3
PA4
PA5
PA6
PA7
PB11
MS31272V5
DS10198 Rev 9 67/271

107
Figure 17. STM32L476Rx, external SMPS device, LQFP64 pinout(1)
PB3 (JTDO-TRACESWO)
PA14 (JTCK-SWCLK)
PB4 (NJTRST)
PA15 (JTDI)
BOOT0
VDD12
PC12
PC10
PC11
VDD
VSS
PB9
PB8
PB7
PB6
PB5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDDUSB
PC13 2 47 VSS
PC14-OSC32_IN (PC14) 3 46 PA13 (JTMS-SWDIO)
PC15-OSC32_OUT (PC15) 4 45 PA12
PH0-OSC_IN (PH0) 5 44 PA11
PH1-OSC_OUT (PH1) 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA/VREF- 12 37 PC6
VDDA/VREF+ 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VSS
VDD
PC4
PB0
PB1
PB2
PB10
VDD12
VDD
PA3
PA4
PA5
PA6
PA7
PB11
MSv45744V1
Table 15. Legend/abbreviations used in the pinout table

Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
TT 3.6 V tolerant I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os

I/O structure
_f (1) I/O, Fm+ capable
(2)
_l I/O, with LCD function supplied by VLCD
_u (3) I/O, with USB function supplied by VDDUSB
(4)
_a I/O, with Analog switch function supplied by VDDA
(5)
_s I/O supplied only by VDDIO2
68/271 DS10198 Rev 9

Table 15. Legend/abbreviations used in the pinout table (continued)

Name Abbreviation Definition
Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in Table 16 are: FT_f, FT_fa, FT_fl, FT_fla.
2. The related I/O structures in Table 16 are: FT_l, FT_fl, FT_lu.
3. The related I/O structures in Table 16 are: FT_u, FT_lu.
4. The related I/O structures in Table 16 are: FT_a, FT_la, FT_fa, FT_fla, TT_a, TT_la.
5. The related I/O structures in Table 16 are: FT_s, FT_fs.
Note: FT_a and FT_fa pins can be connected to analog peripherals inputs. When analog
peripheral is not connected to this FT_a or FT_fa pins (analog switch from GPIO to
peripheral is not closed, for example ADC not uses given pin as ADC input), then GPIO can
accept VDD + 3.6 V (5 V tolerant I/O). However, once the I/O input is connected to the
analog peripheral (for example ADC selects as input channel from this pin), the parasitic
diode from this I/O pin to VDDA and/or VREF+ does not allow to use higher voltage on given
I/O pin than VDDA or VREF+ and pin is no more 5 V-tolerant I/O.
DS10198 Rev 9 69/271

107
70/271
Pinouts and pin description

Table 16. STM32L476xx pin definitions
Pin Number Pin functions
UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
Alternate functions Additional functions
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
TRACECK, TIM3_ETR,
TSC_G7_IO1, LCD_SEG38,
- - - - - - 1 B2 B2 1 1 C3 PE2 I/O FT_l - -
FMC_A23, SAI1_MCLK_A,
EVENTOUT
TRACED0, TIM3_CH1,
- - - - - - 2 A1 A1 2 2 B3 PE3 I/O FT_l - -
DS10198 Rev 9
FMC_A19, SAI1_SD_B,
EVENTOUT
TRACED1, TIM3_CH2,
DFSDM1_DATIN3, TSC_G7_IO3,
- - - - - - 3 B1 B1 3 3 B2 PE4 I/O FT - -
FMC_A20, SAI1_FS_A,
EVENTOUT
TRACED2, TIM3_CH3,
DFSDM1_CKIN3, TSC_G7_IO4,
- - - - - - 4 C2 C2 4 4 C2 PE5 I/O FT - -
FMC_A21, SAI1_SCK_A,
EVENTOUT
TRACED3, TIM3_CH4,
- - - - - - 5 D2 D2 5 5 D3 PE6 I/O FT - FMC_A22, SAI1_SD_A, RTC_TAMP3/WKUP3
EVENTOUT
1 1 B9 B9 B9 A11 6 E2 E2 6 6 B1 VBAT S - - - -
(1) RTC_TAMP1/RTC_TS/
2 2 B8 C7 B8 C10 7 C1 C1 7 7 D4 PC13 I/O FT (2) EVENTOUT
STM32L476xx
RTC_OUT/WKUP2
PC14- (1)
3 3 C9 C9 C9 B11 8 D1 D1 8 8 D2 OSC32_ I/O FT (2) EVENTOUT OSC32_IN
IN (PC14)
Table 16. STM32L476xx pin definitions (continued)
STM32L476xx
UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
PC15-
(1)
OSC32_
4 4 C8 C8 C8 C11 9 E1 E1 9 9 C1 I/O FT (2) EVENTOUT OSC32_OUT
OUT
(PC15)
- - - - - - - D6 D6 10 10 E3 PF0 I/O FT_f - I2C2_SDA, FMC_A0, EVENTOUT -
- - - - - - - D5 D5 11 11 E2 PF1 I/O FT_f - I2C2_SCL, FMC_A1, EVENTOUT -
DS10198 Rev 9
I2C2_SMBA, FMC_A2,
- - - - - - - D4 D4 12 12 E4 PF2 I/O FT - -
EVENTOUT
- - - - - - - E4 E4 13 13 F4 PF3 I/O FT_a - FMC_A3, EVENTOUT ADC3_IN6
- - - - - - - F3 F3 14 14 D1 PF4 I/O FT_a - FMC_A4, EVENTOUT ADC3_IN7
- - - - - - - F4 F4 15 15 F3 PF5 I/O FT_a - FMC_A5, EVENTOUT ADC3_IN8
- - - - - E7 10 F2 F2 16 16 F6 VSS S - - - -
- - - - - - 11 G2 G2 17 17 G5 VDD S - - - -
TIM5_ETR, TIM5_CH1,
- - - - - - - - - 18 18 E1 PF6 I/O FT_a - ADC3_IN9
SAI1_SD_B, EVENTOUT

TIM5_CH2, SAI1_MCLK_B,
- - - - - - - - - 19 19 F2 PF7 I/O FT_a - ADC3_IN10
EVENTOUT
TIM5_CH3, SAI1_SCK_B,
- - - - - - - - - 20 20 F1 PF8 I/O FT_a - ADC3_IN11
EVENTOUT
TIM5_CH4, SAI1_FS_B,
- - - - - - - - - 21 21 G4 PF9 I/O FT_a - ADC3_IN12
TIM15_CH1, EVENTOUT
- - - - - - - - - 22 22 G3 PF10 I/O FT_a - TIM15_CH2, EVENTOUT ADC3_IN13
71/271
72/271

UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
PH0-
5 5 D9 D9 D9 E11 12 F1 F1 23 23 G2 OSC_IN I/O FT - EVENTOUT OSC_IN
(PH0)
PH1-
OSC_
6 6 D8 D8 D8 E10 13 G1 G1 24 24 G1 I/O FT - EVENTOUT OSC_OUT
OUT
(PH1)
DS10198 Rev 9
7 7 E9 E9 E9 E9 14 H2 H2 25 25 H4 NRST I/O RST - - -

LPTIM1_IN1, I2C3_SCL,
DFSDM1_DATIN4,
8 8 F9 F9 F9 F10 15 H1 H1 26 26 H2 PC0 I/O FT_fla - ADC123_IN1
LPUART1_RX, LCD_SEG18,
LPTIM2_IN1, EVENTOUT
LPTIM1_OUT, I2C3_SDA,
9 9 F8 F8 F8 F11 16 J2 J2 27 27 H3 PC1 I/O FT_fla - DFSDM1_CKIN4, LPUART1_TX, ADC123_IN2
LCD_SEG19, EVENTOUT
LPTIM1_IN2, SPI2_MISO,
10 10 F7 F7 F7 F9 17 J3 J3 28 28 H1 PC2 I/O FT_la - DFSDM1_CKOUT, LCD_SEG20, ADC123_IN3
EVENTOUT
LPTIM1_ETR, SPI2_MOSI,
11 11 G7 G7 G7 F8 18 K2 K2 29 29 J4 PC3 I/O FT_a - LCD_VLCD, SAI1_SD_A, ADC123_IN4
LPTIM2_ETR, EVENTOUT
- - - - - - 19 - - 30 30 J1 VSSA S - - - -
STM32L476xx
- - - - - - 20 - - 31 31 J2 VREF- S - - - -
VSSA/
12 12 G9 G9 G9 G11 - J1 J1 - - - S - - - -
VREF-
STM32L476xx
UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
- - G8 G8 G8 G10 21 L1 L1 32 32 K1 VREF+ S - - - VREFBUF_OUT
- - H9 H9 H9 H11 22 M1 M1 33 33 K2 VDDA S - - - -
VDDA/
13 13 - - - - - - - - - - S - - - -
VREF+
TIM2_CH1, TIM5_CH1,
OPAMP1_VINP,
TIM8_ETR, USART2_CTS,
14 14 H8 G5 H8 G9 23 L2 L2 34 34 J3 PA0 I/O FT_a - ADC12_IN5,
DS10198 Rev 9
UART4_TX, SAI1_EXTCLK,
RTC_TAMP2/WKUP1
TIM2_ETR, EVENTOUT
OPAMP1
- - - - - - - M3 M3 - - L1 I TT - - -
_VINM
TIM2_CH2, TIM5_CH2,
(3) USART2_RTS_DE, UART4_RX, OPAMP1_VINM,
15 15 G4 G6 G4 G8 24 M2 M2 35 35 K3 PA1 I/O FT_la
LCD_SEG0, TIM15_CH1N, ADC12_IN6
EVENTOUT
TIM2_CH3, TIM5_CH3,
USART2_TX, LCD_SEG1, ADC12_IN7,
16 16 G6 G4 G6 J11 25 K3 K3 36 36 L2 PA2 I/O FT_la -

SAI2_EXTCLK, TIM15_CH1, WKUP4/LSCO
EVENTOUT
TIM2_CH4, TIM5_CH4,
OPAMP1_VOUT,
17 17 H7 H7 H7 H10 26 L3 L3 37 37 M2 PA3 I/O TT_la - USART2_RX, LCD_SEG2,
ADC12_IN8
TIM15_CH2, EVENTOUT
18 18 J9 J9 J9 H9 27 E3 E3 38 38 F7 VSS S - - - -
19 19 J8 H8 J8 J10 28 H3 H3 39 39 G8 VDD S - - - -
73/271
74/271

UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
SPI1_NSS, SPI3_NSS,
ADC12_IN9,
20 20 G5 H6 G5 F7 29 J4 J4 40 40 L3 PA4 I/O TT_a - USART2_CK, SAI1_FS_B,
DAC1_OUT1
LPTIM2_OUT, EVENTOUT
TIM2_CH1, TIM2_ETR,
ADC12_IN10,
21 21 H6 H5 H6 G7 30 K4 K4 41 41 M3 PA5 I/O TT_a - TIM8_CH1N, SPI1_SCK,
DAC1_OUT2
LPTIM2_ETR, EVENTOUT
TIM1_BKIN, TIM3_CH1,
DS10198 Rev 9
TIM8_BKIN, SPI1_MISO,
USART3_CTS,
OPAMP2_VINP,
22 22 H5 J8 H5 H8 31 L4 L4 42 42 K4 PA6 I/O FT_la - QUADSPI_BK1_IO3, LCD_SEG3,
ADC12_IN11
TIM1_BKIN_COMP2,
TIM8_BKIN_COMP2,
TIM16_CH1, EVENTOUT
OPAMP2
- - - - - - - M4 M4 - - L4 I TT - - -
_VINM
TIM1_CH1N, TIM3_CH2,
(3) TIM8_CH1N, SPI1_MOSI, OPAMP2_VINM,
23 23 H4 H4 H4 J9 32 J5 J5 43 43 M4 PA7 I/O FT_la
QUADSPI_BK1_IO2, LCD_SEG4, ADC12_IN12
TIM17_CH1, EVENTOUT
USART3_TX, LCD_SEG22, COMP1_INM,
24 24 J7 J7 J7 H7 33 K5 K5 44 44 J5 PC4 I/O FT_la -
EVENTOUT ADC12_IN13
USART3_RX, LCD_SEG23, COMP1_INP,
25 - J6 - J6 - 34 L5 L5 45 45 M5 PC5 I/O FT_la -
STM32L476xx
EVENTOUT ADC12_IN14, WKUP5
STM32L476xx
UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
TIM8_CH2N, USART3_CK, OPAMP2_VOUT,
26 25 J5 J4 J5 G6 35 M5 M5 46 46 L5 PB0 I/O TT_la -
QUADSPI_BK1_IO1, LCD_SEG5, ADC12_IN15
COMP1_OUT, EVENTOUT
TIM8_CH3N, DFSDM1_DATIN0,
COMP1_INM,
27 26 J4 J5 J4 J8 36 M6 M6 47 47 M6 PB1 I/O FT_la - USART3_RTS_DE,
ADC12_IN16
DS10198 Rev 9
QUADSPI_BK1_IO0, LCD_SEG6,
RTC_OUT, LPTIM1_OUT,
28 27 J3 J6 J3 J7 37 L6 L6 48 48 K5 PB2 I/O FT_a - I2C3_SMBA, DFSDM1_CKIN0, COMP1_INP
EVENTOUT
- - - - - - - K6 K6 49 49 J6 PF11 I/O FT - EVENTOUT -
- - - - - - - J7 J7 50 50 K6 PF12 I/O FT - FMC_A6, EVENTOUT -
- - - - - E6 - - - 51 51 G6 VSS S - - - -
- - - - - - - - - 52 52 H6 VDD S - - - -

DFSDM1_DATIN6, FMC_A7,
- - - - - - - K7 K7 53 53 L6 PF13 I/O FT - -
EVENTOUT
- - - - - - - J8 J8 54 54 M7 PF14 I/O FT - -
FMC_A8, EVENTOUT
TSC_G8_IO2, FMC_A9,
- - - - - - - J9 J9 55 55 M9 PF15 I/O FT - -
EVENTOUT
TSC_G8_IO3, FMC_A10,
- - - - - - - H9 H9 56 56 K7 PG0 I/O FT - -
EVENTOUT
75/271
76/271

UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
TSC_G8_IO4, FMC_A11,
- - - - - - - G9 G9 57 57 J7 PG1 I/O FT - -
EVENTOUT
TIM1_ETR, DFSDM1_DATIN2,
- - - - E6 H5 38 M7 M7 58 58 M8 PE7 I/O FT - FMC_D4, SAI1_SD_B, -
EVENTOUT
TIM1_CH1N, DFSDM1_CKIN2,
- - - - F6 J5 39 L7 L7 59 59 L7 PE8 I/O FT - FMC_D5, SAI1_SCK_B, -
DS10198 Rev 9
EVENTOUT
TIM1_CH1, DFSDM1_CKOUT,
- - - - - - 40 M8 M8 60 60 J8 PE9 I/O FT - FMC_D6, SAI1_FS_B, -
EVENTOUT
- - - - - H6 - F6 F6 61 61 G7 VSS S - - - -
- - - - - J6 - G6 G6 62 62 E7 VDD S - - - -
TIM1_CH2N, DFSDM1_DATIN4,
TSC_G5_IO1, QUADSPI_CLK,
- - - - - - 41 L8 L8 63 63 M10 PE10 I/O FT - -
FMC_D7, SAI1_MCLK_B,
EVENTOUT
TIM1_CH2, DFSDM1_CKIN4,
- - - - - - 42 M9 M9 64 64 K8 PE11 I/O FT - TSC_G5_IO2, QUADSPI_NCS, -
FMC_D8, EVENTOUT
TIM1_CH3N, SPI1_NSS,
STM32L476xx
- - - - - - 43 L9 L9 65 65 L8 PE12 I/O FT - -
QUADSPI_BK1_IO0, FMC_D9,
EVENTOUT
STM32L476xx
UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
TIM1_CH3, SPI1_SCK,
- - - - - - 44 M10 M10 66 66 L9 PE13 I/O FT - -
QUADSPI_BK1_IO1, FMC_D10,
EVENTOUT
TIM1_CH4, TIM1_BKIN2,
TIM1_BKIN2_COMP2,
- - - - - - 45 M11 M11 67 67 L10 PE14 I/O FT - -
SPI1_MISO, QUADSPI_BK1_IO2,
DS10198 Rev 9
FMC_D11, EVENTOUT
TIM1_BKIN, TIM1_BKIN_COMP1,
- - - - - - 46 M12 M12 68 68 M11 PE15 I/O FT - SPI1_MOSI, QUADSPI_BK1_IO3, -
FMC_D12, EVENTOUT
TIM2_CH3, I2C2_SCL,
SPI2_SCK, DFSDM1_DATIN7,
USART3_TX, LPUART1_RX,
29 28 H3 J3 H3 H4 47 L10 L10 69 69 L11 PB10 I/O FT_fl - -
QUADSPI_CLK, LCD_SEG10,
COMP1_OUT, SAI1_SCK_A,
EVENTOUT

TIM2_CH4, I2C2_SDA,
DFSDM1_CKIN7, USART3_RX,
30 29 G3 H3 G3 J4 48 L11 - 70 - K9 PB11 I/O FT_fl - LPUART1_TX, QUADSPI_NCS, -
LCD_SEG11, COMP2_OUT,
EVENTOUT
- 30 - B8 - B9 - - L11 - 70 - VDD12 S - - - -
31 31 J2 J2 J2 A9 49 F12 F12 71 71 H5 VSS S - - - -
32 32 J1 F1 J1 B10 50 G12 G12 72 72 - VDD S - - - -
77/271
78/271

UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
TIM1_BKIN, TIM1_BKIN_COMP2,
I2C2_SMBA, SPI2_NSS,
DFSDM1_DATIN1, USART3_CK,
33 33 H1 H1 H1 H3 51 L12 L12 73 73 K10 PB12 I/O FT_l - LPUART1_RTS_DE, -
SWPMI1_IO, SAI2_FS_A,
TIM15_BKIN, EVENTOUT
DS10198 Rev 9
TIM1_CH1N, I2C2_SCL,
SPI2_SCK, DFSDM1_CKIN1,
USART3_CTS, LPUART1_CTS,
34 34 H2 H2 H2 H2 52 K12 K12 74 74 J9 PB13 I/O FT_fl - -
SWPMI1_TX, SAI2_SCK_A,
TIM15_CH1N, EVENTOUT
TIM1_CH2N, TIM8_CH2N,
I2C2_SDA, SPI2_MISO,
DFSDM1_DATIN2,
35 35 G2 G3 G2 H1 53 K11 K11 75 75 J10 PB14 I/O FT_fl - USART3_RTS_DE, -
SWPMI1_RX, SAI2_MCLK_A,
TIM15_CH1, EVENTOUT
RTC_REFIN, TIM1_CH3N,
TIM8_CH3N, SPI2_MOSI,
36 36 G1 G1 G1 G2 54 K10 K10 76 76 L12 PB15 I/O FT_l - LCD_SEG15, -
STM32L476xx
SWPMI1_SUSPEND,
SAI2_SD_A, TIM15_CH2,
EVENTOUT
STM32L476xx
UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
USART3_TX, LCD_SEG28,
- - - - F5 G1 55 K9 K9 77 77 K11 PD8 I/O FT_l - -
FMC_D13, EVENTOUT
USART3_RX, LCD_SEG29,
- - - - F4 - 56 K8 K8 78 78 K12 PD9 I/O FT_l - FMC_D14, SAI2_MCLK_A, -
EVENTOUT
USART3_CK, TSC_G6_IO1,
- - - - - - 57 J12 J12 79 79 J11 PD10 I/O FT_l - LCD_SEG30, FMC_D15, -
DS10198 Rev 9
SAI2_SCK_A, EVENTOUT
USART3_CTS, TSC_G6_IO2,
LCD_SEG31, FMC_A16,
- - - - - - 58 J11 J11 80 80 H10 PD11 I/O FT_l - -
SAI2_SD_A, LPTIM2_ETR,
EVENTOUT
TIM4_CH1, USART3_RTS_DE,
- - - - - - 59 J10 J10 81 81 H9 PD12 I/O FT_l - -
FMC_A17, SAI2_FS_A,
TIM4_CH2, TSC_G6_IO4,

- - - - - - 60 H12 H12 82 82 G10 PD13 I/O FT_l - LCD_SEG33, FMC_A18, -
- - - - - D10 - - - 83 83 E5 VSS S - - - -
- - - - - D11 - - - 84 84 F5 VDD S - - - -
TIM4_CH3, LCD_SEG34,
- - - - - - 61 H11 H11 85 85 H11 PD14 I/O FT_l - -
FMC_D0, EVENTOUT
TIM4_CH4, LCD_SEG35,
- - - - - - 62 H10 H10 86 86 J12 PD15 I/O FT_l - -
79/271
FMC_D1, EVENTOUT
80/271

UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
SPI1_SCK, FMC_A12,
- - - - - G3 - G10 G10 87 87 H12 PG2 I/O FT_s - -
SAI2_SCK_B, EVENTOUT
SPI1_MISO, FMC_A13,
- - - - - G4 - F9 F9 88 88 G11 PG3 I/O FT_s - -
SAI2_FS_B, EVENTOUT
SPI1_MOSI, FMC_A14,
- - - - - F2 - F10 F10 89 89 G9 PG4 I/O FT_s - -
SAI2_MCLK_B, EVENTOUT
DS10198 Rev 9
SPI1_NSS, LPUART1_CTS,
- - - - - F1 - E9 E9 90 90 G12 PG5 I/O FT_s - FMC_A15, SAI2_SD_B, -
EVENTOUT
I2C3_SMBA,
- - - - - F3 - G4 G4 91 91 F10 PG6 I/O FT_s - -
LPUART1_RTS_DE, EVENTOUT
I2C3_SCL, LPUART1_TX,
- - - - - F4 - H4 H4 92 92 F9 PG7 I/O FT_fs - -
FMC_INT, EVENTOUT
I2C3_SDA, LPUART1_RX,
- - - - - E4 - J6 J6 93 93 F11 PG8 I/O FT_fs - -
EVENTOUT
- - - - - A10 - - - - - - VSS S - - - -
- - - - - A6 - - - 94 94 M12 VSS S - - - -
- - - - - B6 - - - 95 95 F8 VDDIO2 S - - - -
TIM3_CH1, TIM8_CH1,
37 37 F3 G2 F3 E3 63 E12 E12 96 96 E10 PC6 I/O FT_l - -
STM32L476xx
LCD_SEG24, SDMMC1_D6,
SAI2_MCLK_A, EVENTOUT
STM32L476xx
UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
TIM3_CH2, TIM8_CH2,
38 38 F1 F2 F1 D1 64 E11 E11 97 97 F12 PC7 I/O FT_l - -
TIM3_CH3, TIM8_CH3,
39 39 F2 F3 F2 D2 65 E10 E10 98 98 E12 PC8 I/O FT_l - TSC_G4_IO3, LCD_SEG26, -
SDMMC1_D0, EVENTOUT
DS10198 Rev 9
TIM8_BKIN2, TIM3_CH4,
TIM8_CH4, TSC_G4_IO4,
OTG_FS_NOE, LCD_SEG27,
40 40 E1 E1 E1 D3 66 D12 D12 99 99 E11 PC9 I/O FT_l - -
SDMMC1_D1, SAI2_EXTCLK,
TIM8_BKIN2_COMP1,
EVENTOUT
MCO, TIM1_CH1, USART1_CK,
41 41 E2 E2 E2 E5 67 D11 D11 100 100 D12 PA8 I/O FT_l - OTG_FS_SOF, LCD_COM0, -
TIM1_CH2, USART1_TX,

42 42 E3 E3 E3 C1 68 D10 D10 101 101 D11 PA9 I/O FT_lu - LCD_COM1, TIM15_BKIN, OTG_FS_VBUS
EVENTOUT
TIM1_CH3, USART1_RX,
43 43 D2 D2 D2 C2 69 C12 C12 102 102 C12 PA10 I/O FT_lu - OTG_FS_ID, LCD_COM2, -
TIM1_CH4, TIM1_BKIN2,
USART1_CTS, CAN1_RX,
44 44 D1 D1 D1 D4 70 B12 B12 103 103 B12 PA11 I/O FT_u - OTG_FS_DM, -
TIM1_BKIN2_COMP1,
81/271
EVENTOUT
82/271

UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
TIM1_ETR, USART1_RTS_DE,
45 45 C1 C1 C1 C3 71 A12 A12 104 104 B11 PA12 I/O FT_u - CAN1_TX, OTG_FS_DP, -
EVENTOUT
PA13
(4) JTMS-SWDIO, IR_OUT,
46 46 C2 C2 C2 B1 72 A11 A11 105 105 C11 (JTMS- I/O FT -
OTG_FS_NOE, EVENTOUT
SWDIO)
47 47 B1 B1 B1 A1 - - - - - E8 VSS S - - - -
DS10198 Rev 9
48 48 A1 A1 A1 B2 73 C11 C11 106 106 E9 VDDUSB S - - - -

- - - - - B4 74 F11 F11 107 107 H8 VSS S - - - -
- - - - - A4 75 G11 G11 108 108 H7 VDD S - - - -
PA14
(4)
49 49 B2 B2 B2 D5 76 A10 A10 109 109 C10 (JTCK- I/O FT JTCK-SWCLK, EVENTOUT -
SWCLK)
JTDI, TIM2_CH1, TIM2_ETR,
SPI1_NSS, SPI3_NSS,
PA15 (4)
50 50 A2 C3 A2 B3 77 A9 A9 110 110 D10 I/O FT_l UART4_RTS_DE, TSC_G3_IO1, -
(JTDI)
LCD_SEG17, SAI2_FS_B,
EVENTOUT
SPI3_SCK, USART3_TX,
UART4_TX, TSC_G3_IO2,
51 51 D3 A2 D3 C4 78 B11 B11 111 111 B10 PC10 I/O FT_l - LCD_COM4/LCD_SEG28/ -
STM32L476xx
SAI2_SCK_B, EVENTOUT
STM32L476xx
UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
SPI3_MISO, USART3_RX,
UART4_RX, TSC_G3_IO3,
52 52 C3 D3 C3 A3 79 C10 C10 112 112 C9 PC11 I/O FT_l - LCD_COM5/LCD_SEG29/ -
SPI3_MOSI, USART3_CK,
UART5_TX, TSC_G3_IO4,
DS10198 Rev 9
53 53 B3 B3 B3 C5 80 B10 B10 113 113 B9 PC12 I/O FT_l - LCD_COM6/LCD_SEG30/ -

LCD_SEG42, SDMMC1_CK,
SAI2_SD_B, EVENTOUT
SPI2_NSS, DFSDM1_DATIN7,
- - - - - - 81 C9 C9 114 114 A11 PD0 I/O FT - -
CAN1_RX, FMC_D2, EVENTOUT
SPI2_SCK, DFSDM1_CKIN7,
- - - - - - 82 B9 B9 115 115 A10 PD1 I/O FT - -
CAN1_TX, FMC_D3, EVENTOUT
TIM3_ETR, USART3_RTS_DE,
UART5_RX, TSC_SYNC,
54 - A3 A3 A3 - 83 C8 C8 116 116 D9 PD2 I/O FT_l - LCD_COM7/LCD_SEG31/ -

LCD_SEG43, SDMMC1_CMD,
EVENTOUT
SPI2_MISO, DFSDM1_DATIN0,
- - - - - - 84 B8 B8 117 117 D8 PD3 I/O FT - USART2_CTS, FMC_CLK, -
EVENTOUT
SPI2_MOSI, DFSDM1_CKIN0,
- - - - E5 - 85 B7 B7 118 118 C8 PD4 I/O FT - USART2_RTS_DE, FMC_NOE, -
EVENTOUT
83/271
84/271

UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
USART2_TX, FMC_NWE,
- - - - D4 - 86 A6 A6 119 119 B8 PD5 I/O FT - -
EVENTOUT
- - - - - G5 - - - 120 120 A1 VSS S - - - -
- - - - E4 A2 - - - 121 121 - VDD S - - - -
DFSDM1_DATIN1, USART2_RX,
- - - - D5 - 87 B6 B6 122 122 A9 PD6 I/O FT - FMC_NWAIT, SAI1_SD_A, -
DS10198 Rev 9
EVENTOUT
DFSDM1_CKIN1, USART2_CK,
- - - - D6 - 88 A5 A5 123 123 A8 PD7 I/O FT - -
FMC_NE1, EVENTOUT
SPI3_SCK, USART1_TX,
FMC_NCE/FMC_NE2,
- - A4 A4 A4 D6 - D9 D9 124 124 C7 PG9 I/O FT_s - -
SAI2_SCK_A, TIM15_CH1N,
EVENTOUT
LPTIM1_IN1, SPI3_MISO,
USART1_RX, FMC_NE3,
- - B4 B4 B4 B5 - D8 D8 125 125 D7 PG10 I/O FT_s - -
SAI2_FS_A, TIM15_CH1,
EVENTOUT
LPTIM1_IN2, SPI3_MOSI,
- - C4 - C4 A5 - G3 G3 126 126 B7 PG11 I/O FT_s - USART1_CTS, SAI2_MCLK_A, -
TIM15_CH2, EVENTOUT
LPTIM1_ETR, SPI3_NSS,
STM32L476xx
- - C5 C4 C5 C6 - D7 D7 127 127 A7 PG12 I/O FT_s - USART1_RTS_DE, FMC_NE4, -
SAI2_SD_A, EVENTOUT
I2C1_SDA, USART1_CK,
- - B5 B5 B5 D7 - C7 C7 128 128 D6 PG13 I/O FT_fs - -
FMC_A24, EVENTOUT
STM32L476xx
UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
I2C1_SCL, FMC_A25,
- - A5 A5 A5 C7 - C6 - 129 129 A6 PG14 I/O FT_fs - -
EVENTOUT
- - - - - E1 - F7 F7 130 130 A12 VSS S - - - -
- - B6 B6 B6 E2 - G7 G7 131 131 E6 VDDIO2 S - - - -
LPTIM1_OUT, I2C1_SMBA,
- - - - - B7 - K1 K1 132 - B6 PG15 I/O FT_s - -
EVENTOUT
DS10198 Rev 9
PB3 JTDO-TRACESWO, TIM2_CH2,

(JTDO- (4) SPI1_SCK, SPI3_SCK,
55 54 A6 A6 A6 A7 89 A8 A8 133 132 C6 I/O FT_la COMP2_INM
TRACE USART1_RTS_DE, LCD_SEG7,
SWO) SAI1_SCK_B, EVENTOUT
NJTRST, TIM3_CH1, SPI1_MISO,
SPI3_MISO, USART1_CTS,
PB4 (4)
56 55 C6 C5 C6 E8 90 A7 A7 134 133 D5 I/O FT_la UART5_RTS_DE, TSC_G2_IO1, COMP2_INP
(NJTRST)
LCD_SEG8, SAI1_MCLK_B,
LPTIM1_IN1, TIM3_CH2,

I2C1_SMBA, SPI1_MOSI,
SPI3_MOSI, USART1_CK,
57 56 C7 E7 C7 C8 91 C5 C5 135 134 C5 PB5 I/O FT_la - UART5_CTS, TSC_G2_IO2, -
LCD_SEG9, COMP2_OUT,
SAI1_SD_B, TIM16_BKIN,
EVENTOUT
85/271
86/271

UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
LPTIM1_ETR, TIM4_CH1,
TIM8_BKIN2, I2C1_SCL,
DFSDM1_DATIN5, USART1_TX,
58 57 B7 E8 B7 B8 92 B5 B5 136 135 B5 PB6 I/O FT_fa - TSC_G2_IO3, COMP2_INP
TIM8_BKIN2_COMP2,
SAI1_FS_B, TIM16_CH1N,
EVENTOUT
DS10198 Rev 9
LPTIM1_IN2, TIM4_CH2,
TIM8_BKIN, I2C1_SDA,
DFSDM1_CKIN5, USART1_RX,
59 58 A7 B7 A7 A8 93 B4 B4 137 136 A5 PB7 I/O FT_fla - UART4_CTS, TSC_G2_IO4, COMP2_INM, PVD_IN
LCD_SEG21, FMC_NL,
TIM8_BKIN_COMP1,
TIM17_CH1N, EVENTOUT
60 59 D7 A7 D7 D8 94 A4 A4 138 137 A4 BOOT0 I - - - -
TIM4_CH3, I2C1_SCL,
DFSDM1_DATIN6, CAN1_RX,
61 60 E7 C6 E7 D9 95 A3 A3 139 138 A3 PB8 I/O FT_fl - LCD_SEG16, SDMMC1_D4, -
SAI1_MCLK_A, TIM16_CH1,
EVENTOUT
IR_OUT, TIM4_CH4, I2C1_SDA,
SPI2_NSS, DFSDM1_CKIN6,
62 61 E8 D7 E8 C9 96 B3 B3 140 139 C4 PB9 I/O FT_fl - CAN1_TX, LCD_COM3, -
STM32L476xx
SDMMC1_D5, SAI1_FS_A,
TIM17_CH1, EVENTOUT
TIM4_ETR, LCD_SEG36,
- - - - - - 97 C3 C3 141 140 A2 PE0 I/O FT_l - FMC_NBL0, TIM16_CH1, -
EVENTOUT
STM32L476xx
UFBGA132_SMPS
WLCSP72_SMPS
WLCSP99_SMPS
Pin name
LQFP144_SMPS
LQFP64_SMPS
(function
I/O structure
after
UFBGA132
UFBGA144
WLCSP72
WLCSP81
LQFP100
LQFP144
reset)
Pin type
LQFP64
Notes
LCD_SEG37, FMC_NBL1,
- - - - - - 98 A2 A2 142 141 B4 PE1 I/O FT_l - -
TIM17_CH1, EVENTOUT
- 62 - J1 - J3 - - C6 - 142 - VDD12 S - - - -
63 63 A8 A8 A8 J2 99 D3 D3 143 143 M1 VSS S - - - -
64 64 A9 A9 A9 J1 100 C4 C4 144 144 - VDD S - - - -
- - - - - F6 - - - - - - VSS S - - - -
DS10198 Rev 9
- - - - - F5 - - - - - - VSS S - - - -
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output
mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the
system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0351 reference manual.
3. OPAMPx_VINM pins are not available as additional functions on pins PA1 and PA7 on UFBGA packages. On UFBGA packages, use the OPAMPx_VINM dedicated pins.
4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are
activated.

87/271
Table 17. Alternate function AF0 to AF7(1)
88/271

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
Port TIM1/TIM2/ TIM1/TIM2/ USART1/

SYS_AF TIM5/TIM8/ TIM3/TIM4/ TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM1 USART2/
LPTIM1 TIM5 USART3
PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR - - - USART2_CTS

USART2_RTS_
PA1 - TIM2_CH2 TIM5_CH2 - - - -
DE
PA2 - TIM2_CH3 TIM5_CH3 - - - - USART2_TX
PA3 - TIM2_CH4 TIM5_CH4 - - - - USART2_RX
PA4 - - - - - SPI1_NSS SPI3_NSS USART2_CK
DS10198 Rev 9
PA5 - TIM2_CH1 TIM2_ETR TIM8_CH1N - SPI1_SCK - -
PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO - USART3_CTS
PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N - SPI1_MOSI - -

Port A
PA8 MCO TIM1_CH1 - - - - - USART1_CK
PA9 - TIM1_CH2 - - - - - USART1_TX
PA10 - TIM1_CH3 - - - - - USART1_RX
PA11 - TIM1_CH4 TIM1_BKIN2 - - - - USART1_CTS
USART1_RTS_
PA12 - TIM1_ETR - - - - -
DE
PA13 JTMS-SWDIO IR_OUT - - - - - -
PA14 JTCK-SWCLK - - - - - - -
STM32L476xx
PA15 JTDI TIM2_CH1 TIM2_ETR - - SPI1_NSS SPI3_NSS -
Table 17. Alternate function AF0 to AF7(1) (continued)
STM32L476xx

LPTIM1 TIM5 USART3
PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - - - USART3_CK

DFSDM1_ USART3_RTS_
PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - -
DATIN0 DE
PB2 RTC_OUT LPTIM1_OUT - - I2C3_SMBA - DFSDM1_CKIN0 -
JTDO- USART1_RTS_
PB3 TIM2_CH2 - - - SPI1_SCK SPI3_SCK
TRACESWO DE
PB4 NJTRST - TIM3_CH1 - - SPI1_MISO SPI3_MISO USART1_CTS
DS10198 Rev 9
PB5 - LPTIM1_IN1 TIM3_CH2 - I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK
DFSDM1_
PB6 - LPTIM1_ETR TIM4_CH1 TIM8_BKIN2 I2C1_SCL - USART1_TX
DATIN5
PB7 - LPTIM1_IN2 TIM4_CH2 TIM8_BKIN I2C1_SDA - DFSDM1_CKIN5 USART1_RX
Port B DFSDM1_
PB8 - - TIM4_CH3 - I2C1_SCL - -
DATIN6
PB9 - IR_OUT TIM4_CH4 - I2C1_SDA SPI2_NSS DFSDM1_CKIN6 -
DFSDM1_
PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK USART3_TX

DATIN7
PB11 - TIM2_CH4 - - I2C2_SDA - DFSDM1_CKIN7 USART3_RX
TIM1_BKIN_ DFSDM1_
PB12 - TIM1_BKIN - I2C2_SMBA SPI2_NSS USART3_CK
COMP2 DATIN1
PB13 - TIM1_CH1N - - I2C2_SCL SPI2_SCK DFSDM1_CKIN1 USART3_CTS
DFSDM1_ USART3_RTS_
PB14 - TIM1_CH2N - TIM8_CH2N I2C2_SDA SPI2_MISO
DATIN2 DE
89/271
PB15 RTC_REFIN TIM1_CH3N - TIM8_CH3N - SPI2_MOSI DFSDM1_CKIN2 -

90/271


LPTIM1 TIM5 USART3
DFSDM1_
PC0 - LPTIM1_IN1 - - I2C3_SCL - -
DATIN4
PC1 - LPTIM1_OUT - - I2C3_SDA - DFSDM1_CKIN4 -
DFSDM1_
PC2 - LPTIM1_IN2 - - - SPI2_MISO -
CKOUT
PC3 - LPTIM1_ETR - - - SPI2_MOSI - -
PC4 - - - - - - - USART3_TX
DS10198 Rev 9
PC5 - - - - - - - USART3_RX
PC6 - - TIM3_CH1 TIM8_CH1 - - DFSDM1_CKIN3 -
DFSDM1_
PC7 - - TIM3_CH2 TIM8_CH2 - - -
DATIN3
Port C
PC8 - - TIM3_CH3 TIM8_CH3 - - - -
PC9 - TIM8_BKIN2 TIM3_CH4 TIM8_CH4 - - - -
PC10 - - - - - - SPI3_SCK USART3_TX
PC11 - - - - - - SPI3_MISO USART3_RX
PC12 - - - - - - SPI3_MOSI USART3_CK
STM32L476xx
PC13 - - - - - - - -
PC14 - - - - - - - -
PC15 - - - - - - - -
STM32L476xx

LPTIM1 TIM5 USART3
DFSDM1_
PD0 - - - - - SPI2_NSS -
DATIN7
PD1 - - - - - SPI2_SCK DFSDM1_CKIN7 -
USART3_RTS_
PD2 - - TIM3_ETR - - - -
DE
DFSDM1_
PD3 - - - - - SPI2_MISO USART2_CTS
DATIN0
DS10198 Rev 9
USART2_RTS_
PD4 - - - - - SPI2_MOSI DFSDM1_CKIN0
DE
PD5 - - - - - - - USART2_TX
DFSDM1_
PD6 - - - - - - USART2_RX
DATIN1
Port D
PD7 - - - - - - DFSDM1_CKIN1 USART2_CK
PD8 - - - - - - - USART3_TX
PD9 - - - - - - - USART3_RX

PD10 - - - - - - - USART3_CK
PD11 - - - - - - - USART3_CTS
USART3_RTS_
PD12 - - TIM4_CH1 - - - -
DE
PD13 - - TIM4_CH2 - - - - -
PD14 - - TIM4_CH3 - - - - -
91/271
PD15 - - TIM4_CH4 - - - - -
92/271


LPTIM1 TIM5 USART3
PE0 - - TIM4_ETR - - - - -
PE1 - - - - - - - -
PE2 TRACECK - TIM3_ETR - - - - -
PE3 TRACED0 - TIM3_CH1 - - - - -
DFSDM1_
PE4 TRACED1 - TIM3_CH2 - - - -
DATIN3
PE5 TRACED2 - TIM3_CH3 - - - DFSDM1_CKIN3 -
DS10198 Rev 9
PE6 TRACED3 - TIM3_CH4 - - - - -

DFSDM1_
PE7 - TIM1_ETR - - - - -
DATIN2
PE8 - TIM1_CH1N - - - - DFSDM1_CKIN2 -
Port E
DFSDM1_
PE9 - TIM1_CH1 - - - - -
CKOUT
DFSDM1_
PE10 - TIM1_CH2N - - - - -
DATIN4
DFSDM1_
PE11 - TIM1_CH2 - - - - -
CKIN4
DFSDM1_
PE12 - TIM1_CH3N - - - SPI1_NSS -
DATIN5
PE13 - TIM1_CH3 - - - SPI1_SCK DFSDM1_CKIN5 -
STM32L476xx
TIM1_BKIN2_
PE14 - TIM1_CH4 TIM1_BKIN2 - SPI1_MISO - -
COMP2
TIM1_BKIN_
PE15 - TIM1_BKIN - - SPI1_MOSI - -
COMP1
STM32L476xx

LPTIM1 TIM5 USART3
PF0 - - - - I2C2_SDA - - -
PF1 - - - - I2C2_SCL - - -
PF2 - - - - I2C2_SMBA - - -
PF3 - - - - - - - -
PF4 - - - - - - - -
PF5 - - - - - - - -
DS10198 Rev 9
PF6 - TIM5_ETR TIM5_CH1 - - - - -

PF7 - - TIM5_CH2 - - - - -
Port F PF8 - - TIM5_CH3 - - - - -
PF9 - - TIM5_CH4 - - - - -
PF10 - - - - - - - -
PF11 - - - - - - - -
PF12 - - - - - - - -
DFSDM1_

PF13 - - - - - - -
DATIN6
PF14 - - - - - - DFSDM1_CKIN6 -
PF15 - - - - - - - -
93/271
94/271


LPTIM1 TIM5 USART3
PG0 - - - - - - - -
PG1 - - - - - - - -
PG2 - - - - - SPI1_SCK - -
PG3 - - - - - SPI1_MISO - -
PG4 - - - - - SPI1_MOSI - -
PG5 - - - - - SPI1_NSS - -
DS10198 Rev 9
PG6 - - - - I2C3_SMBA - - -
PG7 - - - - I2C3_SCL - - -
PG8 - - - - I2C3_SDA - - -
Port G
PG9 - - - - - - SPI3_SCK USART1_TX
PG10 - LPTIM1_IN1 - - - - SPI3_MISO USART1_RX
PG11 - LPTIM1_IN2 - - - - SPI3_MOSI USART1_CTS

USART1_RTS_
PG12 - LPTIM1_ETR - - - - SPI3_NSS
DE
PG13 - - - - I2C1_SDA - - USART1_CK
PG14 - - - - I2C1_SCL - - -
STM32L476xx
PG15 - LPTIM1_OUT - - I2C1_SMBA - - -
PH0 - - - - - - - -
Port H
PH1 - - - - - - - -
1. Refer to Table 18 for AF8 to AF15.
Table 18. Alternate function AF8 to AF15(1)
STM32L476xx
Port UART4/ SDMMC1/COMP1/ TIM2/TIM15/

UART5/ CAN1/TSC OTG_FS/QUADSPI LCD COMP2/FMC/ SAI1/SAI2 TIM16/TIM17/ EVENTOUT
LPUART1 SWPMI1 LPTIM2
PA0 UART4_TX - - - - SAI1_EXTCLK TIM2_ETR EVENTOUT

PA1 UART4_RX - - LCD_SEG0 - - TIM15_CH1N EVENTOUT
PA2 - - - LCD_SEG1 - SAI2_EXTCLK TIM15_CH1 EVENTOUT
PA3 - - - LCD_SEG2 - - TIM15_CH2 EVENTOUT
PA4 - - - - - SAI1_FS_B LPTIM2_OUT EVENTOUT
PA5 - - - - - - LPTIM2_ETR EVENTOUT
TIM1_BKIN_ TIM8_BKIN_
PA6 - - QUADSPI_BK1_IO3 LCD_SEG3 TIM16_CH1 EVENTOUT
COMP2 COMP2
DS10198 Rev 9
PA7 - - QUADSPI_BK1_IO2 LCD_SEG4 - - TIM17_CH1 EVENTOUT

Port A PA8 - - OTG_FS_SOF LCD_COM0 - - LPTIM2_OUT EVENTOUT
PA9 - - - LCD_COM1 - - TIM15_BKIN EVENTOUT
PA10 - - OTG_FS_ID LCD_COM2 - - TIM17_BKIN EVENTOUT
TIM1_BKIN2_
PA11 - CAN1_RX OTG_FS_DM - - - EVENTOUT
COMP1
PA12 - CAN1_TX OTG_FS_DP - - - - EVENTOUT

PA13 - - OTG_FS_NOE - - - - EVENTOUT
PA14 - - - - - - - EVENTOUT
UART4_RTS
PA15 TSC_G3_IO1 - LCD_SEG17 - SAI2_FS_B - EVENTOUT
_DE
95/271
96/271


PB0 - - QUADSPI_BK1_IO1 LCD_SEG5 COMP1_OUT - - EVENTOUT

PB1 - - QUADSPI_BK1_IO0 LCD_SEG6 - - LPTIM2_IN1 EVENTOUT
PB2 - - - - - - - EVENTOUT
PB3 - - - LCD_SEG7 - SAI1_SCK_B - EVENTOUT
UART5_RTS SAI1_MCLK_
PB4 TSC_G2_IO1 - LCD_SEG8 - TIM17_BKIN EVENTOUT
_DE B
PB5 UART5_CTS TSC_G2_IO2 - LCD_SEG9 COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT
TIM8_BKIN2_
DS10198 Rev 9
PB6 - TSC_G2_IO3 - - SAI1_FS_B TIM16_CH1N EVENTOUT

COMP2
TIM8_BKIN_
PB7 UART4_CTS TSC_G2_IO4 - LCD_SEG21 FMC_NL TIM17_CH1N EVENTOUT
COMP1
SAI1_MCLK_
Port B PB8 - CAN1_RX - LCD_SEG16 SDMMC1_D4 TIM16_CH1 EVENTOUT
A
PB9 - CAN1_TX - LCD_COM3 SDMMC1_D5 SAI1_FS_A TIM17_CH1 EVENTOUT
LPUART1_
PB10 - QUADSPI_CLK LCD_SEG10 COMP1_OUT SAI1_SCK_A - EVENTOUT
RX
PB11 LPUART1_TX - QUADSPI_NCS LCD_SEG11 COMP2_OUT - - EVENTOUT
LPUART1_
PB12 TSC_G1_IO1 - LCD_SEG12 SWPMI1_IO SAI2_FS_A TIM15_BKIN EVENTOUT
RTS_DE
LPUART1_
PB13 TSC_G1_IO2 - LCD_SEG13 SWPMI1_TX SAI2_SCK_A TIM15_CH1N EVENTOUT
CTS
STM32L476xx
SAI2_MCLK_
PB14 - TSC_G1_IO3 - LCD_SEG14 SWPMI1_RX TIM15_CH1 EVENTOUT
A
PB15 - TSC_G1_IO4 - LCD_SEG15 SWPMI1_SUSPEND SAI2_SD_A TIM15_CH2 EVENTOUT

STM32L476xx

LPUART1_
PC0 - - LCD_SEG18 - - LPTIM2_IN1 EVENTOUT
RX
PC1 LPUART1_TX - - LCD_SEG19 - - - EVENTOUT
PC2 - - - LCD_SEG20 - - - EVENTOUT
PC3 - - - LCD_VLCD - SAI1_SD_A LPTIM2_ETR EVENTOUT
SAI2_MCLK_
DS10198 Rev 9
PC6 - TSC_G4_IO1 - LCD_SEG24 SDMMC1_D6 - EVENTOUT

A
SAI2_MCLK_
PC7 - TSC_G4_IO2 - LCD_SEG25 SDMMC1_D7 - EVENTOUT
B
PC8 - TSC_G4_IO3 - LCD_SEG26 SDMMC1_D0 - - EVENTOUT
Port C TIM8_BKIN2_
PC9 - TSC_G4_IO4 OTG_FS_NOE LCD_SEG27 SDMMC1_D1 SAI2_EXTCLK EVENTOUT
COMP1
LCD_COM4/
PC10 UART4_TX TSC_G3_IO2 - LCD_SEG28/ SDMMC1_D2 SAI2_SCK_B - EVENTOUT
LCD_SEG40

LCD_COM5/
SAI2_MCLK_
PC11 UART4_RX TSC_G3_IO3 - LCD_SEG29/ SDMMC1_D3 - EVENTOUT
B
LCD_SEG41
LCD_COM6/
PC12 UART5_TX TSC_G3_IO4 - LCD_SEG30/ SDMMC1_CK SAI2_SD_B - EVENTOUT
LCD_SEG42
PC13 - - - - - - - EVENTOUT
PC14 - - - - - - - EVENTOUT
97/271
PC15 - - - - - - - EVENTOUT
98/271


PD0 - CAN1_RX - - FMC_D2 - - EVENTOUT

PD1 - CAN1_TX - - FMC_D3 - - EVENTOUT
LCD_COM7/
PD2 UART5_RX TSC_SYNC - LCD_SEG31/ SDMMC1_CMD - - EVENTOUT
LCD_SEG43
PD3 - - - - FMC_CLK - - EVENTOUT
PD4 - - - - FMC_NOE - - EVENTOUT
PD5 - - - - FMC_NWE - - EVENTOUT
DS10198 Rev 9
PD6 - - - - FMC_NWAIT SAI1_SD_A - EVENTOUT
Port D PD7 - - - - FMC_NE1 - - EVENTOUT
PD8 - - - LCD_SEG28 FMC_D13 - - EVENTOUT

SAI2_MCLK_
PD9 - - - LCD_SEG29 FMC_D14 - EVENTOUT
A
PD10 - TSC_G6_IO1 - LCD_SEG30 FMC_D15 SAI2_SCK_A - EVENTOUT
PD11 - TSC_G6_IO2 - LCD_SEG31 FMC_A16 SAI2_SD_A LPTIM2_ETR EVENTOUT
PD12 - TSC_G6_IO3 - LCD_SEG32 FMC_A17 SAI2_FS_A LPTIM2_IN1 EVENTOUT
PD13 - TSC_G6_IO4 - LCD_SEG33 FMC_A18 - LPTIM2_OUT EVENTOUT
STM32L476xx
STM32L476xx

PE0 - - - LCD_SEG36 FMC_NBL0 - TIM16_CH1 EVENTOUT

PE1 - - - LCD_SEG37 FMC_NBL1 - TIM17_CH1 EVENTOUT
SAI1_MCLK_
PE2 - TSC_G7_IO1 - LCD_SEG38 FMC_A23 - EVENTOUT
A
PE3 - TSC_G7_IO2 - LCD_SEG39 FMC_A19 SAI1_SD_B - EVENTOUT
PE4 - TSC_G7_IO3 - - FMC_A20 SAI1_FS_A - EVENTOUT
PE5 - TSC_G7_IO4 - - FMC_A21 SAI1_SCK_A - EVENTOUT
PE6 - - - - FMC_A22 SAI1_SD_A - EVENTOUT
DS10198 Rev 9
PE7 - - - - FMC_D4 SAI1_SD_B - EVENTOUT

Port E
PE8 - - - - FMC_D5 SAI1_SCK_B - EVENTOUT
PE9 - - - - FMC_D6 SAI1_FS_B - EVENTOUT
SAI1_MCLK_
PE10 - TSC_G5_IO1 QUADSPI_CLK - FMC_D7 - EVENTOUT
B
PE11 - TSC_G5_IO2 QUADSPI_NCS - FMC_D8 - - EVENTOUT
PE12 - TSC_G5_IO3 QUADSPI_BK1_IO0 - FMC_D9 - - EVENTOUT
PE13 - TSC_G5_IO4 QUADSPI_BK1_IO1 - FMC_D10 - - EVENTOUT

PE14 - - QUADSPI_BK1_IO2 - FMC_D11 - - EVENTOUT
PE15 - - QUADSPI_BK1_IO3 - FMC_D12 - - EVENTOUT
99/271
100/271


PF0 - - - - FMC_A0 - - EVENTOUT

PF6 - - - - - SAI1_SD_B - EVENTOUT
DS10198 Rev 9
SAI1_MCLK_
PF7 - - - - - - EVENTOUT
Port F B
PF8 - - - - - SAI1_SCK_B - EVENTOUT
PF9 - - - - - SAI1_FS_B TIM15_CH1 EVENTOUT
PF10 - - - - - - TIM15_CH2 EVENTOUT
PF11 - - - - - - - EVENTOUT
PF14 - TSC_G8_IO1 - - FMC_A8 - - EVENTOUT
PF15 - TSC_G8_IO2 - - FMC_A9 - - EVENTOUT
STM32L476xx
STM32L476xx

PG0 - TSC_G8_IO3 - - FMC_A10 - - EVENTOUT

PG1 - TSC_G8_IO4 - - FMC_A11 - - EVENTOUT
PG2 - - - - FMC_A12 SAI2_SCK_B - EVENTOUT
PG3 - - - - FMC_A13 SAI2_FS_B - EVENTOUT
SAI2_MCLK_
PG4 - - - - FMC_A14 - EVENTOUT
B
LPUART1_
PG5 - - - FMC_A15 SAI2_SD_B - EVENTOUT
CTS
DS10198 Rev 9
LPUART1_
PG6 - - - - - - EVENTOUT
RTS_DE
PG7 LPUART1_TX - - - FMC_INT - - EVENTOUT
Port G LPUART1_
PG8 - - - - - - EVENTOUT
RX
FMC_NCE/
PG9 - - - - SAI2_SCK_A TIM15_CH1N EVENTOUT
FMC_NE2
PG10 - - - - FMC_NE3 SAI2_FS_A TIM15_CH1 EVENTOUT

SAI2_MCLK_
PG11 - - - - - TIM15_CH2 EVENTOUT
A
PG12 - - - - FMC_NE4 SAI2_SD_A - EVENTOUT
PG13 - - - - FMC_A24 - - EVENTOUT
PG14 - - - - FMC_A25 - - EVENTOUT
PG15 - - - - - - - EVENTOUT
101/271
102/271


PH0 - - - - - - - EVENTOUT
Port H
PH1 - - - - - - - EVENTOUT
1. Refer to Table 17 for AF0 to AF7.
DS10198 Rev 9
STM32L476xx
STM32L476xx Memory mapping
5 Memory mapping
Figure 18. STM32L476xx memory map
0xFFFF FFFF 0xBFFF FFFF

Cortex™-M4 Reserved
0xA000 1400
with FPU
7 Internal
QUADSPI registers
Peripherals 0xA000 1000
FMC registers
0xE000 0000 0xA000 0000
0x5FFF FFFF
Reserved
6 0x5006 0C00
AHB2
0x4800 0000
0xC000 0000 Reserved
0x4002 4400
FMC and AHB1
5 QUADSPI 0x4002 0000
registers Reserved
0x4001 6400
0xA000 0000 APB2
QUADSPI flash 0x4001 0000
bank Reserved
0x4000 9800
4 0x9000 0000
APB1
0x4000 0000
0x8000 0000 0x1FFF FFFF

Reserved
0x1FFF F810
Option Bytes
3 0x1FFF F800
Reserved
0x1FFF F000
0x6000 0000 System memory
0x1FFF 8000
Reserved
0x1FFF 7810
Options Bytes
2 0x1FFF 7800
Reserved
0x1FFF 7400
Peripherals OTP area
0x4000 0000
0x1FFF 7000
System memory
1 0x1FFF 0000
Reserved
0x1000 8000
SRAM1
0x2000 0000 SRAM2
0x1000 0000
Reserved
0 CODE
0x0810 0000
Flash memory
0x0800 0000
Reserved
0x0000 0000
0x0010 0000 Flash, system memory
or SRAM, depending on
0x0000 0000 BOOT configuration
Reserved
MS34100V3
DS10198 Rev 9 103/271

107
Memory mapping STM32L476xx
Table 19. STM32L476xx memory map and peripheral register boundary addresses(1)
Size
Bus Boundary address Peripheral
(bytes)
0xA000 1000 - 0xA000 13FF 1 KB QUADSPI

AHB3
0xA000 0000 - 0xA000 0FFF 4 KB FMC
0x5006 0800 - 0x5006 0BFF 1 KB RNG
0x5004 0400 - 0x5006 07FF 129 KB Reserved
0x5004 0000 - 0x5004 03FF 1 KB ADC
0x5000 0000 - 0x5003 FFFF 16 KB OTG_FS
0x4800 2000 - 0x4FFF FFFF ~127 MB Reserved
0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH
AHB2 0x4800 1800 - 0x4800 1BFF 1 KB GPIOG
0x4800 1400 - 0x4800 17FF 1 KB GPIOF
0x4800 1000 - 0x4800 13FF 1 KB GPIOE
0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD
0x4800 0800 - 0x4800 0BFF 1 KB GPIOC
0x4800 0400 - 0x4800 07FF 1 KB GPIOB
0x4800 0000 - 0x4800 03FF 1 KB GPIOA
- 0x4002 4400 - 0x47FF FFFF ~127 MB Reserved
0x4002 4000 - 0x4002 43FF 1 KB TSC
0x4002 3400 - 0x4002 3FFF 1 KB Reserved
0x4002 3000 - 0x4002 33FF 1 KB CRC
0x4002 2000 - 0x4002 23FF 1 KB FLASH registers
AHB1
0x4002 1000 - 0x4002 13FF 1 KB RCC
0x4002 0400 - 0x4002 07FF 1 KB DMA2
0x4002 0000 - 0x4002 03FF 1 KB DMA1
104/271 DS10198 Rev 9

(continued)
Size
(bytes)
0x4001 6400 - 0x4001 FFFF 39 KB Reserved

0x4001 6000 - 0x4000 63FF 1 KB DFSDM1
0x4001 5C00 - 0x4000 5FFF 1 KB Reserved
0x4001 5800 - 0x4000 5BFF 1 KB SAI2
APB2 0x4001 5400 - 0x4000 57FF 1 KB SAI1
0x4001 4C00 - 0x4000 53FF 2 KB Reserved
0x4001 4800 - 0x4001 4BFF 1 KB TIM17
0x4001 4400 - 0x4001 47FF 1 KB TIM16
0x4001 4000 - 0x4001 43FF 1 KB TIM15
0x4001 3C00 - 0x4001 3FFF 1 KB Reserved
0x4001 3800 - 0x4001 3BFF 1 KB USART1
0x4001 3400 - 0x4001 37FF 1 KB TIM8
0x4001 3000 - 0x4001 33FF 1 KB SPI1
0x4001 2C00 - 0x4001 2FFF 1 KB TIM1
0x4001 2800 - 0x4001 2BFF 1 KB SDMMC1
APB2 0x4001 2000 - 0x4001 27FF 2 KB Reserved
0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL
0x4001 0800- 0x4001 1BFF 5 KB Reserved
0x4001 0400 - 0x4001 07FF 1 KB EXTI
0x4001 0200 - 0x4001 03FF COMP
0x4001 0030 - 0x4001 01FF 1 KB VREFBUF
0x4001 0000 - 0x4001 002F SYSCFG
DS10198 Rev 9 105/271

107
Memory mapping STM32L476xx
(continued)
Size
(bytes)
0x4000 9800 - 0x4000 FFFF 26 KB Reserved

0x4000 9400 - 0x4000 97FF 1 KB LPTIM2
0x4000 8C00 - 0x4000 93FF 2 KB Reserved
0x4000 8800 - 0x4000 8BFF 1 KB SWPMI1
0x4000 8400 - 0x4000 87FF 1 KB Reserved
0x4000 8000 - 0x4000 83FF 1 KB LPUART1
0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1
0x4000 7800 - 0x4000 7BFF 1 KB OPAMP
0x4000 7400 - 0x4000 77FF 1 KB DAC1
0x4000 7000 - 0x4000 73FF 1 KB PWR
APB1
0x4000 6400 - 0x4000 67FF 1 KB CAN1
0x4000 6000 - 0x4000 63FF 1 KB Reserved
0x4000 5C00- 0x4000 5FFF 1 KB I2C3
0x4000 5800 - 0x4000 5BFF 1 KB I2C2
0x4000 5400 - 0x4000 57FF 1 KB I2C1
0x4000 5000 - 0x4000 53FF 1 KB UART5
0x4000 4C00 - 0x4000 4FFF 1 KB UART4
0x4000 4800 - 0x4000 4BFF 1 KB USART3
0x4000 4400 - 0x4000 47FF 1 KB USART2
106/271 DS10198 Rev 9

(continued)
Size
(bytes)
0x4000 4000 - 0x4000 43FF 1 KB Reserved

0x4000 3C00 - 0x4000 3FFF 1 KB SPI3
0x4000 3800 - 0x4000 3BFF 1 KB SPI2
0x4000 3400 - 0x4000 37FF 1 KB Reserved
0x4000 3000 - 0x4000 33FF 1 KB IWDG
0x4000 2C00 - 0x4000 2FFF 1 KB WWDG
0x4000 2800 - 0x4000 2BFF 1 KB RTC
APB1 0x4000 2400 - 0x4000 27FF 1 KB LCD
0x4000 1800 - 0x4000 23FF 3 KB Reserved
0x4000 1400 - 0x4000 17FF 1 KB TIM7
0x4000 1000 - 0x4000 13FF 1 KB TIM6
0x4000 0C00- 0x4000 0FFF 1 KB TIM5
0x4000 0800 - 0x4000 0BFF 1 KB TIM4
0x4000 0400 - 0x4000 07FF 1 KB TIM3
0x4000 0000 - 0x4000 03FF 1 KB TIM2
1. The gray color is used for reserved boundary addresses.
DS10198 Rev 9 107/271

107
Electrical characteristics STM32L476xx
6 Electrical characteristics
6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 19.
6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 20.
Figure 19. Pin loading conditions Figure 20. Pin input voltage
MCU pin MCU pin

C = 50 pF VIN
MS19210V1 MS19211V1
108/19 DS10198 Rev 9

STM32L476xx Electrical characteristics
6.1.6 Power supply scheme
Figure 21. Power supply scheme
VBAT
VBAT
VBAT
Backup circuitry
1.55 – 3.6 V Backup
(LSE,circuitry
RTC,
Backup circuitry
1.55 (LSE,registers)
RTC,
1.55 ––3.6
3.6VV Backup
(LSE, RTC,
Backup registers)
Backup registers)
Power switch
Power
Powerswitch
switch
VVDD 2 x VDD12
DD VVCORE
CORE
nnx xVDD
VDD
1.05 – 1.32 V Regulator
Regulator
VVDDIO1
DDIO1
OUT
OUT
Level shifter
shifter
VDD Kernel
Kernellogic
logic
IO
IO VCORE
nnxx100
100nF
nF GPIOs (CPU, Digital
(CPU, Digital
nGPIOs
x VDD logic
logic
Level
+1xx4.7
+1 4.7μF
μF IN
Regulator
IN && Memories)
Memories)
VDDIO1
n nx xVSS
VSS
OUT
Level shifter
Kernel logic
n x 100 nF VDDIO2 IO (CPU, Digital
VDDIO2 GPIOs logic
+1 x 4.7 μF IN & Memories)
m xmVDDIO2
x VDDIO2
VDDIO2
VDDIO2
m x100 nF OUT
shifter
m x100 nF n x VSS OUT

shifter
+4.7 μF IO
+4.7 μF GPIOs IO
logic
Level
GPIOs IN logic
Level
IN
VDDIO2 m x VSS
mm x VSS
x VDDIO2
VDDIO2
VDDA
m x100 nF VDDA VDDA OUT
Level shifter
VDDA
+4.7 μF IO
VREF GPIOs ADCs/
logic
10 nF VREF+ DACs/
ADCs/
IN
10
+1nF
μF VVREF+
REF-
OPAMPs/
DACs/
m x VSS COMPs/
OPAMPs/
+1 μF
100 nF +1 μF VREF- VREF
COMPs/
VSSA VREF
VDDA
VDDA
VSSA
VREF MS35001V1
ADCs/
10 nF VREF+ DACs/
+1 μF OPAMPs/
100 nF +1 μF VREF- COMPs/ MS35001V2
VREFBUF
VSSA
MSv45701V1
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
DS10198 Rev 9 109/19

233
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
110/19 DS10198 Rev 9

6.1.7 Current consumption measurement
Figure 22. Current consumption measurement scheme with and without external
SMPS power supply
IDD_USB
VDDUSB
IDD_USB
VDDUSB
IDD_VBAT
VBAT
IDD_VBAT
VBAT
IDD
VDD12
SMPS
IDD
VDD VDD
VDDIO2 VDDIO2
IDDA IDDA
VDDA VDDA
MSv45730V1
6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics,
Table 21: Current characteristics and Table 22: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
Table 20. Voltage characteristics(1)

Symbol Ratings Min Max Unit
External main supply voltage (including

VDDX - VSS VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT, -0.3 4.0 V
VREF+)
Range 1 -0.3
VDD12 - VSS External SMPS supply voltage 1.4 V
Range 2 -0.3
min (VDD, VDDA, VDDIO2, VDDUSB,
Input voltage on FT_xxx pins VSS-0.3
VLCD) + 4.0(3)(4)
VIN(2) Input voltage on TT_xx pins VSS-0.3 4.0 V

Input voltage on BOOT0 pin VSS 9.0
Input voltage on any other pins VSS-0.3 4.0
DS10198 Rev 9 111/19

233
Table 20. Voltage characteristics(1) (continued)

Symbol Ratings Min Max Unit
Variations between different VDDX power

|∆VDDx| - 50 mV
pins of the same domain
Variations between all the different ground
|VSSx-VSS| - 50 mV
pins(5)
Allowed voltage difference for VREF+ >
VREF+ - VDDA - 0.4 V
VDDA
1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT) and ground (VSS, VSSA) pins must always be connected to the
external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 21: Current characteristics for the maximum allowed injected
current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
Table 21. Current characteristics

Symbol Ratings Max Unit
∑IVDD Total current into sum of all VDD power lines (source)(1)(2) 150
(1)
∑IVSS Total current out of sum of all VSS ground lines (sink) 150
IVDD(PIN) Maximum current into each VDD power pin (source)(1)(2) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100
Output current sunk by any I/O and control pin except FT_f 20
IIO(PIN) Output current sunk by any FT_f pin 20
Output current sourced by any I/O and control pin 20 mA
Total output current sunk by sum of all I/Os and control pins(3) 100
∑IIO(PIN)
(3)
Total output current sourced by sum of all I/Os and control pins 100
Injected current on FT_xxx, TT_xx, RST and B pins, except PA4,
-5/+0(5)
IINJ(PIN)(4) PA5
Injected current on PA4, PA5 -5/0
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(6) 25
1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. Valid also for VDD12 on SMPS packages.
3. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
4. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
5. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 20: Voltage
characteristics for the minimum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).
112/19 DS10198 Rev 9

Table 22. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 150 °C
DS10198 Rev 9 113/19

233
6.3 Operating conditions
6.3.1 General operating conditions
Table 23. General operating conditions

Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency - 0 80

fPCLK1 Internal APB1 clock frequency - 0 80 MHz
fPCLK2 Internal APB2 clock frequency - 0 80
1.71
VDD Standard operating voltage - (1) 3.6 V
Full frequency range 1.08

VDD12 Standard operating voltage 1.32 V
Up to 26 MHz 1.05
At least one I/O in PG[15:2] used 1.08 3.6
VDDIO2 PG[15:2] I/Os supply voltage V
PG[15:2] not used 0 3.6
ADC or COMP used 1.62
DAC or OPAMP used 1.8
VDDA Analog supply voltage VREFBUF used 2.4 3.6 V
ADC, DAC, OPAMP, COMP,

0
VREFBUF not used
VBAT Backup operating voltage - 1.55 3.6 V
USB used 3.0 3.6
VDDUSB USB supply voltage V
USB not used 0 3.6
TT_xx I/O -0.3 VDDIOx+0.3
BOOT0 0 9
VIN I/O input voltage Min(Min(VDD, VDDA, V
VDDIO2, VDDUSB,
All I/O except BOOT0 and TT_xx -0.3
VLCD)+3.6 V,
5.5 V)(2)(3)
LQFP144 - - 625
LQFP100 - - 476
LQFP64 - - 444
Power dissipation at
TA = 85 °C for suffix 6 UFBGA144 - - 377
PD mW
or UFBGA132 - - 363
TA = 105 °C for suffix 7(4)
WLCSP81 - - 487
WLCSP72 - - 434
WLCSP99 - - 476
114/19 DS10198 Rev 9

Table 23. General operating conditions (continued)

LQFP144 - - 156
LQFP100 - - 119
LQFP64 - - 111
Power dissipation at TA = UFBGA144 - - 94

PD mW
125 °C for suffix 3(4) UFBGA132 - - 90
WLCSP81 - - 121
WLCSP72 - - 108
WLCSP99 - - 119
Ambient temperature for the Maximum power dissipation –40 85

suffix 6 version Low-power dissipation(5) –40 105

TA °C
suffix 7 version Low-power dissipation (5)
–40 125

suffix 3 version Low-power dissipation(5) –40 130
Suffix 6 version –40 105
TJ Junction temperature range Suffix 7 version –40 125 °C
Suffix 3 version –40 130
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between Min(VDD, VDDA, VDDIO2, VDDUSB, VLCD)+3.6 V and 5.5V.
3. For operation with voltage higher than Min (VDD, VDDA, VDDIO2, VDDUSB, VLCD) +0.3 V, the internal Pull-up and Pull-Down
resistors must be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.10: Thermal
characteristics).
5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.10:
Thermal characteristics).
6.3.2 Operating conditions at power-up / power-down

The parameters given in Table 24 are derived from tests performed under the ambient
temperature condition summarized in Table 23.
Table 24. Operating conditions at power-up / power-down(1)

VDD rise time rate 0 ∞

tVDD - µs/V
VDD fall time rate 10 ∞
VDDA rise time rate 0 ∞
tVDDA - µs/V
VDDA fall time rate 10 ∞
DS10198 Rev 9 115/19

233
Table 24. Operating conditions at power-up / power-down(1) (continued)

VDDUSB rise time rate 0 ∞

tVDDUSB - µs/V
VDDUSB fall time rate 10 ∞
VDDIO2 rise time rate 0 ∞
tVDDIO2 - µs/V
VDDIO2 fall time rate 10 ∞
1. At power-up, the VDD12 voltage should not be forced externally.
The requirements for power-up/down sequence specified in Section 3.9.1: Power supply
schemes must be respected.
6.3.3 Embedded reset and power control block characteristics

temperature conditions summarized in Table 23: General operating conditions.
Table 25. Embedded reset and power control block characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit
Reset temporization after

tRSTTEMPO(2) VDD rising - 250 400 μs
BOR0 is detected
Rising edge 1.62 1.66 1.7
VBOR0(2) Brown-out reset threshold 0 V
Falling edge 1.6 1.64 1.69
Rising edge 2.06 2.1 2.14
VBOR1 Brown-out reset threshold 1 V
Falling edge 1.96 2 2.04
Rising edge 2.26 2.31 2.35
Rising edge 2.56 2.61 2.66
Rising edge 2.85 2.90 2.95
Programmable voltage Rising edge 2.1 2.15 2.19

VPVD0 V
detector threshold 0 Falling edge 2 2.05 2.1
Rising edge 2.26 2.31 2.36
VPVD1 PVD threshold 1 V
Rising edge 2.41 2.46 2.51
Rising edge 2.56 2.61 2.66
Rising edge 2.69 2.74 2.79
116/19 DS10198 Rev 9

Table 25. Embedded reset and power control block characteristics (continued)
Rising edge 2.85 2.91 2.96

Rising edge 2.92 2.98 3.04
Hysteresis in
continuous - 20 -
Vhyst_BORH0 Hysteresis voltage of BORH0 mode mV
Hysteresis in
- 30 -
other mode
Hysteresis voltage of BORH
Vhyst_BOR_PVD - - 100 - mV
(except BORH0) and PVD
IDD BOR(3) (except BOR0) and
(2) - - 1.1 1.6 µA
(BOR_PVD) PVD consumption from VDD
VDDUSB peripheral voltage
VPVM1 - 1.18 1.22 1.26 V
monitoring
VDDIO2 peripheral voltage
VPVM2 - 0.92 0.96 1 V
monitoring
VDDA peripheral voltage Rising edge 1.61 1.65 1.69

VPVM3 V
monitoring Falling edge 1.6 1.64 1.68
VDDA peripheral voltage Rising edge 1.78 1.82 1.86

VPVM4 V
monitoring Falling edge 1.77 1.81 1.85
Vhyst_PVM3 PVM3 hysteresis - - 10 - mV
Vhyst_PVM4 PVM4 hysteresis - - 10 - mV
IDD
PVM1 and PVM2
(PVM1/PVM2) - - 0.2 - µA
(2) consumption from VDD
IDD
PVM3 and PVM4
(PVM3/PVM4) - - 2 - µA
(2) consumption from VDD
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.
DS10198 Rev 9 117/19

233
6.3.4 Embedded voltage reference

temperature and supply voltage conditions summarized in Table 23: General operating
conditions.
Table 26. Embedded internal voltage reference

Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage –40 °C < TA < +130 °C 1.182 1.212 1.232 V
ADC sampling time when
tS_vrefint (1) reading the internal reference - 4(2) - - µs
voltage
Start time of reference voltage
tstart_vrefint - - 8 12(2) µs
buffer when ADC is enable
VREFINT buffer consumption
from VDD when converted by - - 12.5 20(2) µA
IDD(VREFINTBUF)
ADC
Internal reference voltage
∆VREFINT spread over the temperature VDD = 3 V - 5 7.5(2) mV
range
Average temperature
TCoeff –40°C < TA < +130°C - 30 50(2) ppm/°C
coefficient
ACoeff Long term stability 1000 hours, T = 25°C - 300 1000(2) ppm
VDDCoeff Average voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V
VREFINT_DIV1 1/4 reference voltage 24 25 26
%
VREFINT_DIV2 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3 3/4 reference voltage 74 75 76
1. The shortest sampling time can be determined in the application by multiple iterations.
118/19 DS10198 Rev 9

Figure 23. VREFINT versus temperature
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
-40 -20 0 20 40 60 80 100 120 °C
Mean Min Max
MSv40169V1
DS10198 Rev 9 119/19

233
6.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 22: Current consumption
measurement scheme with and without external SMPS power supply.
The IDD_ALL parameters given in Table 27 to Table 49 represent the total MCU consumption
including the current supplying VDD, VDD12, VDDIO2, VDDA, VLCD, VDDUSB and VBAT.
Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “Number of wait states according
to CPU clock (HCLK) frequency” available in the RM0351 reference manual).
• When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 27 to Table 50 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 23: General
operating conditions.
120/19 DS10198 Rev 9

STM32L476xx
running from flash, ART enable (Cache ON Prefetch OFF)
Conditions TYP MAX(1)
Symbol Parameter Unit
- Voltage fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
scaling
26 MHz 2.88 2.93 3.05 3.23 3.58 3.20 3.37 3.51 3.93 4.76
16 MHz 1.83 1.87 1.98 2.16 2.49 2.01 2.16 2.30 2.72 3.34
8 MHz 0.98 1.02 1.12 1.29 1.62 1.10 1.17 1.31 1.73 2.56
Range 2 4 MHz 0.55 0.59 0.69 0.85 1.18 0.61 0.70 0.89 1.24 1.95
2 MHz 0.34 0.37 0.47 0.64 0.96 0.37 0.46 0.64 0.98 1.71
fHCLK = fHSE up to 1 MHz 0.23 0.26 0.36 0.53 0.85 0.27 0.33 0.50 0.86 1.57
48MHz included,
Supply 100 kHz 0.14 0.17 0.27 0.43 0.75 0.17 0.21 0.38 0.74 1.44
IDD_ALL bypass mode
current in mA
DS10198 Rev 9
(Run) PLL ON above 80 MHz 10.2 10.3 10.5 10.7 11.1 11.22 11.8 12.1 12.5 13.3
Run mode
48 MHz all
peripherals disable 72 MHz 9.24 9.31 9.47 9.69 10.1 10.16 10.7 11.0 11.4 12.2
64 MHz 8.25 8.32 8.46 8.68 9.09 9.08 9.6 9.9 10.3 11.1
Range 1 48 MHz 6.28 6.35 6.5 6.72 7.11 6.91 7.3 7.6 8.0 8.8
32 MHz 4.24 4.30 4.44 4.65 5.04 4.66 4.97 5.26 5.67 6.51
24 MHz 3.21 3.27 3.4 3.61 3.98 3.53 3.76 4.05 4.46 5.30
16 MHz 2.19 2.24 2.36 2.56 2.94 2.41 2.66 2.95 3.16 3.99
2 MHz 272 303 413 592 958 330 393 579 954 1704
Supply
1 MHz 154 184 293 473 835 195 265 457 822 1572
Electrical characteristics
IDD_ALL current in fHCLK = fMSI
µA
(LPRun) Low-power all peripherals disable 400 kHz 78 108 217 396 758 110 180 380 755 1505
run mode
100 kHz 42 73 182 360 723 75 138 331 706 1456
1. Guaranteed by characterization results, unless otherwise specified.
121/19
122/19
(VDD12 = 1.10 V)
Conditions(1) TYP
- fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C
80 MHz 3.67 3.70 3.77 3.85 3.99

72 MHz 3.32 3.35 3.40 3.48 3.63
64 MHz 2.97 2.99 3.04 3.12 3.27
48 MHz 2.26 2.28 2.34 2.42 2.56
32 MHz 1.52 1.55 1.60 1.67 1.81
Supply current in Run fHCLK = fHSE up to 48MHz included, bypass mode 24 MHz 1.15 1.18 1.22 1.30 1.43
IDD_ALL(Run) mA
mode PLL ON above 48 MHz all peripherals disable 16 MHz 0.79 0.81 0.85 0.92 1.06
DS10198 Rev 9
8 MHz 0.42 0.44 0.48 0.56 0.70

4 MHz 0.24 0.25 0.30 0.37 0.51
2 MHz 0.15 0.16 0.20 0.28 0.41
1 MHz 0.10 0.11 0.16 0.23 0.37
100 kHz 0.06 0.07 0.12 0.19 0.32
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,
VDD12 = 1.10 V
STM32L476xx
STM32L476xx
running from flash, ART disable
Voltage
- fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
scaling
26 MHz 3.15 3.19 3.31 3.50 3.85 3.47 3.70 3.84 4.26 4.88
16 MHz 2.24 2.28 2.39 2.57 2.90 2.46 2.60 2.74 3.16 3.78
8 MHz 1.26 1.29 1.40 1.57 1.89 1.40 1.50 1.64 2.06 2.68
Range 2 4 MHz 0.71 0.75 0.85 1.02 1.34 0.79 0.88 1.06 1.38 2.21
2 MHz 0.42 0.45 0.55 0.72 1.04 0.46 0.55 0.73 1.09 1.88
fHCLK = fHSE up to
48MHz included, 1 MHz 0.27 0.30 0.40 0.57 0.89 0.30 0.38 0.57 0.90 1.61
Supply
IDD_ALL bypass mode 100 kHz 0.14 0.17 0.27 0.43 0.75 0.17 0.22 0.40 0.74 1.44
current in mA
Run mode
48 MHz all
72 MHz 9.06 9.13 9.28 9.51 9.92 9.97 10.36 10.65 11.06 11.69
peripherals disable
DS10198 Rev 9
64 MHz 8.96 9.04 9.22 9.48 9.92 9.86 10.25 10.54 10.95 11.79
Range 1 48 MHz 7.64 7.72 7.91 8.17 8.62 8.40 8.76 8.90 9.52 10.36
32 MHz 5.49 5.57 5.74 5.98 6.40 6.04 6.40 6.69 7.10 7.94
24 MHz 4.16 4.22 4.36 4.57 4.96 4.60 4.86 5.15 5.56 6.19
16 MHz 2.93 2.99 3.13 3.35 3.75 3.22 3.43 3.72 4.13 4.97
2 MHz 358 392 503 683 1050 435 501 694 1069 1819
Supply
IDD_ALL current in fHCLK = fMSI 1 MHz 197 230 340 519 880 245 312 512 887 1637
µA
(LPRun) Low-power all peripherals disable 400 kHz 97 126 235 414 778 130 202 402 777 1527
run
100 kHz 47 77 186 365 726 85 147 347 711 1472
123/19
124/19
ART disable and power supplied by external SMPS (VDD12 = 1.10 V)
Conditions(1) TYP
- fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C
80 MHz 3.59 3.63 3.70 3.81 3.95

72 MHz 3.26 3.28 3.34 3.42 3.57
64 MHz 3.22 3.25 3.31 3.41 3.57
48 MHz 2.75 2.78 2.84 2.94 3.10
32 MHz 1.97 2.00 2.06 2.15 2.30
Supply current in Run fHCLK = fHSE up to 48MHz included, bypass mode 24 MHz 1.50 1.52 1.57 1.64 1.78
IDD_ALL(Run) mA
mode PLL ON above 48 MHz all peripherals disable 16 MHz 1.05 1.07 1.13 1.20 1.35
8 MHz 0.54 0.56 0.60 0.68 0.82
DS10198 Rev 9
4 MHz 0.31 0.32 0.37 0.44 0.58

2 MHz 0.18 0.19 0.24 0.31 0.45
1 MHz 0.12 0.13 0.17 0.25 0.38
100 kHz 0.06 0.07 0.12 0.19 0.32
VDD12 = 1.10 V
STM32L476xx
STM32L476xx
running from SRAM1
Voltage 105 125 105 125
- fHCLK 25 °C 55 °C 85 °C 25 °C 55 °C 85 °C
scaling °C °C °C °C
26 MHz 2.88 2.94 3.05 3.23 3.58 3.18 3.26 3.40 4.02 4.65
16 MHz 1.83 1.87 1.98 2.15 2.50 2.01 2.16 2.30 2.72 3.34
8 MHz 0.97 1.00 1.11 1.27 1.62 1.07 1.16 1.32 1.73 2.36
Range 2 4 MHz 0.54 0.57 0.67 0.84 1.18 0.59 0.69 0.88 1.23 1.96
2 MHz 0.33 0.36 0.46 0.62 0.96 0.37 0.45 0.63 0.98 1.70
fHCLK = fHSE up to
48MHz included, 1 MHz 0.22 0.25 0.35 0.51 0.85 0.25 0.33 0.50 0.86 1.57
Supply
IDD_ALL bypass mode 100 kHz 0.12 0.15 0.25 0.41 0.75 0.15 0.21 0.39 0.74 1.45
current in mA
Run mode
48 MHz all
72 MHz 9.25 9.31 9.46 9.68 10.1 10.18 10.41 10.55 10.76 11.80
peripherals disable
DS10198 Rev 9
64 MHz 8.25 8.31 8.46 8.67 9.08 9.08 9.37 9.66 9.87 10.91
Range 1 48 MHz 6.26 6.33 6.48 6.69 7.11 6.89 7.11 7.25 7.67 8.50
32 MHz 4.22 4.28 4.42 4.63 5.03 4.64 4.86 5.15 5.56 6.19
24 MHz 3.20 3.25 3.38 3.59 3.99 3.52 3.70 3.84 4.26 5.09
16 MHz 2.18 2.22 2.35 2.55 2.94 2.40 2.55 2.84 3.25 4.09
2 MHz 242 275 384 562 924 300 380 573 927 1677
Supply
fHCLK = fMSI 1 MHz 130 162 269 445 809 180 243 435 810 1560
IDD_ALL current in
all peripherals disable µA
(LPRun) low-power 400 kHz 61 90 197 374 734 95 160 353 728 1478
FLASH in power-down
run mode
100 kHz 26 56 163 339 702 55 122 314 679 1429
125/19
Table 32. Current consumption in Run, code with data processing running from
126/19
SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V)
Conditions(1) TYP
- fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C
80 MHz 3.67 3.70 3.77 3.85 3.99

72 MHz 3.33 3.35 3.40 3.48 3.63
64 MHz 2.97 2.99 3.04 3.12 3.26
48 MHz 2.25 2.28 2.33 2.40 2.56
32 MHz 1.52 1.54 1.59 1.66 1.81
fHCLK = fHSE up to 48MHz included, bypass mode 24 MHz 1.15 1.17 1.22 1.29 1.43
IDD_ALL(Run) Supply current in Run mode mA
PLL ON above 48 MHz all peripherals disable 16 MHz 0.78 0.80 0.84 0.92 1.06
8 MHz 0.42 0.43 0.48 0.55 0.70
DS10198 Rev 9
4 MHz 0.23 0.25 0.29 0.36 0.51

2 MHz 0.14 0.16 0.20 0.27 0.41
1 MHz 0.09 0.11 0.15 0.22 0.37
100 kHz 0.05 0.06 0.11 0.18 0.32
VDD12 = 1.10 V
STM32L476xx
running from flash, ART enable (Cache ON Prefetch OFF)
Conditions TYP TYP
Symbol Parameter Unit Unit
Voltage
- Code 25 °C 25 °C
scaling
Reduced code(1) 2.9 111
fHCLK = 26 MHz
Coremark 3.1 118
Range 2
Dhrystone 2.1 3.1 mA 119 µA/MHz
fHCLK = fHSE up
to 48 MHz Fibonacci 2.9 112
Supply included, bypass While(1) 2.8 108
IDD_ALL
current in mode PLL ON
(Run) Reduced code (1)
10.2 127
Run mode above 48 MHz fHCLK = 80 MHz
all peripherals Coremark 10.9 136
Range 1
disable
Dhrystone 2.1 11.0 mA 137 µA/MHz
Fibonacci 10.5 131
While(1) 9.9 124
(1)
Reduced code 272 136
Supply Coremark 291 145
IDD_ALL current in fHCLK = fMSI = 2 MHz
Dhrystone 2.1 302 µA 151 µA/MHz
(LPRun) Low-power all peripherals disable
run Fibonacci 269 135
While(1) 269 135
1. Reduced code used for characterization results provided in Table 27, Table 29, Table 31.
(VDD12 = 1.10 V)
Conditions(1) TYP TYP
Symbol Parameter Voltage Unit Unit
- Code 25 °C 25 °C
scaling
fHCLK = 26 MHz
Coremark 1.34 51
Dhrystone 2.1 1.34 51
fHCLK = fHSE up to
48 MHz included, Fibonacci 1.25 48
Supply bypass mode PLL While(1) 1.21 46
IDD_ALL
current in ON above mA µA/MHz
(Run) Reduced code(2) 3.67 46
Run mode 48 MHz
fHCLK = 80 MHz

disable Dhrystone 2.1 3.95 49
Fibonacci 3.77 47
While(1) 3.56 44
DS10198 Rev 9 127/19

233
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters:
SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V
(VDD12 = 1.05 V)
- Code 25 °C 25 °C
scaling
fHCLK = fHSE up to Reduced code(2) 1.14 44
fHCLK = 26 MHz
48 MHz included, Coremark 1.22 47
Supply bypass mode PLL
IDD_ALL Dhrystone 2.1 1.22 47
current in ON above mA µA/MHz
(Run)
Run mode 48 MHz Fibonacci 1.14 44
all peripherals
disable While(1) 1.10 42
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters:
SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.05 V
running from flash, ART disable
Conditions TYP TYP
Voltage
- Code 25 °C 25 °C
scaling

fHCLK = 80 MHz fHCLK = 26 MHz
Coremark 2.9 111

Range 2
fHCLK = fHSE up to Dhrystone 2.1 2.8 mA 111 µA/MHz

Supply bypass mode
IDD_ALL While(1) 2.6 100
current in PLL ON above
Run mode 48 MHz
Range 1
disable Dhrystone 2.1 9.1 mA 114 µA/MHz

Fibonacci 9.0 112
While(1) 9.3 116
Reduced code(1) 358 179
While(1) 385 192
128/19 DS10198 Rev 9

Table 37. Typical current consumption in Run modes, with different codes running from
flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V)
- Code 25 °C 25 °C
scaling

Coremark 1.25 48
fHCLK = fHSE up to Dhrystone 2.1 1.21 46
Supply bypass mode While(1) 1.12 43
IDD_ALL
current in PLL ON above mA µA/MHz
Run mode 48 MHz
disable Dhrystone 2.1 3.27 41
Fibonacci 3.24 40
While(1) 3.34 42
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS
input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V
Table 38. Typical current consumption in Run modes, with different codes running
from flash, ART disable and power supplied by external SMPS (VDD12 = 1.05 V)
- Code 25 °C 25 °C
scaling
fHCLK = 26 MHz

Supply
IDD_ALL bypass mode
current in Dhrystone 2.1 1.10 mA 42 µA/MHz
(Run) PLL ON above
Run mode Fibonacci 1.06 41
48 MHz
all peripherals While(1) 1.02 39
DS10198 Rev 9 129/19

233
running from SRAM1
Conditions TYP TYP
Voltage
- Code 25 °C 25 °C
scaling

Coremark 2.9 111
Range 2
fHCLK = fHSE up to Dhrystone 2.1 2.9 mA 111 µA/MHz
Supply bypass mode
IDD_ALL While(1) 2.6 100
current in PLL ON above
Run mode 48 MHz all
peripherals Range 1 Coremark 10.4 130
disable Dhrystone 2.1 10.3 mA 129 µA/MHz
Fibonacci 9.6 120
While(1) 9.3 116
Reduced code(1) 242 121
While(1) 242 121
- Code 25 °C 25 °C
scaling
Coremark 1.25 48
fHCLK = fHSE up to
Supply While(1) 1.12 43
IDD_ALL bypass mode
current in mA µA/MHz
(Run) PLL ON above Reduced code(2) 3.67 46
Run mode
48 MHz all
Coremark 3.74 47
peripherals disable
Fibonacci 3.45 43
While(1) 3.34 42
130/19 DS10198 Rev 9

- Code 25 °C 25 °C
scaling
fHCLK = 26 MHz
Supply
IDD_ALL bypass mode
current in Dhrystone 2.1 1.14 mA 44 µA/MHz
(Run) PLL ON above
Run mode Fibonacci 1.02 39
48 MHz all
peripherals disable While(1) 1.02 39
DS10198 Rev 9 131/19

233
132/19
Table 42. Current consumption in Sleep and Low-power sleep modes, flash ON
Voltage
scaling
26 MHz 0.92 0.96 1.07 1.25 1.59 1.012 1.14 1.36 1.77 2.40
16 MHz 0.61 0.65 0.75 0.92 1.27 0.69 0.78 0.97 1.32 2.04
8 MHz 0.36 0.40 0.50 0.66 1.01 0.42 0.50 0.68 1.03 1.75
Range 2 4 MHz 0.24 0.27 0.37 0.53 0.87 0.28 0.36 0.54 0.89 1.60
fHCLK = fHSE up 2 MHz 0.18 0.20 0.30 0.47 0.81 0.215 0.29 0.46 0.82 1.53
to 48 MHz
Supply included, bypass 1 MHz 0.15 0.17 0.27 0.43 0.77 0.18 0.25 0.44 0.78 1.49
IDD_ALL current in mode 100 kHz 0.12 0.14 0.24 0.41 0.74 0.15 0.21 0.39 0.74 1.44
mA
(Sleep) sleep PLL ON above 80 MHz 2.96 3.00 3.13 3.33 3.73 3.26 3.43 3.72 4.13 4.97
mode, 48 MHz all
72 MHz 2.69 2.73 2.85 3.05 3.45 2.96 3.21 3.50 3.71 4.54
peripherals
DS10198 Rev 9
disable 64 MHz 2.41 2.45 2.58 2.77 3.17 2.65 2.88 3.17 3.58 4.21
Range 1 48 MHz 1.88 1.93 2.07 2.27 2.67 2.10 2.27 2.41 2.83 3.66
32 MHz 1.30 1.35 1.48 1.68 2.08 1.43 1.56 1.85 2.26 3.10
24 MHz 1.01 1.05 1.17 1.37 1.76 1.11 1.23 1.52 1.93 2.77
16 MHz 0.71 0.75 0.87 1.07 1.45 0.80 0.90 1.19 1.60 2.44
Supply 2 MHz 96 126 233 412 775 130 202 402 777 1527
current in 1 MHz 65 94 202 381 742 95 166 358 733 1483
IDD_ALL f =f
low-power HCLK MSI µA
(LPSleep) all peripherals disable 400 kHz 43 73 181 359 718 75 138 331 706 1456
sleep
mode 100 kHz 33 63 171 348 708 65 128 322 691 1441
STM32L476xx
Table 43. Current consumption in Sleep, flash ON and power supplied by external SMPS
STM32L476xx
(VDD12 = 1.10 V)
Conditions(1) TYP
- fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C
80 MHz 1.06 1.08 1.13 1.20 1.34

72 MHz 0.97 0.98 1.02 1.10 1.24
64 MHz 0.87 0.88 0.93 1.00 1.14
48 MHz 0.68 0.69 0.74 0.82 0.96
32 MHz 0.47 0.49 0.53 0.60 0.75
fHCLK = fHSE up to 48 MHz included, bypass
24 MHz 0.36 0.38 0.42 0.49 0.63
IDD_ALL(Sleep) Supply current in sleep mode, mode PLL ON above 48 MHz all peripherals mA
disable 16 MHz 0.26 0.27 0.31 0.38 0.52
8 MHz 0.16 0.17 0.22 0.28 0.44
4 MHz 0.10 0.12 0.16 0.23 0.38
2 MHz 0.08 0.09 0.13 0.20 0.35
DS10198 Rev 9
1 MHz 0.06 0.07 0.12 0.19 0.33

100 kHz 0.05 0.06 0.10 0.18 0.32
VDD12 = 1.10 V
Table 44. Current consumption in Low-power sleep modes, flash in power-down

Voltage
scaling
2 MHz 81 110 217 395 754 115 182 375 750 1500
Supply current
IDD_ALL fHCLK = fMSI 1 MHz 50 78 185 362 720 80 149 342 717 1456
in low-power µA
(LPSleep) all peripherals disable 400 kHz 28 57 163 340 698 60 122 314 689 1429
sleep mode
100 kHz 18 47 155 332 686 50 114 313 688 1438
133/19
134/19
Table 45. Current consumption in Stop 2 mode
- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 1.14 3.77 14.7 34.7 77 2.7 9 37 87 193
2.4 V 1.15 3.86 15 35.5 79.1 2.7 10 38 89 198
LCD disabled
3V 1.18 3.97 15.4 36.4 81.3 2.8 10 39 91 203
Supply current in 3.6 V 1.26 4.11 16 38 85.1 3.0 10 40 95 213(2)
IDD_ALL
Stop 2 mode, µA
(Stop 2) 1.8 V 1.43 3.98 15 35 77.3 3.2 10 38 88 193
RTC disabled
LCD enabled(3) 2.4 V 1.49 4.07 15.3 35.8 79.4 3.2 10 38 90 199
clocked by LSI 3V 1.54 4.24 15.7 36.7 81.6 3.3 11 39 92 204
3.6 V 1.75 4.47 16.1 38.3 85.4 3.5 11 40 96 214
1.8 V 1.42 4.04 15 34.9 77.2 3.1 10 38 87 193
DS10198 Rev 9
RTC clocked by LSI, 2.4 V 1.5 4.22 15.4 35.7 79.2 3.2 11 39 89 198
LCD disabled 3V 1.64 4.37 15.8 36.7 81.4 3.4 11 40 92 204
3.6 V 1.79 4.65 16.6 38.4 85.4 3.6 12 42 96 214
1.8 V 1.53 4.07 15.1 35.1 77.4 3.3 10 38 88 194
RTC clocked by LSI, 2.4 V 1.62 4.32 15.5 35.9 79.5 3.4 11 39 90 199
LCD enabled(3) 3V 1.69 4.43 15.9 36.8 81.7 3.5 11 40 92 204
IDD_ALL Supply current in 3.6 V 1.86 4.65 16.7 38.5 85.5 3.7 12 42 96 214
(Stop 2 with Stop 2 mode, µA
RTC) RTC enabled 1.8 V 1.5 4.13 15.2 35.3 77.6 3.2 10 38 88 194
RTC clocked by LSE 2.4 V 1.63 4.33 15.6 36 79.6 3.4 11 39 90 199
bypassed at
32768Hz,LCD disabled 3 V 1.79 4.55 16.1 37 81.8 3.6 11 40 93 205
3.6 V 2.04 4.9 16.8 38.7 85.6 3.9 12 42 97 214
1.8 V 1.43 3.99 14.7 35 - 3.2 10 37 88 -
RTC clocked by LSE
quartz(4) 2.4 V 1.54 4.11 15 35.8 - 3.3 10 38 90 -
in low drive mode, 3V 1.67 4.29 15.5 36.7 - 3.4 11 39 92 -
STM32L476xx
LCD disabled
3.6 V 1.87 4.57 16.2 38.3 - 3.7 11 41 96 -
STM32L476xx
Table 45. Current consumption in Stop 2 mode (continued)
- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
Wakeup clock is
MSI = 48 MHz,
3V 1.9 - - - -
voltage Range 1.
See (5).
Supply current Wakeup clock is
IDD_ALL MSI = 4 MHz,
during wakeup
(wakeup from voltage Range 2. 3V 2.24 - - - - - mA
from Stop 2
Stop 2)
mode See (5).
Wakeup clock is
HSI16 = 16 MHz,
voltage Range 1. 3V 2.1 - - - -
See (5).
DS10198 Rev 9

2. Guaranteed by test in production.
3. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for IVLCD.
4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
5. Wakeup with code execution from flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings.

- - VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 6.59 24.7 92.7 208 437 16 62 232 520 1093
LCD 2.4 V 6.65 24.8 92.9 209 439 17 62 232 523 1098
-
disabled 3V 6.65 24.9 93.3 210 442 17 62 233 525 1105
Supply current
IDD_ALL in Stop 1 3.6 V 6.70 25.1 93.8 212 447 17 63 235 530 1118
µA
(Stop 1) mode, 1.8 V 7.00 25.2 97.2 219 461 18 63 243 548 1153
LCD
RTC disabled
enabled(2) 2.4 V 7.14 25.4 97.5 220 463 18 64 244 550 1158
-
clocked by 3V 7.24 25.7 97.7 221 465 18 64 244 553 1163
135/19
LSI
3.6 V 7.36 26.1 98.7 223 471 18 65 247 558 1178
Table 46. Current consumption in Stop 1 mode (continued)
136/19
- - VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 6.88 25.0 93.1 209 439 17 63 233 523 1098
LCD 2.4 V 7.02 25.2 93.7 210 441 18 63 234 525 1103
disabled 3V 7.12 25.4 94.2 212 444 18 64 236 530 1110
RTC clocked by 3.6 V 7.25 25.7 95.2 214 449 18 64 238 535 1123
LSI 1.8 V 7.01 26.1 99.0 223 467 18 65 248 558 1168
LCD 2.4 V 7.14 26.3 99.6 225 470 18 66 249 563 1175
enabled(2) 3V 7.31 26.6 100.0 226 474 18 67 250 565 1185
Supply current
IDD_ALL 3.6 V 7.41 26.9 102.0 229 480 19 67 255 573 1200
in stop 1
(Stop 1 with µA
mode, 1.8 V 6.91 25.2 93.4 210 440 17 63 234 525 1100
RTC)
RTC enabled RTC clocked by
LCD 2.4 V 7.04 25.3 94.2 211 443 18 63 236 528 1108
LSE bypassed
disabled 3V 7.19 25.7 95.0 212 446 18 64 238 530 1115
at 32768 Hz
DS10198 Rev 9
3.6 V 7.97 26.0 96.1 215 451 20 65 240 538 1128

1.8 V 6.85 25.0 93.0 208.3 - 17 63 233 521 -
RTC clocked by 2.4 V 6.94 25.1 93.2 209.3 - 17 63 233 523 -
LCD
LSE quartz(3) in
disabled 3V 7.10 25.2 93.6 210.3 - 18 63 234 526 -
low drive mode
3.6 V 7.34 25.4 94.1 212.3 - 18 64 235 531 -
Wakeup clock MSI = 48 MHz,
voltage Range 1. 3V 1.47 - - - -
See (4).
Supply current Wakeup clock MSI = 4 MHz,
IDD_ALL
during voltage Range 2. 3V 1.7 - - - -
(wakeup - mA
wakeup from See (4).
from Stop1)
Stop 1
Wakeup clock
HSI16 = 16 MHz,
3V 1.62 - - - -
voltage Range 1.
See (4).
STM32L476xx
2. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for IVLCD.
STM32L476xx
VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 108 132 217 356 631 153 213 426 773 1461
Supply 2.4 V 110 134 219 358 634 158 218 431 778 1468
IDD_ALL current in
3V 111 135 220 360 637 161 221 433 783 1476 µA
(Stop 0) Stop 0 mode,
RTC disabled 1488
3.6 V 113 137 222 363 642 166 226 438 791 (2)

DS10198 Rev 9
137/19
Table 48. Current consumption in Standby mode
138/19
- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 114 355 1540 4146 10735 176 888 3850 10365 26838
2.4 V 138 407 1795 4828 12451 223 1018 4488 12070 31128
Supply current no independent watchdog 3V 150 486 2074 5589 14291 263 1215 5185 13973 35728
in Standby 43748
IDD_ALL mode (backup 3.6 V 198 618 2608 6928 17499 383 1545 6520 17320 (2)
nA
(Standby) registers
retained), 1.8 V 317 - - - - - - - - -
RTC disabled with independent 2.4 V 391 - - - - - - - - -
watchdog 3V 438 - - - - - - - - -
3.6 V 566 - - - - - - - - -
1.8 V 377 621 1873 4564 11318 491 1207 4250 10867 27537
2.4 V 464 756 2210 5348 13166 614 1436 4986 12694 31986
DS10198 Rev 9
RTC clocked by LSI, no

independent watchdog 3V 572 913 2599 6219 15197 770 1727 5815 14729 36815
3.6 V 722 1144 3253 7724 18696 1012 2176 7294 18275 45184
nA
1.8 V 456 - - - - - - - - -
RTC clocked by LSI, with 2.4 V 557 - - - - - - - - -
Supply current independent watchdog 3V 663 - - - - - - - - -
in Standby
IDD_ALL 3.6 V 885 - - - - - - - - -
mode (backup
(Standby
registers 1.8 V 289 527 1747 4402 11009 - - - - -
with RTC)
retained),
RTC clocked by LSE 2.4 V 396 671 2108 5202 12869 - - - - -
RTC enabled
bypassed at 32768Hz 3V 528 853 2531 6095 14915 - - - - -
3.6 V 710 1111 3115 7470 18221 - - - - -
nA
1.8 V 416 640 1862 4479 11908 - - - - -
RTC clocked by LSE 2.4 V 514 796 2193 5236 13689 - - - - -
quartz (3) in low drive mode 3 V 652 961 2589 6103 15598 - - - - -
STM32L476xx
3.6 V 821 1226 3235 7551 17947 - - - - -
Table 48. Current consumption in Standby mode (continued)
STM32L476xx
- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
Supply current 1.8 V 235 641 2293 5192 11213 588 1603 5733 12980 28033
IDD_ALL to be added in 2.4 V 237 645 2303 5213 11246 593 1613 5758 13033 28115
Standby mode - nA
(SRAM2)(4) 3V 236 647 2306 5221 11333 593 1618 5765 13053 28333
when SRAM2
is retained 3.6 V 235 646 2308 5200 11327 595 1620 5770 13075 28350
IDD_ALL Supply current Wakeup clock is
(wakeup during wakeup MSI = 4 MHz. 3V 1.7 - - - - - mA
from from Standby
See (5).
Standby) mode
4. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IDD_ALL(Standby
DS10198 Rev 9
+ RTC) + IDD_ALL(SRAM2).
Table 49. Current consumption in Shutdown mode

- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
Supply current 1.8 V 29.8 194 1110 3250 9093 75 485 2775 8125 22733
in Shutdown 2.4 V 44.3 237 1310 3798 10473 111 593 3275 9495 26183
mode
IDD_ALL 3V 64.1 293 1554 4461 12082 160 733 3885 11153 30205
(backup - nA
(Shutdown)
registers
retained) RTC 3.6 V 112 420 2041 5689 15186 280 1050 5103 14223 37965
disabled
139/19
Table 49. Current consumption in Shutdown mode (continued)
140/19
- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 210 378 1299 3437 9357 - - - - -
Supply current RTC clocked by LSE 2.4 V 303 499 1577 4056 10825 - - - - -
in Shutdown bypassed at 32768 Hz 3V 422 655 1925 4820 12569 - - - - -
IDD_ALL mode 3.6 V 584 888 2511 6158 15706 - - - - -
(Shutdown (backup nA
with RTC) registers 1.8 V 329 499 1408 3460 - - - - - -
retained) RTC RTC clocked by LSE 2.4 V 431 634 1688 4064 - - - - - -
enabled quartz (2) in low drive
mode 3V 554 791 2025 4795 - - - - - -
3.6 V 729 1040 2619 6129 - - - - - -
Supply current Wakeup clock is
IDD_ALL
during wakeup
(wakeup from MSI = 4 MHz. 3V 0.6 - - - - - - - - - mA
from Shutdown
Shutdown) See (3).
DS10198 Rev 9
mode
STM32L476xx
Table 50. Current consumption in VBAT mode
STM32L476xx
- VBAT 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 4 29 196 587 1663 10.8 73 490 1468 4158
2.4 V 5.27 36 226 673 1884 13.2 90 565 1683 4710
RTC disabled
3V 6 42 264 775 2147 15.5 106 660 1938 5368
3.6 V 10 58 323 919 2488 25.8 144 808 2298 6220
1.8 V 183 201 367 729 - - - - - -
RTC enabled and 2.4 V 268 295 486 901 - - - - - -
Backup domain
IDD_VBAT clocked by LSE nA
supply current 3V 376 412 602 1075 - - - - - -
bypassed at 32768 Hz
3.6 V 508 558 752 1299 - - - - - -
1.8 V 302 344 521 915 1978 - - - - -
RTC enabled and 2.4 V 388 436 639 1091 2289 - - - - -
clocked by LSE
DS10198 Rev 9
quartz(2) 3V 494 549 784 1301 2656 - - - - -

3.6 V 630 692 971 1571 3115 - - - - -
141/19
I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 70: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 51: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
I SW = V DDIOx × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
142/19 DS10198 Rev 9

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 51. The MCU is placed
under the following conditions:
• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 20:
Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in
Table 51. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 51. Peripheral current consumption

Low-power run
Peripheral Range 1 Range 2 Unit
and sleep
Bus Matrix(1) 4.5 3.7 4.1

ADC independent clock domain 0.4 0.1 0.2
ADC AHB clock domain 5.5 4.7 5.5
CRC 0.4 0.2 0.3
DMA1 1.4 1.3 1.4
DMA2 1.5 1.3 1.4
FLASH 6.2 5.2 5.8
FMC 8.9 7.5 8.4
GPIOA(2) 4.8 3.8 4.4
(2)
GPIOB 4.8 4.0 4.6
GPIOC(2) 4.5 3.8 4.3
(2)
GPIOD 4.6 3.9 4.4
AHB µA/MHz
GPIOE(2) 5.2 4.5 4.9
GPIOF(2) 5.9 4.9 5.7
(2)
GPIOG 4.3 3.8 4.2
(2)
GPIOH 0.7 0.6 0.8
OTG_FS independent clock
23.2 N/A N/A
domain
OTG_FS AHB clock domain 16.4 N/A N/A
QUADSPI 7.8 6.7 7.3
RNG independent clock domain 2.2 N/A N/A
RNG AHB clock domain 0.6 N/A N/A
SRAM1 0.9 0.8 0.9
DS10198 Rev 9 143/19

233
Table 51. Peripheral current consumption (continued)

Low-power run
and sleep
SRAM2 1.6 1.4 1.6

AHB TSC 1.8 1.4 1.6 µA/MHz
All AHB Peripherals 118.5 77.3 87.6
(3)
AHB to APB1 bridge 0.9 0.7 0.9
CAN1 4.6 4.0 4.4
DAC1 2.4 1.9 2.2
I2C1 independent clock domain 3.7 3.1 3.2
I2C1 APB clock domain 1.3 1.1 1.5
LCD 1.0 0.8 0.9
LPUART1 independent clock
2.1 1.6 2.0
domain
LPUART1 APB clock domain 0.6 0.6 0.6
LPTIM1 independent clock
3.3 2.6 2.9
domain
LPTIM1 APB clock domain 0.9 0.8 1.0
APB1 µA/MHz
LPTIM2 independent clock
3.1 2.7 2.9
domain
LPTIM2 APB clock domain 0.8 0.6 0.7
OPAMP 0.4 0.4 0.3
PWR 0.5 0.5 0.4
SPI2 1.8 1.6 1.6
SPI3 2.1 1.7 1.8
SWPMI1 independent clock
2.3 1.8 2.2
domain
SWPMI1 APB clock domain 1.1 1.1 1.0
TIM2 6.8 5.7 6.3
TIM3 5.4 4.6 5.0
TIM4 5.2 4.4 4.9
TIM5 6.5 5.5 6.1
TIM6 1.1 1.0 1.0
TIM7 1.1 0.9 1.0
144/19 DS10198 Rev 9

Table 51. Peripheral current consumption (continued)

Low-power run
and sleep
USART2 independent clock

4.1 3.6 3.8
domain
USART2 APB clock domain 1.4 1.1 1.5
4.7 4.1 4.2
domain
UART4 independent clock
APB1 3.9 3.2 3.5
domain
UART4 APB clock domain 1.5 1.3 1.6
UART5 independent clock
3.9 3.2 3.5
domain
UART5 APB clock domain 1.3 1.2 1.4
WWDG 0.5 0.5 0.5
All APB1 on 84.2 70.7 80.2
AHB to APB2 bridge(4) 1.0 0.9 0.9
DFSDM1 5.6 4.6 5.3
FW 0.7 0.5 0.7
SAI1 independent clock domain 2.6 2.1 2.3
SAI1 APB clock domain 2.1 1.8 2.0 µA/MHz
SAI2 independent clock domain 3.3 2.7 3.0

SAI2 APB clock domain 2.4 2.1 2.2
SDMMC1 independent clock
4.7 3.9 4.2
domain
SDMMC1 APB clock domain 2.5 1.9 2.1
APB2 SPI1 2.0 1.6 1.9
SYSCFG/VREFBUF/COMP 0.6 0.4 0.5
TIM1 8.3 6.9 7.9
TIM8 8.6 7.1 8.1
TIM15 4.1 3.4 3.9
TIM16 3.0 2.5 2.9
TIM17 3.0 2.4 2.9
4.9 4.0 4.4
domain
All APB2 on 56.8 43.3 48.2
ALL 256.8 189.6 215.5
DS10198 Rev 9 145/19

233
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when
the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current
consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog
mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes).
3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1.
4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2.
The consumption for the peripherals when using SMPS can be found using STM32CubeMX
PCC tool.
6.3.6 Wakeup time from low-power modes and voltage scaling

transition times
The wakeup times given in Table 52 are the latency between the event and the execution of
the first user instruction.
The device goes in low-power mode after the WFE (Wait For Event) instruction.
Table 52. Low-power mode wakeup timings(1)

Symbol Parameter Conditions Typ Max Unit
Wakeup time from Sleep

tWUSLEEP - 6 6
mode to Run mode
Nb of
CPU
Wakeup time from Low- Wakeup in flash with flash in power-down during cycles
tWULPSLEEP power sleep mode to Low- low-power sleep mode (SLEEP_PD=1 in 6 9.3
power run mode FLASH_ACR) and with clock MSI = 2 MHz
Wakeup clock MSI = 48 MHz 5.6 10.9

Range 1
Wakeup clock HSI16 = 16 MHz 4.7 10.4
Wake up time from Stop 0
mode to Run mode in flash
Range 2 Wakeup clock HSI16 = 16 MHz 4.5 10.5
tWUSTOP0 µs
Range 1
mode to Run mode in Wakeup clock MSI = 24 MHz 0.8 2.72
SRAM1
146/19 DS10198 Rev 9

Table 52. Low-power mode wakeup timings(1) (continued)


Range 1
Range 1
tWUSTOP1 mode to Run mode in Wakeup clock MSI = 24 MHz 5.0 6.5 µs
SRAM1

mode to Low-power run 12.7 20
Regulator in
mode in flash
low-power
Wakeup clock MSI = 2 MHz
mode (LPR=1 in
PWR_CR1)
mode to Low-power run 10.7 21.5
mode in SRAM1

Range 1
tWUSTOP2 µs
Range 1
Wakeup clock HSI16 = 16 MHz 5.7 8
mode to Run mode in Wakeup clock MSI = 24 MHz 5.5 6.65
SRAM1
Wakeup time from Standby Wakeup clock MSI = 8 MHz 14.3 20.8
tWUSTBY Range 1 µs
mode to Run mode Wakeup clock MSI = 4 MHz 20.1 35.5
tWUSTBY Wakeup time from Standby Wakeup clock MSI = 8 MHz 14.3 24.3
Range 1 µs
SRAM2 with SRAM2 to Run mode Wakeup clock MSI = 4 MHz 20.1 38.5
Wakeup time from
tWUSHDN Shutdown mode to Run Range 1 Wakeup clock MSI = 4 MHz 256 330.6 µs
mode
1. Guaranteed by characterization results.
DS10198 Rev 9 147/19

233
Table 53. Regulator modes transition times(1)

Wakeup time from Low-power run mode to

tWULPRUN Code run with MSI 2 MHz 5 7
Run mode(2)
µs
Regulator transition time from Range 2 to
tVOST Code run with MSI 24 MHz 20 40
Range 1 or Range 1 to Range 2(3)
2. Time until REGLPF flag is cleared in PWR_SR2.
3. Time until VOSF flag is cleared in PWR_SR2.
Table 54. Wakeup time using USART/LPUART(1)

Wakeup time needed to calculate the Stop 0 mode - 1.7

tWUUSART maximum USART/LPUART baudrate
allowing to wakeup up from stop mode Stop 1 mode and Stop 2 µs
tWULPUART - 8.5
when USART/LPUART clock source is mode
HSI16
6.3.7 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 24: High-speed external clock
source AC timing diagram.
Table 55. High-speed external user clock characteristics(1)

Voltage scaling
- 8 48
Range 1
fHSE_ext User external clock source frequency MHz
Voltage scaling
- 8 26
Range 2
VHSEH OSC_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx
V
VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDDIOx
Voltage scaling
7 - -
tw(HSEH) Range 1
OSC_IN high or low time ns
tw(HSEL) Voltage scaling
18 - -
Range 2
148/19 DS10198 Rev 9

Figure 24. High-speed external clock source AC timing diagram
tw(HSEH)
VHSEH
90%
10%
VHSEL
tr(HSE) t
tf(HSE) tw(HSEL)
THSE
MS19214V2
Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 25.
Table 56. Low-speed external user clock characteristics(1)

fLSE_ext User external clock source frequency - - 32.768 1000 kHz

VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx
V
VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time - 250 - - ns
tw(LSEL)
Figure 25. Low-speed external clock source AC timing diagram
tw(LSEH)
VLSEH
90%
10%
VLSEL
tr(LSE) t
tf(LSE) tw(LSEL)
TLSE
MS19215V2
DS10198 Rev 9 149/19

233
High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 57. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 57. HSE oscillator characteristics(1)

fOSC_IN Oscillator frequency - 4 8 48 MHz

RF Feedback resistor - - 200 - kΩ
(3)
During startup - - 5.5
VDD = 3 V,
Rm = 30 Ω, - 0.44 -
CL = 10 pF@8 MHz
VDD = 3 V,
Rm = 45 Ω, - 0.45 -
CL = 10 pF@8 MHz
IDD(HSE) HSE current consumption VDD = 3 V, mA

Rm = 30 Ω, - 0.68 -
CL = 5 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 0.94 -
CL = 10 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 1.77 -
CL = 20 pF@48 MHz
Maximum critical crystal
Gm Startup - - 1.5 mA/V
transconductance
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 26). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
150/19 DS10198 Rev 9

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 26. Typical application with an 8 MHz crystal
Resonator with integrated

capacitors
CL1
OSC_IN fHSE
Bias
8 MHz controlled
resonator RF gain
REXT (1) OSC_OUT

CL2
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 58. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 58. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

LSEDRV[1:0] = 00
- 250 -
Low drive capability
LSEDRV[1:0] = 01
- 315 -
Medium low drive capability
IDD(LSE) LSE current consumption nA
LSEDRV[1:0] = 10
- 500 -
Medium high drive capability
LSEDRV[1:0] = 11
- 630 -
High drive capability
LSEDRV[1:0] = 00
- - 0.5
Low drive capability
LSEDRV[1:0] = 01
- - 0.75
Maximum critical crystal Medium low drive capability
Gmcritmax µA/V
gm LSEDRV[1:0] = 10
- - 1.7
Medium high drive capability
LSEDRV[1:0] = 11
- - 2.7
High drive capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
DS10198 Rev 9 151/19

233
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 27. Typical application with a 32.768 kHz crystal
Resonator with integrated

capacitors
CL1
OSC32_IN fLSE
32.768 kHz Drive

resonator programmable
amplifier
OSC32_OUT
CL2
MS30253V2
Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
152/19 DS10198 Rev 9

6.3.8 Internal clock source characteristics

The parameters given in Table 59 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 23: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
Table 59. HSI16 oscillator characteristics(1)

fHSI16 HSI16 Frequency VDD=3.0 V, TA=30 °C 15.88 - 16.08 MHz

Trimming code is not a
0.2 0.3 0.4
multiple of 64
TRIM HSI16 user trimming step %
Trimming code is a
-4 -6 -8
multiple of 64
DuCy(HSI16)(2) Duty Cycle - 45 - 55 %
HSI16 oscillator frequency TA= 0 to 85 °C -1 - 1 %

∆Temp(HSI16)
drift over temperature TA= -40 to 125 °C -2 - 1.5 %
HSI16 oscillator frequency
∆VDD(HSI16) VDD=1.62 V to 3.6 V -0.1 - 0.05 %
drift over VDD
HSI16 oscillator start-up
tsu(HSI16)(2) - - 0.8 1.2 μs
time
HSI16 oscillator
tstab(HSI16)(2) - - 3 5 μs
stabilization time
HSI16 oscillator power
IDD(HSI16)(2) - - 155 190 μA
consumption
DS10198 Rev 9 153/19

233
Figure 28. HSI16 frequency versus temperature

MHz
16.4
+2 %
16.3
+1.5 %
16.2
+1 %
16.1
16
15.9
15.8 -1 %
-1.5 %
15.7
-2 %
15.6
-40 -20 0 20 40 60 80 100 120 °C
Mean min max
MSv39299V2
154/19 DS10198 Rev 9

Multi-speed internal (MSI) RC oscillator
Table 60. MSI oscillator characteristics(1)

Range 0 99 100 101

Range 1 198 200 202
kHz
Range 2 396 400 404
Range 3 792 800 808
Range 4 0.99 1 1.01
Range 5 1.98 2 2.02
MSI mode
Range 6 3.96 4 4.04
Range 7 7.92 8 8.08
MHz
Range 8 15.8 16 16.16
Range 9 23.8 24 24.4
MSI frequency Range 10 31.7 32 32.32

after factory Range 11 47.5 48 48.48
fMSI calibration, done
at VDD=3 V and Range 0 - 98.304 -
TA=30 °C Range 1 - 196.608 -
kHz
Range 2 - 393.216 -
Range 3 - 786.432 -
Range 4 - 1.016 -
PLL mode Range 5 - 1.999 -
XTAL=
32.768 kHz Range 6 - 3.998 -
Range 7 - 7.995 -
MHz
Range 8 - 15.991 -
Range 9 - 23.986 -
Range 10 - 32.014 -
Range 11 - 48.005 -
MSI oscillator TA= -0 to 85 °C -3.5 - 3
∆TEMP(MSI)(2) frequency drift MSI mode %
over temperature TA= -40 to 125 °C -8 - 6
DS10198 Rev 9 155/19

233
Table 60. MSI oscillator characteristics(1) (continued)

VDD=1.62 V
-1.2 -
to 3.6 V
Range 0 to 3 0.5
VDD=2.4 V
-0.5 -
to 3.6 V
MSI oscillator VDD=1.62 V

-2.5 -
frequency drift to 3.6 V
(2)
∆VDD(MSI) MSI mode Range 4 to 7 0.7 %
over VDD VDD=2.4 V
(reference is 3 V) -0.8 -
to 3.6 V
VDD=1.62 V
-5 -
to 3.6 V
Range 8 to 11 1.2
VDD=2.4 V
-1.6 -
to 3.6 V
Frequency TA= -40 to 85 °C - 1 2
∆FSAMPLING
variation in MSI mode %
(MSI)(2)(6) TA= -40 to 125 °C - 2 4
sampling mode(3)
for next
- - - 3.458
P_USB Period jitter for PLL mode transition
ns
Jitter(MSI)(6) USB clock(4) Range 11 for paired
- - - 3.916
transition
for next
- - - 2
MT_USB Medium term jitter PLL mode transition
ns
Jitter(MSI)(6) for USB clock(5) Range 11 for paired
- - - 1
transition
RMS cycle-to-
CC jitter(MSI)(6) PLL mode Range 11 - - 60 - ps
cycle jitter
P jitter(MSI)(6) RMS Period jitter PLL mode Range 11 - - 50 - ps
Range 0 - - 10 20
Range 1 - - 5 10
MSI oscillator Range 2 - - 4 8

tSU(MSI)(6) us
start-up time Range 3 - - 3 7
Range 4 to 7 - - 3 6
Range 8 to 11 - - 2.5 6
10 % of final
- - 0.25 0.5
frequency
MSI oscillator PLL mode 5 % of final
tSTAB(MSI)(6) - - 0.5 1.25 ms
stabilization time Range 11 frequency
1 % of final
- - - 2.5
frequency
156/19 DS10198 Rev 9

Table 60. MSI oscillator characteristics(1) (continued)

Range 0 - - 0.6 1
Range 1 - - 0.8 1.2
Range 2 - - 1.2 1.7
Range 3 - - 1.9 2.5
Range 4 - - 4.7 6
MSI oscillator Range 5 - - 6.5 9
MSI and
IDD(MSI)(6) power µA
PLL mode Range 6 - - 11 15
consumption
Range 7 - - 18.5 25
Range 8 - - 62 80
Range 9 - - 85 110
Range 10 - - 110 130
Range 11 - - 155 190
2. This is a deviation for an individual part once the initial frequency has been measured.
3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.
4. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter
of MSI @48 MHz clock.
5. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles.
For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28
cycles.
For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over
56 cycles.
DS10198 Rev 9 157/19

233
Figure 29. Typical current consumption versus MSI frequency
Low-speed internal (LSI) RC oscillator
Table 61. LSI oscillator characteristics(1)

VDD = 3.0 V, TA = 30 °C 31.04 - 32.96

fLSI LSI Frequency kHz
VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.5 - 34
LSI oscillator start-
tSU(LSI)(2) - - 80 130 μs
up time
LSI oscillator
tSTAB(LSI)(2) 5% of final frequency - 125 180 μs
stabilization time
LSI oscillator power
IDD(LSI)(2) - - 110 180 nA
consumption
6.3.9 PLL characteristics

The parameters given in Table 62 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 23: General operating conditions.
158/19 DS10198 Rev 9

Table 62. PLL, PLLSAI1, PLLSAI2 characteristics(1)

PLL input clock(2) - 4 - 16 MHz

fPLL_IN
PLL input clock duty cycle - 45 - 55 %
Voltage scaling Range 1 2.0645 - 80
fPLL_P_OUT PLL multiplier output clock P MHz
Voltage scaling Range 2 2.0645 - 26
Voltage scaling Range 1 8 - 80
fPLL_Q_OUT PLL multiplier output clock Q MHz
fPLL_R_OUT PLL multiplier output clock R MHz
fVCO_OUT PLL VCO output MHz
tLOCK PLL lock time - - 15 40 μs
RMS cycle-to-cycle jitter - 40 -
Jitter System clock 80 MHz ±ps
RMS period jitter - 30 -
VCO freq = 64 MHz - 150 200
PLL power consumption on VCO freq = 96 MHz - 200 260

IDD(PLL) μA
VDD(1) VCO freq = 192 MHz - 300 380
VCO freq = 344 MHz - 520 650
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between the 3 PLLs.
6.3.10 Flash memory characteristics
Table 63. Flash memory characteristics(1)

tprog 64-bit programming time - 81.69 90.76 µs
one row (32 double normal programming 2.61 2.90

tprog_row
word) programming time fast programming 1.91 2.12
one page (2 Kbyte) normal programming 20.91 23.24 ms

tprog_page
programming time fast programming 15.29 16.98
tERASE Page (2 KB) erase time - 22.02 24.47
one bank (512 Kbyte) normal programming 5.35 5.95

tprog_bank s
programming time fast programming 3.91 4.35
Mass erase time
tME - 22.13 24.59 ms
(one or two banks)
DS10198 Rev 9 159/19

233
Table 63. Flash memory characteristics(1) (continued)

Average consumption Write mode 3.4 -

from VDD Erase mode 3.4 -
IDD mA
Write mode 7 (for 2 μs) -
Maximum current (peak)
Erase mode 7 (for 41 μs) -
Table 64. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit
NEND Endurance TA = –40 to +105 °C 10 kcycles

1 kcycle(2) at TA = 85 °C 30
(2)
1 kcycle at TA = 105 °C 15
1 kcycle(2) at TA = 125 °C 7
tRET Data retention Years
(2)
10 kcycles at TA = 55 °C 30
10 kcycles(2) at TA = 85 °C 15
10 kcycles(2) at TA = 105 °C 10
2. Cycling performed over the whole temperature range.
160/19 DS10198 Rev 9

6.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 65. They are based on the EMS levels and classes
defined in application note AN1709.
Table 65. EMS characteristics

Level/
Symbol Parameter Conditions
Class
VDD = 3.3 V, TA = +25 °C,

Voltage limits to be applied on any I/O pin
VFESD fHCLK = 80 MHz, 3B
to induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, TA = +25 °C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 80 MHz, 4A
pins to induce a functional disturbance conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)
DS10198 Rev 9 161/19

233
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 66. EMI characteristics

Max vs. [fHSE/fHCLK]
Monitored
Symbol Parameter Conditions Unit
frequency band
fMSI = 24 MHz 8 MHz / 80 MHz
0.1 MHz to 30 MHz -9 2

VDD = 3.6 V, TA = 25 °C,
LQFP144 package 30 MHz to 130 MHz -8 3 dBµV
SEMI Peak level
compliant with 130 MHz to 1 GHz -10 14
IEC 61967-2
EMI Level 1.5 3.5 -
6.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 67. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)
TA = +25 °C, conforming

Electrostatic discharge
VESD(HBM) to ANSI/ESDA/JEDEC 2 2000
voltage (human body model)
JS-001
V
Electrostatic discharge TA = +25 °C,
VESD(CDM) voltage (charge device conforming to ANSI/ESD C3 250
model) STM5.3.1
162/19 DS10198 Rev 9

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 68. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II level A(1)

1. Negative injection is limited to -30 mA for PF0, PF1, PG6, PG7, PG8, PG12, PG13, PG14.
6.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 69.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 69. I/O current injection susceptibility

Functional
susceptibility
Symbol Description Unit
Negative Positive
injection injection
Injected current on BOOT0 pin -0 0

IINJ Injected current on pins except PA4, PA5, BOOT0 -5 N/A(1) mA
Injected current on PA4, PA5 pins -5 0
1. Injection is not possible.
DS10198 Rev 9 163/19

233
6.3.14 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 70 are derived from tests
performed under the conditions summarized in Table 23: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant (except BOOT0).
Note: For information on GPIO configuration, refer to the application note AN4899 “STM32 GPIO
configuration for hardware settings and low-power consumption” available from the ST
website www.st.com.
Table 70. I/O static characteristics

I/O input low level

voltage except 1.62 V<VDDIOx<3.6 V - - 0.3xVDDIOx(2)
BOOT0
I/O input low level
voltage except 1.62 V<VDDIOx<3.6 V - - 0.39xVDDIOx-0.06(3)
VIL(1) BOOT0 V
I/O input low level
voltage except 1.08 V<VDDIOx<1.62 V - - 0.43xVDDIOx-0.1(3)
BOOT0
BOOT0 I/O input low
1.62 V<VDDIOx<3.6 V - - 0.17xVDDIOx(3)
level voltage
I/O input high level
voltage except 1.62 V<VDDIOx<3.6 V 0.7xVDDIOx(2) - -
BOOT0
voltage except 1.62 V<VDDIOx<3.6 V 0.49xVDDIOX+0.26(3) - -
VIH (1) BOOT0 V
voltage except 1.08 V<VDDIOx<1.62 V 0.61xVDDIOX+0.05(3) - -
BOOT0
BOOT0 I/O input high
1.62 V<VDDIOx<3.6 V 0.77xVDDIOX(3) - -
level voltage
TT_xx, FT_xxx and
NRST I/O input 1.62 V<VDDIOx<3.6 V - 200 -
hysteresis
Vhys(3) mV
FT_sx 1.08 V<VDDIOx<1.62 V - 150 -
BOOT0 I/O input
1.62 V<VDDIOx<3.6 V - 200 -
hysteresis
164/19 DS10198 Rev 9

Table 70. I/O static characteristics (continued)

VIN ≤
- - ±100
Max(VDDXXX)(6)(7)
FT_xx input leakage Max(VDDXXX) ≤ VIN ≤
- - 650
current(3)(5) Max(VDDXXX)+1 V(6)(7)
Max(VDDXXX)+1 V <
- - 200
VIN ≤ 5.5 V(6)(7)
VIN ≤ Max(VDDXXX)
(6)(7) - - ±150
FT_lu, FT_u and PC3 Max(VDDXXX) ≤ VIN ≤

- - 2500(3)
I/Os Max(VDDXXX)+1 V(6)(7)
Ilkg(4) nA
Max(VDDXXX)+1 V <
- - 250
VIN ≤ 5.5 V(6)(7)
VIN ≤ Max(VDDXXX)(6) - - ±150
TT_xx input leakage
current Max(VDDXXX) ≤ VIN <
- - 2000(3)
3.6 V(6)
OPAMPx_VINM
(x=1,2) dedicated
(8)
input leakage current - - -
(UFBGA132 and
UFBGA144 only)
Weak pull-up
RPU VIN = VSS 25 40 55 kΩ
equivalent resistor (9)
Weak pull-down
RPD VIN = VDDIOx 25 40 55 kΩ
equivalent resistor(9)
CIO I/O pin capacitance - - 5 - pF
1. Refer to Figure 30: I/O input characteristics.
4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:
ITotal_Ileak_max = 10 µA + [number of IOs where VIN is applied on the pad] ₓ Ilkg(Max).
5. All FT_xx GPIOs except FT_lu, FT_u and PC3 I/Os.
6. Max(VDDXXX) is the maximum value of all the I/O supplies.
7. To sustain a voltage higher than Min(VDD, VDDA, VDDIO2, VDDUSB, VLCD) +0.3 V, the internal Pull-up and Pull-Down
resistors must be disabled.
8. Refer to Ibias in Table 86: OPAMP characteristics for the values of the OPAMP dedicated input leakage current.
9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
DS10198 Rev 9 165/19

233
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 30 for standard I/Os, and in Figure 30 for
5 V tolerant I/Os.
Figure 30. I/O input characteristics
TTL requirement Vih min = 2V
V DDIO
x
x>
1.62
= 0.7x for V DD
IO
min x+
0.26
t Vih 49xV D
DIO
ire men or 0.
requ x<
1.62 >1.62
OS 8<V DD
IO
r VDDIOx
on C
M 1.0 .06 fo
cti 0.0 5 for x VDDIO x-0
odu x+ r 0.39
di n pr .61 xV DDIO
x<
1.62 o
este in = 0 8<VDDIO
T Vih m .1 for
1.0
lation x-0
on simu =0.43
xVDDIO
B ased Vil max dd
TTL requirement Vil max = 0.8V
simu lation il max = 0.3xV
Bas ed on ir ement V
OS requ
produ ction CM
T ested in
MSv37613V1
Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed VOL/VOH).
GPIOs PC13, PC14 and PC15 are supplied through the power switch, limiting source
capability up to 3 mA only.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
• The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 20: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see
Table 20: Voltage characteristics).
166/19 DS10198 Rev 9

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 23: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).
Table 71. Output voltage characteristics(1)

VOL (2)
Output low level voltage for an I/O pin CMOS port - 0.4
|IIO| = 8 mA(3)
VOH Output high level voltage for an I/O pin V VDDIOx-0.4 -
DDIOx ≥ 2.7 V
VOL(4) Output low level voltage for an I/O pin TTL port(2) - 0.4
|IIO| = 8 mA(5)
VOH(4) Output high level voltage for an I/O pin V 2.4 -
DDIOx ≥ 2.7 V
VOL(4) Output low level voltage for an I/O pin PC13, PC14 and PC15 - 0.07
|IIO| = 3 mA
VOH(4) Output high level voltage for an I/O pin V VDDIOx-0.35 -
DDIOx ≥ 2.7 V
VOL(4) Output low level voltage for an I/O pin |IIO| = 20 mA(5) - 1.3
VOH (4)
Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V VDDIOx-1.3 -
(4)
V
VOL Output low level voltage for an I/O pin |IIO| = 4 mA(3) - 0.45
VOH(4) Output high level voltage for an I/O pin VDDIOx ≥ 1.62 V VDDIOx-0.45 -
VOL(4) Output low level voltage for an I/O pin |IIO| = 2 mA - 0.35ₓVDDIOx
VOH (4) Output high level voltage for an I/O pin 1.62 V ≥ VDDIOx ≥ 1.08 V 0.65ₓVDDIOx -
|IIO| = 20 mA
- 0.4
VDDIOx ≥ 2.7 V
Output low level voltage for an FT I/O
VOLFM+ |IIO| = 10 mA
(4) pin in FM+ mode (FT I/O with "f" - 0.4
VDDIOx ≥ 1.62 V
option)
|IIO| = 2 mA
- 0.4
1.62 V ≥ VDDIOx ≥ 1.08 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 20:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. PC13, PC14 and PC15 are tested/characterized at their maximum current of 3 mA.
5. Not applicable to PC13, PC14 and PC15.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 31 and
Table 72, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 23: General
operating conditions.
DS10198 Rev 9 167/19

233
Table 72. I/O AC characteristics(1)(2)

Speed Symbol Parameter Conditions Min Max Unit
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 1
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1
Fmax Maximum frequency MHz
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 10
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 1.5
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1
00
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 25
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 52
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 140
Tr/Tf Output rise and fall time ns
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 17
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 110
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 25
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 10
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 1
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 50
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 15
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 1
01
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 9
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 16
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 40
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 4.5
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 9
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 21
168/19 DS10198 Rev 9

Table 72. I/O AC characteristics(1)(2) (continued)

Speed Symbol Parameter Conditions Min Max Unit
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 50

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 25
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 5
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 100(3)
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37.5
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 5
10
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5.8
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 11
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 28
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 2.5
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 5
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 12
C=30 pF, 2.7 V≤VDDIOx≤3.6 V - 120(3)
C=30 pF, 1.62 V≤VDDIOx≤2.7 V - 50
C=30 pF, 1.08 V≤VDDIOx≤1.62 V - 10
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 180(3)
11 C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 75
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 10
C=30 pF, 2.7 V≤VDDIOx≤3.6 V - 3.3
Tr/Tf Output rise and fall time C=30 pF, 1.62 V≤VDDIOx≤2.7 V - 6 ns
C=30 pF, 1.08 V≤VDDIOx≤1.62 V - 16
Fmax Maximum frequency - 1 MHz
Fm+ C=50 pF, 1.6 V≤VDDIOx≤3.6 V
(4)
Tf Output fall time - 5 ns
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.
Refer to the RM0351 reference manual for a description of GPIO Port configuration register.
3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.
4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.
DS10198 Rev 9 169/19

233
Figure 31. I/O AC characteristics definition(1)
90% 10%
50% 50%
10% 90%
t r(IO)out t f(IO)out
Maximum frequency is achieved with a duty cycle at (45 - 55%) when loaded by the
specified capacitance.
1. Refer to Table 72: I/O AC characteristics.
6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 23: General operating conditions.
Table 73. NRST pin characteristics(1)

NRST input low level

VIL(NRST) - - - 0.3ₓVDDIOx
voltage
V
NRST input high level
VIH(NRST) - 0.7ₓVDDIOx - -
voltage
NRST Schmitt trigger
Vhys(NRST) - - 200 - mV
voltage hysteresis
Weak pull-up
RPU VIN = VSS 25 40 55 kΩ
equivalent resistor(2)
NRST input filtered
VF(NRST) - - - 70 ns
pulse
NRST input not filtered
VNF(NRST) 1.71 V ≤ VDD ≤ 3.6 V 350 - - ns
pulse
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
170/19 DS10198 Rev 9

Figure 32. Recommended NRST pin protection
External
reset circuit(1) VDD
RPU
NRST(2) Internal reset
Filter
0.1 μF(3)
MS19878V3
1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 73: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
6.3.16 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
Table 74. EXTI input characteristics(1)

Pulse length to event

PLEC - 20 - - ns
controller
6.3.17 Analog switches booster
Table 75. Analog switches booster characteristics(1)

Symbol Parameter Min Typ Max Unit
VDD Supply voltage 1.62 - 3.6 V

tSU(BOOST) Booster startup time - - 240 µs
Booster consumption for
- - 250
1.62 V ≤ VDD ≤ 2.0 V
IDD(BOOST) - - 500 µA
2.0 V ≤ VDD ≤ 2.7 V
- - 900
2.7 V ≤ VDD ≤ 3.6 V
DS10198 Rev 9 171/19

233
6.3.18 Analog-to-Digital converter characteristics

Unless otherwise specified, the parameters given in Table 76 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 23: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.
Table 76. ADC characteristics(1) (2)

VDDA Analog supply voltage - 1.62 - 3.6 V

VDDA ≥ 2 V 2 - VDDA V
VREF+ Positive reference voltage
VDDA < 2 V VDDA V
Negative reference
VREF- - VSSA V
voltage
Range 1 0.14 - 80
fADC ADC clock frequency MHz
Range 2 0.14 - 26
Resolution = 12 bits - - 5.33
Sampling rate for FAST Resolution = 10 bits - - 6.15

channels Resolution = 8 bits - - 7.27
fs Msps
Sampling rate for SLOW Resolution = 10 bits - - 4.71

channels Resolution = 8 bits - - 5.33
fADC = 80 MHz
- - 5.33 MHz
fTRIG External trigger frequency Resolution = 12 bits
Resolution = 12 bits - - 15 1/fADC
Conversion voltage
VAIN (3) - 0 - VREF+ V
range(2)
RAIN External input impedance - - - 50 kΩ
Internal sample and hold
CADC - - 5 - pF
capacitor
conversion
tSTAB Power-up time - 1
cycle
fADC = 80 MHz 1.45 µs
tCAL Calibration time
- 116 1/fADC
CKMODE = 00 1.5 2 2.5
Trigger conversion
latency Regular and CKMODE = 01 - - 2.0
tLATR 1/fADC
injected channels without CKMODE = 10 - - 2.25
conversion abort
CKMODE = 11 - - 2.125
172/19 DS10198 Rev 9

Table 76. ADC characteristics(1) (2) (continued)

CKMODE = 00 2.5 3 3.5

Trigger conversion
latency Injected channels CKMODE = 01 - - 3.0
tLATRINJ 1/fADC
aborting a regular CKMODE = 10 - - 3.25
conversion
CKMODE = 11 - - 3.125
fADC = 80 MHz 0.03125 - 8.00625 µs
ts Sampling time
- 2.5 - 640.5 1/fADC
ADC voltage regulator
tADCVREG_STUP start-up time - - - 20 µs
fADC = 80 MHz
0.1875 - 8.1625 µs
Resolution = 12 bits
Total conversion time
tCONV ts + 12.5 cycles for
(including sampling time)
Resolution = 12 bits successive approximation 1/fADC
= 15 to 653
fs = 5 Msps - 730 830
ADC consumption from
IDDA(ADC) fs = 1 Msps - 160 220 µA
the VDDA supply
fs = 10 ksps - 16 50
fs = 5 Msps - 130 160
IDDV_S(ADC) the VREF+ single ended fs = 1 Msps - 30 40 µA
mode
fs = 10 ksps - 0.6 2
fs = 5 Msps - 260 310
IDDV_D(ADC) the VREF+ differential fs = 1 Msps - 60 70 µA
mode
fs = 10 ksps - 1.3 3
1. Guaranteed by design
2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 4: Pinouts and pin description for further details.
The maximum value of RAIN can be found in Table 77: Maximum ADC RAIN.
DS10198 Rev 9 173/19

233
Table 77. Maximum ADC RAIN(1)(2)

RAIN max (Ω)
Sampling cycle Sampling time [ns]
Resolution
@80 MHz @80 MHz
Fast channels(3) Slow channels(4)
2.5 31.25 100 N/A

6.5 81.25 330 100
12.5 156.25 680 470
24.5 306.25 1500 1200
12 bits
47.5 593.75 2200 1800
92.5 1156.25 4700 3900
247.5 3093.75 12000 10000
640.5 8006.75 39000 33000
2.5 31.25 120 N/A
6.5 81.25 390 180
12.5 156.25 820 560
24.5 306.25 1500 1200
10 bits
47.5 593.75 2200 1800
92.5 1156.25 5600 4700
247.5 3093.75 12000 10000
640.5 8006.75 47000 39000
2.5 31.25 180 N/A
6.5 81.25 470 270
12.5 156.25 1000 680
24.5 306.25 1800 1500
8 bits
47.5 593.75 2700 2200
92.5 1156.25 6800 5600
247.5 3093.75 15000 12000
640.5 8006.75 50000 50000
2.5 31.25 220 N/A
6.5 81.25 560 330
12.5 156.25 1200 1000
24.5 306.25 2700 2200
6 bits
47.5 593.75 3900 3300
92.5 1156.25 8200 6800
247.5 3093.75 18000 15000
640.5 8006.75 50000 50000
174/19 DS10198 Rev 9

VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. Fast channels are available by access pins: PC0, PC1, PC2, PC3, PA0.
4. Slow channels are: all ADC inputs except the fast channels.
DS10198 Rev 9 175/19

233
Table 78. ADC accuracy - limited test conditions 1(1)(2)(3)(4)

Sym-
Parameter Conditions(5) Min Typ Max Unit
bol
Single Fast channel (max speed) - 4 5

Total ended Slow channel (max speed) - 4 5
ET unadjusted
error Fast channel (max speed) - 3.5 4.5
Differential
Slow channel (max speed) - 3.5 4.5
Single Fast channel (max speed) - 1 2.5

ended Slow channel (max speed) - 1 2.5
Offset
EO
Differential
Single Fast channel (max speed) - 2.5 4.5

ended Slow channel (max speed) - 2.5 4.5
EG Gain error LSB
Fast channel (max speed) - 2.5 3.5
Differential

Differential ended Slow channel (max speed) - 1 1.5
ED linearity
error ADC clock frequency ≤ Fast channel (max speed) - 1 1.2
80 MHz, Differential
Slow channel (max speed) - 1 1.2
Sampling rate ≤ 5.33 Msps,
VDDA = VREF+ = 3 V, Single Fast channel (max speed) - 1.5 2.5
Integral TA = 25 °C ended Slow channel (max speed) - 1.5 2.5
EL linearity
error Fast channel (max speed) - 1 2
Differential
Slow channel (max speed) - 1 2
Single Fast channel (max speed) 10.4 10.5 -

Effective ended Slow channel (max speed) 10.4 10.5 -
ENOB number of bits
bits Fast channel (max speed) 10.8 10.9 -
Differential
Slow channel (max speed) 10.8 10.9 -
Single Fast channel (max speed) 64.4 65 -

Signal-to-
ended Slow channel (max speed) 64.4 65 -
noise and
SINAD
distortion Fast channel (max speed) 66.8 67.4 -
ratio Differential
dB
Single Fast channel (max speed) 65 66 -
ended Slow channel (max speed) 65 66 -
Signal-to-
SNR
noise ratio Fast channel (max speed) 67 68 -
Differential
Slow channel (max speed) 67 68 -
176/19 DS10198 Rev 9

Table 78. ADC accuracy - limited test conditions 1(1)(2)(3)(4) (continued)

Sym-
bol
ADC clock frequency ≤ Single Fast channel (max speed) - -74 -73
Total 80 MHz, ended Slow channel (max speed) - -74 -73
THD harmonic Sampling rate ≤ 5.33 Msps, dB
distortion VDDA = VREF+ = 3 V, Fast channel (max speed) - -79 -76
Differential
TA = 25 °C Slow channel (max speed) - -79 -76
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The above table gives the ADC performance in 12-bit mode.
VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.
DS10198 Rev 9 177/19

233

Sym-
bol

Total ended Slow channel (max speed) - 4 6.5
ET unadjusted
Differential

ended Slow channel (max speed) - 1 5
Offset
EO
error Fast channel (max speed) - 1.5 3
Differential
Slow channel (max speed) - 1.5 3
Single Fast channel (max speed) - 2.5 6

ended Slow channel (max speed) - 2.5 6
EG Gain error LSB
Fast channel (max speed) - 2.5 3.5
Differential

ED linearity
error Fast channel (max speed) - 1 1.2
ADC clock frequency ≤ Differential
80 MHz, Slow channel (max speed) - 1 1.2
Sampling rate ≤ 5.33 Msps, Fast channel (max speed) - 1.5 3.5
Single
2 V ≤ VDDA ended
Integral Slow channel (max speed) - 1.5 3.5
EL linearity
Differential
Single Fast channel (max speed) 10 10.5 -

Effective ended Slow channel (max speed) 10 10.5 -
ENOB number of bits
Differential

Signal-to-
noise and
SINAD
distortion Fast channel (max speed) 66 67.4 -
ratio Differential
Slow channel (max speed) 66 67.4 -
dB
Signal-to-
SNR
noise ratio Fast channel (max speed) 66.5 68 -
Differential
Slow channel (max speed) 66.5 68 -
178/19 DS10198 Rev 9


Sym-
bol
Single Fast channel (max speed) - -74 -65

ADC clock frequency ≤
THD harmonic dB
Sampling rate ≤ 5.33 Msps, Fast channel (max speed) - -79 -70
distortion
2 V ≤ VDDA Differential
Slow channel (max speed) - -79 -71
DS10198 Rev 9 179/19

233

Sym-
bol

Total ended Slow channel (max speed) - 4.5 6.5
ET unadjusted
Differential

Offset
EO
Differential
Single Fast channel (max speed) - 4.5 7

EG Gain error LSB
Fast channel (max speed) - 3.5 4
Differential

Differential ended Slow channel (max speed) - 1.2 1.5
ED linearity ADC clock frequency ≤
Sampling rate ≤ 5.33 Msps, Slow channel (max speed) - 1 1.2
1.65 V ≤ VDDA = VREF+ ≤ Fast channel (max speed) - 3 3.5
Single
3.6 V,
Integral ended Slow channel (max speed) - 2.5 3.5
EL linearity Voltage scaling Range 1
Differential
Single Fast channel (max speed) 10 10.4 -

Effective ended Slow channel (max speed) 10 10.4 -
ENOB number of bits
Differential

Signal-to-
noise and
SINAD
distortion Fast channel (max speed) 65 66 -
ratio Differential
dB
Signal-to-
SNR
Differential
180/19 DS10198 Rev 9


Sym-
bol
80 MHz, ended
Total Slow channel (max speed) - -71 -67
Sampling rate ≤ 5.33 Msps,
THD harmonic Fast channel (max speed) - -72 -71 dB
1.65 V ≤ VDDA = VREF+ ≤
distortion
3.6 V, Differential
Slow channel (max speed) - -72 -71
Voltage scaling Range 1
DS10198 Rev 9 181/19

233

Sym-
bol

Total ended Slow channel (max speed) - 4 5
ET unadjusted
Differential

ended Slow channel (max speed) - 2 4
Offset
EO
Differential

ended Slow channel (max speed) - 4 4.5
EG Gain error LSB
Fast channel (max speed) - 3 4
Differential
Slow channel (max speed) - 3 4

ED linearity
error ADC clock frequency ≤ Fast channel (max speed) - 1 1.2
1.65 V ≤ VDDA = VREF+ ≤
3.6 V, Single Fast channel (max speed) - 2.5 3
Integral Voltage scaling Range 2 ended Slow channel (max speed) - 2.5 3
EL linearity
Differential
Single Fast channel (max speed) 10.2 10.5 -

Effective ended Slow channel (max speed) 10.2 10.5 -
ENOB number of bits
Differential

Signal-to-
noise and
SINAD
distortion Fast channel (max speed) 65 66 -
ratio Differential
dB
Signal-to-
SNR
Differential
182/19 DS10198 Rev 9


Sym-
bol
THD harmonic 1.65 V ≤ VDDA = VREF+ ≤ dB
distortion 3.6 V, Fast channel (max speed) - -73 -72
Differential
Voltage scaling Range 2 Slow channel (max speed) - -73 -72
DS10198 Rev 9 183/19

233
Figure 33. ADC accuracy characteristics
VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+
(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA
MSv19880V6
Figure 34. Typical connection diagram when using the ADC with FT/TT pins featuring
analog switch function
VDDA(4) VREF+(4)
I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter
(2)
Cparasitic Ilkg(3) CADC
VAIN Sampling
switch with
multiplexing
VSS VSS VSSA
MSv67871V3
1. Refer to Table 76: ADC characteristics for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 70: I/O static characteristics). A high Cparasitic value will downgrade
conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 70: I/O static characteristics for the values of Ilkg.
4. Refer to Figure 21: Power supply scheme.
General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 21: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
184/19 DS10198 Rev 9

6.3.19 Digital-to-Analog converter characteristics
Table 82. DAC characteristics(1)

DAC output buffer OFF (no resistive

load on DAC1_OUTx pin or internal 1.71 -
Analog supply voltage for
VDDA connection) 3.6
DAC ON
Other modes 1.80 -
DAC output buffer OFF (no resistive V

load on DAC1_OUTx pin or internal 1.71 -
VREF+ Positive reference voltage connection) VDDA
Other modes 1.80 -
VREF- Negative reference voltage - VSSA
DAC output connected to VSSA 5 - -

RL Resistive load kΩ
buffer ON connected to VDDA 25 - -
RO Output Impedance DAC output buffer OFF 9.6 11.7 13.8 kΩ
Output impedance sample VDD = 2.7 V - - 2
RBON and hold mode, output kΩ
buffer ON VDD = 2.0 V - - 3.5
Output impedance sample VDD = 2.7 V - - 16.5

RBOFF and hold mode, output kΩ
buffer OFF VDD = 2.0 V - - 18.0
CL DAC output buffer ON - - 50 pF

Capacitive load
CSH Sample and hold mode - 0.1 1 µF
VREF+
Voltage on DAC1_OUTx DAC output buffer ON 0.2 -
VDAC_OUT – 0.2 V
output
DAC output buffer OFF 0 - VREF+
±0.5 LSB - 1.7 3
Settling time (full scale: for Normal mode
±1 LSB - 1.6 2.9
a 12-bit code transition DAC output
between the lowest and the buffer ON ±2 LSB - 1.55 2.85
tSETTLING highest input codes when CL ≤ 50 pF, µs
±4 LSB - 1.48 2.8
DAC1_OUTx reaches final RL ≥ 5 kΩ
value ±0.5LSB, ±1 LSB, ±8 LSB - 1.4 2.75
±2 LSB, ±4 LSB, ±8 LSB) Normal mode DAC output buffer
- 2 2.5
OFF, ±1LSB, CL = 10 pF
Wakeup time from off state Normal mode DAC output buffer ON
- 4.2 7.5
(setting the ENx bit in the CL ≤ 50 pF, RL ≥ 5 kΩ
tWAKEUP(2) µs
DAC Control register) until Normal mode DAC output buffer
final value ±1 LSB - 2 5
OFF, CL ≤ 10 pF
Normal mode DAC output buffer ON
PSRR VDDA supply rejection ratio - -80 -28 dB
CL ≤ 50 pF, RL = 5 kΩ, DC
DS10198 Rev 9 185/19

233
Table 82. DAC characteristics(1) (continued)

Minimal time between two

consecutive writes into the
DAC_DORx register to
guarantee a correct
DAC1_OUTx for a small
TW_to_W variation of the input code - - µs
(1 LSB)
DAC_MCR:MODEx[2:0] =
000 or 001 CL ≤ 50 pF, RL ≥ 5 kΩ 1
DAC_MCR:MODEx[2:0] =
010 or 011 CL ≤ 10 pF 1.4
DAC output buffer
- 0.7 3.5
DAC1_OUTx ON, CSH = 100 nF
Sampling time in sample ms
pin connected DAC output buffer
and hold mode (code - 10.5 18
OFF, CSH = 100 nF
transition between the
tSAMP lowest input code and the DAC1_OUTx
highest input code when pin not
DAC1_OUTx reaches final connected DAC output buffer
- 2 3.5 µs
value ±1LSB) (internal OFF
connection
only)
Sample and hold mode,
Ileak Output leakage current - - -(3) nA
DAC1_OUTx pin connected
Internal sample and hold
CIint - 5.2 7 8.8 pF
capacitor
tTRIM Middle code offset trim time DAC output buffer ON 50 - - µs
Middle code offset for 1 trim VREF+ = 3.6 V - 1500 -

Voffset µV
code step VREF+ = 1.8 V - 750 -
No load, middle
- 315 500
DAC output code (0x800)
buffer ON No load, worst code
- 450 670
(0xF1C)
DAC consumption from DAC output No load, middle
IDDA(DAC) - - 0.2 µA
VDDA buffer OFF code (0x800)
315 ₓ 670 ₓ
Sample and hold mode, CSH = Ton/(Ton Ton/(Ton
-
100 nF +Toff) +Toff)
(4) (4)
186/19 DS10198 Rev 9

Table 82. DAC characteristics(1) (continued)

No load, middle
- 185 240
DAC output code (0x800)
buffer ON No load, worst code
- 340 400
(0xF1C)
DAC output No load, middle
- 155 205
buffer OFF code (0x800)
DAC consumption from
IDDV(DAC) 185 ₓ 400 ₓ µA
VREF+
Sample and hold mode, buffer ON, Ton/(Ton Ton/(Ton
-
CSH = 100 nF, worst case +Toff) +Toff)
(4) (4)
155 ₓ 205 ₓ
Sample and hold mode, buffer OFF, Ton/(Ton Ton/(Ton
-
CSH = 100 nF, worst case +Toff) +Toff)
(4) (4)
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Refer to Table 70: I/O static characteristics.
4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0351 reference manual for more details.
Figure 35. 12-bit buffered / non-buffered DAC
Buffered/non-buffered DAC
(1)
Buffer
RLOAD
12-bit
DACx_OUT
digital to
analog
converter
CLOAD
ai17157d
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
DS10198 Rev 9 187/19

233
Table 83. DAC accuracy(1)

.
Differential non DAC output buffer ON - - ±2

DNL
linearity (2) DAC output buffer OFF - - ±2
- monotonicity 10 bits guaranteed
DAC output buffer ON
- - ±4
Integral non CL ≤ 50 pF, RL ≥ 5 kΩ
INL
linearity(3) DAC output buffer OFF
- - ±4
CL ≤ 50 pF, no RL
VREF+ = 3.6 V - - ±12

CL ≤ 50 pF, RL ≥ 5 kΩ LSB
Offset error at
Offset VREF+ = 1.8 V - - ±25
code 0x800(3)
DAC output buffer OFF
- - ±8
CL ≤ 50 pF, no RL
Offset error at DAC output buffer OFF
Offset1 - - ±5
code 0x001(4) CL ≤ 50 pF, no RL
Offset Error at VREF+ = 3.6 V - - ±5

OffsetCal code 0x800
CL ≤ 50 pF, RL ≥ 5 kΩ
after calibration VREF+ = 1.8 V - - ±7

- - ±0.5
CL ≤ 50 pF, RL ≥ 5 kΩ
(5)
Gain Gain error %
DAC output buffer OFF
- - ±0.5
CL ≤ 50 pF, no RL
Total - - ±30
CL ≤ 50 pF, RL ≥ 5 kΩ
TUE unadjusted LSB
error DAC output buffer OFF
- - ±12
CL ≤ 50 pF, no RL
Total
unadjusted DAC output buffer ON
TUECal - - ±23 LSB
error after CL ≤ 50 pF, RL ≥ 5 kΩ
calibration
CL ≤ 50 pF, RL ≥ 5 kΩ - 71.2 -
Signal-to-noise 1 kHz, BW 500 kHz
SNR dB
ratio DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz - 71.6 -
BW 500 kHz
- -78 -
Total harmonic CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
THD dB
distortion DAC output buffer OFF
- -79 -
CL ≤ 50 pF, no RL, 1 kHz
188/19 DS10198 Rev 9

Table 83. DAC accuracy(1) (continued)


Signal-to-noise - 70.4 -
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
SINAD and distortion dB
ratio DAC output buffer OFF
- 71 -
- 11.4 -
Effective CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
ENOB bits
number of bits DAC output buffer OFF
- 11.5 -
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON.
DS10198 Rev 9 189/19

233
6.3.20 Voltage reference buffer characteristics
Table 84. VREFBUF characteristics(1)

VRS = 0 2.4 - 3.6

Normal mode
Analog supply VRS = 1 2.8 - 3.6
VDDA
voltage VRS = 0 1.65 - 2.4
Degraded mode(2)
VRS = 1 1.65 - 2.8
V
(3)
VRS = 0 2.046 2.048 2.049(3)
Normal mode
Voltage VRS = 1 2.498(3) 2.5 2.502(3)
VREFBUF_
reference
OUT output VRS = 0 VDDA-150 mV - VDDA
Degraded mode(2)
VRS = 1 VDDA-150 mV - VDDA
Trim step
TRIM - - - ±0.05 ±0.1 %
resolution
CL Load capacitor - - 0.5 1 1.5 µF
Equivalent
esr Serial Resistor - - - - 2 Ω
of Cload
Static load
Iload - - - - 4 mA
current
Iload = 500 µA - 200 1000
Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V ppm/V
Iload = 4 mA - 100 500
Load
Iload_reg 500 μA ≤ Iload ≤4 mA Normal mode - 50 500 ppm/mA
regulation
Tcoeff_
-40 °C < TJ < +125 °C - - vrefint +
Temperature 50
TCoeff ppm/ °C
coefficient Tcoeff_
0 °C < TJ < +50 °C - - vrefint +
50
Power supply DC 40 60 -
PSRR dB
rejection 100 kHz 25 40 -
CL = 0.5 µF(4) - 300 350
tSTART Start-up time CL = 1.1 µF(4) - 500 650 µs
(4)
CL = 1.5 µF - 650 800
Control of
maximum DC
current drive
IINRUSH on VREFBUF_ - - - 8 - mA
OUT during
start-up phase
(5)
190/19 DS10198 Rev 9

Table 84. VREFBUF characteristics(1) (continued)

Iload = 0 µA - 16 25
VREFBUF
IDDA(VREF
consumption Iload = 500 µA - 18 30 µA
BUF)
from VDDA
Iload = 4 mA - 35 50
1. Guaranteed by design, unless otherwise specified.
2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA -
drop voltage).
4. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.
5. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in
the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1.
DS10198 Rev 9 191/19

233
6.3.21 Comparator characteristics
Table 85. COMP characteristics(1)

VDDA Analog supply voltage - 1.62 - 3.6

Comparator input voltage
VIN - 0 - VDDA V
range
VBG(2) Scaler input voltage - VREFINT
VSC Scaler offset voltage - - ±5 ±10 mV
Scaler static consumption BRG_EN=0 (bridge disable) - 200 300 nA

IDDA(SCALER)
from VDDA BRG_EN=1 (bridge enable) - 0.8 1 µA
tSTART_SCALER Scaler startup time - - 100 200 µs
High-speed VDDA ≥ 2.7 V - - 5

mode VDDA < 2.7 V - - 7
Comparator startup time to
tSTART reach propagation delay VDDA ≥ 2.7 V - - 15 µs
specification Medium mode
VDDA < 2.7 V - - 25
Ultra-low-power mode - - 80
High-speed VDDA ≥ 2.7 V - 55 80

ns
mode VDDA < 2.7 V - 65 100
Propagation delay for
tD(3) 200 mV step VDDA ≥ 2.7 V - 0.55 0.9
with 100 mV overdrive Medium mode
VDDA < 2.7 V - 0.65 1 µs
Ultra-low-power mode - 5 12
Full common
Voffset Comparator offset error - - ±5 ±20 mV
mode range
No hysteresis - 0 -
Low hysteresis 4 8 16
Vhys Comparator hysteresis mV
Medium hysteresis 8 15 30
High hysteresis 15 27 52
192/19 DS10198 Rev 9

Table 85. COMP characteristics(1) (continued)

Static - 400 600

Ultra-low- With 50 kHz nA
power mode ±100 mV overdrive - 1200 -
square signal
Static - 5 7
Comparator consumption
IDDA(COMP) Medium mode With 50 kHz
from VDDA ±100 mV overdrive - 6 -
square signal
µA
Static - 70 100
High-speed With 50 kHz
mode ±100 mV overdrive - 75 -
square signal
Comparator input bias - - - -(4)

Ibias nA
current
2. Refer to Table 26: Embedded internal voltage reference.
4. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 70: I/O static characteristics.
6.3.22 Operational amplifiers characteristics
Table 86. OPAMP characteristics(1)

Analog supply
VDDA - 1.8 - 3.6 V
voltage(2)
Common mode
CMIR - 0 - VDDA V
input range
Input offset 25 °C, No Load on output. - - ±1.5

VIOFFSET mV
voltage All voltage/Temp. - - ±3
Input offset Normal mode - ±5 -

∆VIOFFSET μV/°C
voltage drift Low-power mode - ±10 -
Offset trim step
TRIMOFFSETP at low common
- - 0.8 1.1
TRIMLPOFFSETP input voltage
(0.1 ₓ VDDA)
mV
Offset trim step
TRIMOFFSETN at high common
- - 1 1.35
TRIMLPOFFSETN input voltage
(0.9 ₓ VDDA)
DS10198 Rev 9 193/19

233
Table 86. OPAMP characteristics(1) (continued)

Normal mode - - 500

ILOAD Drive current VDDA ≥ 2 V
Low-power mode - - 100
µA
Drive current in Normal mode - - 450
ILOAD_PGA VDDA ≥ 2 V
PGA mode Low-power mode - - 50
Resistive load Normal mode 4 - -

(connected to
RLOAD VDDA < 2 V
VSSA or to
VDDA) Low-power mode 20 - -
kΩ
Resistive load
Normal mode 4.5 - -
in PGA mode
RLOAD_PGA (connected to VDDA < 2 V
VSSA or to
Low-power mode 40 - -
VDDA)
CLOAD Capacitive load - - - 50 pF
Common mode Normal mode - -85 -

CMRR dB
rejection ratio Low-power mode - -90 -
CLOAD ≤ 50 pf,
Normal mode 70 85 -
Power supply RLOAD ≥ 4 kΩ DC
PSRR dB
rejection ratio CLOAD ≤ 50 pf,
Low-power mode 72 90 -
RLOAD ≥ 20 kΩ DC
Normal mode VDDA ≥ 2.4 V 550 1600 2200
(OPA_RANGE = 1)
Gain Bandwidth Low-power mode 100 420 600
GBW kHz
Product Normal mode 250 700 950
VDDA < 2.4 V
Low-power mode (OPA_RANGE = 0) 40 180 280
Normal mode - 700 -
Slew rate VDDA ≥ 2.4 V
(from 10 and Low-power mode - 180 -
SR(3) V/ms
90% of output Normal mode - 300 -
voltage) VDDA < 2.4 V
Low-power mode - 80 -
Normal mode 55 110 -
AO Open loop gain dB
Low-power mode 45 110 -
VDDA -
Normal mode - -
High saturation Iload = max or Rload = 100
VOHSAT(3)
voltage min Input at VDDA. VDDA -
Low-power mode - - mV
50
Low saturation Normal mode Iload = max or Rload = - - 100

VOLSAT(3)
voltage Low-power mode min Input at 0. - - 50
Normal mode - 74 -
φm Phase margin °
194/19 DS10198 Rev 9


Normal mode - 13 -
GM Gain margin dB
CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ
Normal mode - 5 10
follower
Wake up time configuration
tWAKEUP µs
from OFF state. CLOAD ≤ 50 pf,
RLOAD ≥ 20 kΩ
Low-power mode - 10 30
follower
configuration
TJ ≤ 75 °C - - 1
Dedicated input TJ ≤ 85 °C - - 3
OPAMP input (UFBGA132 only) TJ ≤ 105 °C - - 8
Ibias nA
bias current
TJ ≤ 125 °C - - 15
General purpose input (all packages
- - -(4)
except UFBGA132)
- 2 -
Non inverting - 4 -
PGA gain(3) - -
gain value - 8 -
- 16 -
PGA Gain = 2 - 80/80 -
120/
R2/R1 internal PGA Gain = 4 - -
40
resistance
Rnetwork 140/ kΩ/kΩ
values in PGA PGA Gain = 8 - -
mode(5) 20
150/
PGA Gain = 16 - -
10
Resistance
Delta R variation (R1 or - -15 - 15 %
R2)
PGA gain error PGA gain error - -1 - 1 %
GBW/
Gain = 2 - - -
2
GBW/
PGA bandwidth Gain = 4 - -
4
-
PGA BW for different non MHz
inverting gain GBW/
Gain = 8 - - -
8
GBW/
Gain = 16 - - -
16
DS10198 Rev 9 195/19

233

at 1 kHz, Output
Normal mode - 500 -
loaded with 4 kΩ
at 1 kHz, Output
Voltage noise loaded with 20 kΩ
en nV/√Hz
density at 10 kHz, Output
Normal mode - 180 -
loaded with 4 kΩ
at 10 kHz, Output
loaded with 20 kΩ
OPAMP Normal mode - 120 260
no Load, quiescent
IDDA(OPAMP)(3) consumption µA
Low-power mode mode - 45 100
from VDDA
2. The temperature range is limited to 0 °C-125 °C when VDDA is below 2 V
4. Mostly I/O leakage, when used in analog mode. Refer to Ilkg parameter in Table 70: I/O static characteristics.
5. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between
OPAMP inverting input and ground. The PGA gain =1+R2/R1
196/19 DS10198 Rev 9

6.3.23 Temperature sensor characteristics
Table 87. TS characteristics

TL(1) VTS linearity with temperature - ±1 ±2 °C

(2)
Avg_Slope Average slope 2.3 2.5 2.7 mV/°C
V30 Voltage at 30°C (±5 °C)(3) 0.742 0.76 0.785 V
tSTART
Sensor Buffer Start-up time in continuous mode(4) - 8 15 µs
(TS_BUF)(1)
tSTART(1) Start-up time when entering in continuous mode(4) - 70 120 µs
tS_temp(1) ADC sampling time when reading the temperature 5 - - µs
Temperature sensor consumption from VDD, when

IDD(TS)(1) - 4.7 7 µA
selected by ADC
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 8:
Temperature sensor calibration values.
4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
6.3.24 VBAT monitoring characteristics
Table 88. VBAT monitoring characteristics

R Resistor bridge for VBAT - 3×39 - kΩ

Q Ratio on VBAT measurement - 3 - -
(1)
Er Error on Q -10 - 10 %
tS_vbat(1) ADC sampling time when reading the VBAT 12 - - µs
Table 89. VBAT charging characteristics

Battery VBRS = 0 - 5 -
RBC charging kΩ
resistor VBRS = 1 - 1.5 -
DS10198 Rev 9 197/19

233
6.3.25 LCD controller characteristics

The devices embed a built-in step-up converter to provide a constant LCD reference voltage
independently from the VDD voltage. An external capacitor Cext must be connected to the
VLCD pin to decouple this converter.
Table 90. LCD controller characteristics(1)
VLCD LCD external voltage - - 3.6

VLCD0 LCD internal reference voltage 0 - 2.62 -
VLCD3 LCD internal reference voltage 3 - 3.04 - V
Buffer OFF
0.2 - 2
(BUFEN=0 is LCD_CR register)
Cext VLCD external capacitance μF
Buffer ON
1 - 2
(BUFEN=1 is LCD_CR register)
Supply current from VDD at Buffer OFF
- 3 -
VDD = 2.2 V (BUFEN=0 is LCD_CR register)
(2)
ILCD μA
Supply current from VDD at Buffer OFF
- 1.5 -
VDD = 3.0 V (BUFEN=0 is LCD_CR register)
Buffer OFF
- 0.5 -
(BUFFEN = 0, PON = 0)
Buffer ON
- 0.6 -
Supply current from VLCD (BUFFEN = 1, 1/2 Bias)
IVLCD μA
(VLCD = 3 V) Buffer ON
- 0.8 -
(BUFFEN = 1, 1/3 Bias)
Buffer ON
- 1 -
(BUFFEN = 1, 1/4 Bias)
RHN Total High Resistor value for Low drive resistive network - 5.5 - MΩ
RLN Total Low Resistor value for High drive resistive network - 240 - kΩ
V44 Segment/Common highest level voltage - VLCD -
V34 Segment/Common 3/4 level voltage - 3/4 VLCD -
V12 Segment/Common 1/2 level voltage - 1/2 VLCD - V
V0 Segment/Common lowest level voltage - 0 -
198/19 DS10198 Rev 9

2. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, minimum pulse ON duration, division ratio= 64, all pixels
active, no LCD connected.
DS10198 Rev 9 199/19

233
6.3.26 DFSDM characteristics

Unless otherwise specified, the parameters given in Table 91 for DFSDM are derived from
tests performed under the ambient temperature, fAPB2 frequency and VDD supply voltage
conditions summarized in Table 23: General operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 ₓ VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDM1_CKINy, DFSDM1_DATINy, DFSDM1_CKOUT for
DFSDM).
Table 91. DFSDM characteristics(1)

DFSDM
fDFSDMCLK - - - fSYSCLK
clock
MHz
fCKIN Input clock 20
SPI mode (SITP[1:0] = 01) - -
(1/TCKIN) frequency (fDFSDMCLK/4)
Output clock
fCKOUT - - - 20 MHz
frequency
Even division
CKOUTDIV[7:0] = n 45 50 55
Output clock 1.62 < 1,3,5,..
DuCyCKOUT frequency VDD %
duty cycle < 3.6 V Odd division (((n/2+1)/ (((n/2+1)/
((n/2+1)/
CKOUTDIV[7:0] = n (n+1))*100) (n+1))*100)
(n+1))*100
2,4,6,.. -5 +5
Input clock SPI mode (SITP[1:0] = 01),
twh(CKIN)
high and low External clock mode (SPICKSEL[1:0] TCKIN/2-0.5 TCKIN/2 -
twl(CKIN)
time = 0)
SPI mode (SITP[1:0]=01),
Data input
tsu External clock mode (SPICKSEL[1:0] 0 - -
setup time
= 0)
SPI mode (SITP[1:0]=01), ns
Data input
th External clock mode (SPICKSEL[1:0] 2 - -
hold time
= 0)
Manchester Manchester mode (SITP[1:0] = 10 or
(CKOUT (2 ₓ
data period 11),
TManchester DIV+1) ₓ - CKOUTDIV) ₓ
(recovered Internal clock mode (SPICKSEL[1:0]
TDFSDMCLK TDFSDMCLK
clock period) ≠ 0)
200/19 DS10198 Rev 9

Figure 16: DFSDM timing diagram

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6.3.27 Timer characteristics

The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
DS10198 Rev 9 201/19

233
Table 92. TIMx(1) characteristics

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 80 MHz 12.5 - ns
Timer external clock - 0 fTIMxCLK/2 MHz

fEXT
frequency on CH1 to CH4 f
TIMxCLK = 80 MHz 0 40 MHz
TIMx (except TIM2
- 16
ResTIM Timer resolution and TIM5) bit
TIM2 and TIM5 - 32
16-bit counter clock - 1 65536 tTIMxCLK

tCOUNTER
period fTIMxCLK = 80 MHz 0.0125 819.2 µs
Maximum possible count - - 65536 × 65536 tTIMxCLK

tMAX_COUNT
with 32-bit counter fTIMxCLK = 80 MHz - 53.68 s
1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.
Table 93. IWDG min/max timeout period at 32 kHz (LSI)(1)

Min timeout RL[11:0]= Max timeout RL[11:0]=
Prescaler divider PR[2:0] bits Unit
0x000 0xFFF
/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there
is always a full RC period of uncertainty.
Table 94. WWDG min/max timeout value at 80 MHz (PCLK)

Prescaler WDGTB Min timeout value Max timeout value Unit
1 0 0.0512 3.2768
2 1 0.1024 6.5536
ms
4 2 0.2048 13.1072
8 3 0.4096 26.2144
202/19 DS10198 Rev 9

6.3.28 Communication interfaces characteristics

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0351 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FT_f I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 95. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit
Maximum pulse width of spikes

tAF that are suppressed by the analog 50(2) 260(3) ns
filter
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
DS10198 Rev 9 203/19

233
SPI characteristics
Unless otherwise specified, the parameters given in Table 96 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 23: General operating conditions.
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 96. SPI characteristics(1)

Master mode receiver/full duplex

2.7 < VDD < 3.6 V 24
Voltage Range 1
Master mode receiver/full duplex
1.71 < VDD < 3.6 V 13
Voltage Range 1
Master mode transmitter
1.71 < VDD < 3.6 V 40
Voltage Range 1
fSCK Slave mode receiver

SPI clock frequency 1.71 < VDD < 3.6 V - - 40 MHz
1/tc(SCK)
Voltage Range 1
Slave mode transmitter/full duplex
2.7 < VDD < 3.6 V 26(2)
Voltage Range 1
Slave mode transmitter/full duplex
1.71 < VDD < 3.6 V 16(2)
Voltage Range 1
Voltage Range 2 13
1.08 < VDDIO2 < 1.32 V(3) 8
tsu(NSS) NSS setup time Slave mode, SPI prescaler = 2 4ₓTPCLK - - ns
th(NSS) NSS hold time Slave mode, SPI prescaler = 2 2ₓTPCLK - - ns
tw(SCKH)
SCK high and low time Master mode TPCLK-2 TPCLK TPCLK+2 ns
tw(SCKL)
tsu(MI) Master mode 3.5 - -
Data input setup time ns
tsu(SI) Slave mode 3 - -
th(MI) Master mode 6.5 - -
Data input hold time ns
th(SI) Slave mode 3 - -
ta(SO) Data output access time Slave mode 9 - 36 ns
tdis(SO) Data output disable time Slave mode 9 - 16 ns
204/19 DS10198 Rev 9

Table 96. SPI characteristics(1) (continued)

Slave mode 2.7 < VDD < 3.6 V

- 12.5 19
Voltage Range 1
tv(SO) - 12.5 30
Voltage Range 1
Data output valid time ns
- 12.5 33
Voltage Range 2
- Slave mode 1.08 < VDDIO2 < 1.32 V(3) - 25 62.5

tv(MO) Master mode - 2.5 12.5
th(SO) Slave mode 9 - -
- Data output hold time Slave mode 1.08 < VDDIO2 < 1.32 V(3) 24 - - ns
th(MO) Master mode 0 - -
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50 %.
3. SPI mapped on Port G.
Figure 36. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
th(SI)
tsu(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41658V1
DS10198 Rev 9 205/19

233
Figure 37. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41659V1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
Figure 38. SPI timing diagram - master mode

High
NSS input
tc(SCK)
SCK Output
CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI)
tw(SCKL) tf(SCK)
MISO
INPUT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
MSB OUT BIT1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)
ai14136d
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
206/19 DS10198 Rev 9

Quad SPI characteristics

Unless otherwise specified, the parameters given in Table 97 and Table 98 for Quad SPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 23: General operating conditions, with the
following configuration:
• Capacitive load C = 15 or 20 pF
function characteristics.
Table 97. Quad SPI characteristics in SDR mode(1)

1.71 < VDD< 3.6 V, CLOAD = 20 pF

- - 40
Voltage Range 1
1.71 < VDD< 3.6 V, CLOAD = 15 pF
- - 48
FCK Voltage Range 1
Quad SPI clock frequency MHz
1/t(CK) 2.7 < VDD< 3.6 V, CLOAD = 15 pF
- - 60
Voltage Range 1
1.71 < VDD < 3.6 V CLOAD = 20 pF
- - 26
Voltage Range 2
tw(CKH) Quad SPI clock high and t(CK)/2-2 - t(CK)/2
fAHBCLK= 48 MHz, presc=0
tw(CKL) low time t(CK)/2 - t(CK)/2+2
Voltage Range 1 4 - -
ts(IN) Data input setup time
Voltage Range 2 3.5 - -
th(IN) Data input hold time ns
Voltage Range 1 - 2.5 5
tv(OUT) Data output valid time
Voltage Range 2 - 3 5
th(OUT) Data output hold time
Voltage Range 2 2 - -
DS10198 Rev 9 207/19

233
Table 98. QUADSPI characteristics in DDR mode(1)

1.71 < VDD < 3.6 V, CLOAD = 20 pF

- - 40
Voltage Range 1
2 < VDD < 3.6 V, CLOAD = 20 pF
- - 48
FCK Quad SPI clock Voltage Range 1
MHz
1/t(CK) frequency 1.71 < VDD < 3.6 V, CLOAD = 15 pF
- - 48
Voltage Range 1
1.71 < VDD < 3.6 V CLOAD = 20 pF
- - 26
Voltage Range 2
tw(CKH) Quad SPI clock high t(CK)/2-2 - t(CK)/2
fAHBCLK = 48 MHz, presc=0
tw(CKL) and low time t(CK)/2 - t(CK)/2+2
tsf(IN);tsr(IN) Data input setup time 3.5 - -
Voltage Range 1 and 2
thf(IN); thr(IN) Data input hold time 6.5 - -
ns
Voltage Range 1 11 12
tvf(OUT);tvr(OUT) Data output valid time -
Voltage Range 2 15 19
Voltage Range 1 6 -
thf(OUT); thr(OUT) Data output hold time -
Voltage Range 2 8 -
Figure 39. Quad SPI timing diagram - SDR mode

tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK)
Clock
tv(OUT) th(OUT)
Data output D0 D1 D2
ts(IN) th(IN)
Data input D0 D1 D2
MSv36878V1
Figure 40. Quad SPI timing diagram - DDR mode

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)
Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)
Data output IO0 IO1 IO2 IO3 IO4 IO5
tsf(IN) thf(IN) tsr(IN) thr(IN)
Data input IO0 IO1 IO2 IO3 IO4 IO5

MSv36879V3
208/19 DS10198 Rev 9

SAI characteristics
Unless otherwise specified, the parameters given in Table 99 for SAI are derived
from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized inTable 23: General operating conditions, with
the following configuration:
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output
alternate function characteristics (CK,SD,FS).
Table 99. SAI characteristics(1)

fMCLK SAI Main clock output - - 50 MHz

Master transmitter
2.7 ≤ VDD ≤ 3.6 - 18.5
Voltage Range 1
Master transmitter
1.71 ≤ VDD ≤ 3.6 - 12.5
Voltage Range 1
Master receiver
- 25
Voltage Range 1
fCK SAI clock frequency(2) Slave transmitter MHz
2.7 ≤ VDD ≤ 3.6 - 22.5
Voltage Range 1
Slave transmitter
1.71 ≤ VDD ≤ 3.6 - 14.5
Voltage Range 1
Slave receiver
- 25
Voltage Range 1
Voltage Range 2 - 12.5
Master mode
- 22
2.7 ≤ VDD ≤ 3.6
tv(FS) FS valid time ns
Master mode
- 40
1.71 ≤ VDD ≤ 3.6
th(FS) FS hold time Master mode 10 - ns
tsu(FS) FS setup time Slave mode 1 - ns
th(FS) FS hold time Slave mode 2 - ns
tsu(SD_A_MR) Master receiver 2.5 -
Data input setup time ns
tsu(SD_B_SR) Slave receiver 3 -
th(SD_A_MR) Master receiver 8 -
Data input hold time ns
th(SD_B_SR) Slave receiver 4 -
DS10198 Rev 9 209/19

233
Table 99. SAI characteristics(1) (continued)

Slave transmitter (after enable edge)

- 22
2.7 ≤ VDD ≤ 3.6
tv(SD_B_ST) Data output valid time ns
Slave transmitter (after enable edge)
- 34
1.71 ≤ VDD ≤ 3.6
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 10 - ns
Master transmitter (after enable edge)
- 27
2.7 ≤ VDD ≤ 3.6
tv(SD_A_MT) Data output valid time ns
Master transmitter (after enable edge)
- 40
1.71 ≤ VDD ≤ 3.6
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 10 - ns
2. APB clock frequency must be at least twice SAI clock frequency.
Figure 41. SAI master timing waveforms

1/fSCK
SAI_SCK_X
th(FS)
SAI_FS_X
(output) tv(FS) tv(SD_MT) th(SD_MT)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_MR) th(SD_MR)
SAI_SD_X Slot n
(receive)
MS32771V1
210/19 DS10198 Rev 9

Figure 42. SAI slave timing waveforms
1/fSCK
SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)
SAI_FS_X
(input) tsu(FS) tv(SD_ST) th(SD_ST)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_SR) th(SD_SR)
SAI_SD_X Slot n
(receive)
MS32772V1
SDMMC characteristics
Unless otherwise specified, the parameters given in Table 100 for SDIO are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 23: General operating conditions, with the following
configuration:
characteristics.
Table 100. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1)

fPP Clock frequency in data transfer mode - 0 - 50 MHz

- SDIO_CK/fPCLK2 frequency ratio - - - 4/3 -
tW(CKL) Clock low time fPP = 50 MHz 8 10 - ns
tW(CKH) Clock high time fPP = 50 MHz 8 10 - ns
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU Input setup time HS fPP = 50 MHz 2 - - ns
tIH Input hold time HS fPP = 50 MHz 4.5 - - ns
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV Output valid time HS fPP = 50 MHz - 12 14 ns
tOH Output hold time HS fPP = 50 MHz 9 - - ns
CMD, D inputs (referenced to CK) in SD default mode
tISUD Input setup time SD fPP = 50 MHz 2 - - ns
tIHD Input hold time SD fPP = 50 MHz 4.5 - - ns
DS10198 Rev 9 211/19

233
Table 100. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1) (continued)

CMD, D outputs (referenced to CK) in SD default mode

tOVD Output valid default time SD fPP = 50 MHz - 4.5 5 ns
tOHD Output hold default time SD fPP = 50 MHz 0 - - ns
Table 101. eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V(1)(2)

fPP Clock frequency in data transfer mode - 0 - 50 MHz

- SDIO_CK/fPCLK2 frequency ratio - - - 4/3 -
tW(CKL) Clock low time fPP = 50 MHz 8 10 - ns
tW(CKH) Clock high time fPP = 50 MHz 8 10 - ns
CMD, D inputs (referenced to CK) in eMMC mode
tISU Input setup time HS fPP = 50 MHz 0 - - ns
tIH Input hold time HS fPP = 50 MHz 5 - - ns
CMD, D outputs (referenced to CK) in eMMC mode
tOV Output valid time HS fPP = 50 MHz - 13.5 15.5 ns
tOH Output hold time HS fPP = 50 MHz 9 - - ns
2. CLOAD = 20pF.
Figure 43. SDIO high-speed mode
212/19 DS10198 Rev 9

Figure 44. SD default mode
CK
tOVD tOHD
D, CMD
(output)
ai14888
USB OTG full speed (FS) characteristics

The STM32L476xx USB interface is fully compliant with the USB specification version 2.0
and is USB-IF certified (for Full-speed device operation).
Table 102. USB OTG DC electrical characteristics

Symbol Parameter Conditions Min(1) Typ Max(1) Unit
USB OTG full speed transceiver

VDDUSB - 3.0(2) - 3.6 V
operating voltage
VDI(3) Differential input sensitivity Over VCM range 0.2 - -
Differential input common mode
VCM(3) Includes VDI range 0.8 - 2.5
range V
Single ended receiver input
VSE(3) - 0.8 - 2.0
threshold
VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) - - 0.3
V
VOH Static output level high RL of 15 kΩ to VSS(4) 2.8 - 3.6
Pull down resistor on PA11,
RPD(3) VIN = VDD 14.25 - 24.8 kΩ
PA12 (USB_FS_DP/DM)
Pull Up Resistor on PA12
VIN = VSS, during idle 0.9 1.25 1.575 kΩ
(USB_FS_DP)
Pull Up Resistor on PA12 VIN = VSS during
RPU(3) 1.425 2.25 3.09 kΩ
(USB_FS_DP) reception
Pull Up Resistor on PA10
- - - 14.5 kΩ
(OTG_FS_ID)
1. All the voltages are measured from the local ground potential.
2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed
electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
4. RL is the load connected on the USB OTG full speed drivers.
Note: When VBUS sensing feature is enabled, PA9 should be left at its default state (floating
input), not as alternate function. A typical 200 µA current consumption of the sensing block
(current to voltage conversion to determine the different sessions) can be observed on PA9
when the feature is enabled.
DS10198 Rev 9 213/19

233
Figure 45. USB OTG timings – definition of data signal rise and fall time
Cross over
points
Differential
data lines
VCRS
VSS
tf tr
ai14137b
Table 103. USB OTG electrical characteristics(1)

Driver characteristics
trLS Rise time in LS(2) CL = 200 to 600 pF 75 300 ns

tfLS Fall time in LS(2) CL = 200 to 600 pF 75 300 ns
trfmLS Rise/ fall time matching in LS tr/tf 80 125 %
trFS Rise time in FS(2) CL = 50 pF 4 20 ns
tfFS Fall time in FS(2) CL = 50 pF 4 20 ns
trfmFS Rise/ fall time matching in FS tr/tf 90 111 %
VCRS Output signal crossover voltage (LS/FS) - 1.3 2.0 V
ZDRV Output driver impedance(3) Driving high or low 28 44 Ω
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.
Table 104. USB BCD DC electrical characteristics(1)

Symbol Parameter Conditions Min. Typ. Max. Unit
Primary detection mode

- - - 300 μA
consumption
IDD(USBBCD)
Secondary detection mode
- - - 300 μA
consumption
Data line leakage
RDAT_LKG - 300 - - kΩ
resistance
VDAT_LKG Data line leakage voltage - 0.0 - 3.6 V
Dedicated charging port
RDCP_DAT - - - 200 Ω
resistance across D+/D-
VLGC_HI Logic high - 2.0 - 3.6 V
VLGC_LOW Logic low - - - 0.8 V
VLGC Logic threshold - 0.8 - 2.0 V
214/19 DS10198 Rev 9

Table 104. USB BCD DC electrical characteristics(1) (continued)

Symbol Parameter Conditions Min. Typ. Max. Unit
VDAT_REF Data detect voltage - 0.25 - 0.4 V

VDP_SRC D+ source voltage - 0.5 - 0.7 V
VDM_SRC D- source voltage - 0.5 - 0.7 V
IDP_SINK D+ sink current - 25 - 175 μA
IDM_SINK D- sink current - 25 - 175 μA
CAN (controller area network) interface

function characteristics (CAN_TX and CAN_RX).
DS10198 Rev 9 215/19

233
6.3.29 FSMC characteristics

Unless otherwise specified, the parameters given in Table 105 to Table 118 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 23, with the following configuration:
• Measurement points are done at CMOS levels: 0.5VDD
characteristics.
Asynchronous waveforms and timings

Figure 46 through Figure 49 represent asynchronous waveforms and Table 105 through
Table 112 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
In all timing tables, the THCLK is the HCLK clock period.
216/19 DS10198 Rev 9

Figure 46. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
tw(NE)
FMC_NE
tv(NOE_NE) t w(NOE) t h(NE_NOE)
FMC_NOE
FMC_NWE
tv(A_NE) t h(A_NOE)
FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)
FMC_NBL[1:0]
t h(Data_NE)
t su(Data_NOE) th(Data_NOE)
t su(Data_NE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
DS10198 Rev 9 217/19

233
Table 105. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2)

tw(NE) FMC_NE low time 2THCLK-0.5 2THCLK+0.5

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 1
tw(NOE) FMC_NOE low time 2THCLK-0.5 2THCLK+1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 3.5
th(A_NOE) Address hold time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 2
ns
th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 -
tsu(Data_NE) Data to FMC_NEx high setup time THCLK-1 -
tsu(Data_NOE) Data to FMC_NOEx high setup time THCLK-0.5 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 1
tw(NADV) FMC_NADV low time - THCLK+0.5
1. CL = 30 pF.
Table 106. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT

timings(1)(2)
tw(NE) FMC_NE low time 7THCLK-0.5 7THCLK+0.5
tw(NOE) FMC_NWE low time 5THCLK-0.5 5THCLK+0.5

tw(NWAIT) FMC_NWAIT low time THCLK-0.5 - ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK+2 -

th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK -
1. CL = 30 pF.
218/19 DS10198 Rev 9

Figure 47. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)
FMC_NEx
FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)
FMC_NWE
tv(A_NE) th(A_NWE)
FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)
FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
Table 107. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)

tw(NE) FMC_NE low time 3THCLK-1 3THCLK+2

tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK-0.5 THCLK+1.5
tw(NWE) FMC_NWE low time THCLK-1 THCLK+1
th(NE_NWE) FMC_NWE high to FMC_NE high hold time THCLK-0.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
th(A_NWE) Address hold time after FMC_NWE high THCLK-1 -
ns
tv(BL_NE) FMC_NEx low to FMC_BL valid - 1.5
th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK-0.5 -
tv(Data_NE) Data to FMC_NEx low to Data valid - THCLK+4
th(Data_NWE) Data hold time after FMC_NWE high THCLK+1 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 1
tw(NADV) FMC_NADV low time - THCLK+0.5
1. CL = 30 pF.
DS10198 Rev 9 219/19

233
Table 108. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT

timings(1)(2)
tw(NE) FMC_NE low time 8THCLK+0.5 8THCLK+0.5

tw(NWE) FMC_NWE low time 6THCLK-0.5 6THCLK+0.5
ns
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+2 -
1. CL = 30 pF.
Figure 48. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)
FMC_ NE
tv(NOE_NE) t h(NE_NOE)
FMC_NOE
t w(NOE)
FMC_NWE
tv(A_NE) th(A_NOE)
FMC_ A[25:16] Address

tv(BL_NE) th(BL_NOE)
FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)
FMC_ AD[15:0] Address Data
t v(NADV_NE) th(AD_NADV)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
220/19 DS10198 Rev 9

Table 109. Asynchronous multiplexed PSRAM/NOR read timings(1)(2)

tw(NE) FMC_NE low time 3THCLK-0.5 3THCLK+2

tv(NOE_NE) FMC_NEx low to FMC_NOE low 2THCLK-0.5 2THCLK+0.5
tw(NOE) FMC_NOE low time THCLK+0.5 THCLK+1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1
tw(NADV) FMC_NADV low time THCLK-0.5 THCLK+1
FMC_AD(address) valid hold time after
th(AD_NADV) 0 - ns
FMC_NADV high
th(A_NOE) Address hold time after FMC_NOE high THCLK-0.5 -
th(BL_NOE) FMC_BL time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 2
tsu(Data_NE) Data to FMC_NEx high setup time THCLK-2 -
tsu(Data_NOE) Data to FMC_NOE high setup time THCLK-1 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
1. CL = 30 pF.
Table 110. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)(2)

tw(NE) FMC_NE low time 8THCLK+2 8THCLK+4
tw(NOE) FMC_NWE low time 5THCLK-1 5THCLK+1.5

ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK+1.5 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+1 -
1. CL = 30 pF.
DS10198 Rev 9 221/19

233
Figure 49. Asynchronous multiplexed PSRAM/NOR write waveforms
tw(NE)
FMC_ NEx
FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)
FMC_NWE
tv(A_NE) th(A_NWE)
FMC_ A[25:16] Address

tv(BL_NE) th(BL_NWE)
FMC_ NBL[1:0] NBL

t v(A_NE) t v(Data_NADV) th(Data_NWE)
FMC_ AD[15:0] Address Data
t v(NADV_NE) th(AD_NADV)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32756V1
222/19 DS10198 Rev 9

Table 111. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)


tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK-0.5 THCLK+1
2xTHCLK+1.
tw(NWE) FMC_NWE low time 2xTHCLK-1.5
5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time THCLK-0.5 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1
tw(NADV) FMC_NADV low time THCLK-0.5 THCLK+1 ns
FMC_AD(adress) valid hold time after
th(AD_NADV) THCLK-2 -
FMC_NADV high
th(A_NWE) Address hold time after FMC_NWE high THCLK-1 -
th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK+0.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 1.5
tv(Data_NADV) FMC_NADV high to Data valid - THCLK +4
th(Data_NWE) Data hold time after FMC_NWE high THCLK +0.5 -
1. CL = 30 pF.
Table 112. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)

tw(NWE) FMC_NWE low time 7THCLK-1.5 7THCLK+1.5

ns
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK-3 -
1. CL = 30 pF.
Synchronous waveforms and timings
Figure 50 through Figure 53 represent synchronous waveforms and Table 113

through Table 116 provide the corresponding timings. The results shown in these
tables are obtained with the following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR flash; DataLatency = 0 for PSRAM
DS10198 Rev 9 223/19

233
Figure 50. Synchronous multiplexed NOR/PSRAM read timings
tw(CLK) tw(CLK) BUSTURN = 0
FMC_CLK
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:16]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
t d(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)
FMC_AD[15:0] AD[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32757V1
224/19 DS10198 Rev 9

Table 113. Synchronous multiplexed NOR/PSRAM read timings(1)(2)

tw(CLK) FMC_CLK period 2THCLK-1 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK+0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3.5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5 ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK+1 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 4
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 0 -
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 2.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 0 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 -
1. CL = 30 pF.
DS10198 Rev 9 225/19

233
Figure 51. Synchronous multiplexed PSRAM write timings
tw(CLK) tw(CLK) BUSTURN = 0
FMC_CLK
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
FMC_A[25:16]
td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE
td(CLKL-ADIV) td(CLKL-Data)
td(CLKL-ADV) td(CLKL-Data)
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)
td(CLKH-NBLH)
FMC_NBL
MSv38001V1
226/19 DS10198 Rev 9

Table 114. Synchronous multiplexed PSRAM write timings(1)(2)

tw(CLK) FMC_CLK period 2THCLK-1 -

td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK+0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 -
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2
ns
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK+1 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 4
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 5.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2.5
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK+1 -
1. CL = 30 pF.
DS10198 Rev 9 227/19

233
Figure 52. Synchronous non-multiplexed NOR/PSRAM read timings
tw(CLK) tw(CLK)
FMC_CLK
Data latency = 0
FMC_NEx
FMC_NADV
FMC_A[25:0]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
MS32759V1
Table 115. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2)

tw(CLK) FMC_CLK period 2THCLK -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2.5
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK-0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 -
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK - ns
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 2
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK-0.5 -
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 0 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 5 -
228/19 DS10198 Rev 9

1. CL = 30 pF.
Figure 53. Synchronous non-multiplexed PSRAM write timings

tw(CLK) tw(CLK)
FMC_CLK
Data latency = 0
FMC_NEx
FMC_NADV
FMC_A[25:0]
td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE
td(CLKL-Data) td(CLKL-Data)
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL
MSv38002V1
DS10198 Rev 9 229/19

233
Table 116. Synchronous non-multiplexed PSRAM write timings(1)(2)

tw(CLK) FMC_CLK period 2THCLK-0.5 -

td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK+0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2.5 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK-1 -
ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK-1 -
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 4.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 1.5 -
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK+1 -
1. CL = 30 pF.
NAND controller waveforms and timings
Figure 54 through Figure 57 represent synchronous waveforms, and Table 117 and
Table 118 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
• COM.FMC_SetupTime = 0x02
• COM.FMC_WaitSetupTime = 0x03
• COM.FMC_HoldSetupTime = 0x02
• COM.FMC_HiZSetupTime = 0x03
• ATT.FMC_SetupTime = 0x01
• ATT.FMC_WaitSetupTime = 0x03
• ATT.FMC_HoldSetupTime = 0x02
• ATT.FMC_HiZSetupTime = 0x03
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth_16b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize_512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
230/19 DS10198 Rev 9

Figure 54. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
td(NCE-NOE) th(NOE-ALE)
FMC_NOE (NRE)
tsu(D-NOE) th(NOE-D)
FMC_D[15:0]
MSv38003V1
Figure 55. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NWE) th(NWE-ALE)
FMC_NWE
FMC_NOE (NRE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MSv38004V1
Figure 56. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NOE) th(NOE-ALE)
FMC_NWE
tw(NOE)
FMC_NOE
tsu(D-NOE) th(NOE-D)
FMC_D[15:0]
MSv38005V1
DS10198 Rev 9 231/19

233
Figure 57. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NWE) tw(NWE) th(NOE-ALE)
FMC_NWE
FMC_NOE
td(D-NWE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MSv38006V1
Table 117. Switching characteristics for NAND flash read cycles(1)(2)

Tw(N0E) FMC_NOE low width 4THCLK-1 4THCLK+1

Tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 16 -
Th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 6 - ns
Td(NCE-NOE) FMC_NCE valid before FMC_NOE low - 3THCLK+1
Th(NOE-ALE) FMC_NOE high to FMC_ALE invalid 2THCLK-2 -
1. CL = 30 pF.
Table 118. Switching characteristics for NAND flash write cycles(1)(2)

Tw(NWE) FMC_NWE low width 4THCLK-1 4THCLK+1

Tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid - 2.5
Th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 3THCLK-4 -
ns
Td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5THCLK-3 -
Td(NCE_NWE) FMC_NCE valid before FMC_NWE low - 3THCLK+1
Th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2THCLK-2 -
1. CL = 30 pF.
232/19 DS10198 Rev 9

6.3.30 SWPMI characteristics

The Single Wire Protocol Master Interface (SWPMI) and the associated SWPMI_IO
transceiver are compliant with the ETSI TS 102 613 technical specification.
Table 119. SWPMI electrical characteristics(1)

SWP Class B
tSWPSTART SWPMI regulator startup time - - 300 μs
2.7 V ≤ VDD ≤ 3,3V
VCORE voltage range 1 500 - -
tSWPBIT SWP bit duration ns
VCORE voltage range 2 620 - -
DS10198 Rev 9 233/19

233
Package information STM32L476xx
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
7.1 Device marking

Refer to technical note “Reference device marking schematics for STM32 microcontrollers
and microprocessors” (TN1433) available on www.st.com, for the location of pin 1 / ball A1
as well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example (if any) is provided in the corresponding package
information subsection.
234/271 DS10198 Rev 9

STM32L476xx Package information
7.2 LQFP144 package information

This LQFP is a 144-pin, 20 x 20 mm low-profile quad flat package.
Note: See list of notes in the notes section.
Figure 58. LQFP144 - Outline(15)
BOTTOM VIEW
2 1
(2)
R1
H
R2
B
B-
N
O
TI
C
SE
(6) B GAUGE PLANE
0.25
D 1/4
S
B
L
3
E 1/4 (L1)
(1) (11)
4x N/4 TIPS
aaa C A-B D SECTION A-A
bbb H A-B D 4x
(N-4)x e
C
A
0.05 (12) ddd C A-B D
A2 A1 b ccc C
D (4)
D1 (2) (5)
(10) (3) D (9) (11)
N (4)
b WITH PLATING
1
2
3 E 1/4
(11) (11)
c c1
(6)
D 1/4 (2)
(3) A B (3) (5)
E1 E b1 BASE METAL
(11)
SECTION B-B
A A
(Section A-A)
TOP VIEW
1A_LQFP144_ME_V2
DS10198 Rev 9 235/271

261
Table 120. LQFP144 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max
A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 22.00 BSC 0.8661 BSC
(2)(5)
D1 20.00 BSC 0.7874 BSC
E(4) 22.00 BSC 0.8661 BSC
E1(2)(5) 20.00 BSC 0.7874 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 144
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa 0.20 0.0079
bbb 0.20 0.0079
ccc 0.08 0.0031
ddd 0.08 0.0031
236/271 DS10198 Rev 9

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.
DS10198 Rev 9 237/271

261
Figure 59. LQFP144 - Recommended footprint
108 73
1.35
109 0.35 72
0.50
19.90 17.85
22.60
144 37
1 36
19.90
22.60
1A_LQFP144_FP
1. Dimensions are expressed in millimeters.
238/271 DS10198 Rev 9

7.3 UFBGA144 package information

This UFBGA is a 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array
package.
Figure 60. UFBGA144 - Outline
C Seating plane
ddd Z
A4 A3 A2 A1 A
E1 A1 ball A1 ball A
identifier index area E
e F
A
F
D1 D
e
B
M
12 1
BOTTOM VIEW Øb (144 balls) TOP VIEW
Ø eee M C A B
Ø fff M C A02Y_ME_V2
Table 121. UFBGA144 - Mechanical data

Symbol
Min. Typ. Max. Min. Typ. Max.
A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
b 0.360 0.400 0.440 0.0091 0.0110 0.0130
D 9.950 10.000 10.050 0.2736 0.2756 0.2776
D1 8.750 8.800 8.850 0.2343 0.2362 0.2382
E 9.950 10.000 10.050 0.2736 0.2756 0.2776
E1 8.750 8.800 8.850 0.2343 0.2362 0.2382
e 0.750 0.800 0.850 - 0.0197 -
DS10198 Rev 9 239/271

261
Table 121. UFBGA144 - Mechanical data (continued)

Symbol
Min. Typ. Max. Min. Typ. Max.
F 0.550 0.600 0.650 0.0177 0.0197 0.0217

ddd - - 0.080 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.080 - - 0.0020
Figure 61. UFBGA144 - Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 122. UFBGA144 - Recommended PCB design rules (0.80 mm pitch BGA)
Dimension Recommended values
Pitch 0.80 mm
Dpad 0.400 mm
0.550 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.400 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm
240/271 DS10198 Rev 9

7.4 UFBGA132 package information

This UFBGA is a 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package
Figure 62. UFBGA132 - Outline

A1 ball identifier
E1 B A
e E
Z
D1 D
12 1
BOTTOM VIEW Øb (132 balls) TOP VIEW
Øeee M C A B
Ø fff M C
A4
ddd C
A2 A3
b A1 A
SEATING
PLANE
UFBGA132_A0G8_ME_V2
Table 123. UFBGA132 - Mechanical data

Symbol
A - - 0.600 - - 0.0236
A1 - - 0.110 - - 0.0043
A2 - 0.450 - - 0.0177 -
A3 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 6.850 7.000 7.150 0.2697 0.2756 0.2815
D1 - 5.500 - - 0.2165 -
E 6.850 7.000 7.150 0.2697 0.2756 0.2815
E1 - 5.500 - - 0.2165 -
DS10198 Rev 9 241/271

261
Table 123. UFBGA132 - Mechanical data (continued)

Symbol
e - 0.500 - - 0.0197 -
Z - 0.750 - - 0.0295 -
ddd - 0.080 - - 0.0031 -
eee - 0.150 - - 0.0059 -
fff - 0.050 - - 0.0020 -
Figure 63. UFBGA132 - Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 124. UFBGA132 - Recommended PCB design rules (0.5 mm pitch BGA)
Pitch 0.5 mm
Dpad 0.280 mm
Dsm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
Ball diameter 0.280 mm
242/271 DS10198 Rev 9


This LQFP is 100 lead, 14 x 14 mm low-profile quad flat package.
ș2 ș
(2)
R1
H
R2
B
B-
N
O
(6)
TI
C
SE
D1/4 B GAUGE PLANE
S
E1/4
B ș
4x N/4 TIPS
ș L
4x (L1)
aaa C A-B D
bbb H A-B D (1) (11)
BOTTOM VIEW SECTION A-A
(N-4) x e (13)
C
A (9) (11)
0.05
ccc C b WITH PLATING
A2 A1 b aaa C A-BD
(12)
SIDE VIEW
D (4)
(11) c
(2) (5) D1 c1 (11)
D (3)
(10) (4)
N
b1 BASE METAL
1 (11)
2
3 E1/4 SECTION B-B
D1/4 (6) (2)

A B
(5)
E1 E
SECTION A-A
A A
TOP VIEW 1L_LQFP100_ME_V3
DS10198 Rev 9 243/271

261

Symbol
A - 1.50 1.60 - 0.0590 0.0630

(12)
A1 0.05 - 0.15 0.0019 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 16.00 0.6299
(2)(5)
D1 14.00 0.5512
E(4) 16.00 0.6299
E1(2)(5) 14.00 0.5512
e - 0.50 - - 0.0197 -
L 0.45 0.60 0.75 0.177 0.0236 0.0295
(1)(11)
L1 1.00 - 0.0394 -
N 100
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa 0.20 0.0079
bbb 0.20 0.0079
ccc 0.08 0.0031
ddd 0.08 0.0031
244/271 DS10198 Rev 9

Notes:
as 0.15 mm.
from the lead tip.
body.

75 51
76 50
0.5
0.3
16.7 14.3
100 26
1.2
1 25
12.3
16.7
1L_LQFP100_FP_V1
DS10198 Rev 9 245/271

261
7.6 WLCSP99 package information

This WLCSP is a 99-ball, 4.42 x 3.77 mm, 0.35 mm pitch, wafer level chip scale package
Figure 66. WLCSP99 – Outline
bbb Z
A1 BALL LOCATION A1
F
11 10 9 8 7 6 5 4 3 2 1
G
A
B DETAIL A
C
E e2
F
H
e J
e
A
e1
BOTTOM VIEW SIDE VIEW
A3 A2
FRONT VIEW
BUMP
X
eee Z
E Z
b (33x)
A1 ORIENTATION ccc Z XY
REFERENCE ddd Z
SEATING PLANE
DETAIL A
ROTATED 90
(4x)
aaa
Y
D
TOP VIEW
B0JR_WLCSP99_ME_V1

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.
246/271 DS10198 Rev 9

Table 126. WLCSP99 - Mechanical data

Symbol
A(2) - - 0.580 - - 0.0228

A1 - 0.170 - - 0.0067 -
A2 - 0.380 - - 0.0150 -
(3)
A3 - 0.025 - - 0.0010 -
(4)
Øb 0.200 0.230 0.250 0.0079 0.0091 0.0098
D 4.40 4.42 4.44 0.1732 0.1740 0.1748
E 3.75 3.77 3.79 0.1476 0.1484 0.1492
e - 0.350 - - 0.0138 -
e1 - 3.500 - - 0.1378 -
e2 - 2.800 - - 0.1102 -
F(5) - 0.460 - - 0.0181 -
G(5) - 0.485 - - 0.0191 -
aaa - - 0.100 - - 0.0039
bbb - - 0.100 - - 0.0039
ccc(6) - - 0.100 - - 0.0039
ddd(7) - - 0.050 - - 0.0020
eee - - 0.050 - - 0.0020
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
5. Calculated dimensions are rounded to the 3rd decimal place
6. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.
7. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone ddd perpendicular to datum Z and located on true
position as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.
Each tolerance zone ddd in the array is contained entirely in the respective zone ccc above. The axis of
each ball must lie simultaneously in both tolerance zones
DS10198 Rev 9 247/271

261
Figure 67. WLCSP99 – Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 127. WLCSP99 - Recommended PCB design rules

Pitch 0.35 mm
Dpad 0.200 mm
Dsm 0.275 mm
Stencil thickness 0.08 mm
Device marking
The following figures give examples of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
248/271 DS10198 Rev 9

Figure 68. WLCSP99 (external SMPS device) marking (package top view)
TBD
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS10198 Rev 9 249/271

261

This WLCSP is a 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale
package.
Figure 69. WLCSP81 - Outline
e1 A1 ball bbb Z A1 ball

location location D
e
e
Detail A
e2 E
J
G
9 1 aaa
A3
F
Bottom view A2 Top view
Bump side A Wafer back side
Side view
Detail A
rotated by 90°
eee Z A1
b Seating plane Z
Ø ccc M ZXY
Øddd M Z
A05Z_ME_V1

3. Primary datum Z and seating plane are defined by the spherical crowns of the bump
4. Bump position designation per JESD 95-1, SPP-010.

Symbol
A 0.525 0.555 0.585 0.0207 0.0219 0.0230
A1 - 0.175 - - 0.0069 -
A2 - 0.380 - - 0.0150 -
(2)
A3 - 0.025 - - 0.0010 -
(3)
b 0.220 0.250 0.280 0.0087 0.0098 0.0110
D 4.3734 4.4084 4.4434 0.1722 0.1736 0.1749
E 3.7244 3.7594 3.7944 0.1466 0.1480 0.1494
250/271 DS10198 Rev 9

Table 128. WLCSP81 - Mechanical data (continued)

Symbol
e - 0.400 - - 0.0157 -
e1 - 3.200 - - 0.1260 -
e2 - 3.200 - - 0.1260 -
F - 0.6042 - - 0.0238 -
G - 0.2797 - - 0.0110 -
aaa - - 0.100 - - 0.0039
bbb - - 0.100 - - 0.0039
ccc - - 0.100 - - 0.0039
ddd - - 0.050 - - 0.0020
eee - - 0.050 - - 0.0020
2. Back side coating
Figure 70. WLCSP81- Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 129. WLCSP81 - Recommended PCB design rules (0.4 mm pitch)

Pitch 0.4 mm
Dpad 0.225 mm
Dsm
DS10198 Rev 9 251/271

261
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 71. WLCSP81 marking (package top view)
Ball A1 identifier
L476MEY6
(1)
Product identification
Revision code
Y WW 3
Date code
MSv40100V1
252/271 DS10198 Rev 9


This WLCSP is a 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale
package.
Figure 72. WLCSP72 - Outline
bbb Z
e1
D X
e Y
e Detail A
E
e2
G
aaa
A3 A1 ball location
F A2
Bottom view A Top view
Bump side Side view Wafer back side
Bump
eee Z
A1
b (72X) Z
Ø ccc M Z XY Seating plane
Øddd M Z Detail A
rotated by 90° A02R_ME_V1

Symbol
A 0.525 0.555 0.585 0.0207 0.0219 0.0230
A1 - 0.175 - - 0.0069 -
A2 - 0.380 - - 0.0150 -
(2)
A3 - 0.025 - - 0.0010 -
(3)
b 0.220 0.250 0.280 0.0087 0.0098 0.0110
D 4.3734 4.4084 4.4434 0.1722 0.1736 0.1749
E 3.7244 3.7594 3.7944 0.1466 0.1480 0.1494
e - 0.400 - - 0.0157 -
e1 - 3.200 - - 0.1260 -
e2 - 3.200 - - 0.1260 -
F - 0.6042 - - 0.0238 -
DS10198 Rev 9 253/271

261
Table 130. WLCSP72 - Mechanical data (continued)

Symbol
G - 0.2797 - - 0.0110 -
aaa - 0.100 - - 0.0039 -
bbb - 0.100 - - 0.0039 -
ccc - 0.100 - - 0.0039 -
ddd - 0.050 - - 0.0020 -
eee - 0.050 - - 0.0020 -
2. Back side coating
Figure 73. WLCSP72 - Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 131. WLCSP72 - Recommended PCB design rules (0.4 mm pitch BGA)
Pitch 0.4 mm
Dpad 0.225 mm
0.290 mm typ. (depends on the solder mask
Dsm
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
254/271 DS10198 Rev 9

Figure 74. WLCSP72 marking (package top view)
Ball A1 identifier
L476JGY6
(1)
Product identification
Revision code
Date code
Y WW 3
MSv36870V3
DS10198 Rev 9 255/271

261

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.

BOTTOM VIEW
2 1
(2)
R1
H
R2
B
B-
N
O
TI
C
SE
B GAUGE PLANE
D 1/4
0.25
(6)
S
B
L
4x N/4 TIPS
E 1/4 3
(L1)
aaa C A-B D (1) (11)
bbb H A-B D 4x
SECTION A-A
(13) (N – 4)x e
C
A
0.05
A2 A1 (12)
b
ddd C A-B D ccc C
D (4)
(5) (2) D1 (9) (11)
(10)
D (3) b WITH PLATING
N (4)
1 E 1/4 (11) (11)

2
3 c c1
(3) A (6) B (3) (5)
D 1/4 (2)
E1 E b1 BASE METAL
(11)
A A SECTION B-B
(Section A-A)
TOP VIEW 5W_LQFP64_ME_V1
256/271 DS10198 Rev 9


Symbol
A - - 1.60 - - 0.0630
A1(12) 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
c(11) 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 12.00 BSC 0.4724 BSC
(2)(5)
D1 10.00 BSC 0.3937 BSC
E(4) 12.00 BSC 0.4724 BSC
(2)(5)
E1 10.00 BSC 0.3937 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 64
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
(1)
aaa 0.20 0.0079
(1)
bbb 0.20 0.0079
(1)
ccc 0.08 0.0031
ddd(1) 0.08 0.0031
DS10198 Rev 9 257/271

261
Notes:
as 0.15 mm.
from the lead tip.
body.
48 33
0.30
49 0.5 32
12.70
10.30
10.30
64 17
1.20
1 16
7.80
12.70
5W_LQFP64_FP_V2
1. Dimensions are expressed in millimeters.
258/271 DS10198 Rev 9

7.10 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 22: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of all IDDXXX and VDDXXX, expressed in Watts. This is the
maximum chip internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ ((VDDIOx – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 133. Package thermal characteristics

Symbol Parameter Value Unit
Thermal resistance junction-ambient

45
LQFP64 - 10 × 10 mm / 0.5 mm pitch
42
LQFP100 - 14 × 14mm
32
LQFP144 - 20 × 20 mm
53
UFBGA144 - 10 × 10 mm
ΘJA °C/W
55
UFBGA132 - 7 × 7 mm
46
WLCSP72
41
WLCSP81
42
WLCSP99
7.10.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
DS10198 Rev 9 259/271

261
7.10.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32L476xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range is best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application

Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL = 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V = 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in Table 133 TJmax is calculated as follows:
– For LQFP64, 45 °C/W
TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Section 8:
Ordering information.
In this case, parts must be ordered at least with the temperature range suffix 6 (see Part
numbering).
Note: With this given PDmax user can find the TAmax allowed for a given device temperature range
(order code suffix 6 or 7).
Suffix 6: TAmax = TJmax - (45°C/W × 447 mW) = 105-20.115 = 84.885 °C
Suffix 7: TAmax = TJmax - (45°C/W × 447 mW) = 125-20.115 = 104.885 °C
Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
260/271 DS10198 Rev 9

Assuming the following application conditions:

Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL = 0.4 V
PINTmax = 20 mA × 3.5 V = 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
Using the values obtained in Table 133 TJmax is calculated as follows:
– For LQFP64, 45 °C/W
TJmax = 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C
This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Ordering information) unless we reduce the power dissipation in order to be able
to use suffix 6 parts.
Refer to Figure 77 to select the required temperature range (suffix 6 or 7) according to your
ambient temperature or power requirements.
Figure 77. LQFP64 PD max vs. TA

700
600
500
PD (mW)
400 Suffix 6
300
Suffix 7
200
100
0
65 75 85 95 105 115 125 135
TA (°C) MSv32143V1
DS10198 Rev 9 261/271

261
Ordering information STM32L476xx
8 Ordering information
Table 134. STM32L476xx ordering information scheme

Example: STM32 L 476 R G T 6 P M TR
Device family
STM32 = Arm® based 32-bit microcontroller
Product type
L = ultra-low-power
Device subfamily
476: STM32L476xx
Pin count
R = 64 pins
J = 72 pins
M = 81 pins
V = 100/99 pins
Q = 132 pins
Z = 144 pins
Flash memory size
C = 256 KB of flash memory
E = 512 KB of flash memory
G = 1 MB of flash memory
Package
T = LQFP ECOPACK®2
I = UFBGA (7 × 7 mm) ECOPACK®2
J = UFBGA (10 × 10 mm) ECOPACK®2
Y = CSP ECOPACK®2
Temperature range
6 = Industrial temperature range, -40 to 85 °C (105 °C junction)
Option
Blank = Standard production with integrated LDO
P = Dedicated pinout supporting external SMPS
Option specific package
M = Specific supply chain(1)
Blank = Standard
Packing
TR = tape and reel
xxx = programmed parts
1. This option is available only on STM32L476MGY6MTR part number under specific ordering conditions.
Contact your nearest ST sales office for availability.
For a list of available options (such as speed, package) or for further information on any
aspect of this device contact the nearest ST sales office.
262/271 DS10198 Rev 9

STM32L476xx Important security notice
9 Important security notice
The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.
DS10198 Rev 9 263/271

263
Revision history STM32L476xx
10 Revision history
Table 135. Document revision history

Date Revision Changes
29-May-2015 1 Initial release.

Updated Table 1: Device summary and Table 85: COMP
15-Jun-2015 2
characteristics.
Changed alternate function pin name “SWDAT” into
“SWDIO” in all the document.
Updated Section 3.9.1: Power supply schemes.
Updated Section 3.15.1: Temperature sensor.
In all Section 6: Electrical characteristics, renamed table
footnotes related to test and characterization.
Added Note 2.
Updated Table 51: Low-power mode wakeup timings.
Updated Table 52: Regulator modes transition times.
Updated Table 58: HSI16 oscillator characteristics.
Added Table 30: HSI16 frequency versus temperature.
Updated Table 59: MSI oscillator characteristics.
Updated Table 61: LSI oscillator characteristics.
Updated Table 69: I/O current injection susceptibility.
Removed first Note in Table 70: I/O static
characteristics.
Removed second Note in Table 71: Output voltage
characteristics.
Updated Table 76: ADC characteristics.
18-Sep-2015 3 Updated Table 78: ADC accuracy - limited test
conditions 1.
Added Table 79: ADC accuracy - limited test conditions
2.
3.
4.
Updated Table 83: DAC accuracy.
Updated Table 84: VREFBUF characteristics.
Added Section 6.3.26: DFSDM characteristics.
Updated Section : Quad SPI characteristics.
Updated Table 97: Quad SPI characteristics in SDR
mode.
Updated Table 98: QUADSPI characteristics in DDR
mode.
Updated Table 103: USB OTG electrical characteristics.
Updated Section 7.4: UFBGA132 package information.
Updated Section 7.8: WLCSP72 package information.
Updated Table 66: LQFP64 marking (package top view).
264/271 DS10198 Rev 9

STM32L476xx Revision history
Table 135. Document revision history (continued)

In all the document:

– Stop 1 with main regulator becomes Stop 0
– Stop 1 with low-power regulator remains as Stop 1.
In Section 4: Pinouts and pin description:
– PC14/OSC32_IN becomes PC14-OSC32_IN (PC14)
– PC15/OSC32_OUT becomes PC15-OSC32_OUT
(PC15)
– PH0/OSC_IN becomes PH0-OSC_IN (PH0)
– PH1/OSC_OUT becomes PH1-OSC_OUT (PH1)
– PA13 becomes PA13 (JTMS-SWDIO)
– PA14 becomes PA14 (JTCK-SWCLK)
– PA15 becomes PA15 (JTDI)
– PB3 becomes PB3 (JTDO-TRACESWO)
– PB4 becomes PB4 (NJTRST).
Added Table 13: STM32L476xx USART/UART/LPUART
features.
03-Dec-2015 4 Added Note 5.
Updated Table 25: Embedded internal voltage
reference.
Updated Table 45: Current consumption in Stop 2 mode.
Updated Table 48: Current consumption in Standby
mode.
Updated Table 49: Current consumption in Shutdown
mode.
Updated Table 51: Low-power mode wakeup timings.
Added Figure 25: VREFINT versus temperature.
Updated Figure 30: HSI16 frequency versus
temperature.
Updated Table 70: I/O static characteristics.
Updated Table 82: DAC characteristics.
Updated Figure 62: UFBGA132 - Outline.
Updated Table 123: UFBGA132 - Mechanical data.
In whole document:
– DFSDM peripheral name updated to DFSDM1
– Introduced SMPS product variant
Added:
06-Jul-2017 5
– Section 3.24.5: Infrared interface (IRTIM)
– Section 6.3.16: Extended interrupt and event
controller input (EXTI) characteristics
– Section 6.3.30: SWPMI characteristics
DS10198 Rev 9 265/271

270

– Figure 7: STM32L476Zx, external SMPS device,

LQFP144 pinout(1)(2)
– Figure 13: STM32L476Mx WLCSP81 ballout(1)(2)
– Section 6.3.16: Extended interrupt and event
controller input (EXTI) characteristics
– Section 6.3.30: SWPMI characteristics
– Table 28: Current consumption in Run modes, code
with data processing running from flash, ART enable
(Cache ON Prefetch OFF) and power supplied by
external SMPS (VDD12 = 1.10 V)
– Table 30: Current consumption in Run modes, code
with data processing running from flash, ART disable
and power supplied by external SMPS (VDD12 =
1.10 V)
– Table 32: Current consumption in Run, code with data
processing running from SRAM1 and power supplied
by external SMPS (VDD12 = 1.10 V)
– Table 34: Typical current consumption in Run, with
different codes running from flash, ART enable
external SMPS (VDD12 = 1.10 V)
– Table 35: Typical current consumption in Run, with
different codes running from flash, ART enable
5 external SMPS (VDD12 = 1.05 V)
06-Jul-2017
(continued) – Table 37: Typical current consumption in Run modes,
with different codes running from flash, ART disable
1.10 V)
– Table 38: Typical current consumption in Run modes,
with different codes running from flash, ART disable
1.05 V)
– Table 40: Typical current consumption in Run mode,
with different codes running from SRAM1 and power
supplied by external SMPS (VDD12 = 1.10 V)
– Table 41: Typical current consumption in Run mode,
with different codes running from SRAM1 and power
supplied by external SMPS (VDD12 = 1.05 V)
– Table 43: Current consumption in Sleep, flash ON and
power supplied by external SMPS (VDD12 = 1.10 V)
– Table 54: Wakeup time using USART/LPUART
– Table 104: USB BCD DC electrical characteristics
– Figure 5: Voltage reference buffer
Sections updated:
– Section : Features
– Section 2: Description
– Section 3.9.1: Power supply schemes
– Section 3.9.3: Voltage regulator
266/271 DS10198 Rev 9


– Section 3.14.2: Extended interrupt/event controller

(EXTI)
– Section 3.24.6: Independent watchdog (IWDG)
– Section 3.27: Universal synchronous/asynchronous
receiver transmitter (USART)
– Section 3.28: Low-power universal asynchronous
receiver transmitter (LPUART)
– Section 3.34: Universal serial bus on-the-go full-speed
(OTG_FS)
– Section 6.2: Absolute maximum ratings
– Section 6.3.5: Supply current characteristics
– Section 6.3.18: Analog-to-Digital converter
characteristics
– Section 7: Package information
– Section 8: Ordering information
Tables updated:
– Table 2: STM32L476xx family device features and
peripheral counts
– Table 4: STM32L476xx modes overview
– Table 6: STM32L476xx peripherals interconnect
matrix to add TIM16/TIM17
5 – Table 16: STM32L476xx pin definitions on pin PA3
06-Jul-2017
(continued) updated I/O structure from TT to TT_la, on pin
VSSA/VREF- updated type to supply pin, added
SMPS packages
– Table 17: Alternate function AF0 to AF7
– Table 18: Alternate function AF8 to AF15
– Table 20: Voltage characteristics
– Table 21: Current characteristics
– Table 23: General operating conditions
– Table 24: Operating conditions at power-up / power-
down
– Table 26: Embedded internal voltage reference
– Table 52: Low-power mode wakeup timings
– Table 75: Analog switches booster characteristics:
deleted VBOOST.
– Table 82: DAC characteristics
– Table 85: COMP characteristics to add Ibias
parameter
– Table 86: OPAMP characteristics
– Table 102: USB OTG DC electrical characteristics
– Table 103: USB OTG electrical characteristics
– Table 137: STM32L476xx ordering information
scheme
DS10198 Rev 9 267/271

270

Figure updated:
Figure 1: STM32L476xx block diagram
Figure 62: UFBGA132 - Outline
Footnotes updated for:
– Table 16: STM32L476xx pin definitions
– Table 20: Voltage characteristics
5
06-Jul-2017 – Table 70: I/O static characteristics
(continued)
– Table 84: VREFBUF characteristics
– Table 85: COMP characteristics
– Table 77: Maximum ADC RAIN
– Figure 32: Recommended NRST pin protection
– Figure 34: Typical connection diagram when using the
ADC with FT/TT pins featuring analog switch function
Added SMPS option to UFBGA132 package.
Aligned DAC instance (DAC1) and DAC output channels
(DAC1_OUTx) terminology in all the document.
Updated Table 1: STM32L476xx block diagram.
09-Mar-2018 6 Added Figure 10: STM32L476Qx, external SMPS
device, UFBGA132 ballout(1)(2).
Updated Table 16: STM32L476xx pin definitions.
Updated Table 20: Voltage characteristics.
Updated Table 82: DAC characteristics.
Added UFBGA144 package.
Updated Section 3.9.1: Power supply schemes.
Added Figure 3: Power-up/down sequence.
24-May-2018 7 Updated Figure 4: Clock tree.
Updated Section 6.3.2: Operating conditions at power-
up / power-down.
Updated Table 137: STM32L476xx ordering information
scheme.
07-Jun-2019 8
scheme.
268/271 DS10198 Rev 9


Added WLCSP99 package on cover page silhouette.

Updated Section 1: Introduction.
Updated Section 2: Description including Table 2:
STM32L476xx family device features and peripheral
counts.
Updated Section 3.23: True random number generator
(RNG).
Updated Figure 6: STM32L476Zx LQFP144 pinout(1)(2).
Updated Figure 7: STM32L476Zx, external SMPS
device, LQFP144 pinout(1)(2).
Updated Figure 8: STM32L476Zx UFBGA144
ballout(1)(2).
Updated Figure 9: STM32L476Qx UFBGA132
ballout(1)(2).
Updated Figure 10: STM32L476Qx, external SMPS
device, UFBGA132 ballout(1)(2).
Added Figure 12: STM32L476VxY, external SMPS
device, WLCSP99 ballout(1)(2).
Updated Figure 13: STM32L476Mx WLCSP81
ballout(1)(2).
Updated Figure 13: STM32L476Mx WLCSP81
01-Mar-2024 9
ballout(1)(2).
Updated Figure 15: STM32L476Jx, external SMPS
device, WLCSP72 ballout(1)(2).
Added Note:.
Added WLCSP99 package in Table 16: STM32L476xx
pin definitions.
Added VREF+ in Table 20: Voltage characteristics.
Updated ∆VDD(MSI) range 8 to 11 in Table 60: MSI
oscillator characteristics.
Added Note:.
Updated Section : Output driving current including
Table 71: Output voltage characteristics.
Updated Table 91: DFSDM characteristics.
Updated Figure 40: Quad SPI timing diagram - DDR
mode.
Added Section 7.6: WLCSP99 package information,
updated all other sections from Section 7.2: LQFP144
package information to Section 7.9: LQFP64 package
information.
scheme.
DS10198 Rev 9 269/271

270

Updated Table 1: Device summary

Updated Table 2: STM32L476xx family device features
and peripheral counts
Renamed Figure 16: STM32L476Rx LQFP64 pinout(1)
Renamed Figure 17: STM32L476Rx, external SMPS
device, LQFP64 pinout(1)
Updated Table 23: General operating conditions
Updated Table 45: Current consumption in Stop 2 mode
Updated Table 47: Current consumption in Stop 0 mode
Updated Table 48: Current consumption in Standby
9 mode
01-Mar-2024
(continued) Updated Figure 33: ADC accuracy characteristics
Updated Table 90: LCD controller characteristics
Updated Table 133: Package thermal characteristics
Updated Section 8: Ordering information
Added general section for Section 7.1: Device marking
Removed Device marking from Section 7.5: LQFP100
package information, Section 1.8: UFBGA100 package
information, Section 7.9: LQFP64 package information,
Section 1.14: UFBGA64 package information,
Section 1.19: LQFP48 package information,
Section 1.20: UFQFPN48 package information
270/271 DS10198 Rev 9

STM32L476xx
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product
or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2024 STMicroelectronics – All rights reserved
DS10198 Rev 9 271/271

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STM32L476xx

Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,

March 2024 DS10198 Rev 9 1/271

– 3x I2C FM+(1 Mbit/s), SMBus/PMBus • 14-channel DMA controller

STM32L476RC, STM32L476VC, STM32L476JE, STM32L476ME, STM32L476QE,

2/271 DS10198 Rev 9

DS10198 Rev 9 3/271

3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

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Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

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running from flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

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Table 82. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

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Table 134. STM32L476xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

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Figure 1. STM32L476xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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Figure 47. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 219

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The STM32L476xx devices are ultra-low-power microcontrollers based on the

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Table 2. STM32L476xx family device features and peripheral counts

512 1 512 1 256 512 1 1 512 1 512 1 256 512 1

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Table 2. STM32L476xx family device features and peripheral counts (continued)

Random generator Yes

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Figure 1. STM32L476xx block diagram

CLK, NE[4:1], NL, NBL[1:0],

VDD Power management

XTAL OSC OSC_IN

UART4 RX, TX, CTS, RTS as AF

UART5 RX, TX, CTS, RTS as AF

CMD, CK as AF SDIO / MMC

1 compl. channel, BKIN as AF TIM17

RX, TX, CK,CTS, USART1

SAI1 VLCD = 2.5V to 3.6V

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

INP, INM, OUT COMP1 IO

1. Only available when using external SMPS supply mode.

Note: AF: alternate function on I/O pins.

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3.1 Arm® Cortex®-M4 core with FPU

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

3.3 Memory protection unit