Application Guide Volume III AG2020-07

Applying the SEL-651R at the Point of Common

Coupling for Interconnection Protection
Brett Cockerham and Luke Booth

PURPOSE
Federal incentives, better technology, and a desire for cleaner power are contributing to Distributed
Energy Resources (DER) becoming more common. DER provide unique scenarios not previously
protected by traditional distribution protection schemes. DER connect to Area Electric Power
Systems (Area EPS) through a point of common coupling (PCC). This application guide explains
how to set an SEL-651R Advanced Recloser Control to protect at the PCC to maintain confor-
mance with your interconnection agreement. In developing this application guide, we used IEEE
1547 as the industry-recognized standard for protection at the PCC. This application guide seeks to
help settings developers adhere to this standard while providing them flexibility to accommodate
future revisions to the standard.

OUTLINE
This application guide explains how to modify the SEL-651R-2 default settings file to implement
typical protection at the PCC. The outline is as follows:
➤ Creating a New Settings File
➤ Global Settings
➤ Group Settings
➢ Identifier and Instrument Transformer Settings
➢ Voltage Element Settings
➢ Frequency Element Settings
➢ Directional Element Settings
➢ Overcurrent Element Settings
➢ Power Element Settings
➢ Synchronism Check Element Settings
➢ Close Logic Equations
➢ Trip Logic Equations
➤ Front-Panel Settings
➤ Report Settings

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APPLICATION
Figure 1 shows the example system configuration that serves as the basis for this application
guide.

Utility Distribution System

Load
PTR = 7200/120
12.47 kV/ 480 V DER
CTR = 500/1
B1 R1
Customer
PCC Load
VZ VY
Load
Source Load
SEL-651R-2

Figure 1 Example System One-Line Diagram

Creating a New Settings File

First, create a new settings file for the SEL-651R-2 in ACSELERATOR QuickSet® SEL-5030
Software. Use the following steps to create your settings file:
Step 1. Select File > New to open the Settings Editor selection window.
Step 2. Select SEL-651R under Device Family, SEL-651R-2 under Device Model, and 008
under Version, and then select OK.
Step 3. Enter the part number of the device and select OK. Figure 2 shows the SEL-651R-2
model options.

Figure 2 SEL-651R-2 Model Options

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Global Settings
To fully set the SEL-651R, review the settings this section describes to ensure that the device is
configured correctly.
NFREQ, the nominal frequency of the system, is set to a default value of 60 Hz. It can be changed
to 50 Hz.
PHROT, short for phase rotation, is set to a default value of ABC. It can be changed to ACB for
ACB systems.
Figure 3 shows entry of these settings.

Figure 3 Setting Nominal Frequency and Phase Rotation

The phasing of the lines going through a recloser can be in any orientation, which causes a
challenge in assigning each CT between the recloser and SEL-651R to the correct phase. The
SEL-651R defines the current terminations as I1, I2, and I3. The SEL-651R allows the user to
label the inputs I1, I2, and I3 from the recloser to the phases connected to the system.
The Global setting IPCONN defines the current pole connection. Table 1 displays the different
connection options with the corresponding IPCONN setting.
Table 1 Current Connection Setting IPCONN

Phase CT Signal Connections Required Global Setting

I1 Terminals I2 Terminals I3 Terminals IPCONN

IA IB IC ABC
IA IC IB ACB
IB IA IC BAC
IB IC IA BCA
IC IA IB CAB
IC IB IA CBA

CTPOL is a setting that can mathematically manipulate CT polarity. If the value for this setting is
POS, the SEL-651R maintains the polarity of the CTs on the system. If CTPOL is set to NEG, the
CT polarity is effectively inverted. This is useful in defining the direction of the power, impedance,
and directional overcurrent elements.

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VYCONN and VZCONN specify how the SEL-651R voltage connections are connected to the
system. As with the current inputs, the voltage inputs are labeled by pole (i.e., V1Y, V2Y, V3Y and
V1Z, V2Z, V3Z) into the SEL-651R. Table 2 displays the voltage selection options for Terminal Y.
Substitute Z for Y in the table to get the voltage selection options for Terminal Z.
Table 2 Voltage Connection Setting VYCONN

VY-Terminal Signal Required Global

“VY” Available as Setting Choice for:
Connections Setting

V1Y V2Y V3Y VYCONN := EPHANT VSELECT FSELECT

VA VB VC ABC no yes yes
VA VC VB ACB no yes yes
VB VA VC BAC no yes yes
VB VC VA BCA no yes yes
VC VA VB CAB no yes yes
VC VB VA CBA no yes yes
VA – – A yes no yes
VB – – B yes no yes
VC – – C yes no yes
VAB – – AB yes no yes
VBC – – BC yes no yes
VCA – – CA yes no yes
– – – OFF no no no

VSELECT determines which voltage input, whether VY or VZ, should be used for protection
functions that require three-phase voltage. It also enables loss-of-potential (LOP) protection.

NOTE: The undervoltage/overvoltage elements are unaffected by the setting of VSELECT.

FSELECT determines which voltage terminal, whether VY or VZ, provides frequency

measurement for applications of frequency in the recloser control.
Figure 4 shows entry of the current and voltage connection settings.

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Figure 4 Current and Voltage Connection Settings

Group Settings
Identifier and Instrument Transformer Settings
Next, as Figure 5 shows, specify the current transformer ratio, potential transformer ratio, and
nominal system voltage.

NOTE: Consult the SEL-651R-2 instruction manual for guidance in setting PTRY, PTRZ, and VNOM when
using low-energy analog (LEA) inputs.

Figure 5 Identifier and Instrument Transformer Settings

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Voltage Elements Settings

The PCC recloser control must respond to abnormal voltages by disconnecting the DER from the
Area EPS. The abnormal voltage windows and the clearing time to disconnect may differ accord-
ing to interconnection agreements. Table 3 lists example voltage windows and the associated clear-
ing times. If any voltage disturbance lies in a window Table 3 provides, the DER disconnect from
the Area EPS.
Table 3 Interconnection System Response to Abnormal Voltages (IEEE Std. 1547-2018
Category 1 Default Settings)

Voltage Range (% of Base Voltage) Clearing Time (s)

V < 45 0.16
V < 70 2.00
V > 110 2.00
V > 120 0.16

The clearing time is defined as the time between the start of the abnormal condition and the
operating device disconnecting the DER from the Area EPS. For this example, we assume a 3-
cycle recloser clearing time.
The undervoltage and overvoltage elements in the SEL-651R-2 are set in volts secondary. Time
delays can be implemented through the use of SELOGIC variable and timers. The timers are set in
units of cycles. The delay in Table 3 must therefore be converted to cycles to be set correctly in the
SEL-651R-2. The time-delay conversion shown in Equation 1 assumes a measured 60 Hz
fundamental frequency.

60 cycles = 1 s
Equation 1

If we assume a nominal secondary voltage of 120 V phase-to-neutral, Table 4 derives the set points
and the applicable time delays from Equation 1. For the time delays in this example, we assume a
3-cycle recloser clearing time.
Table 4 Interconnection System Response Delay to Abnormal Voltages (VNOM = 120 V)

Voltage Range
Delay Setting (Cycles)
(Volts Secondary)
0.45 • VNOM = 54 9.6 – 3 = 6.6
0.70 • VNOM = 84 120 – 3 = 117
1.1 • VNOM = 132 120 – 3 = 117
1.2 • VNOM = 144 9.6 – 3 = 6.6

The SEL-651R-2 has two sets of voltage inputs, one corresponding to a set of Y terminals (load)
and the other to a set of Z terminals (source). For this setting example (refer to Figure 1), we
consider the utility to be the source and connected to the Z terminals. We consider the DER site to
be the load and connected to the Y terminals.
The SEL-651R-2 has voltage-sensing capability on both sides of the recloser, so we can implement
the voltage elements in close logic for hot-source (energized) and dead-load (de-energized)
supervision. An adequate voltage measurement for determining an energized source is 92 percent
of the rated nominal voltage (VNOM). We can use 15 percent of the rated nominal voltage
(VNOM) to determine the presence or absence of voltage.

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The Close Logic Equations section reviews the previous voltage set points in more detail. For this
example, we use both the Y and Z terminals. The SEL-651R-2 uses Relay Word bits that assert
(turn on) or deassert (turn off) based on meeting certain criteria related to set points in the recloser
control. Table 5 lists undervoltage and overvoltage settings and the corresponding Relay Word bits.
Additionally, two elements (59YP1P and 59ZP1P) will be used to verify healthy voltage on both
sides of the recloser.
Table 5 Voltage Settings and Corresponding Relay Word Bits

Under/Overvoltage Settings Relay Word Bits Example Definition

27YP1P 27YA1, 27YB1, 27YC1, and 3P27Y De-energized Load
59YP1P 59YA1, 59YB1, 59YC1, and 3P59Y Healthy Voltage Check
27ZP1P 27ZA1, 27ZB1, and 27ZC1 Undervoltage Level 1
27ZP2P 27ZA2, 27ZB2, and 27ZC2 Undervoltage Level 2
59ZP1P 59ZA1, 59ZB1, 59ZC1, and 3P59Z Healthy Voltage Check
59ZP2P 59ZA2, 59ZB2, and 59ZC2 Overvoltage Level 1
59ZP3P 59ZA3, 59ZB3, and 59ZC3 Overvoltage Level 2

By using the set points derived in Table 4, we can now add the settings into the SEL-651R-2
setting file, as shown in Figure 6.

Figure 6 Voltage Element Settings

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Depending on whether DER are conventional positive-sequence sources or line-commutated

inverter-based sources, LOP logic will be necessary to supervise the undervoltage elements.
Figure 7 demonstrates the use of SELOGIC variables to apply undervoltage tripping, including
associated time delays, for conventional positive-sequence sources. The under- and overvoltage
Relay Word bits serve as an input to the timer logic. If the input remains asserted for the duration
of the specified time, the associated SELOGIC variable timer output SVxxT asserts (turns on).
A blown fuse condition may cause the recloser control to erroneously trip for undervoltage. You
can use LOP logic to set the SEL-651R-2 to guard against this occurrence for positive-sequence
sources.

Figure 7 Voltage Time-Delayed Settings for Positive-Sequence Sources

Set the input for time-delayed voltage protection similarly for both positive-sequence and inverter-
based DER. However, inverters can respond differently in comparison to conventional rotating
positive-sequence sources and could falsely assert LOP during abnormal system events.
Additionally, voltage elements are the primary protection for inverter-based sources; therefore, not
tripping for a blown fuse could compromise protection. For these reasons, remove NOT LOP from
the input logic for applications where the SEL-651R is used on inverter-based DER.

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Figure 8 Voltage Time-Delayed Settings for Inverter-Based Sources

SV03T, SV04T, SV05T, and SV06T are voltage element-driven timers. To trip the PCC for an
abnormal voltage condition, include these Relay Word bits in the trip logic equation.

Frequency Element Settings

You may want the PCC recloser control to respond to abnormal fundamental frequency by discon-
necting the DER from the Area EPS. The abnormal fundamental frequency threshold and delay
can vary based on interconnection agreements. Table 6 lists example thresholds and the associated
clearing times. If the PCC recloser control determines that the fundamental frequency exceeds
(overfrequency) or falls below (underfrequency) the specified thresholds, the DER disconnect
from the Area EPS.
Table 6 Interconnection System Response to Abnormal Frequency (IEEE Std. 1547-2018
Default Settings)

Frequency Range (Hz) Clearing Time (s)

< 57 0.16
< 58.5 300
> 61.2 300
> 62 0.16

The SEL-651R is equipped with six frequency elements with independent timers. Each element
can be set as either an overfrequency or an underfrequency element, depending on the set point. If
the set point exceeds the nominal frequency, the element operates as an overfrequency element. If
the set point is lower than the nominal frequency, the element operates as an underfrequency
element.

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For the DER to separate from the Area EPS within the specified time shown in Table 6, recloser
tripping time must be subtracted from the overall clearing time.
Beginning with firmware R408, the SEL-651R allows setting of the frequency time delay in units
of cycles or seconds, as defined by setting E81. When E81 = 1–6, cycles will be the applied units.
When E81 = E1–E6, seconds will be the applied units. Equation 2 illustrates how to use the pickup
setting to convert from seconds to cycles.

Time Delay (cyc) = Time Delay (s) • Pickup Setting (Hz)

Equation 2

For this example, the time delay will be applied in seconds. This example assumes, again, that the
recloser will extinguish the arc in 3 cycles, and this time will be subtracted from the time delay. If
we use the default settings from Table 7, four frequency elements will be necessary.
Table 7 Default Frequency Settings

Frequency Set Point (Hz) Time Delay (S) Definition

57 0.16 – 0.05 = 0.11 Underfrequency Level 1
58.5 300 – 0.05 = 299.95 Underfrequency Level 2
61.2 300 – 0.05 = 299.95 Overfrequency Level 1
62 0.16 – 0.05 = 0.11 Overfrequency Level 2

The SEL-651R-2 has an undervoltage supervision check for all frequency elements that ensures
frequency elements do not operate for a fault condition. A fault condition creates a transient that
can result in incorrect system frequency measurement. Therefore, set 27B81 to assert for all fault
conditions. For this example, the undervoltage supervision check (27B81P) will be set to
70 percent of VNOM. If the measured voltage is less than 27B81P, the frequency elements will be
blocked until the system voltage recovers above the specified threshold.

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Figure 9 Frequency Element Settings

The Relay Word bits associated with the frequency element time delays are 81D1T, 81D2T,
81D3T, and 81D4T. To trip the PCC for an abnormal frequency condition, include these Relay
Word bits in the trip equation. Note that frequency measurement can come from either the Y or Z
voltage terminal. To detect abnormal and healthy frequency conditions on the Area EPS, regard-
less of the physical state of the recloser, use the source terminals (FSELECT = VZ) for frequency
protection.

Directional Element Settings

Directional elements can be used to supervise an overcurrent element that only enables for faults in
the desired tripping direction. Because inverter-based DER can challenge the operating principle
of directional elements, it is necessary before applying directional element control to carefully
consider use of such sources. In many cases, the inverter-based DER cannot source utility faults at
levels exceeding full-load amperes. Therefore, current magnitude alone could be used to
differentiate between forward and reverse faults for these cases.
The directional elements allow for automatically entered (AUTO or AUTO2) and manually
entered (Y) settings.
The ORDER setting may be Q, V, QV, or VQ. Q is the negative-sequence directional element,
while V is the zero-sequence voltage-polarized directional element. When a fault occurs, the logic
checks the quantities available for the first element listed, and the recloser control uses that
element if the logic determines it is reliable for that fault.

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The ORDER setting is contingent on many factors including application, source type, transformer
connections, and protection philosophy. Setting guidelines have been published for conventional
rotating positive-sequence sources in [1]. Existing guidelines may need adjusting for inverter-
based DER. The zero-sequence directional element (ORDER=V) has been popularized in recent
years due to the response of inverter-based DER during a fault. All directional settings should be
carefully reviewed especially for these source types. See the SEL-651R-2 instruction manual for
more information on directional element settings.
This example follows the guidance in [1]. Set ORDER to QV and E32 = AUTO2. Additionally, set
50P32P to assert for all three-phase faults within the zone of protection.

Figure 10 Directional Control Settings

During an LOP condition (e.g., blown PT fuse), the Q and V directional elements are impacted and
can be unreliable. Therefore, if ELOP = Y or Y1, the voltage-polarized directional elements are
disabled and blocked from operation. If ELOP = Y1 and an LOP condition occurs, any directional
element-controlled overcurrent element is disabled entirely. However, if ELOP = Y and an LOP
condition occurs, the overcurrent elements that were controlled in the forward direction remain
enabled. For this example, set ELOP to Y.

Figure 11 Enable LOP Condition

Overcurrent Element Settings

Overcurrent protection is necessary for most applications at the PCC to provide coordination
between the SEL-651R and other system protection devices. In some cases, it may be necessary to
use multiple phase and ground overcurrent elements to achieve the desired coordination.
For this example, we use two levels of phase and ground overcurrent elements. The first level is
nondirectional, and the second level demonstrates how to torque control an overcurrent element
with a directional element.

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A coordination study ordinarily determines the selection of pickups, curves, and time dials. This
application guide uses generic values for illustration. Figure 12 shows how to set the
nondirectional phase overcurrent element.

Figure 12 Phase Time-Overcurrent Element Settings in QuickSet

The setting 51PTC is the logic equation that supervises the 51P1 element. When programmed as
51PTC = 1, the element is always enabled. The second-level phase overcurrent element will be
torque controlled for faults in the forward direction (32PF). The second level is enabled through
use of the single-phase overcurrent elements, so each phase should be set identically with respect
to the associated settings. Figure 13 and Figure 14 demonstrate this.

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Figure 13 Level 2 A- and B-Phase Time-Overcurrent Elements

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Figure 14 Level 2 C-Phase Time-Overcurrent Elements

As with the phase overcurrent elements, the ground overcurrent elements will be set to allow
Level 1 to operate regardless of the fault direction and Level 2 will be torque controlled for
forward faults (32GF). Additionally, LT01 resides within the default logic so you can use PB01 on
the front of the device to enable and disable ground elements. The present example maintains that
default logic and use for PB01 (see the settings for the 51GTC and 51G2TC torque-control
equations in Figure 15).

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Figure 15 Ground Time-Overcurrent Settings in QuickSet

The SEL-651R-2 should perform no automatic reclosing operations following a protective trip at
the PCC. Figure 16 illustrates how to disable the reclosing function for the recloser control.

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Figure 16 Disabling Reclosing Attempts

In this example, as shown in Figure 1, there is a transformer on the DER of the PCC. When the
PCC recloser closes, the utility distribution feeder supplies magnetizing inrush currents that may
result in a sensitive overcurrent element operating during energization. The second-harmonic
blocking logic can prevent this by blocking the overcurrent elements until inrush currents have
subsided. The second-harmonic blocking should be enabled for the previously discussed condi-
tions. A pickup of 10 percent is the default set point, but this may need adjusting based on the spe-
cific installation. To learn how to empirically measure second-harmonic content, refer to
Mitigation of Undesired Operation of Recloser Controls Due to Distribution Line Inrush available
from the Technical Papers listing on the SEL website. Figure 17 shows the applicable settings.

Figure 17 Second-Harmonic Blocking Settings in QuickSet

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In a distribution system, it is typical for inrush currents to remain above minimum pickups for as
long as 10 cycles. Therefore, a SELOGIC variable and timer could be used to block the overcurrent
elements when the second harmonic content exceeds the threshold. However, the SELOGIC
variable will unblock the element after 10 cycles. Additionally, there can be measurable
second-harmonic content during fault conditions. If second-harmonic content exceeds the
threshold, therefore, the overcurrent element is only delayed by the specified time and not blocked
continuously. It may be desirable to adjust the timer to another value based on the system
configuration.
Figure 18 shows the SELOGIC variable and time configured for this condition.

Figure 18 SELOGIC Variable Settings for Dropout Time Using Harmonic Blocking

Note that we add the logic NOT(HBL2T AND SV10T), as shown in Figure 27, to supervise the
overcurrent elements for inrush conditions, so coordination studies with upstream protection must
use the time-overcurrent settings with a 10-cycle minimum trip response to model this device.

Power Element Settings

The SEL-651R-2 is equipped with four three-phase power elements. You can set each element
independently to detect either watts or VARs in the forward or the reverse direction. To set these
elements, it is critical to know what constitutes a forward and reverse direction to the recloser
control. Figure 1 shows a typical ac connection in addition to the resulting forward and reverse
power flow direction for the SEL-651R. The direction of current flow and the CT polarity
markings dictate how the recloser control interprets forward and reverse power flow. Notice in
Figure 19, when current flows from left to right, that the current first hits the positive polarity
marking of the CT; this results in positive power flow. Similarly, when the current flows from right
to left, the current first hits the negative polarity of the CT; this results in negative power flow.

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+WATTS –WATTS DER

I (amperes) I (amperes)

R1
Customer
PCC
Load
VZ VY

SEL-651R-2

Figure 19 SEL-651R AC Connection Diagram

Three-phase power elements can be set to operate for power export violations. If the
interconnection agreement includes this constraint, the SEL-651R can be set to detect a power
flow in the reverse direction. For power export violations, set the power element (PWRnT, where
n = 1, 2, 3, or 4) to –WATTS. For other applications that require forward direction power elements,
set the recloser control power element to +WATTS.
Use Equation 3 to calculate the reverse three-phase power element pickup.

WATTs
3PWR1P = -----------------------------
CTR  PTR
Equation 3

where:
3PWR1P is the three-phase power element pickup in secondary Watts
WATTs is the desired three-phase power set point in primary Watts
CTR is the current transformer ratio, (xxx/1)
PTR is the potential transformer ratio, (xxx/1)

Through the use of Equation 3, we can calculate the SEL-651R power element pickup setting for
an example primary threshold of 100 kW. Note that a higher PT ratio results in a smaller secondary
power element pickup. For this reason, if you need sensitive power element pickups (such as in a
no-export contract), you may need to use traditional wire-wound PTs rather than the capacitive or
resistive voltage dividers commonly available with the attached recloser.

CTR: 500/1
PTR: 120/1
100 kW
3PWR1P = -------------------- = 3.34 VA
60  500
Equation 4

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A minimum time delay of 5 cycles prevents the power elements from operating during system
transients. In some cases, it may be desirable to use the NOT of an overcurrent element (51P) to
supervise the power element. This can prevent lack of coordination with other protection elements.
For this example, a 10-cycle delay provides added security. Figure 20 shows how to specify these
settings into QuickSet.

Figure 20 Power Element Settings in QuickSet

Additional three-phase power elements are available and can be used for additional
interconnection guidelines such as satisfying minimum import criteria. The Relay Word bit
3PWR1 may be used in the TR logic equation to trip the recloser through use of the power
element.

Synchronism Check Element Settings

In some installations, the PCC is the device that joins the DER to the Area EPS. Before PCC clos-
ing, several important criteria, mandated by the interconnection agreement, must be met. When
these criteria are met, the synchronism check element additionally supervises the closing by
measuring the voltage, frequency, and angle on both sides of the recloser. If the voltage, frequency,
and angle are all in the required windows, the SEL-651R is free to close. The synchronism check
settings use voltage functions VP and VS. Generator source selection setting EGSELECT assigns
which voltage terminals (VZ or VY) function as VP and VS. In this example, the DER side is con-
nected to VY terminals, so EGSELECT = VY. When EGSELECT = VY, VY terminals are
assigned to the VP function and VZ terminals are assigned to the VS function. Figure 21 shows the
location of synchronism check element settings in QuickSet.

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Figure 21 Synchronism Check Element Settings in QuickSet

The Relay Word bit 25A1 asserts once the two sources are synchronized within the voltage,
frequency, and angle windows, and the bit may now be used to supervise a close command in the
close logic equation of the SEL-651R.

Close Logic Equations

Before you initiate a close at the PCC, it may be required for supervision logic to verify that
conditions are safe to connect the utility with the DER site. The supervision logic may include
hot-source and dead-line logic, in addition to a synchronism check. The logic for this example
incorporates hot-source and dead-line (HS-DL) logic in addition to synchronism check to
supervise any local, remote, or automatic restoration closing.
This HS-DL logic allows a close to be issued so that the utility can supply power to DER auxiliary
loads when the DER source is offline. Recall that Table 5 defines the de-energized load conditions
(3P27Y verifies that the DER source is offline) and energized source conditions (3P59Z verifies
that the utility source is online). We therefore use Relay Word bits 3P27Y and 3P59Z to supervise
the HS-DL logic.
We will also include the Relay Word bit 25A1 to supervise closing when both sources are
energized, to ensure synchronization of the two sources prior to the closing action.

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When you issue either a local or remote close, it is possible that the supervision logic is not
immediately satisfied. It may therefore be desirable to add a timer that allows a close within a
specified time window. If that window expires prior to a close, it would be necessary to reinitialize
the close logic. If the supervision logic evaluates as a true condition anytime during the specified
time window, the SEL-651R-2 issues the close. The logic in Figure 22 illustrates the close
permissive and timer logic.

Figure 22 Close Permissive Logic and Associated Timer in QuickSet

where:
PB11_PUL is the front-panel CLOSE pushbutton
LT05 is the front-panel PUSH BUTTONS LOCKED pushbutton (and thus is in the unlocked
state)
CC3 is the remote close
LT03 is remote functions enabled
SV01 is the close permissive and timer

The default SEL-651R-2 includes several unused AUX pushbuttons that can be programmed for
custom functions. Pushbutton 10, for example, can be used to enable and disable automatic
restoration close permissive logic. Figure 23 shows the logic to enable and disable the automatic
restoration feature.

Figure 23 Setting Latch 10 Using Pushbutton 10 for Automatic Restoration Close Permissive
Logic

where:
PB10_PUL is the front-panel automatic restore enable and disable
LT10 is the automatic restore logic enable

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Automatic restore logic can be applied when the PCC recloser control (SEL-651R-2) detects that
the utility has islanded and tripped. After the utility source is reconnected to the feeder, and all
three-phases remain healthy for a specified time, the automatic restore logic issues a close permis-
sive. Figure 24 shows this logic.

Figure 24 Setting SELOGIC Variable 09 for Automatic Restoration Close Permissive Logic

where:
SV09T is the restore close permissive

The close permissive, which incorporates the Relay Word bits SV08 and SV09T, can be included
(as shown in Figure 25) in equations CL3P and ULCL3P.

Figure 25 Setting Close Logic Incorporating SV08 and SV09T in QuickSet

To alert the user of a forthcoming close, use another SELOGIC variable as an oscillator that will
flash both RECLOSER OPEN and RECLOSER CLOSED LEDs. Figure 26 displays this oscillator logic.
SV07T will be incorporated in control LED settings PB11_LED and PB12_LED, as shown in
Figure 34.

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Figure 26 Setting SELOGIC Variable 07 for Imminent Close Oscillator

Trip Logic Equations

When a disturbance occurs on the Area EPS, it is imperative to trip the PCC as quickly as possible
to minimize equipment damage and system stresses as well as to allow the utility to reclose swiftly
for momentary faults. The previous sections listed several protection elements that must be set to
detect faults and/or utility islanding. Figure 27 shows these elements within the trip equations
TR3P and TR3X.

Figure 27 Trip Logic SELOGIC Equations

Direct Transfer Trip Logic

Direct transfer trips (DTT) are commonly used to force the PCC recloser control to operate when a
utility islanding event occurs. This may be necessary when the DER can support an islanded por-
tion of the Area EPS with little deviation in voltage or frequency. Figure 28 shows that one possi-
ble solution for quickly disconnecting the DER from feeding an upstream fault is to use a
communications medium to communicate to the PCC recloser control. The DTT protocol for this
example is MIRRORED BITS® communications. Once the DER are disconnected, the upstream
breaker is free to proceed through the reclose cycle. If the upstream breaker recloses and holds
closed, the next step is to reclose the PCC. The automatic restore logic previously discussed under

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Close Logic Equations on page 21 explains how to achieve this. As suggested by the automatic
restore logic timer, it is necessary to wait some time to verify that the system is stable. Five
minutes is typical and was used in the example.

SYS

IFAULT FAULT
ISYS
EPS
SEL-651R

PCC IFAULT
MIRRORED BITS ® SEL-651R
Communications

DER

Figure 28 One-Line System Displaying Fault Upstream of the PCC

The utility recloser control in this example is also an SEL-651R, but it could be any feeder
protective recloser control. The SEL-651R at the breaker sends a DTT over MIRRORED BITS
communications to the PCC SEL-651R. Once the upstream breaker recloses and holds closed for a
set time, the reclose reset (79RS) Relay Word bit asserts. The PCC SEL-651R uses the VZ
terminals to measure the utility voltage and begins a 5-minute timer. During these 5 minutes, the
recloser control analyzes system voltages and frequency to verify that they are healthy. If they
remain healthy for 5 minutes and the two systems are synchronized, the PCC SEL-651R closes the
recloser. For the MIRRORED BITS communications, transmitted bits include TMB1A–TMB8A
(Channel A) and TMB1B–TMB8B (Channel B). The received bits in the PCC SEL-651R are
RMB1A–RMB8A and RMB1B–RMB8B.
If the PCC SEL-651R receives DTT via transmit MIRRORED BITS from the upstream SEL-651R
and the recloser is closed, the recloser should trip. The trip logic shown in Figure 29 contains the
elements necessary for such a trip.

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Figure 29 Addition of RMB1A to Tripping Conditions

The upstream device begins its reclosing cycle. If it recloses and the fault has cleared, the device
enters the reset state after a specified delay. As described by the automatic restore close logic, if
the utility remains closed in on the line and the voltage is healthy for the specified time, the PCC
issues a close permissive to restore the PCC connection.

Front-Panel Settings
Targeting on the front of the recloser control is an initial visual of the type of event that occurred.
Consider Figure 30. Note that the LED targeting on the recloser control front panel includes
phases, ground, voltage elements, frequency elements, reclosing state, and other elements. You can
program and relabel these LEDs as you want.

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DELAY COLD LOAD

SUPPLY CURVE SCHEME ON
BATTERY HIGH REVERSE
PROBLEM CURRENT POWER ENABLED

A FAULT OVER/UNDER VAY

FREQUENCY DER ON TRIP
OVER/UNDER VBY
B FAULT VOLTAGE DER ON
C FAULT 79 RESET VCY
DER ON
GROUND 79 CYCLE VAZ
UTILITY ON TARGET
VBZ RESET
SEF 79 LOCKOUT
UTILITY ON
FAST ABOVE MIN VCZ
CURVE TRIP UTILITY ON WAKE UP

GROUND FAST AUX 2

ENABLED CURVE
ENABLED

RECLOSE PUSH AUTO

ENABLED BUTTONS RESTORE
LOCKED
ENABLED

REMOTE HOT LINE RECLOSER

ENABLED TAG CLOSED
CLOSE

ALT AUX 1 RECLOSER

SETTINGS OPEN
TRIP

Figure 30 Operator Control and Target LED Layout

It is necessary to program only a few of these LEDs in the RDB file to other than what exists in the
default settings. Notice that Trip Latch T_LED is set to Y for these elements. If setting
TxxLEDL = Y, and a trip occurs while the individual LED equation is true, the Txx_LED remains
latched in.
Figure 31 displays the logic added to LEDs 11 and 12 for frequency and voltage, respectively.

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Figure 31 Frequency and Voltage LED

Add the Level 1 power element to LED 18, as shown in Figure 32.

Figure 32 Reverse Power LED

Apply the logic in Figure 33 to illuminate LEDs 22–24 for healthy voltages on the Z terminals.

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Figure 33 Healthy Z Terminal Voltage LEDs

Within the Close Logic Equations, PB10 was programmed to enable and disable the automation
restoration close logic. If you use this logic, also program the PB10_LED to display the status.
Figure 34 includes the logic necessary for you to use this feature to view automation restoration
close status from the front panel. Additionally, SELOGIC Variable 07 is added to equations
PB11_LED and PB12_LED. This logic alerts the user by flashing both the RECLOSER CLOSED and
RECLOSER OPEN pushbutton LEDs when an imminent close is possible (SV08 or SV09 are asserted).

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Figure 34 Automatic Restoration Enabled and Imminent Close Indication LEDs

A display point message can also be programmed to provide additional clarification that an
imminent close is in progress. Display Point 01 (DP01) provides indication that the close
permissive logic is initiated and timing is as defined by SV08. Also, SV09 is assigned to Display
Point 02 (DP02) to provide indication that the automatic restoration close logic is initiated and
timing.

Figure 35 Display Point Settings

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Report Settings
The report settings are essential for troubleshooting and verifying the intended behavior of the
control. To ensure that the SEL-651R archives relevant data for these purposes, map elements in
which you are interested to the SER and ER equations.
For this example, we incorporated additional elements into equations SER3 and SER4, as shown in
Figure 36 and Figure 37, respectively.

Figure 36 SER 3 Trigger List

Figure 37 SER 4 Trigger List

For this example, as shown in Figure 38, we incorporated additional elements into the ER
equation.

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Figure 38 Event Report Trigger Elements

CONCLUSION
The SEL-651R Recloser Control offers comprehensive protection at the PCC that includes the
voltage and frequency-tripping requirements established by the industry-recognized standard,
IEEE 1547. This application guide demonstrates how to take a default SEL-651R-2 settings file
and configure SELOGIC to apply IEEE 1547 setting guidelines in addition to common protection
and control used at the PCC.

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APPENDIX: SELOGIC EQUATIONS

Table 8 SELOGIC Equations (Sheet 1 of 2)

SELOGIC Equations

SELOGIC Variable and Timer SV03PU := 117.00

Settings SV03DO := 0.00
SV03 := 27ZA1 OR 27ZB1 OR 27ZC1 #Undervoltage Level 1 (Inverter-Based Source)
SV03 := (27ZA1 OR 27ZB1 OR 27ZC1) AND NOT LOP #Undervoltage Level 1
(Positive-Sequence Sources)

SV04PU := 6.50
SV04DO := 0.00
SV04 := 27ZA2 OR 27ZB2 OR 27ZC2 #Undervoltage Level 2 (Inverter-Based Source)
SV04 := (27ZA2 OR 27ZB2 OR 27ZC2) AND NOT LOP #Undervoltage Level 2
(Positive-Sequence Sources)

SV05PU := 117.00
SV05DO := 0.00
SV05 := 59ZA2 OR 59ZB2 OR 59ZC2 #Overvoltage Level 1

SV06PU := 6.50
SV06DO := 0.00
SV06 := 59ZA3 OR 59ZB3 OR 59ZC3 #Overvoltage Level 2

SV07PU := 30.00
SV07DO := 30.00
SV07 := (SV08 OR SV09) AND NOT SV07T #IMMINENT CLOSE OSCILLATOR

SV08PU := 3600.00
SV08DO := 0.00
SV08 := (PB11_PUL AND LT05 OR CC3 AND LT03) AND NOT TRIP3P OR SV08
AND NOT SV08T AND NOT TRIP3P AND NOT CLOSE3P # CLOSE PERMISSIVE
AND TIMER

SV09PU := 18000.00
SV09DO := 0.00
SV09 := 3P59Z AND NOT TRIP3P AND NOT CLOSE3P AND NOT 52A3P AND
LT06 AND LT10 #AUTOMATIC RESTORE CLOSE PERMISSIVE

SV10PU := 0.00
SV10DO := 10.00
SV10 := R_TRIG HBL2T
Latch Bits Set/Reset SET10 := PB10_PUL AND NOT LT10 AND LT05 #AUTO RESTORE ENABLED
SELOGIC Equations RST10 := PB10_PUL AND LT10 AND LT05 #AUTO RESTORE DISABLED

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Table 8 SELOGIC Equations (Sheet 2 of 2)

SELOGIC Equations
CL3P := (SV08 OR SV09T) AND (3P59Z AND 3P27Y OR 25A1) AND FREQOK
AND NOT 81D5 AND NOT 81D6 AND LT06 AND TCCAP # CLOSE FROM
PUSHBUTTON SUPERVISED BY LOCK. ALL CLOSING SUPERVISED BY HOT
Close Logic Equations LINE TAG (LT06) AND TRIP/CLOSE CAPACITOR (TCCAP)

ULCL3P := TRIP3P OR NOT (LT06 AND TCCAP OR CLOSE3P) OR NOT (LT05 OR

CLOSE3P OR CC3 OR 79CY3P OR SV08 OR SV09T)
TR3P := SV03T OR SV04T OR SV05T OR SV06T OR 81D1T OR 81D2T OR 81D3T
OR 81D4T OR 3PWR1 OR R_TRIG SV02T OR PB12_PUL OR OC3
TR3P := SV03T OR SV04T OR SV05T OR SV06T OR 81D1T OR 81D2T OR 81D3T
OR 81D4T OR 3PWR1 OR R_TRIG SV02T OR PB12_PUL OR OC3 OR RMB1A
Trip Logic Equations #Tripping Conditions Including DTT

TR3X := (51PT OR 51AT OR 51BT OR 51CT OR 51G1T OR 51G2T) AND NOT

(HBL2T AND SV10T)
T11_LED := 81D1T OR 81D2T OR 81D3T OR 81D4T # FREQUENCY

T12_LED := SV03T OR SV04T OR SV05T OR SV06T # VOLTAGE

T18_LED := 3PWR1 # REVERSE POWER

Target LED Settings
T22_LED := 59ZA1 # VAZ ON (UTILITY)

T23_LED := 59ZB1 # VBZ ON (UTILITY)

T24_LED := 59ZC1 # VCZ ON (UTILTY)

PB10_LED := LT10 #AUTO RESTORE ENABLED

Operator Control
PB11_LED := 52A3P # RECLOSER CLOSED
LED Settings

PB12_LED := NOT (52A3P) # RECLOSER OPEN

DP01 := SV08, “CLOSE TIME INITIATED”
Display Point Settings
DP02 := SV09, “RESTORE CL TIME INITIATED”
SER3 := PWR_SRC1,TOSLP,BTFAIL,DTFAIL,EN,SV08,LT10,3P59Z,
3P27Y,25A1,81D1T,81D2T,81D3T,81D4T,81D5,81D6
Sequential Events Recorder
Trigger Lists
SER4 := 51A,51AT,51B,51BT,51C,51CT,51G1,51G1T,51G2,51G2T,SV02T,
SV03T,SV04T,SV05T,SV06T,3PWR1,RMB1A,SV09,SV09T
ER := R_TRIG 51P OR R_TRIG 51G1 OR R_TRIG 51A OR R_TRIG 51B OR
Event Report Trigger R_TRIG 51C OR R_TRIG 51G2 OR R_TRIG 81D1 OR R_TRIG 81D2 OR
Elements R_TRIG 81D3 OR R_TRIG 81D4 OR R_TRIG SV03 OR R_TRIG SV04 OR
R_TRIG SV05 OR R_TRIG SV06

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REFERENCES
[1] K. Zimmerman and D. Costello, “Fundamentals and Improvements for Directional Relays,”
presented at the 37th Annual Western Protective Relay Conference, October 2010. Available:
selinc.com.

TECHNICAL SUPPORT
We appreciate your interest in SEL products and services. If you have questions or comments,
please contact us at:
Schweitzer Engineering Laboratories, Inc.
2350 NE Hopkins Court
Pullman, WA 99163-5603 U.S.A.
Tel: +1.509.338.3838
Fax: +1.509.332.7990
Internet: selinc.com/support
Email: [email protected]

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SEL Application Guide 2020-07 Date Code 20200327