EC 6601 - VLSI DESIGN

7UNIT I MOS TRANSISTOR PRINCIPLE

Syllabus:
NMOS and PMOS transistor, Process parameters for MOS and CMOS, Electrical
properties of CMOS circuits and Device modeling, Scaling principles and fundamental
limits, CMOS inverter scaling, propagation delays, Stick diagram, Layout diagrams.
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Introduction:
1. The objective of this course is to learn the design procedure to manufacture a chip (IC).
2. VLSI (Very Large Scale Integration) chip consists billions of MOS transistors.
3. The first unit deals with the basic principles (various characteristics) of MOS transistor and the
CMOS processing technologies.

❖ MOS Transistor Theory:

• The below figure shows some of the symbols that are commonly used for MOS transistors.
The three-terminal symbols in Figure (a) are used in the great majority of schematics. If the
body (substrate or well) connection needs to be shown, the four-terminal symbols in Figure (b)
will be used. Figure(c) shows an example of other symbols that may be encountered in the
literature.

• The MOS transistor is a majority-carrier device in which the current in a conducting channel
between the source and drain is controlled by a voltage applied to the gate. In an nMOS
transistor, the majority carriers are electrons; in a pMOS transistor, the majority carriers are
holes.
➢ Simple MOS structure
• The behavior of MOS transistors can be understood by first examining an
isolated MOS structure with a gate and body but no source or drain.
• The below figure shows a simple MOS structure.
• The top layer of the structure is a good conductor called the gate. (Early
transistors used metal gates. Transistor gates soon changed to use polysilicon)
• The middle layer is a very thin insulating film ofSiO2 called the gate oxide. The
bottom layer is the doped silicon body.
• The figure shows a p-type body in which the carriers are holes. The body is
grounded and a voltage is applied to the gate. The gate oxide is a good insulator.
So almost zero current flows from the gate to the body.
• In the below Figure (a), a negative voltage is applied to the gate, so there is
negative charge on the gate. The mobile positively charged holes are attracted to
the region beneath the gate. This is called the accumulation mode.

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• In Figure (b), a small positive voltage is applied to the gate, resulting in some
positive charge on the gate. The holes in the body are repelled from the region
directly beneath the gate, resulting in a depletion region forming below the
gate.
• In Figure (c), a higher positive potential exceeding a critical threshold voltage
Vt is applied, attracting more positive charge to the gate. The holes are repelled
further and some free electrons in the body are attracted to the region beneath
the gate. This conductive layer of electrons in the p-type body is called the
inversion layer.

Fig: Simple MOS structure

• The threshold voltage depends on the number of dopants in the body and the
thickness tox of the oxide. It is usually positive, as shown in this example, but
can be engineered to be negative.

❖ Three mode(Region) of Operation for nMOS Transistor:

• The below figure shows an nMOS transistor.
• The transistor consists of the MOS stack between two n-type regions called the
source and drain.

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Cutoff Mode (Region):

• In the above figure, the gate-to-source voltage Vgs is less than the threshold
voltage. The source and drain have free electrons.
• The body has free holes but no free electrons. Suppose the source is grounded.
• The junctions between the body and the source or drain are zero-biased or
reverse-biased, so little or no current flows. It means the transistor is OFF, and
this mode of operation is called cutoff.

Linear Mode (Region):

• In the below figure, the gate voltage is greater than the threshold voltage. Now
an inversion region of electrons (majority carriers) called the channel connects
the source and drain, creating a conductive path and turning the transistor ON.

• The number of carriers and the conductivity increases with the gate voltage.
• The potential difference between drain and source is Vds = Vgs - Vgd.
• If Vds = 0 (i.e., Vgs = Vgd),there is no electric field tending to push current from
drain to source. When a small positive potential Vds is applied to the drain,
current Ids flows through the channel from drain to source.
• This mode of operation is termed linear, resistive, triode, non-saturated, or
unsaturated; the current increases with both the drain voltage and gate voltage.

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Saturation Mode (Region):

• If Vds becomes sufficiently large that Vgd < Vt, the channel is no longer inverted
near the drain and becomes pinched off (Figure below).

• However, conduction is still brought about by the drift of electrons under the
influence of the positive drain voltage.
• As electrons reach the end of the channel, they are injected into the depletion
region near the drain and accelerated toward the drain.
• Above this drain voltage the current Ids is controlled only by the gate voltage
and ceases to be influenced by the drain. This mode is called saturation.

Summary: The nMOS transistor has three modes of operation.

1. IfVgs<Vt, the transistor is cut-off (OFF).
2. If Vgs>Vt and Vdsissmall(0<Vds<(Vgs-Vt)), the transistor acts as a linear resistor in which
the current flow is proportionalto Vds.
3. If Vgs>VtandVdsislarge(Vds> (Vgs-Vt)), the transistor acts as a current sourcein which the
current flow becomes independent of Vds.
❖ Ideal I-V Characteristics

MOS transistors have three regions of operation:

• Cutoff or subthreshold region

• Linear region
• Saturation region

Let us derive a model relating the current and voltage (I-V) for an nMOS transistor in each of these
regions. The model assumes that the channel length is long enough that the lateral electric field (the
field between source and drain) is relatively low, which is no longer the case in nanometer devices.
This model is variously known as the long-channel, ideal, first-order, or Shockley model.

Cutoff or Subthreshold region:

• The long-channel model assumes that the current through an OFF transistor is 0.

Linear region:

• When a transistor turns ON (Vgs > Vt), the gate attracts carriers (electrons) to form a
channel.

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• The electrons drift from source to drain at a rate proportional to the electric field
between these regions. Thus, we can compute currents if we know the amount of
charge in the channel and the rate at which it moves.
We know that the charge on each plate of a capacitor is
Q = CV.
Thus, the charge in the channel
𝑄𝑐ℎ𝑎𝑛𝑛𝑒𝑙 =𝐶𝑔 (𝑉𝑔𝑐 − 𝑉𝑡 ) ------ (1)
Where,
Cg is the capacitance of the gate to the channel
𝑉𝑔𝑐 − 𝑉𝑡 is the amount of voltage attracting charge to the channel beyond
the minimum required to invert from p to n.
• The gate voltage is referenced to the channel, which is not grounded. If the source is at
𝑉𝑔 and the drain is at 𝑉𝑔 , the average is
𝑉𝑐 = (𝑉𝑠 + 𝑉𝑑 )/2 = 𝑉𝑠 + 𝑉𝑑𝑠 /2
Therefore, the mean difference between the gate and channel potentials 𝑉𝑔𝑐 is 𝑉𝑔 − 𝑉𝑐 =
𝑉𝑔𝑠 − 𝑉𝑑𝑠 /2 as shown in the below figure.

We can model the gate as a parallel plate capacitor with capacitance proportional to
area over thickness. If the gate has length L and width W and the oxide thickness is 𝑡𝑜𝑥 ,
as shown in the figure, the capacitance is
𝑊𝐿 𝑊𝐿
𝐶𝑔 = 𝑘𝑜𝑥 𝜀𝑜 𝑡 =𝜀𝑜𝑥 𝑡 = 𝐶𝑜𝑥 𝑊𝐿 ----- (2)
𝑜𝑥 𝑜𝑥

Where,
𝜀𝑜 is the permittivity of free space, 8.85 × 10–14 F/cm, and the permittivity of
SiO2 is 𝑘𝑜𝑥 = 3.9 times as great. Often, the 𝜀𝑜𝑥 /𝑡𝑜𝑥 term is called 𝐶𝑜𝑥 , the capacitance
per unit area of the gate oxide.

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• In these processes, we call 𝑡𝑜𝑥 the equivalent oxide thickness (EOT), the
thickness of a layer of SiO2 that has the same 𝐶𝑜𝑥 .
• In this case, 𝑡𝑜𝑥 is thinner than the actual dielectric.
• Each carrier in the channel is accelerated to an average velocity, v, proportional
to the lateral electric field, i.e., the field between source and drain. The constant
of proportionality R is called the mobility.
𝒗 = 𝜇E ----- (3)
• The electric field (E) is the voltage difference between drain and source
𝑉𝑑𝑠
(Vds),divided by the channel length, L⇒E = ----(4)
𝐿
𝑄𝑐ℎ𝑎𝑛𝑛𝑒𝑙
Ids = 𝐿⁄
𝑣
Vgs − Vt − 𝑉𝑑𝑠
𝑊𝐿
= 𝐶𝑜𝑥 ( ⁄ ) 𝑉𝑑𝑠
𝐿 2
V − 𝑉𝑑𝑠⁄
= 𝛽 ( GT 2) 𝑉𝑑𝑠 ----- (5)
𝑊
Where, 𝛽 = 𝜇𝐶𝑜𝑥 𝐿 ; 𝑉𝐺𝑇 = 𝑉𝑔𝑠 − 𝑉𝑡 ---- (6)

• The term 𝑉𝑔𝑠 – 𝑉𝑡 arises so often that it is convenient to abbreviate it as 𝑉𝐺𝑇 EQ

(5) describes the linear region of operation, for Vgs >Vt, but Vds relatively small.
• It is called linear or resistive because when Vds << 𝑉𝐺𝑇 , 𝐼𝑑𝑠 increases almost
linearly with Vds, just like an ideal resistor. Ids increases almost linearly with
Vds just like an ideal resistor.
Saturation Region:
• If Vds>Vdsat ≡ 𝑉𝐺𝑇 , wesay it is pinched off. Beyond this point, called the drain
saturation voltage, increasing the drain voltage has no further effect on current.
• Substituting Vds = Vdsat , at this point of maximum current into EQ (5), we find
an expression for the saturation current that is in dependent of Vds.
𝛽
Ids = 2 VGT 2 ….(7)
• This expression is valid for Vgs>Vt and Vds>Vdsat. Thus, long-channel MOS
transistors are said to exhibit square-law behavior in saturation.
• 𝐼𝑜𝑛 (also called Idsat) is the ON current, Ids, when Vgs = Vds = VDD. 𝐼𝑜𝑓𝑓 is the
OFF current when Vgs = 0 and Vds = VDD. According to the long-channel model,
𝐼𝑜𝑓𝑓 = 0 and
𝛽
𝐼𝑜𝑛 = 2 (𝑉𝐷𝐷 − 𝑉𝑡 )-----(8)

EQ (9) summarizes the current in the three regions:

0 Vgs < 𝑉t Cut − off
V − Vt − Vds
Ids = 𝛽 ( gs ⁄ ) Vds
2 Vds < Vdsat Linear …..(9)
𝛽
{ (Vgs − Vt )2 Vds > Vdsat Saturation }
2

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Figure: IV characteristics of (a) Nmos and (b) pMOS

❖ C-V Characteristics (or) Dynamic Behaviour of MOSFET

• Each terminal of an MOS transistor has capacitance to the other terminals.
• In general, these capacitances are nonlinear and voltage dependent (C-V); however,
they can be approximated as simple capacitors when their behavior is averaged across
the switching voltages of a logic gate.

➢ Simple MOS Capacitance Models

• The gate of an MOS transistor is a good capacitor.
• Indeed, its capacitance is necessary to attract charge to invert the channel, so high gate
capacitance is required to obtain high 𝐼𝑑𝑠 .
• The gate capacitor can be viewed as a parallel plate capacitor with the gate on top and
channel on bottom with the thin oxide dielectric between. Therefore, the capacitance is
𝐶𝑔 = 𝐶𝑜𝑥 WL ------ (1)
• The bottom plate of the capacitor is the channel, which is not one of the transistor’s
terminals.
• When the transistor is on, the channel extends from the source (and reaches the drain if
the transistor is unsaturated, or stops short in saturation).
• Thus, we often approximate the gate capacitance as terminating at the source and call
the capacitance 𝐶𝑔𝑠 . Most transistors used in logic are of minimum manufacturable
length because this results in greatest speed and lowest dynamic power consumption.
• Thus, taking this minimum L as a constant for a particular process, we can define
𝐶𝑔 = 𝐶𝑝𝑒𝑟𝑚𝑖𝑐𝑟𝑜𝑛 * W------(2)
Where,
𝜀
𝐶𝑝𝑒𝑟𝑚𝑖𝑐𝑟𝑜𝑛 = 𝐶𝑜𝑥 L = 𝑡𝑜𝑥------(3)
𝑜𝑥

• In addition to the gate, the source and drain also have capacitances. These
capacitances are not fundamental to operation of the devices, but do impact circuit
performance and hence are called parasitic capacitors.
• The source and drain capacitances arise from the p–n junctions between the source or
drain diffusion and the body and hence are also called diffusion capacitance 𝐶𝑠𝑏 and
𝐶𝑑𝑏 .

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• A depletion region with no free carriers forms along the junction. The depletion region
acts as an insulator between the conducting p- and n-type regions, creating capacitance
across the junction.
• The capacitance of these junctions depends on the area and perimeter of the source and
drain diffusion, the depth of the diffusion, the doping levels, and the voltage.
• As diffusion has both high capacitance and high resistance, it is generally made as
small as possible in the layout.
• Three types of diffusion regions are frequently seen, illustrated by the two series
transistors in Figure below.

Figure: Diffusion region geometries

• In Figure (a), each source and drain has its own isolated region of contacted diffusion.
• In Figure (b), the drain of the bottom transistor and source of the top transistor form a
shared contacted diffusion region.
• In Figure (c), the source and drain are merged into an uncontacted region.

➢ Detailed MOS Gate Capacitance Model

• The MOS gate sits above the channel and may partially overlap the source and drain
diffusion areas.
• Therefore, the gate capacitance has two components: the intrinsic capacitance
𝐶𝑔𝑐 (over the channel) and the overlap capacitances 𝐶𝑔𝑜𝑙 (to the source and drain).
• The intrinsic capacitance was approximated as a simple parallel plate in EQ (1) with
capacitance 𝐶𝑜 = WL𝐶𝑜𝑥 .
• However, the bottom plate of the capacitor depends on the mode of operation of the
transistor.
• The intrinsic capacitance has three components representing the different terminals
connected to the bottom plate: 𝐶𝑔𝑏 (gate-to-body), 𝐶𝑔𝑏 (gate-to-source), and 𝐶𝑔𝑑 (gate-
to-drain).
✓ Cutoff
• When the transistor is OFF (Vgs < Vt), the channel is not inverted and charge
on the gate is matched with opposite charge from the body.
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• This is called Cgb, the gate-to-body capacitance.

• For negative Vgs, the transistor is in accumulation and Cgb = Co
• As Vgs increases but remains below a threshold, a depletion region forms at the
surface. This effectively moves the bottom plate downward from the oxide,
reducing the capacitance.
✓ Linear
• When Vgs > Vt, the channel inverts and again serves as a good conductive
bottom plate. However, the channel is connected to the source and drain, rather
than the body, so Cgb drops to 0.
• At low values of Vds, the channel charge is roughly shared between source and
drain, so Cgs = Cgd = Co /2.
• As Vds increases, the region near the drain becomes less inverted, so a greater
fraction of the capacitance is attributed to the source and a smaller fraction to
the drain.
✓ Saturation
• At Vds > VDSat, the transistor saturates and the channel pinches off.
• At this point, all the intrinsic capacitance is to the source. Because of pinchoff,
the capacitance in saturation reduces to Cgs = 2/3 C0 for an ideal transistor.
• The behavior in these three regions can be approximated as shown in the below
table

• The gate overlaps the source and drain in a real device and also has fringing
fields terminating on the source and drain.

✓ This leads to additional overlap capacitances, as shown in the above figure.

These capacitances are proportional to the width of the transistor.
✓ Typical values are 𝐶𝑔𝑠𝑜𝑙 = 𝐶𝑔𝑑𝑜𝑙 = 0.2 – 0.4 fF/Rm. They should be added to
the intrinsic gate capacitance to find the total.
𝐶𝑔𝑠𝑜𝑙(𝑜𝑣𝑒𝑟𝑙𝑎𝑝) =𝐶𝑔𝑠𝑜𝑙 𝑊
𝐶𝑔𝑑𝑜𝑙(𝑜𝑣𝑒𝑟𝑙𝑎𝑝) =𝐶𝑔𝑑𝑜𝑙 𝑊

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➢ Detailed MOS Diffusion Capacitance Model

• The p–n junction between the source diffusion and the body contributes
parasitic capacitance across the depletion region.
• The capacitance depends on both the area AS and sidewall perimeter PS of the
source diffusion region. The geometry is illustrated in the below figure.

• The area is AS = WD. The perimeter is PS = 2W + 2D. Of this perimeter, W

abuts the channel and the remaining W + 2D does not.
• The total source parasitic capacitance is
𝐶𝑠𝑏 = 𝐴𝑆 ∗ 𝐶𝑗𝑏𝑠 + 𝑃𝑆 ∗ 𝐶𝑗𝑏𝑠𝑠𝑤
Where,
𝐶𝑗𝑏𝑠 - capacitance of the junction between the body and the bottom of
the source, has units of capacitance/area
𝐶𝑗𝑏𝑠𝑠𝑤 - capacitance of the junction between the body and the side walls
of the source, has units of capacitance/length.
• Because the depletion region thickness depends on the bias conditions, these
parasitics are nonlinear. The area junction capacitance term is
𝑉𝑠𝑏 −𝑀
𝐶𝑗𝑏𝑠 =𝐶𝑗 (1+ ) 𝐽
𝜑𝑜

Where,
𝐶𝑗 is the junction capacitance at zero bias and is highly process-
dependent
𝑀𝐽 is the junction grading coefficient, typically in the range of 0.5 to
0.33 depending on the abruptness of the diffusion junction.
𝜑𝑜 is the built-in potential that depends on doping levels.
𝑁𝐴 𝑁𝐷
𝜑𝑜 = 𝑣𝑇 ln 𝑛𝑖 2

Where
𝑣𝑇 is the thermal voltage from thermodynamics, not to be confused with
the threshold voltage 𝑉𝑡 .
It has a value equal to kT/q (26 mV at room temperature), where k = 1.380 ×
10–23 J/K is Boltzmann’s constant, T is absolute temperature (300 K at room
temperature), and q = 1.602 × 10–19 C is the charge of an electron.
NA and ND are the doping levels of the body and source diffusion
region.
𝑛𝑖 is the intrinsic carrier concentration in undoped silicon and has a
value of 1.45 × 1010 cm–3 at 300 K.
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• The sidewall capacitance term is of a similar form but uses different

coefficients.
𝑉
𝐶𝑗𝑏𝑠𝑠𝑤 =𝐶𝐽𝑆𝑊 (1+ 𝜑 𝑠𝑏 )−𝑀𝐽𝑆𝑊
𝑆𝑊

In summary, an MOS transistor can be viewed as a four-terminal device with capacitances between
each terminal pair, as shown in the below figure.

The gate capacitance includes an intrinsic component (to the body, source and drain, or source alone,
depending on operating regime) and overlap terms with the source and drain. The source and drain
have parasitic diffusion capacitance to the body.

❖ Nonideal I-V Effects

• The long-channel I-V model of EQ (9) neglects many effects that are important to devices
with channel lengths below 1 micron.
• The saturation current increases less than quadratically with increasing 𝑉𝑔𝑠 . This is caused
by two effects: velocity saturation and mobility degradation.
• At high lateral field strengths (𝑉𝑑𝑠 /L), carrier velocity ceases to increase linearly with field
strength. This is called velocity saturation and results in lower Ids than expected at high
Vds.
• At high vertical field strengths (Vgs /tox ), the carriers scatter off the oxide interface more
often, slowing their progess. This mobility degradation effect also leads to less current than
expected at high 𝑉𝑔𝑠
• The saturation current of the nonideal transistor increases somewhat with 𝑉𝑑𝑠 . This is caused
by channel length modulation, in which higher 𝑉𝑑𝑠 increases the size of the depletion region
around the drain and thus effectively shortens the channel.
➢ Velocity Saturation
• The behaviour of transistors with very short channel lengths (called shortchannel
devices) deviates considerably from the resistive and saturated models, in channel
length modulation.
• The main culprit for this deficiency is the velocity saturation effect.
𝑑𝑉
𝑣𝑛 = -𝜇𝑛 𝜀(𝑥)= 𝜇𝑛 𝑑𝑥
• Above equation states that the velocity of the carriers is proportional to the electrical
field, independent of the value of that field. In other words, the carrier mobility is a
constant.

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• However, at high field strengths, the carriers fail to follow this linear model. In fact,
when the electrical field along the channel reaches a critical value𝜀𝑐 , the velocity of
the carriers tends to saturatedue to scattering effects (collisions suffered by the
carriers). This is illustrated in the below Figure

• This effect has a profound impact on the operation of the transistor. We will illustrate
this with a first-order derivation of the device characteristics under velocity-saturating
conditions. The velocity as a function of the electrical field, plotted in the above
Figure, can be roughly approximated by the following expression:

------- (1)
• The continuity requirement between the two regions dictates that

--------(2)
• Using a derivation similar to that of Ideal iv characteristics, with the new carrier
velocity expression in EQ (1) gives modified equations for linear and saturation
currents

(3)

➢ Mobility Degradation:
𝑉𝑔𝑠
• Strong vertical electric field (𝐸𝑣𝑒𝑟 = 𝑡 ) resulting from large 𝑉𝑔𝑠 causes the carriers
𝑜𝑥
to scatter against the surface and also reduces the carrier mobility. This is modeled by
replacing µ with µ𝑒𝑓𝑓
• Mobility degradation leads to less current than expected at high 𝑉𝑔𝑠
➢ Channel Length Modulation
• Ideally, 𝐼𝑑𝑠 is independent of 𝑉𝑑𝑠 for a transistor in saturation, making the transistor a
perfect current source.

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• The p–n junction between the drain and body forms a depletion region with a width
𝐿𝑑 that increases with 𝑉𝑑𝑏 , as shown in the below figure

• The depletion region effectively shortens the channel length to

𝐿𝑒𝑓𝑓 = L- 𝐿𝑑 (4)
• To avoid introducing the body voltage into our calculations, assume the source
voltage is close to the body voltage so 𝑉𝑑𝑏 =𝑉𝑑𝑠 .
• Hence, increasing Vds decreases the effective channel length. Shorter channel length
results in higher current; thus, Ids increases with 𝑉𝑑𝑠 in saturation, as shown in the
above figure.
• This can be crudely modeled by multiplying EQ (9) in ideal iv characteristics by a
factor of (1 + 𝑉𝑑𝑠 / 𝑉𝐴 ), where 𝑉𝐴 is called the Early voltage.
• In the saturation region,

(5)

• As channel length gets shorter, the effect of the channel length modulation becomes
relatively more important.
• Hence, VA is proportional to channel length. This channel length modulation model
is a gross oversimplification of nonlinear behavior and is more useful for conceptual
understanding than for accurate device modeling.
• Channel length modulation is very important to analog designers because it reduces
the gain of amplifiers.

➢ The Threshold Voltage

• Consider the case where 𝑉𝐺𝑆 = 0 and drain, source, and bulk are connected to
ground.
• The drain and source are connected by back-to-back pn-junctions (substrate-source
and substrate-drain). Under the mentioned conditions, both junctions have a 0 V bias
and can be considered off, which results in an extremely high resistance between
drain and source.
• Assume now that a positive voltage is applied to the gate (with respect to the
source).
• The gate and substrate form the plates of a capacitor with the gate oxide as the
dielectric.
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• The positive gate voltage causes positive charge to accumulate on the gate electrode
and negative charge on the substrate side.
• The latter manifests itself initially by repelling mobile holes. Hence, a depletion
region is formed below the gate.
• This depletion region is similar to the one occurring in a pn-junction diode.
Consequently, similar expressions hold for the width and the space charge per unit
area.

(6)

With NA the substrate doping and f the voltage across the depletion layer (i.e., the
potential at the oxide-silicon boundary).
• As the gate voltage increases, the potential at the silicon surface at some point
reaches a critical value, where the semiconductor surface inverts to n-type material.
• This point marks the onset of a phenomenon known as strong inversion and occurs
at a voltage equal to twice the Fermi Potential (Eq. (7))

(7)

Further increases in the gate voltage produce no further changes in the depletion
layer width, but result in additional electrons in the thin inversion layer directly
under the oxide. These are drawn into the inversion layer from the heavily doped n+
source region.
• Hence, a continuous n-type channel is formed between the source and drain regions,
the conductivity of which is modulated by the gate-source voltage.
• In the presence of an inversion layer, the charge stored in the depletion region is
fixed and equals

(8)

• This picture changes somewhat in case a substrate bias voltage 𝑉𝑆𝐵 is applied (𝑉𝑆𝐵 is
normally positive for n-channel devices).
• This causes the surface potential required for strong inversion to increase and to
become |–2ϕ𝐹 + VSB|. The charge stored in the depletion region now is expressed by
(9)

• The value of 𝑉𝐺𝑆 where strong inversion occurs is called the threshold voltage 𝑉𝑇 .
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• 𝑉𝑇 is a function of several components, most of which are material constants such as

the difference in work-function between gate and substrate material, the oxide
thickness, the Fermi voltage, the charge of impurities trapped at the surface between
channel and gate oxide, and the dosage of ions implanted for threshold adjustment.
• From the above arguments, it has become clear that the source-bulk voltage 𝑉𝑆𝐵 has
an impact on the threshold as well.
• Rather than relying on a complex (and hardly accurate) analytical expression for the
threshold, we rely on an empirical parameter called 𝑉𝑇0, which is the threshold
voltagefor 𝑉𝑆𝐵 = 0, and is mostly a function of the manufacturing process.
• The threshold voltage under different body-biasing conditions can then be
determined in the following manner:
(10)

• The parameter g (gamma) is called the body-effect coefficient, and expresses the
impact of changes in VSB.
• Observe that the threshold voltage has a positive value for a typical NMOS device,
while it is negative for a normal PMOS transistor.
➢ Body Effect
• Until now, we have considered a transistor to be a three-terminal device with gate,
source, and drain. However, the body is an implicit fourth terminal.
• When a voltage Vsb is applied between the source and body, it increases the amount
of charge required to invert the channel, hence, it increases the threshold voltage.
• The threshold voltage can be modeled as

(11)

Where,
𝑉𝑡0 is the threshold voltage when the source is at the body potential, ϕ𝑠 is the
surface potential at threshold and γis the body effect coefficient.

➢ Drain-Induced Barrier Lowering

• The drain voltage 𝑉𝑑𝑠 creates an electric field that affects the threshold voltage.
(12)
• This drain-induced barrier lowering (DIBL) effect is especially pronounced in
short-channel transistors. It can be modeled as

(13)
Where,
𝜂is the DIBL coefficient, typically on the order of 0.1
• Drain-induced barrier lowering causes Ids to increase with 𝑉𝑑𝑠 in saturation, in much
the same way as channel length modulation does.
• More significantly, DIBL increases subthreshold leakage at high 𝑉𝑑𝑠

➢ Subthreshold Conduction

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 EC 6601 - VLSI DESIGN

• The long-channel transistor I-V model assumes current only flows from source to
drain when 𝑉𝑔𝑠 >𝑉𝑡 .
• In real transistors, current does not abruptly cut off below threshold, but rather drops
off exponentially, as seen in Figure.

• When the gate voltage is high, the transistor is strongly ON. When the gate falls
below 𝑉𝑡 , the exponential decline in current appears as a straight line on the
logarithmic scale.
• This regime of 𝑉𝑔𝑠 <𝑉𝑡 is called weak inversion.
• The subthreshold leakage current increases significantly with 𝑉𝑑𝑠 because of drain-
induced barrier lowering.
• The current in this region can be approximated by the expression
(14)

➢ Gate Leakage
• For gate oxides thinner than 15–20 A, there is a nonzero probability that an electron
in the gate will find itself on the wrong side of the oxide, where it will get whisked
away through the channel.
• This effect of carriers crossing a thin barrier is called tunneling, and results in
leakage current through the gate.
➢ Junction Leakage
• The p–n junctions between diffusion and the substrate or well form diodes, as shown
in Figure.

• The well-to-substrate junction is another diode. The substrate and well are tied to
GND or VDD to ensure these diodes do not become forward biased in normal
operation.
• However, reverse-biased diodes still conduct a small amount of current 𝐼𝐷

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 EC 6601 - VLSI DESIGN

(15)

Where,
𝐼𝑆 depends on doping levels and on the area and perimeter of the
diffusion regionand
𝑉𝐷 is the diode voltage

➢ Temperature Dependence
• Transistor characteristics are influenced by temperature. Carrier mobility decreases
with temperature. An approximate relation is

(16)

Where,
T is the absolute temperature,
𝑇𝑟 is room temperature, and
𝑘𝜇 is a fitting parameter with a typical value of about 1.5.

• 𝑉𝑠𝑎𝑡 also decreases with temperature, dropping by about20% from 300 to 400 K.
• The magnitude of the threshold voltage decreases nearly linearly with temperature
and may be approximated by
(17)

Where,
𝑘𝑣𝑡 is typically about 1–2 mV/K.
𝐼𝑜𝑛 at high 𝑉𝐷𝐷 decreases with temperature.

➢ Geometry Dependence
• The layout designer draws transistors with width and length 𝑊𝑑𝑟𝑎𝑤𝑛 and 𝐿𝑑𝑟𝑎𝑤𝑛 .
• The actual gate dimensions may differ by some factors 𝑋𝑊 and 𝑋𝐿 .
• For example, the manufacturer may create masks with narrower polysilicon or may
over etch the polysilicon to provide shorter channels (negative XL) without changing
the overall design rules or metal pitch.
• Moreover, the source and drain tend to diffuse laterally under the gate by 𝐿𝐷 ,
producing a shorter effective channel length that the carriers must traverse between
source and drain.
• Similarly, WD accounts for other effects that shrink the transistor width. Putting
these factors together, we can compute effective transistor lengths and widths that
should be used in place of L and W in the current and capacitance equations.
• The factors of two come from lateral diffusion on both sides of the channel.

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 EC 6601 - VLSI DESIGN

(18)

•Therefore, a transistor drawn twice as long may have an effective length that is more
than twice as great.
• Threshold voltages also vary with transistor dimensions because of the short and
narrow channel effects.
➢ Hot-Carrier Effects
• Threshold voltages in short-channel devices also have the tendency to drift over
time. This is the result of the hot-carrier effect.
• Over the last decades, device dimensions have been scaled down continuously, while
the power supply and the operating voltages were kept constant.
• The resulting increase in the electrical field strength causes an increasing velocity of
the electrons, which can leave the silicon and tunnel into the gate oxide upon
reaching a high-enough energy level.
• Electrons trapped in the oxide change the threshold voltage, typically increasing the
thresholds of NMOS devices, while decreasing the VT of PMOS transistors.
• For an electron to become hot, an electrical field of at least 104 V/cm is necessary.
This condition is easily met in devices with channel lengths around or below 1 mm.
• The hot-electron phenomenon can lead to along-term reliability problem, where a
circuit might degrade or fail after being in use for awhile.

❖ DC Transfer Characteristics
• The DC transfer characteristics of a circuit relate the output voltage to the input
voltage, assuming the input changes slowly enough that capacitances have plenty of
time to charge or discharge.
• Specific ranges of input and output voltages are defined as valid 0 and 1 logic levels.
➢ Static CMOS Inverter DC Characteristics
• Let us derive the DC transfer function (𝑉𝑜𝑢𝑡 vs. 𝑉𝑖𝑛 ) for the static CMOS inverter
shown in Figure

• Table shown below outlines various regions of operation for the n- and p-transistors.

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 EC 6601 - VLSI DESIGN

• In this table, 𝑉𝑡𝑛 is the threshold voltage of the n-channel device, and 𝑉𝑡𝑝 is the
threshold voltage of the p-channel device. Note that 𝑉𝑡𝑝 is negative.
• The equations are given both in terms of 𝑉𝑔𝑠 /𝑉𝑑𝑠 and 𝑉𝑖𝑛 /𝑉𝑜𝑢𝑡 .
• As the source of the nMOS transistor is grounded, 𝑉𝑔𝑠𝑛 = 𝑉𝑖𝑛 and 𝑉𝑑𝑠𝑛 = 𝑉𝑜𝑢𝑡 .
• As the source of the pMOS transistor is tied to 𝑉𝐷𝐷 , 𝑉𝑔𝑠𝑝 = 𝑉𝑖𝑛 – 𝑉𝐷𝐷 and 𝑉𝑑𝑠𝑝 = 𝑉𝑜𝑢𝑡
– 𝑉𝐷𝐷 .

• The objective is to find the variation in output voltage (Vout) as a function of the
input voltage (Vin).
• Given Vin, we must find Vout subject to the constraint that Idsn=|Idsp|. For
simplicity, we assume Vtp= –Vtnand that the pMOS transistor is 2–3 timesas wide as
the nMOS transistor so 𝛽𝑛 = 𝛽𝑝 .

The plot shows Idsn and Idsp in terms of Vdsn and Vdsp for various values of Vgsn and Vgsp.

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Above figure shows the same plot of Idsn and |Idsp| now in terms of Vout for various values of Vin.
The possible operating points of the inverter, marked with dots, are the values of Vout where Idsn=
|Idsp| for a given value of Vin.
The supply current IDD= Idsn= |Idsp| is also plotted against Vin in the below Figure showing that both
transistors are momentarily ON as Vin passes through voltages between GND and VDD, resulting in a
pulse of current drawn from the power supply.

• The operation of the CMOS inverter can be divided into five regions indicated in the below
figure. The state of each transistor in each region is shown in Table.
o In region A, the nMOS transistor is OFF so the pMOS transistor pulls the output
to VDD.
o In region B, the nMOS transistor starts to turn ON, pulling the output down.
o In region C, both transistors are in saturation.
o In region D, the pMOS transistor is partially ON
o In region E, the pMOS transistor is completely OFF, leaving the nMOS
transistor to pull the output down to GND

➢ Beta Ratio Effects

• We have seen that for 𝛽𝑛 = 𝛽𝑝 the inverter threshold voltage Vinv is VDD/2.
• This may be desirable because it maximizes noise margins and allows a capacitive load to
charge and discharge in equal times by providing equal current source and sink capabilities.
• Inverters with different beta ratios r =𝛽𝑝 /𝛽𝑛 are calledskewed inverters.

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 EC 6601 - VLSI DESIGN

• If r >1, the inverter is HI-skewed. If r <1,the inverter is LO-skewed. If r = 1, the inverter has
normal skew or is unskewed.
• A HI-skew inverter has a stronger pMOS transistor. Therefore, if the input is VDD /2, we
would expect the output will be greater than VDD /2.
• In other words, the input threshold must be higher than for an unskewed inverter. Similarly, a
LO-skew inverter has a weaker pMOS transistor and thus a lower switching threshold.
• Figure shown below explores the impact of skewing the beta ratio on the DC transfer
characteristics.

• As the beta ratio is changed, the switching threshold moves. However, the output voltage
transition remains sharp.
• Gates are usually skewed by adjusting the widths of transistors while maintaining minimum
length for speed.
➢ Noise Margin
• Noise margin is closely related to the DC voltage characteristics.
• This parameter allows you to determine the allowable noise voltage on the input of a gate so
that the output will not be corrupted.
• The specification most commonly used to describe noise margin (or noise immunity) uses two
parameters: the LOW noise margin, NML, and the HIGH noise margin, NMH.
• NML is defined as the difference in maximum LOW input voltage recognized by the receiving
gate and the maximum LOW output voltage produced by the driving gate.

• The value of NMH is the difference between the minimum HIGH output voltage ofthe driving
gate and the minimum HIGH input voltage recognized by the receiving gate.

Where,
VIH = minimum HIGH input voltage
VIL = maximum LOW input voltage
VOH= minimum HIGH output voltage
VOL = maximum LOW output voltage

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 EC 6601 - VLSI DESIGN

• Inputs between VIL and VIH are said to be in the indeterminate region or forbidden zoneand
do not represent legal digital logic levels.
• Therefore, it is generally desirable to have VIH as close as possible to VIL and for this value
to be midway in the “logic swing,” VOL to VOH.
• This implies that the transfer characteristic should switch abruptly; that is, there should be
high gain in the transition region. For the purpose of calculating noise margins, the transfer
characteristic of the inverter and the definition of voltage levels VIL, VOL, VIH, and VOH are
shown in Figure below.

• Logic levels are defined at the unity gain point where the slope is –1. This gives a conservative
bound on the worst case static noise margin.
• Note that the output is slightly degraded when the input is at its worst legal value; this is called
noise feedthrough or propagated noise.
• If either NML or NMH for a gate are too small, the gate may be disturbed by noise that occurs
on the inputs.
• An unskewed gate has equal noise margins, which maximizes immunity to arbitrary noise
sources.
• If a gate sees more noise in the high or low input state, the gate can be skewed to improve that
noise margin at the expense of the other.
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 EC 6601 - VLSI DESIGN

• Note that if |Vtp| = Vtn, then NMH and NML increase asthreshold voltages are increased.

❖ CMOS FABRICATION PROCESS

The CMOS can be fabricated using different processes such as:
❑ N-well process for CMOS fabrication
❑ P-well process
❑ Twin tub-CMOS-fabrication process
❑ Silicon on Insulator

• CMOS can be obtained by integrating both the NMOS and PMOS transistors on the same
chip substrate.
• For integrating these NMOS and PMOS devices on the same chip, special regions called as
wells or tubs are required in which semiconductor type and substrate type are opposite to
each other.
• A P-well has to be created on a N-substrate or N-well has to be created on a P-substrate.

➢ N-well process
Step1:Substrate
Primarily, the process starts with a P-substrate.

Step2: Oxidation
The wafer is first oxidized in a high-temperature (typically 900–1200 °C) furnace that
causes Si and O2 to react and become SiO2 on the wafer surface.

Step3: Photoresist
The oxide must be patterned to define the n-well.
An organic photoresist that softens where exposed to light is spun onto the wafer.

Step4: Masking
The photoresist is exposed through the n-well mask that allows light to pass through
only where the well should be.

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 EC 6601 - VLSI DESIGN

Step5: Photoresist removal

A part of the photoresist layer is removed by treating the wafer with the basic or acidic
solution.

Step6: Removal of SiO2 using acid etching

The oxide is etched with hydrofluoric acid (HF) where it is not protected by the
photoresist.

Step7: Removal of photoresist

Then the remaining photoresist is stripped away using a mixture of acids called piranha
etch.

Step8: Formation of the N-well

The well is formed where the substrate is not covered with oxide. Two ways to add
dopants are diffusion and ion implantation.
In the diffusion process, the wafer is placed in a furnace with a gas containing the
dopants. When heated, dopant atoms diffuse into the substrate. The well is wider than the hole
in the oxide on account of lateral diffusion.
With ion implantation, dopant ions are accelerated through an electric field and blasted
into the substrate.
In either method, the oxide layer prevents dopant atoms from entering the substrate
where no well is intended.

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 EC 6601 - VLSI DESIGN

Step9: Removal of SiO2

Finally, the remaining oxide is stripped with hydrofluoric acid.

Step10: Deposition of polysilicon

The transistor gates are formed next.
The thin oxide is grown in a furnace. Then the wafer is placed in a reactor with silane
gas (SiH4) and heated again to grow the polysilicon layer through a process called chemical
vapor deposition.
The polysilicon is heavily doped to form a reasonably good conductor.

Step11: Removing the layer barring a small area for the Gates
Except the two small regions required for forming the Gates of NMOS and PMOS, the
remaining layer is stripped off.

Step12: Oxidation process

Next, an oxidation layer is formed on this layer with two small regions for the
formation of the gate terminals of NMOS and PMOS.

Step13: Masking and N-diffusion

By using the masking process small gaps are made for the purpose of N-diffusion.

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 EC 6601 - VLSI DESIGN

The n-type (n+) dopants are diffused or ion implanted, and the three n+ are formed for the
formation of the terminals of NMOS.

Notice that the polysilicon gate over the nMOS transistor blocks the diffusion so the source
and drain are separated by a channel under the gate.
This is called a self-aligned process because the source and drain of the transistor are
automatically formed adjacent to the gate without the need to precisely align the masks
Step14: Oxide stripping
Finally, the protective oxide is stripped.

Step15: P-diffusion
Similar to the above N-diffusion process, the process is repeated for the p-diffusion
mask.

Step16: Thick field oxide

A thick-field oxide is formed in all regions except the terminals of the PMOS and
NMOS.

Step17: Metallization
Aluminum is sputtered on the whole wafer.

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 EC 6601 - VLSI DESIGN

Step18: Removal of excess metal

The excess metal is removed from the wafer layer.

Step19: Terminals
The terminals of the PMOS and NMOS are made from respective gaps.

Step20: Assigning the names to the terminals

Assigning the names of the terminals of the NMOS and PMOS

➢ P-well process
• P-well process is almost similar to the N-well.
• The only difference in p-well process is that it consists of a main N-substrate and, thus,
P-wells itself acts as substrate for the N-devices.
➢ Twin Tub-CMOS Fabrication Process
Different steps of the fabrication of the CMOS using the twin-tub process are as follows:
• Lightly doped n+ or p+ substrate is taken and, to protect the latch up, epitaxial layer is
used.
• The high-purity controlled thickness of the layers of silicon are grown with exact
dopant concentrations.
• The dopant and its concentration in Silicon are used to determine electrical properties.
• Formation of the tub
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 EC 6601 - VLSI DESIGN

• Thin oxide construction

• Implantation of the source and drain
• Cuts for making contacts
• Metallization

➢ Silicon On Insulator (SOI)

• Silicon on Insulator (SOI) is a process where the transistors are fabricated on an
insulator.
• SOI stands in contrast to conventional bulk processes in which the transistors are
fabricated on a conductive substrate.
• Two main insulators are used: SiO2 and sapphire.
• Advantage:
▪ Elimination of the capacitance between the source/drain regions and body, leading to
higher-speed devices.
▪ Lower subthreshold leakage due to steeper subthreshold slope.
• Drawback:
▪ Time-dependent threshold variations caused by the floating body.
✓ Sapphire Substrate:
• A thin layer of silicon is formed on the sapphire surface. The thin layer of silicon is
selectively doped to define different threshold transistors.
• Gate oxide is grown on top of this and then polysilicon gates are defined. Following
this, the nMOS and pMOS transistors are formed by implantation.

✓ Silicon-based SOI Process:

• A silicon substrate is used and a buried silicon oxide (BOX) is grown on top of the
silicon substrate.
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 EC 6601 - VLSI DESIGN

• A thin silicon layer is then grown on top of the buried oxide and this is selectively
implanted to form nMOS and pMOS transistor regions.
• Gate, source, and drain regions are then defined in a similar fashion to a bulk process.

❖ Scaling
• The only constant in VLSI design is constant change.
• As transistors become smaller, they switch faster, dissipate less power, and are
cheaper to manufacture.
• As the technical challenges have become greater, the pace of innovation has actually
accelerated because of ferocious competition across the industry.
• Such scaling is unprecedented in the history of technology. However, scaling also
exacerbates reliability issues, increases complexity, and introduces new problems.
• Designers need to be able to predict the effect of this feature size scaling on chip
performance to plan future products, ensure existing products will scale gracefully to
future processes for cost reduction, and anticipate looming design challenges.
• This section examines how transistors and interconnect scale, and the implications of
scaling for design.
➢ Transistor Scaling
• Dennard’s Scaling Law predicts that the basic operational characteristics of a MOS
transistor can be preserved and the performance improved if the critical parameters of
a device are scaled by a dimensionless factor S.
• These parameters include the following:
o All dimensions (in the x, y, and z directions)
o Device voltages
o Doping concentration densities

• This approach is also called constant field scaling because the electric fields remain
the same as both voltage and distance shrink.
• In contrast, constant voltage scaling shrinks the devices but not the power supply.
Another approach is lateral scaling, in which only the gate length is scaled.
• This is commonly called agate shrink because it can be done easily to an existing
mask database for a design. The effects of these types of scaling are illustrated in
Table (nextpage).
• The industry generally scales process generations with; this is also called a 30%
shrink. It reduces the cost (area) of a transistor by a factor of two. A 5% gate shrink (S

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 EC 6601 - VLSI DESIGN

= 1.05) is commonly applied as a process becomes mature to boost the speed of

components in that process.
• This constant voltage scaling offered quadratic delay improvement as well as cost
reduction.
• Constant voltage scaling increased the electric fields in devices.
• Maintaining a constant field has the further benefit that many nonlinear factors and
wear out mechanisms are essentially unaffected.
• Unfortunately, voltage scaling has dramatically slowed since the 90 nm generation
because of leakage, and this may ultimately limit CMOS scaling.

➢ Interconnect Scaling
• Wires also tend to be scaled equally in width and thickness to maintain an aspect ratio
close to 2.1, the below table shows the resistance, capacitance, and delay per unit
length.
• Wires can be classified as local, semi global, and global.
• Local wires run within functional units and use the bottom layers of metal.
• Semi global(or scaled ) wires run across larger blocks or cores, typically using middle
layers of metal. Both local and semi global wires scale with feature size.
• Global wires run across the entire chip using upper levels of metal. For example,
global wires might connect cores to a shared cache. Global wires do not scale with
feature size; indeed, they may get longer (by a factor of Dc , on the order of 1.1)
because die size has been gradually increasing.
• Most local wires are short enough that their resistance does not matter.

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 EC 6601 - VLSI DESIGN

• Like gates,their capacitance per unit length is remaining constant, so their delay is
improving just like gates.
• Semiglobal wires long enough to require repeaters are speeding up, but not as fast as
gates. This is a relatively minor problem.
• Global wires, even with optimal repeaters, are getting slower as technology scales.
The time to cross a chip in a nanometer process can be multiple cycles, and this delay
must be accounted for in the microarchitecture.
• Observe that when wire thickness is scaled, the capacitance per unit length remains
constant.
• Hence, a reasonable initial estimate of the capacitance of a minimum-pitch wire is
about 0.2 fF/𝜇m, independent of the process. In other words, wire capacitance
isroughly 1/5 of gate capacitance per unit length.

❖ Propagation delay and rise/fall times

The below definitions are illustrated using below figure
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 EC 6601 - VLSI DESIGN

❑ Propagation delay time, tpd= maximum time from theinput crossing 50% to the output
crossing 50%
❑ Contamination delay time, tcd= minimum time from theinput crossing 50% to the output
crossing 50%
❑ Rise time, tr= time for a waveform to rise from 20% to80% of its steady-state value
❑ Fall time, tf= time for a waveform to fall from 80% to20% of its steady-state value
❑ Edge rate, trf= (tr+ tf)/2

Delay in Multistage Logic Networks

Figure 4.29 shows the logical and electrical efforts of each stage in a multistage path as a
function of the sizes of each stage. The path of interest (the only path in this case) is
marked with the dashed blue line. Observe that logical effort is independent of size, while
electrical effort depends on sizes. This section develops some metrics for the path as a
whole that are independent of sizing decisions.

The path logical effort G can be expressed as the products of the logical efforts of each
stage along the path.

The path electrical effort H can be given as the ratio of the output capacitance the path
must drive divided by the input capacitance presented by the path. This is more convenient
than defining path electrical effort as the product of stage electrical efforts because
we do not know the individual stage electrical efforts until gate sizes are selected.

The path effort F is the product of the stage efforts of each stage. Recall that the stage
effort of a single stage is f = gh. Can we by analogy state F = GH for a path?

In paths that branch, . This is illustrated in Figure 4.30, a circuit with a twoway
branch. Consider a path from the primary input to one of the outputs. The path logical
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 EC 6601 - VLSI DESIGN

effort is G = 1 × 1 = 1. The path electrical effort is H = 90/5 = 18. Thus, GH = 18. But
F = f1 f2 = g1h1g2h2 = 1 × 6 × 1 × 6 = 36. In other words, F = 2GH in this path on account
of the two-way branch.
We must introduce a new kind of effort to account for branching between stages of a
path. This branching effort b is the ratio of the total capacitance seen by a stage to the
capacitance on the path; in Figure 4.30 it is (15 + 15)/15 = 2.

The path branching effort B is the product of the branching efforts between stages.

Now we can define the path effort F as the product of the logical, electrical, and branching
efforts of the path. Note that the product of the electrical efforts of the stages is actually
BH, not just H.

We can now compute the delay of a multistage network. The path delay D is the sum
of the delays of each stage. It can also be written as the sum of the path effort delay DF and
path parasitic delay P:

The product of the stage efforts is F, independent of gate sizes. The path effort delay
is the sum of the stage efforts. The sum of a set of numbers whose product is constant is minimized by
choosing all the numbers to be equal. In other words, the path delay is minimized
when each stage bears the same effort. If a path has N stages and each bears the
same effort, that effort must be

Thus, the minimum possible delay of an N-stage path with path effort F and path parasitic
delay P is

This is a key result of Logical Effort. It shows that the minimum delay of the path can be
estimated knowing only the number of stages, path effort, and parasitic delays without the
need to assign transistor sizes. This is superior to simulation, in which delay depends on sizes
and you never achieve certainty that the sizes selected are those that offer minimum delay.
It is also straightforward to select gate sizes to achieve this least delay. Combining
EQs (4.21) and (4.22) gives us the capacitance transformation formula to find the best input
capacitance for a gate given the output capacitance it drives.

Starting with the load at the end of the path, work backward applying the capacitance
transformation to determine the size of each stage. Check the arithmetic by verifying that
the size of the initial stage matches the specification.

Example 4.13
Estimate the minimum delay of the path from A to B in Figure 4.31
and choose transistor sizes to achieve this delay. The initial NAND2
gate may present a load of 8 􀁑 of transistor width on the input and
the output load is equivalent to 45 􀁑 of transistor width.

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 EC 6601 - VLSI DESIGN

SOLUTION: The path logical effort is G = (4/3)  (5/3)  (5/3) = 100/

27. The path electrical effort is H = 45/8. The path branching effort
is B = 3  2 = 6. The path effort is F = GBH = 125. As there are
three stages, the best stage effort is . The path parasitic
delay is P = 2 + 3 + 2 = 7. Hence, the minimum path delay is
D = 3  5 + 7 = 22 in units of 􀁑, or 4.4 FO4 inverter delays. The
gate sizes are computed with the capacitance transformation from
EQ (4.41) working backward along the path: y = 45  (5/3)/5 = 15.
x = (15 + 15)  (5/3)/5 = 10. We verify that the initial 2-input
NAND gate has the specified size of (10 + 10 + 10)  (4/3)/5 = 8.
The transistor sizes in Figure 4.32 are chosen to give the desired
amount of input capacitance while achieving equal rise and fall
delays. For example, a 2-input NOR gate should have a 4:1 P/N
ratio. If the total input capacitance is 15, the pMOS width must be
12 and the nMOS width must be 3 to achieve that ratio.
We can also check that our delay was achieved. The NAND2 gate
delay is d1 = g1h1 + p1 = (4/3)  (10 + 10 + 10)/8 + 2 = 7. The NAND3
gate delay is d2 = g2h2 + p2 = (5/3)  (15 + 15)/10 + 3 = 8. The NOR2 gate delay is d3 =
g3h3 + p3 = (5/3)  45/15 + 2 = 7. Hence, the path delay is 22, as predicted.
Recall that delay is expressed in units of 􀁑. In a 65 nm process with 􀁑 = 3 ps, the delay
is 66 ps. Alternatively, a fanout-of-4 inverter delay is 5􀁑, so the path delay is 4.4 FO4s.

Problem:1

Consider the logic network of Figure 6.19, which may represent the critical path of a more complex
logic block. The output of the network is loaded with a capacitance which is 5 times larger than the
input capacitance of the first gate, which is a minimum-sized inverter. The effective fanout of the path
hence equals F = CL/Cg1 = 5.

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H = FG = 125/9, and the optimal stage effort h is = 1.93. Taking into account the gate types,
we derive the fanout factors:
f1 = 1.93;
f2 = 1.93´(3/5) = 1.16;
f3 = 1.16;
f4=1.93. Notice that the inverters are assigned larger electrical efforts than the more complex gates
because they are better at driving loads. From this, we can derive the sizes of the gates (with respect to
their minimum-sized versions):
a = f1/g2 = 1.16;
b = f1f2/g3= 1.34;
c = f1f2f3/g4=2.60.

❖ Layout Design Rules

• Layout rules, also referred to as design rules, which can be consideredas prescription for
preparing the photomasks that are used in the fabrication ofintegrated circuits.
• The rules are defined in terms of feature sizes (widths), separations, andoverlaps.
• The main objective of the layout rules is to build reliably functional circuits in assmall an
area as possible.
Design rules for layouts with two metal layers inan n-well process is as follows:
❑ Metal and diffusion have minimum width and spacing of 4 𝜆.
❑ Contacts are 2 𝜆 × 2 𝜆 and must be surrounded by 1 𝜆 on the layers above
andbelow.
❑ Polysilicon uses a width of 2 𝜆.
❑ Polysilicon overlaps diffusion by 2 𝜆, where a transistor is desired and has a
spacing of 1 𝜆 away where no transistor is desired.
❑ Polysilicon and contacts have a spacing of 3 𝜆from other polysilicon or
contacts.
❑ N-well surrounds pMOS transistors by 6 𝜆and avoids nMOS transistors by 6 𝜆.

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CMOS Inverter:

Fig: Inverter - 𝜆 based design rules

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Fig: Inverter layout

2-INPUT NAND GATE:

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LAYOUT:

2-INPUT NOR GATE:

LAYOUT:

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3-INPUT NAND GATE:

4-INPUT NAND GATE:

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 EC 6601 - VLSI DESIGN

LAYOUT:

4-INPUT NOR GATE:

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LAYOUT:

❖ Stick Diagrams
• Because layout is time-consuming, designers need fast waysto plan cells and estimate
area before committing to a fulllayout.
• Stick diagrams are easy to draw because they do notneed to be drawn to scale.
• The below figure shows stick diagrams for an inverter and a 3-inputNAND gate.

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