This document contains an internal test for a course on Embedded Systems. The test has 8 multiple choice questions covering topics like challenges in embedded system design, characteristics of embedded systems, embedded system design process, serial bus protocols, bus architectures, direct memory access, and interrupts. The questions map to 2 course outcomes related to embedded system hardware and software.
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This document contains an internal test for a course on Embedded Systems. The test has 8 multiple choice questions covering topics like challenges in embedded system design, characteristics of embedded systems, embedded system design process, serial bus protocols, bus architectures, direct memory access, and interrupts. The questions map to 2 course outcomes related to embedded system hardware and software.
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Candidate Code: ………………………………
Name: ………………………………
Saintgits College of Engineering, Kottayam (Autonomous)
Kottukulam Hills, Pathamuttom P.O, Kottayam-686 532
SIXTH SEMESTER B.TECH. INTERNAL TEST - I, MARCH 2024
Course Code : 20ECT342
Course Name : Embedded Systems
Time : 2 Hrs Max. Marks : 50.00
PART A (Answer all questions) 1.Enumerate any 4 challenges of embedded system design. [ Mark : 5 ] 2.What are the characteristics of an embedded system? Explain any two in detail. [ Mark : 5 ] 3.Compare the linear EDLC model and iterartive EDLC model. [ Mark : 5 ] 4.The GPS moving map is a handheld device that displays for the user a map of the terrain around the user’s current position; the map display changes as the user and the map device change position. The moving map obtains its position from the GPS, a satellite-based navigation system. Explain different steps involved in the embedded system design process with respect to the example of GPS moving map. [ Mark : 10 ] PART B (Answer all questions) 5.List the different serial bus protocols. Explain any one in detail with help of necessary figures. [ Mark : 5 ] 6.Compare PCI and PCI-X bus. [ Mark : 5 ] 7.Elucidate the relevance of DMA. [ Mark : 5 ] 8. What is an interrupt? How interrupts are handled in a processor? Explain ISR. [ Mark : 10 ] Mapping Questions to Course Outcomes
Sections PART A PART B
Qn No. Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Course CO1 CO1 CO1 CO1 CO2 CO2 CO2 CO2 Outcomes Taxonomy 2 2 3 3 3 3 3 3 Level