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    Module 5 Co

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    Adarsh Kumar
    This document provides an overview of the basic processing unit. It discusses how the processor fetches and executes instructions through three main phases: fetch, decode, and execute. It describes the instruction register (IR) and program counter (PC) that keep track of instructions. It also outlines the registers and arithmetic logic unit (ALU) used to store and manipulate data as instructions are executed. These components work together to perform operations like transferring data between registers and memory.

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    Module 5 Co

    Uploaded by

    Adarsh Kumar
    11 views4 pages
    This document provides an overview of the basic processing unit. It discusses how the processor fetches and executes instructions through three main phases: fetch, decode, and execute. It describes the instruction register (IR) and program counter (PC) that keep track of instructions. It also outlines the registers and arithmetic logic unit (ALU) used to store and manipulate data as instructions are executed. These components work together to perform operations like transferring data between registers and memory.

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    Module 5 co

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    This document provides an overview of the basic processing unit. It discusses how the processor fetches and executes instructions through three main phases: fetch, decode, and execute. It describes the instruction register (IR) and program counter (PC) that keep track of instructions. It also outlines the registers and arithmetic logic unit (ALU) used to store and manipulate data as instructions are executed. These components work together to perform operations like transferring data between registers and memory.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    11 views4 pages

    Module 5 Co

    Uploaded by

    Adarsh Kumar
    This document provides an overview of the basic processing unit. It discusses how the processor fetches and executes instructions through three main phases: fetch, decode, and execute. It describes the instruction register (IR) and program counter (PC) that keep track of instructions. It also outlines the registers and arithmetic logic unit (ALU) used to store and manipulate data as instructions are executed. These components work together to perform operations like transferring data between registers and memory.

    Copyright:

    © All Rights Reserved
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    Download as pdf or txt
    of 4

    MMm

    Module 5
    Basic Processing Unit

    Fundamental Concepts
    • Processor fetches one instruction at a time, and performs the operation specified.
    • Instructions are fetched from successive memory locations until a branch or a jump instruction is
    encountered.
    • Processor keeps track of the address of the memory location containing the next instruction to be fetched
    using Program Counter (PC).
    • Instruction Register (IR): When an instruction is fetched, it is placed in the instruction register
    • The sequence of operations involved in processing an instruction constitutes an instruction cycle, which
    can be subdivided into 3 major phases:
    o Fetch cycle
    o Decode cycle
    o Execute cycle
    Executing an Instruction
     Fetch the contents of the memory location pointed to by the PC. The contents of this location are loaded
    into the IR (fetch phase) denoted as
    IR← [[PC]]
     Assuming that the memory is byte addressable, increment the contents of the PC by 4 (fetch phase).
    PC← [PC] + 4
     Carry out the actions specified by the instruction in the IR (execution phase).
    MMm

    • The registers Y, Z and Temp are used only by the processor unit for temporary storage during the
    execution of some instructions.
    • These registers are never used for storing data generated by one instruction for later use byanother
    instruction.
    • The programmer cannot access these registers.
    • The IR and the instruction decoder are integral parts of the control circuitry in the processing unit.
    • All other registers and the ALU are used for storing and manipulating data.
    • The data registers, ALU and the interconnecting bus is referred to as data path.
    • Register R0 through R(n-1) are the processor registers.
    • The number and use of these register vary considerably from processor to processor.
    • These registers include general purpose registers and special purpose registers such as stack pointer,
    index registers and pointers.
    • These are 2 options provided for A input of the ALU.
    • The multiplexer (MUX) is used to select one of the two inputs.
    • It selects either output of Y register or a constant number as an A input for the ALU according to the
    status of the select input.
    • It selects output of Y when select input is 1 (select Y) and it selects a constant number when select input
    is 0(select C) as an input A for the multiplier.
    • The constant number is used to increment the contents of program counter.
    For the execution of various instructions processor has to perform one or more of the following basic
    operations:

    o Transfer a word of data from one processor register to another or to the ALU.
    o Perform the arithmetic or logic operations on the data from the processor registers and store the
    result in a processor register.
    o Fetch a word of data from specified memory location and load them into a processor register.
    o Store a word of data from a processor register into a specified memory location.

    REGISTER TRANSFERS
    Each register has input and output gating and these gates are controlled by corresponding control signals.
    • The input and output gates are nothing but the electronic switches which can be controlled by the control signals

    • Two control signals are used to place the contents of that register on the bus or to load the data on the bus into register.
    • The input and output of register Ri are connected to the bus via switchws controlled by the signals Riin and Riout.
    • When Riin is set to 1,the data on the bus are loaded into Ri.
    • Whwn Riout is set to 1, the contents of register Ri are placed on the bus.while Riout. is equal to 0,the bus can be used for
    transferring data from other registers.
    • All operations and data transfers within the processor take place within time periods defined by the processor clock.
    • In the figure 2 a two-input multiplexer is used to select the data applied to the input of an edge-triggered D flip-flop.
    • When the control input Riin is equal to 1, the multiplexer selects the data on the bus. This data will be loaded into the flip-
    flop at the rising edge of the clock.
    • When Riin equal to 0,the multiplexer feeds back the value currently stored in the flip flop.
    • The Q output of the flip flop is connected to the bus via a tri-state gate.
    • When Riout is equal to 0,the gate’s output is in the high-impedance state.This corresponds to the open circuit state of a
    switch. When Riout =1 ,the gate drives the bus to 0 or 1,depending on the value of Q.
    MMm

    Example
    Suppose we wish to transfer the contents of register R1 to register R4. This can be
    accomplished as follows

    • Enable the output of registers R1 by setting R1out to 1. This places the contents of
    R1 on the processor bus.
    • Enable the input of register R4 by setting R4out to 1. This loads data from the
    processor bus into register R4.

    All operations and data transfers within the processor take place within time periods
    defined by the processor clock.
    The control signals that govern a particular transfer are asserted at the start of the clock cycle.
    MMm

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