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FPGA - Sequence Generator

1. The document describes a design of a sequence generator using JK flip flops that generates a sequence from the digits in a mobile number. 2. The design is implemented on Basys 3 and Zybo Z7 boards and utilizes a small percentage (max 6%) of the board resources. 3. Analysis of the utilization reports provides insights to optimize the design and efficiently use board resources. The technology views also provide overviews of the FPGA architectures and resources on the boards.

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18 views11 pages

FPGA - Sequence Generator

1. The document describes a design of a sequence generator using JK flip flops that generates a sequence from the digits in a mobile number. 2. The design is implemented on Basys 3 and Zybo Z7 boards and utilizes a small percentage (max 6%) of the board resources. 3. Analysis of the utilization reports provides insights to optimize the design and efficiently use board resources. The technology views also provide overviews of the FPGA architectures and resources on the boards.

Uploaded by

sarudhoni7
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Name: SARVESH.

R
Roll Number: CB.EN.U4ECE21140
Subject: 19ECE343 FPGA Based Design
Class / Batch: ECE-B
Due Date: 12th March 2024
Title: Evaluation Assignment
Q. Using structural model, design a sequence generator using positive edge triggered JK
flip flop. The sequence of operation: m{Digits in your mobile number, 8,9). If a digit
repeats, consider it only once.

PHONE NUMBER: 7397179038

SEQUENCE:{7,3,9,1,0,8}

TRUTH TABLE:

STATE DIAGRAM:
EXCITATION TABLE:

K-MAPs:
Logic Circuit with Labels:

CODE:

module jkff(input j, input k, input clk, input rs, output reg q, output reg qn);
always @(posedge clk or posedge rs) begin
if (rs) begin
q <= 1'b0;
qn <= 1'b1;
end
else begin
if (j & ~k) begin
q <= 1'b1;
end
else if (~j & k) begin
q <= 1'b0;
end
else if (j & k) begin
q <= ~q;
end
end
end
endmodule

module sd7(input clk, input rs, output qa, output qb, output qc, output qd);
wire qan, qbn, qcn, qdn;
wire ja, ka, jb, kb, jc, kc, jd, kd;

assign ja = ((~qc)&(~qd))+((~qb)&qc);
assign ka = ~qc;
assign jb = qa&(~qd);
assign kb = 1'b1;
assign jc = qa &(~qd);
assign kc = ~qb;
assign jd = qa;
assign kd = (~qa)&(~qc);

jkff jkff1(ja, ka, clk, rs, qa, qan);


jkff jkff2(jb, kb, clk, rs, qb, qbn);
jkff jkff3(jc, kc, clk, rs, qc, qcn);
jkff jkff4(jd, kd, clk, rs, qd, qdn);
endmodule
SCREENSHOT OF CODE:
OUTPUT WAVEFORM:

Synthesis Report for Basys 3 and Zybo Z7:


Basys 3 :

Zybo Z7 :
Layout :

Basys 3 :

Zybo Z7 :
RTL Schematic:

INFERENCE OF UTILIZATION REPORT:


Analysis of resource usage can be observed, this includes elements like LUTs (Look-Up
Tables), FFs (Flip-Flops), BRAMs (Block RAMs), DSP slices (Digital Signal Processing), and
I/O pins. Comparing this against the total available resources on the FPGA gives an idea of
how much more complex the design can become before reaching full capacity. This particular
design uses very less resources to run as we can see from the report(max 6%).
Examining the distribution of resources (like LUTs, FFs) across different modules of the
design, helps in identifying areas where optimization may be possible. This could involve
restructuring the logic, pipelining, or other techniques to reduce resource usage.
Helps in comparison between different designs like the two boards we have used in this design.
In summary, utilization reports are crucial for optimizing FPGA designs, ensuring they meet
performance requirements, and making efficient use of available resources. They provide
insights into various aspects of your design's implementation on the FPGA platform.

Technology view for Basys3 and Zybo Z7


Basys 3:
The Technology View provides an overview of the Artix-7 FPGA architecture, highlighting its
key features such as LUTs, FFs, BRAMs, DSP slices, and I/O pins.
It presents a breakdown of the available resources on the Artix-7 FPGA, including the total
number of logic cells, flip-flops, block RAMs, DSP slices, and I/O pins. This information helps
in understanding the capacity of the FPGA and how efficiently the design utilizes these
resources.
Details about configuration options and debugging features available on the Artix-7 FPGA are
also included in the Technology View, assisting designers in the development and debugging
process
Zybo Z7:
The Technology View provides an overview of the Zynq-7000 SoC architecture, highlighting
the integration of FPGA fabric and ARM Cortex-A9 processors. It presents details about the
FPGA fabric, including LUTs, FFs, BRAMs, DSP slices, and I/O pins, as well as the ARM
processor cores and peripherals available within the SoC.
It presents a breakdown of the available resources on both the FPGA fabric and the ARM
processor subsystem, enabling designers to understand the capacity of each component and
how efficiently the design utilizes these resources
Details about configuration options and debugging features available on the Zynq-7000 SoC
are included in the Technology View, assisting designers in the development and debugging
process for both FPGA and software components.

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