DATASHEET

ISL6255, ISL6255A FN9203

Highly Integrated Battery Charger with Automatic Power Source Selector for Rev 2.00
Notebook Computers May 23, 2006

The ISL6255, ISL6255A is a highly integrated battery charger Features

controller for Li-Ion/Li-Ion polymer batteries. High Efficiency is
achieved by a synchronous buck topology and the use of a • ±0.5% Charge Voltage Accuracy (-10°C to 100°C)
MOSFET, instead of a diode, for selecting power from the • ±3% Accurate Input Current Limit
adapter or battery. The low side MOSFET emulates a diode at
• ±3% Accurate Battery Charge Current Limit
light loads to improve the light load efficiency and prevent
system bus boosting. • ±25% Accurate Battery Trickle Charge Current Limit
(ISL6255A)
The constant output voltage can be selected for 2, 3 and 4
series Li-Ion cells with 0.5% accuracy over temperature. It can • Programmable Charge Current Limit, Adapter Current
also be programmed between 4.2V+5%/cell and 4.2V-5%/cell Limit and Charge Voltage
to optimize battery capacity. When supplying the load and • Fixed 300kHz PWM Synchronous Buck Controller with
battery charger simultaneously, the input current limit for the Diode Emulation at Light Load
AC adapter is programmable to within 3% accuracy to avoid
• Output for Current Drawn from AC Adapter
overloading the AC adapter, and to allow the system to make
efficient use of available adapter power for charging. It also • AC Adapter Present Indicator
has a wide range of programmable charging current. The • Fast Input Current Limit Response
ISL6255, ISL6255A provides outputs that are used to monitor
the current drawn from the AC adapter, and monitor for the • Input Voltage Range 7V to 25V
presence of an AC adapter. The ISL6255, ISL6255A • Support 2, 3 and 4 Cells Battery Pack
automatically transitions from regulating current mode to
• Up to 17.64V Battery-Voltage Set Point
regulating voltage mode.
• Control Adapter Power Source Select MOSFET
ISL6255, ISL6255A has a feature for automatic power source
selection by switching to the battery when the AC adapter is • Thermal Shutdown
removed or switching to the AC adapter when the AC adapter
• Aircraft Power Capable
is available. It also provides a DC adapter monitor to support
aircraft power applications with the option of no battery • DC Adapter Present Indicator
charging. • Battery Discharge MOSFET Control
Ordering Information • Less than 10µA Battery Leakage Current
PART • Support Pulse Charging
NUMBER PART TEMP PACKAGE PKG.
(Notes 1, 2) MARKING RANGE (°C) (Pb-free) DWG. # • Charge Any Battery Chemistry: Li-Ion, NiCd, NiMH, etc.

ISL6255HRZ ISL6255HRZ -10 to 100 28 Ld 5x5 QFN L28.55 • Pb-Free Plus Anneal Available (RoHS Compliant)
ISL6255HAZ ISL6255HAZ -10 to 100 28 Ld QSOP M28.15
Applications
ISL6255AHRZ ISL6255AHRZ -10 to 100 28 Ld 5x5 QFN L28.55
• Notebook, Desknote and Sub-notebook Computers
ISL6255AHAZ ISL6255AHAZ -10 to 100 28 Ld QSOP M28.15
• Personal Digital Assistant
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-T” for Tape and Reel.

FN9203 Rev 2.00 Page 1 of 22

May 23, 2006
ISL6255, ISL6255A

Pinouts
ISL6255, ISL6255A ISL6255, ISL6255A
(28 LD QFN) (28 LD QSOP)
TOP VIEW TOP VIEW

DCPRN

ACPRN
DCSET

ACSET

CSON
DCIN
VDD
DCIN 1 28 DCPRN

VDD 2 27 ACPRN
28 27 26 25 24 23 22
ACSET 3 26 CSON
EN 1 21 CSOP 4 25
DCSET CSOP
CELLS 2 20 CSIN EN 5 24 CSIN

CELLS 6 23 CSIP
ICOMP 3 19 CSIP
ICOMP 7 22 SGATE
VCOMP 4 18 SGATE
VCOMP 8 21 BGATE
ICM 5 17 BGATE ICM 9 20 PHASE

VREF 10 19 UGATE
VREF 6 16 PHASE
CHLIM 11 18 BOOT
CHLIM 7 15 UGATE
ACLIM 12 17 VDDP
8 9 10 11 12 13 14 VADJ 13 16 LGATE
GND 14 15 PGND
ACLIM

BOOT
GND
VADJ

PGND

LGATE

VDDP

FN9203 Rev 2.00 Page 2 of 22

May 23, 2006
ISL6255, ISL6255A

Absolute Maximum Ratings Thermal Information

DCIN, CSIP, CSON to GND. . . . . . . . . . . . . . . . . . . . . -0.3V to +28V Thermal Resistance JA (°C/W) JC (°C/W)
CSIP-CSIN, CSOP-CSON . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V QFN Package (Notes 4, 5). . . . . . . . . . 39 9.5
CSIP-SGATE, CSIP-BGATE . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V QSOP Package (Note 4) . . . . . . . . . . . 80 NA
PHASE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7V to 30V Junction Temperature Range. . . . . . . . . . . . . . . . . .-10°C to +150°C
BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +35V Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C
BOOT to VDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 28V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
ACLIM, ACPRN, CHLIM, DCPRN, VDD to GND. . . . . . . -0.3V to 7V Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
BOOT-PHASE, VDDP-PGND . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
ACSET and DCSET to GND (Note 3) . . . . . . . . -0.3V to VDD+0.3V
ICM, ICOMP, VCOMP to GND. . . . . . . . . . . . . . -0.3V to VDD+0.3V
VREF, CELLS to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
EN, VADJ, PGND to GND . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
UGATE. . . . . . . . . . . . . . . . . . . . . . . . . PHASE-0.3V to BOOT+0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . . . . . PGND-0.3V to VDDP+0.3V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
3. When the voltage across ACSET and DCSET is below 0V, the current through ACSET and DCSET should be limited to less than 1mA.
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF,
VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, CVDD = 1µF, IVDD = 0mA,
TA = -10°C to +100°C, TJ  125°C, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SUPPLY AND BIAS REGULATOR
DCIN Input Voltage Range 7 25 V
DCIN Quiescent Current EN = VDD or GND, 7V DCIN 25V 1.4 3 mA
Battery Leakage Current (Note 6) DCIN = 0, no load 3 10 µA
VDD Output Voltage/Regulation 7V DCIN 25V, 0 IVDD 30mA 4.925 5.075 5.225 V
VDD Undervoltage Lockout Trip Point VDD Rising 4.0 4.4 4.6 V
Hysteresis 200 250 400 mV
Reference Output Voltage VREF 0 IVREF  300µA 2.365 2.39 2.415 V
Battery Charge Voltage Accuracy CSON = 16.8V, CELLS = VDD, VADJ = Float -0.5 0.5 %
CSON = 12.6V, CELLS = GND, VADJ = Float -0.5 0.5 %
CSON = 8.4V, CELLS = Float, VADJ = Float -0.5 0.5 %
CSON = 17.64V, CELLS = VDD, VADJ = VREF -0.5 0.5 %
CSON = 13.23V, CELLS = GND, VADJ = VREF -0.5 0.5 %
CSON = 8.82V, CELLS = Float, VADJ = VREF -0.5 0.5 %
CSON = 15.96V, CELLS = VDD, VADJ = GND -0.5 0.5 %
CSON = 11.97V, CELLS = GND, VADJ = GND -0.5 0.5 %
CSON = 7.98V, CELLS = Float, VADJ = GND -0.5 0.5 %
TRIP POINTS
ACSET Threshold 1.24 1.26 1.28 V
ACSET Input Bias Current Hysteresis 2.2 3.4 4.4 µA
ACSET Input Bias Current ACSET  1.26V 2.2 3.4 4.4 µA
ACSET Input Bias Current ACSET < 1.26V -1 0 1 µA
DCSET Threshold 1.24 1.26 1.28 V

FN9203 Rev 2.00 Page 3 of 22

May 23, 2006
ISL6255, ISL6255A

Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF,
VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, CVDD = 1µF, IVDD = 0mA,
TA = -10°C to +100°C, TJ  125°C, unless otherwise noted. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DCSET Input Bias Current Hysteresis 2.2 3.4 4.4 µA
DCSET Input Bias Current DCSET  1.26V 2.2 3.4 4.4 µA
DCSET Input Bias Current DCSET < 1.26V -1 0 1 µA
OSCILLATOR
Frequency 245 300 355 kHz
PWM Ramp Voltage (peak-peak) CSIP = 18V 1.6 V
CSIP = 11V 1 V
SYNCHRONOUS BUCK REGULATOR
Maximum Duty Cycle 97 99 99.6 %
UGATE Pull-Up Resistance BOOT-PHASE = 5V, 500mA source current 1.8 3.0 
UGATE Source Current BOOT-PHASE = 5V, BOOT-UGATE = 2.5V 1.0 A
UGATE Pull-down Resistance BOOT-PHASE = 5V, 500mA sink current 1.0 1.8 
UGATE Sink Current BOOT-PHASE = 5V, UGATE-PHASE = 2.5V 1.8 A
LGATE Pull-Up Resistance VDDP-PGND = 5V, 500mA source current 1.8 3.0 
LGATE Source Current VDDP-PGND = 5V, VDDP-LGATE = 2.5V 1.0 A
LGATE Pull-Down Resistance VDDP-PGND = 5V, 500mA sink current 1.0 1.8 
LGATE Sink Current VDDP-PGND = 5V, LGATE = 2.5V 1.8 A
CHARGING CURRENT SENSING AMPLIFIER
Input Common-Mode Range 0 18 V
Input Offset Voltage Guaranteed by design -2.5 0 2.5 mV
Input Bias Current at CSOP 0 < CSOP < 18V 0.25 2 µA
Input Bias Current at CSON 0 < CSON < 18V 75 100 µA
CHLIM Input Voltage Range 0 3.6 V
CSOP to CSON Full-Scale Current Sense ISL6255: CHLIM = 3.3V 157 165 173 mV
Voltage
ISL6255A: CHLIM = 3.3V 160 165 170 mV
ISL6255: CHLIM = 2.0V 95 100 105 mV
ISL6255A: CHLIM = 2.0V 97 100 103 mV
ISL6255: CHLIM = 0.2V 5.0 10 15.0 mV
ISL6255A: CHLIM = 0.2V 7.5 10 12.5 mV
CHLIM Input Bias Current CHLIM = GND or 3.3V, DCIN = 0V -1 1 µA
CHLIM Power-Down Mode Threshold CHLIM rising 80 88 95 mV
Voltage
CHLIM Power-Down Mode Hysteresis 15 25 40 mV
Voltage
ADAPTER CURRENT SENSING AMPLIFIER
Input Common-Mode Range 7 25 V
Input Offset Voltage Guaranteed by design -2 2 mV
Input Bias Current at CSIP and CSIN CSIP = CSIN = 25V 100 130 µA
Combined
Input Bias Current at CSIN 0 < CSIN < DCIN, Guaranteed by design 0.10 1 µA

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May 23, 2006
ISL6255, ISL6255A

Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF,
VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, CVDD = 1µF, IVDD = 0mA,
TA = -10°C to +100°C, TJ  125°C, unless otherwise noted. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ADAPTER CURRENT LIMIT THRESHOLD
CSIP to CSIN Full-Scale Current Sense ACLIM = VREF 97 100 103 mV
Voltage
ACLIM = Float 72 75 78 mV
ACLIM = GND 47 50 53 mV
ACLIM Input Bias Current ACLIM = VREF 10 16 20 µA
ACLIM = GND -20 -16 -10 µA
VOLTAGE REGULATION ERROR AMPLIFIER
Error Amplifier Transconductance from CELLS = VDD 30 µA/V
CSON to VCOMP
CURRENT REGULATION ERROR AMPLIFIER
Charging Current Error Amplifier 50 µA/V
Transconductance
Adapter Current Error Amplifier 50 µA/V
Transconductance
BATTERY CELL SELECTOR
CELLS Input Voltage for 4 Cell Select 4.3 V
CELLS Input Voltage for 3 Cell Select 2 V
CELLS Input Voltage for 2 Cell Select 2.1 4.2 V
MOSFET DRIVER
BGATE Pull-Up Current CSIP-BGATE = 3V 10 30 45 mA
BGATE Pull-Down Current CSIP-BGATE = 5V 2.7 4.0 5.0 mA
CSIP-BGATE Voltage High 8 9.6 11 V
CSIP-BGATE Voltage Low 50 0 50 mV
DCIN-CSON Threshold for CSIP-BGATE DCIN = 12V, CSON Rising -100 0 100 mV
Going High
DCIN-CSON Threshold Hysteresis 250 300 400 mV
SGATE Pull-Up Current CSIP-SGATE = 3V 7 12 15 mA
SGATE Pull-Down Current CSIP-SGATE = 5V 50 160 370 µA
CSIP-SGATE Voltage High 8 9 11 V
CSIP-SGATE Voltage Low -50 0 50 mV
CSIP-CSIN Threshold for CSIP-SGATE 2.5 8 13 mV
Going High
CSIP-CSIN Threshold Hysteresis 1.3 5 8 mV
LOGIC INTERFACE
EN Input Voltage Range 0 VDD V
EN Threshold Voltage Rising 1.030 1.06 1.100 V
Falling 0.985 1.000 1.025 V
Hysteresis 30 60 90 mV
EN Input Bias Current EN = 2.5V 1.8 2.0 2.2 µA
ACPRN Sink Current ACPRN = 0.4V 3 8 11 mA
ACPRN Leakage Current ACPRN = 5V -0.5 0.5 µA
DCPRN Sink Current DCPRN = 0.4V 3 8 11 mA

FN9203 Rev 2.00 Page 5 of 22

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ISL6255, ISL6255A

Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF,
VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, CVDD = 1µF, IVDD = 0mA,
TA = -10°C to +100°C, TJ  125°C, unless otherwise noted. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DCPRN Leakage Current DCPRN = 5V -0.5 0.5 µA
ICM Output Accuracy CSIP-CSIN = 100mV -3 0 +3 %
(Vicm = 19.9 x (Vcsip-Vcsin))
CSIP-CSIN = 75mV -4 0 +4 %
CSIP-CSIN = 50mV -5 0 +5 %
Thermal Shutdown Temperature 150 °C
Thermal Shutdown Temperature Hysteresis 25 °C
NOTE:
6. This is the sum of currents in these pins (CSIP, CSIN, BGATE, BOOT, UGATE, PHASE, CSOP, CSON) all tied to 16.8V. No current in pins EN,
ACSET, DCSET, VADJ, CELLS, ACLIM, CHLIM.

Typical Operating Performance DCIN = 20V, 4S2P Li-Battery, TA = 25°C, unless otherwise noted.

0.6 0.1

VREF=2.390V

VREF LOAD REGULATION ACCURACY (%)

VDD=5.075V
VDD LOAD REGULATION ACCURACY (%)

EN=0 0.08
0.3

0.06

0
0.04

-0.3
0.02

-0.6 0

0 8 16 24 32 40 0 100 200 300 400

LOAD CURRENT (mA) LOAD CURRENT (µA)

FIGURE 1. VDD LOAD REGULATION FIGURE 2. VREF LOAD REGULATION

10 1
9
Test

8 0 .9 6
| ICM ACCURACY | (%)

VCSON=8.4V
7
0 .9 2 VCSON=12.6V 2 CELLS
6 (3 CELLS)
EFFICIENCY (%)

5 VCSON=16.8V
0 .8 8
4 CELLS
4
3 0 .8 4

2
0 .8
1
0 0 .76
10 20 30 40 50 60 70 80 90 100
0 0 .5 1 1.5 2 2.5 3 3 .5 4
CSIP-CSIN (mV)
CHARGE CURRENT (A)

FIGURE 3. ICM ACCURACY vs AC ADAPTER CURRENT FIGURE 4. SYSTEM EFFICIENCY vs CHARGE CURRENT

FN9203 Rev 2.00 Page 6 of 22

May 23, 2006
ISL6255, ISL6255A

Typical Operating Performance DCIN = 20V, 4S2P Li-Battery, TA = 25°C, unless otherwise noted. (Continued)

LOAD
CURRENT
DCIN 5A/div
10V/div
ADAPTER
CURRENT
5A/div
ACSET
1V/div CHARGE
CURRENT
2A/div
DCSET
1V/div LOAD STEP: 0-4A
CHARGE CURRENT: 3A
AC ADAPTER CURRENT LIMIT: 5.15A BATTERY
DCPRN VOLTAGE
5V/div 2V/div
ACPRN
5V/div

FIGURE 5. AC AND DC ADAPTER DETECTION FIGURE 6. LOAD TRANSIENT RESPONSE

CSON
5V/div INDUCTOR
CURRENT
2A/div
EN
BATTERY BATTERY
5V/div REMOVAL
INSERTION

CSON
10V/div
INDUCTOR
CURRENT
2A/div VCOMP
VCOMP 2V/div
CHARGE
CURRENT ICOMP ICOMP
2A/div 2V/div

FIGURE 7. CHARGE ENABLE AND SHUTDOWN FIGURE 8. BATTERY INSERTION AND REMOVAL

CHLIM=0.2V
CSON=8V

PHASE
PHASE 10V/div
10V/div

INDUCTOR
CURRENT UGATE
1A/div 2V/div

UGATE LGATE
5V/div 2V/div

FIGURE 9. AC ADAPTER REMOVAL FIGURE 10. AC ADAPTER INSERTION

FN9203 Rev 2.00 Page 7 of 22

May 23, 2006
ISL6255, ISL6255A

Typical Operating Performance DCIN = 20V, 4S2P Li-Battery, TA = 25°C, unless otherwise noted. (Continued)

BGATE-CSIP
SGATE-CSIP
2V/div
ADAPTER REMOVAL 2V/div

SYSTEM BUS
VOLTAGE
SYSTEM BUS
10V/div
VOLTAGE
10V/div

SGATE-CSIP
BGATE-CSIP 2V/div
2V/div
INDUCTOR
INDUCTOR CURRENT
CURRENT ADAPTER INSERTION 2A/div
2A/div

FIGURE 11. SWITCHING WAVEFORMS AT DIODE EMULATION FIGURE 12. SWITCHING WAVEFORMS IN CC MODE

CHARGE
CURRENT
1A/div

CHLIM
1V/div

FIGURE 13. TRICKLE TO FULL-SCALE CHARGING

Functional Pin Descriptions PHASE

The Phase connection pin connects to the high side MOSFET
BOOT
source, output inductor, and low side MOSFET drain.
Connect BOOT to a 0.1µF ceramic capacitor to PHASE pin
and connect to the cathode of the bootstrap schottky diode. CSOP/CSON
CSOP/CSON is the battery charging current sensing
UGATE
positive/negative input. The differential voltage across CSOP
UGATE is the high side MOSFET gate drive output. and CSON is used to sense the battery charging current, and
SGATE is compared with the charging current limit threshold to
regulate the charging current. The CSON pin is also used as
SGATE is the AC adapter power source select output. The
the battery feedback voltage to perform voltage regulation.
SGATE pin drives an external P-MOSFET used to switch to AC
adapter as the system power source. CSIP/CSIN
BGATE CSIP/CSIN is the AC adapter current sensing positive/negative
input. The differential voltage across CSIP and CSIN is used to
Battery power source select output. This pin drives an external
sense the AC adapter current, and is compared with the AC
P-channel MOSFET used to switch the battery as the system
adapter current limit to regulate the AC adapter current.
power source. When the voltage at CSON pin is higher than
the AC adapter output voltage at DCIN, BGATE is driven to low GND
and selects the battery as the power source. GND is an analog ground.
LGATE
LGATE is the low side MOSFET gate drive output; swing
between 0V and VDDP.

FN9203 Rev 2.00 Page 8 of 22

May 23, 2006
ISL6255, ISL6255A

DCIN VDDP
The DCIN pin is the input of the internal 5V LDO. Connect it to VDDP is the supply voltage for the low-side MOSFET gate
the AC adapter output. Connect a 0.1µF ceramic capacitor driver. Connect a 4.7 resistor to VDD and a 1F ceramic
from DCIN to CSON. capacitor to power ground.

ACSET ICOMP
ACSET is an AC adapter detection input. Connect to a resistor ICOMP is a current loop error amplifier output.
divider from the AC adapter output.
VCOMP
ACPRN VCOMP is a voltage loop amplifier output.
Open-drain output signals AC adapter is present. ACPRN pulls
CELLS
low when ACSET is higher than 1.26V; and pulled high when
ACSET is lower than 1.26V. This pin is used to select the battery voltage. CELLS = VDD for
a 4S battery pack, CELLS = GND for a 3S battery pack,
DCSET CELLS = Float for a 2S battery pack.
DCSET is a lower voltage adapter detection input (like aircraft
VADJ
power 15V).Allows the adapter to power the system where
battery charging has been disabled. VADJ adjusts battery regulation voltage. VADJ = VREF for
4.2V+5%/cell; VADJ = Floating for 4.2V/cell; VADJ = GND for
DCPRN 4.2V-5%/cell. Connect to a resistor divider to program the
Open-drain output signals DC adapter is present. DCPRN pulls desired battery cell voltage between 4.2V-5% and 4.2V+5%.
low when DCSET is higher than 1.26V; and pulled high when
CHLIM
DCSET is lower than 1.26V.
CHLIM is the battery charge current limit set pin.CHLIM input
EN voltage range is 0.1V to 3.6V. When CHLIM = 3.3V, the set
EN is the Charge Enable input. Connecting EN to high enables point for CSOP-CSON is 165mV. The charger shuts down if
the charge control function, connecting EN to low disables CHLIM is forced below 88mV.
charging functions. Use with a thermistor to detect a hot
ACLIM
battery and suspend charging.
ACLIM is the adapter current limit set pin. ACLIM = VREF for
ICM 100mV, ACLIM = Floating for 75mV, and ACLIM = GND for
ICM is the adapter current output. The output of this pin 50mV. Connect a resistor divider to program the adapter
produces a voltage proportional to the adapter current. current limit threshold between 50mV and 100mV.

PGND VREF
PGND is the power ground. Connect PGND to the source of VREF is a 2.39V reference output pin. It is internally
the low side MOSFET. compensated. Do not connect a decoupling capacitor.

VDD
VDD is an internal LDO output to supply IC analog circuit.
Connect a 1F ceramic capacitor to ground.

FN9203 Rev 2.00 Page 9 of 22

May 23, 2006
ISL6255, ISL6255A

ICM SGATE CSIP CSIN

CHLIM
DCSET DCPRN
CSOP CSON GND

ACSET
EN
+ CA1 -
+

+
+
Reference VREF
CA1´X19.9
- CA2
-

+
+
ACPRN - 1.065V
CA2
´ 20 1.26V -
1.06V +
VDD
PGND - -CSON
VREF 1.26V
+ CA2 + Selector
CELLS
BGATE
- VCA2V Voltage
LGATE 152K - gm3
Adapter -

+
VDDP 1.27V gm2
Current -
+ DCIN
ACLIM
514K

2.1V
gm3
VDDP Limit Set
Adapter
Selector
152K
VADJ
+ LDO
+
+
Current Limit Set LDO
Voltage + -
PWM
Min Regulator 514K VDD
Regulator
- gm1
Current
ICOMP
PHASE 0.25 CA2
VCA2
0.25V
Buffer ++- VREF
2.1V Min
Min
+- BOOT
UGATE + - VCOMP
Voltage
Voltage
Buffer
Buffer
gm1
gm1
Buffer
Buffer UGATE
Voltage
Voltage
VCOMP - +
+-
Min
Min 2.1V
BOOT
VREF 0.25V ++-- Buffer
0.25 VCA2
CA2 PHASE
ICOMP
-
Current
gm1
Regulator
VDD 514K Regulator Min
PWM
Voltage + -
LDO Current Limit Set
+
+
LDO +
VADJ
152K
Selector
Adapter
VDDP
2.1V

Limit Set
gm3
514K
DCIN + Current ACLIM
-
- gm2 1.27V
Adapter VDDP
LGATE
+

gm3 - 152K
Voltage VCA2V -
BGATE + Selector CA2
CELLS 1.26V
+ VREF
- CSON - PGND
VDD
1.06V
- 1.065V
+
1.26V - ´ 20
X
CA2 -
ACPRN
- CA2
CA1´ 19.9
+
+

VREF Reference + + CA1 -

+ EN
+

ACSET

GND CSON CSOP

DCPRN DCSET
CHLIM
CSIN SGATE CSIP ICM

FIGURE 14. FUNCTIONAL BLOCK DIAGRAM

FN9203 Rev 2.00 Page 10 of 22

May 23, 2006
ISL6255, ISL6255A

AC ADAPTER Q3

VDD C8
R8
130k 0.1µF CSON
1% Q5

R9 DCIN
DCIN SGATE
10.2k
1% CSIP
ACSET
ACSET
C2 R2
ISL6255
ISL6255 0.1
0.1µF 20m
C7
ISL6255A
ISL6255A
ISL6255A SYSTEM LOAD
1µF
1
CSIN
CSIN
VDDP
VDDP R3
3.3V R10 18
4.7 BGATE
VDD
VDD VDDP
C1:10 µF Q4
R5 C9 BOOT
BOOT
100k 1
1µF D2
To Host UGATE
UGATE
ACPRN
ACPRN C4 Q1
Controller
C6:6.8nF
0.1
0.1µF
ICOMP
ICOMP PHASE
PHASE
R6: 10k C5:10nF
VCOMP
VCOMP LGATE D1 L
Q2 Optional 10µH
FLOATING
VADJ
VADJ PGND
PGND
4.2V/CELL

CHARGE CSOP
CSOP
EN
EN
ENABLE C3 R4 R1
1
1µF 2.2 40m
ACLIM
ACLIM CSON
CSON BAT+

C10 Battery
VREF
VREF CELLS VDD
4 CELLS 10
10µF Pack
R12 2.6A CHARGE LIMIT
VREF 20k 1% 253mA Trickle Charge BAT-
ICM
CHLIM
CHLIM C11
R13 R11 R7: 100
GND 3300pF
1.87k 130k
1% 1%
TRICKLE
CHARGE Q6

FIGURE 15. ISL6255, ISL6255A TYPICAL APPLICATION CIRCUIT WITH FIXED CHARGING PARAMETERS

FN9203 Rev 2.00 Page 11 of 22

May 23, 2006
ISL6255, ISL6255A

ADAPTER

Q3
R8 VDD C8
130k 0.1µ
0.1
Q5 CSON
1%

R14 R9 DCIN
DCIN SGATE
SGATE
100k 10.2k
1% 1% CSIP
CSIP
ACSET
ACSET
C2 R2
0.1µF
0.1 20m
R15 DCSET
DCSET SYSTEM LOAD
11.5k CSIN
ISL6255 CSIN
C7 ISL6255
ISL6255
1% R3: 18
1µF ISL6255A
ISL6255A
ISL6255A
VDDP
VDDP BGATE
BGATE Q4
C9 R10 VDDP C1:10µF
C1:10
1
1µF 4.7 BOOT
BOOT
VCC VDD
VDD D2
R16 R5 UGATE
UGATE Q1
100k 100k C4
DIGITAL
ACPRN
ACPRN 0.1µF
0.1
INPUT PHASE
PHASE
DIGITAL DCPRN
DCPRN
INPUT LGATE
LGATE D1
Q2 Optional L
10µH
10
D/A OUTPUT CHLIM
CHLIM PGND
PGND

OUTPUT EN
EN
R7: 100 CSOP
CSOP
R4 R1
C3
A/D INPUT ICM
ICM 40m
1
1µF 2.2
C11
VREF CSON
CSON BAT+
3300pF
HOST 5.15A INPUT ACLIM
ACLIM
CURRENT LIMIT GND C10
CELLS
CELLS 3 CELLS 10µF
10
VREF
VREF
C6
6.8nF VADJ
VADJ FLOATING
R11,R12 4.2V/CELL BATTERY
R13: 10K ICOMP
ICOMP
AVDD/VREF Pack
GND
GND
VCOMP
VCOMP
R6 C5
10k 10nF
SCL SCL
SDL SDL
A/D INPUT TEMP
GND BAT-

FIGURE 16. ISL6255, ISL6255A TYPICAL APPLICATION CIRCUIT WITH µP CONTROL AND AIRCRAFT POWER SUPPORT

FN9203 Rev 2.00 Page 12 of 22

May 23, 2006
ISL6255, ISL6255A

Theory of Operation ACLIM, and to prevent a system crash and AC adapter

overload.
Introduction
The ISL6255, ISL6255A includes all of the functions necessary PWM Control
to charge 2 to 4 cell Li-Ion and Li-polymer batteries. A high The ISL6255, ISL6255A employs a fixed frequency PWM
efficiency synchronous buck converter is used to control the current mode control architecture with a feed-forward function.
charging voltage and charging current up to 10A. The ISL6255, The feed-forward function maintains a constant modulator gain
ISL6255A has input current limiting and analog inputs for of 11 to achieve fast line regulation as the buck input voltage
setting the charge current and charge voltage; CHLIM inputs changes. When the battery charge voltage approaches the
are used to control charge current and VADJ inputs are used to input voltage, the DC/DC converter operates in dropout mode,
control charge voltage. where there is a timer to prevent the frequency from dropping
into the audible frequency range. It can achieve duty cycle of
The ISL6255, ISL6255A charges the battery with constant up to 99.6%.
charge current, set by CHLIM input, until the battery voltage
rises up to a programmed charge voltage set by VADJ input; To prevent boosting of the system bus voltage, the battery
then the charger begins to operate at a constant voltage charge charger operates in standard-buck mode when CSOP-CSON
mode. The charger also drives an adapter isolation P-channel drops below 4.25mV. Once in standard-buck mode, hysteresis
MOSFET to efficiently switch in the adapter supply. does not allow synchronous operation of the DC/DC converter
until CSOP-CSON rises above 12.5mV.
ISL6255, ISL6255A is a complete power source selection
controller for single battery systems and also aircraft power An adaptive gate drive scheme is used to control the dead time
applications. It drives a battery selector P-channel MOSFET to between two switches. The dead time control circuit monitors
efficiently select between a single battery and the adapter. It the LGATE output and prevents the upper side MOSFET from
controls the battery discharging MOSFET and switches to the turning on until LGATE is fully off, preventing cross-conduction
battery when the AC adapter is removed, or, switches to the and shoot-through. In order for the dead time circuit to work
AC adapter when the AC adapter is inserted for single battery properly, there must be a low resistance, low inductance path
system. from the LGATE driver to MOSFET gate, and from the source
of MOSFET to PGND. The external Schottky diode is between
The EN input allows shutdown of the charger through a the VDDP pin and BOOT pin to keep the bootstrap capacitor
command from a micro-controller. It also uses EN to safely charged.
shutdown the charger when the battery is in extremely hot
conditions. The amount of adapter current is reported on the Setting the Battery Regulation Voltage
ICM output. Figure 14 shows the IC functional block diagram. The ISL6255, ISL6255A uses a high-accuracy trimmed band-
gap voltage reference to regulate the battery charging voltage.
The synchronous buck converter uses external N-channel
The VADJ input adjusts the charger output voltage, and the
MOSFETs to convert the input voltage to the required charging
VADJ control voltage can vary from 0 to VREF, providing a
current and charging voltage. Figure 15 shows the ISL6255,
10% adjustment range (from 4.2V-5% to 4.2V+5%) on CSON
ISL6255A typical application circuit with charging current and
regulation voltage. An overall voltage accuracy of better than
charging voltage fixed at specific values. The typical
0.5% is achieved.
application circuit shown in Figure 16 shows the ISL6255,
ISL6255A typical application circuit which uses a micro- The per-cell battery termination voltage is a function of the
controller to adjust the charging current set by CHLIM input for battery chemistry. Consult the battery manufacturers to
aircraft power applications. The voltage at CHLIM and the determine this voltage.
value of R1 sets the charging current. The DC/DC converter
• Float VADJ to set the battery voltage VCSON = 4.2V 
generates the control signals to drive two external N-channel
number of the cells,
MOSFETs to regulate the voltage and current set by the
ACLIM, CHLIM, VADJ and CELLS inputs. • Connect VADJ to VREF to set 4.41V  number of cells,

The ISL6255, ISL6255A features a voltage regulation loop • Connect VADJ to ground to set 3.99V  number of the cells.
(VCOMP) and two current regulation loops (ICOMP). The So, the maximum battery voltage of 17.6V can be achieved. Note
VCOMP voltage regulation loop monitors CSON to ensure that that other battery charge voltages can be set by connecting a
its voltage never exceeds the voltage and regulates the battery resistor divider from VREF to ground. The resistor divider should
charge voltage set by VADJ. The ICOMP current regulation be sized to draw no more than 100µA from VREF; or connect a
loops regulate the battery charging current delivered to the low impedance voltage source like the D/A converter in the micro-
battery to ensure that it never exceeds the charging current controller. The programmed battery voltage per cell can be
limit set by CHLIM; and the ICOMP current regulation loops determined by the following equation:
also regulate the input current drawn from the AC adapter to VCELL  0.175 VVADJ  3.99 V
ensure that it never exceeds the input current limit set by

FN9203 Rev 2.00 Page 13 of 22

May 23, 2006
ISL6255, ISL6255A

An external resistor divider from VREF sets the voltage at current sense resistor R1 will degrade accuracy due to the
VADJ according to: smaller signal to the input of the current sense amplifier. There
R bot_VADJ  514k is a trade-off between accuracy and power dissipation. A low
V VADJ = VREF  ------------------------------------------------------------------------------------------------- pass filter is recommended to eliminate switching noise.
R top_VADJ  514k + R  514k
bot_VADJ Connect the resistor to the CSOP pin instead of the CSON pin,
as the CSOP pin has lower bias current and less influence on
where Rbot_VADJ and Rtop_VADJ are external resistors at
current-sense accuracy and voltage regulation accuracy.
VADJ.

To minimize accuracy loss due to interaction with VADJ's Setting the Input Current Limit
internal resistor divider, ensure the AC resistance looking back The total input current from an AC adapter, or other DC source,
into the resistor divider is less than 25k. is a function of the system supply current and the battery-
charging current. The input current regulator limits the input
Connect CELLS as shown in Table 1 to charge 2, 3 or 4 Li+
current by reducing the charging current, when the input
cells. When charging other cell chemistries, use CELLS to
current exceeds the input current limit set point. System
select an output voltage range for the charger. The internal
current normally fluctuates as portions of the system are
error amplifier gm1 maintains voltage regulation. The voltage
powered up or down. Without input current regulation, the
error amplifier is compensated at VCOMP. The component
source must be able to supply the maximum system current
values shown in Figure 16 provide suitable performance for
and the maximum charger input current simultaneously. By
most applications. Individual compensation of the voltage
using the input current limiter, the current capability of the AC
regulation and current-regulation loops allows for optimal
adapter can be lowered, reducing system cost.
compensation.
TABLE 1. CELL NUMBER PROGRAMMING
The ISL6255, ISL6255A limits the battery charge current when
the input current-limit threshold is exceeded, ensuring the
CELLS CELL NUMBER battery charger does not load down the AC adapter voltage.
VDD 4 This constant input current regulation allows the adapter to
GND 3
fully power the system and prevent the AC adapter from
overloading and crashing the system bus.
Float 2
An internal amplifier gm3 compares the voltage between CSIP
and CSIN to the input current limit threshold voltage set by
Setting the Battery Charge Current Limit
ACLIM. Connect ACLIM to REF, Float and GND for the full-
The CHLIM input sets the maximum charging current. The scale input current limit threshold voltage of 100mV, 75mV and
current set by the current sense-resistor connects between 50mV, respectively, or use a resistor divider from VREF to
CSOP and CSON. The full-scale differential voltage between ground to set the input current limit as the following equation
CSOP and CSON is 165mV for CHLIM = 3.3V, so the
1  0.05 
maximum charging current is 4.125A for a 40m sensing IINPUT   VACLIM  0.050 
R2  VREF 
resistor. Other battery charge current-sense threshold values
can be set by connecting a resistor divider from VREF or 3.3V An external resistor divider from VREF sets the voltage at
to ground, or by connecting a low impedance voltage source ACLIM according to:
like a D/A converter in the micro-controller. Unlike VADJ and R bot_ACLIM  152k
ACLIM, CHLIM does not have an internal resistor divider V ACLIM = VREF  ------------------------------------------------------------------------------------------------------
R top_ACLIM  152k + R  152k
network. The charge current limit threshold is given by: bot_ACLIM

165mV V CHLIM where Rbot_ACLIM and Rtop_ACLIM are external resistors at

I CHG = ------------------- ----------------------
R1 3.3V
ACLIM.
To set the trickle charge current for the dumb charger, a To minimize accuracy loss due to interaction with ACLIM's
resistor in series with a switch Q6 (Figure 15) controlled by the internal resistor divider, ensure the AC resistance looking back
micro-controller is connected from CHLIM pin to ground. The into the resistor divider is less than 25k.
trickle charge current is determined by:
When choosing the current sense resistor, note that the
165mV V CHLIM ,trickle voltage drop across this resistor causes further power
I CHG = ------------------- ----------------------------------------
R1 3.3V dissipation, reducing efficiency. The AC adapter current sense
accuracy is very important. Use a 1% tolerance current-sense
When the CHLIM voltage is below 88mV (typical), it will disable resistor. The highest accuracy of ±3% is achieved with 100mV
the battery charge. When choosing the current sensing current-sense threshold voltage for ACLIM = VREF, but it has
resistor, note that the voltage drop across the sensing resistor the highest power dissipation. For example, it has 400mW
causes further power dissipation, reducing efficiency. However, power dissipation for rated 4A AC adapter and 1W sensing
adjusting CHLIM voltage to reduce the voltage across the

FN9203 Rev 2.00 Page 14 of 22

May 23, 2006
ISL6255, ISL6255A

resistor may have to be used. ±4% and ±6% accuracy can be LDO Regulator
achieved with 75mV and 50mV current-sense threshold VDD provides a 5.0V supply voltage from the internal LDO
voltage for ACLIM = Floating and ACLIM = GND, respectively. regulator from DCIN and can deliver up to 30mA of current.
A low pass filter is suggested to eliminate the switching noise. The MOSFET drivers are powered by VDDP, which must be
Connect the resistor to CSIN pin instead of CSIP pin because connected to VDDP as shown in Figure 15. VDDP connects to
CSIN pin has lower bias current and less influence on the VDD through an external low pass filter. Bypass VDDP and
current-sense accuracy. VDD with a 1µF capacitor.

AC Adapter Detection Shutdown

Connect the AC adapter voltage through a resistor divider to The ISL6255, ISL6255A features a low-power shutdown mode.
ACSET to detect when AC power is available, as shown in Driving EN low shuts down the ISL6255, ISL6255A. In
Figure 15. ACPRN is an open-drain output and is high when shutdown, the DC/DC converter is disabled, and VCOMP and
ACSET is less than Vth,rise, and active low when ACSET is ICOMP are pulled to ground. The ICM, ACPRN and DCPRN
above Vth,fall. Vth,rise and Vth,fall are given by: outputs continue to function.

R  EN can be driven by a thermistor to allow automatic shutdown

Vth ,rise   8  1   VACSET
 R9 
of the ISL6255, ISL6255A when the battery pack is hot. Often a
NTC thermistor is included inside the battery pack to measure
its temperature. When connected to the charger, the thermistor
R  forms a voltage divider with a resistive pull-up to the VREF.
Vth,fall   8  1   V ACSET  I hys R8
R
 9  The threshold voltage of EN is 1.0V with 60mV hysteresis. The
thermistor can be selected to have a resistance vs temperature
Where Ihys is the ACSET input bias current hysteresis and characteristic that abruptly decreases above a critical
VACSET = 1.24V (min), 1.26V (typ) and 1.28V (max). The temperature. This arrangement automatically shuts down the
hysteresis is IhysR8, where Ihys = 2.2µA (min), 3.4µA (typ) and ISL6255, ISL6255A when the battery pack is above a critical
4.4µA (max). temperature.
DC Adapter Detection Another method for inhibiting charging is to force CHLIM below
Connect the DC adapter voltage like aircraft power through a 85mV (typ).
resistor divider to DCSET to detect when DC power is
available, as shown in Figure 16. DCPRN is an open-drain
Supply Isolation
output and is high when DCSET is less than Vth,rise, and If the voltage across the adapter sense resistor R2 is typically
active low when DCSET is above Vth,fall. Vth,rise and Vth,fall greater than 8mV, the P-channel MOSFET controlled by
are given by: SGATE is turned on reducing the power dissipation. If the
 R 14 
voltage across the adapter sense resistor R2 is less than 3mV,
V th rise =  ---------- + 1  V DCSET SGATE turns off the P-channel MOSFET isolating the adapter
 R 15 
from the system bus.

Battery Power Source Selection and Aircraft Power

 R 14  Application
V th fall =  ---------- + 1  V DCSET – I hys R 14
 R 15  The battery voltage is monitored by CSON. If the battery voltage
measured on CSON is less than the adapter voltage measured
Where Ihys is the DCSET input bias current hysteresis and on DCIN, then the P-channel MOSFET controlled by BGATE
VDCSET = 1.24V (min), 1.26V (typ) and 1.28V (max). The turns off and the P-channel MOSFET controlled by SGATE is
hysteresis is IhysR14, where Ihys = 2.2µA (min), 3.4µA (typ) allowed to turn on when the adapter current is high enough. If it is
and 4.4µA (max). greater, then the P-channel MOSFET controlled by SGATE turns
Current Measurement off and BGATE turns on the battery discharge P-channel
MOSFET to minimize the power loss. Also, the charging function
Use ICM to monitor the input current being sensed across
is disabled. If designing for airplane power, DCSET is tied to a
CSIP and CSIN. The output voltage range is 0 to 2.5V. The
resistor divider sensing the adapter voltage. When a user is
voltage of ICM is proportional to the voltage drop across CSIP
plugged into the 15V airplane supply and the battery voltage is
and CSIN, and is given by the following equation:
lower than 15V, the MOSFET driven by BGATE (See Figure 16) is
ICM = 19.9  I INPUT  R 2 turned off which keeps the battery from supplying the system bus.
The comparator looking at CSON and DCIN has 300mV of
hysteresis to avoid chattering. Only 2S and 3S are supported for
where IINPUT is the DC current drawn from the AC adapter.
DC aircraft power applications. For 4S battery packs, set
ICM has ±3% accuracy. It is recommended to have an RC filter
DCSET = 0.
at the ICM output for minimizing the switching noise.

FN9203 Rev 2.00 Page 15 of 22

May 23, 2006
ISL6255, ISL6255A

Short Circuit Protection and 0V Battery Charging the output voltage. The RMS value of the output ripple current
Since the battery charger will regulate the charge current to the Irms is given by:
limit set by CHLIM, it automatically has short circuit protection VIN ,MAX
and is able to provide the charge current to wake up an IRMS  D 1  D 
12 L fs
extremely discharged battery.
where the duty cycle D is the ratio of the output voltage (battery
Over Temperature Protection
voltage) over the input voltage for continuous conduction mode
If the die temp exceeds 150°C, it stops charging. Once the die which is typical operation for the battery charger. During the
temp drops below 125°C, charging will start up again. battery charge period, the output voltage varies from its initial
battery voltage to the rated battery voltage. So, the duty cycle
Application Information change can be in the range of between 0.5 and 0.88 for the
The following battery charger design refers to the typical minimum battery voltage of 10V (2.5V/Cell) and the maximum
application circuit in Figure 15, where typical battery battery voltage of 16.8V. The maximum RMS value of the
configuration of 4S2P is used. This section describes how to output ripple current occurs at the duty cycle of 0.5 and is
select the external components including the inductor, input expressed as:
and output capacitors, switching MOSFETs, and current
VIN ,MAX
sensing resistors. I RMS 
4 12 L f s
Inductor Selection
The inductor selection has trade-offs between cost, size and For VIN,MAX = 19V, L = 10H, and fs = 300kHz, the maximum
efficiency. For example, the lower the inductance, the smaller RMS current is 0.46A. A typical 10µF ceramic capacitor is a
the size, but ripple current is higher. This also results in higher good choice to absorb this current and also has very small
AC losses in the magnetic core and the windings, which size. The tantalum capacitor has a known failure mechanism
decrease the system efficiency. On the other hand, the higher when subjected to high surge current.
inductance results in lower ripple current and smaller output EMI considerations usually make it desirable to minimize ripple
filter capacitors, but it has higher DCR (DC resistance of the current in the battery leads. Beads may be added in series with
inductor) loss, and has slower transient response. So, the the battery pack to increase the battery impedance at 300kHz
practical inductor design is based on the inductor ripple current switching frequency. Switching ripple current splits between
being ±(15-20)% of the maximum operating DC current at the battery and the output capacitor depending on the ESR of
maximum input voltage. The required inductance can be the output capacitor and battery impedance. If the ESR of the
calculated from: output capacitor is 10m and battery impedance is raised to
VIN ,MAX  VBAT VBAT 2 with a bead, then only 0.5% of the ripple current will flow in
L
 IL VIN ,MAX fs the battery.

Where VIN,MAX, VBAT, and fs are the maximum input voltage, MOSFET Selection
battery voltage and switching frequency, respectively. The The Notebook battery charger synchronous buck converter
inductor ripple current I is found from: has the input voltage from the AC adapter output. The
maximum AC adapter output voltage does not exceed 25V.
 I L  30%  I BAT,MAX
Therefore, 30V logic MOSFET should be used.
where the maximum peak-to-peak ripple current is 30% of the The high side MOSFET must be able to dissipate the
maximum charge current is used. conduction losses plus the switching losses. For the battery
For VIN,MAX = 19V, VBAT = 16.8V, IBAT,MAX = 2.6A, and charger application, the input voltage of the synchronous buck
fs = 300kHz, the calculated inductance is 8.3µH. Choosing the converter is equal to the AC adapter output voltage, which is
closest standard value gives L = 10µH. Ferrite cores are often relatively constant. The maximum efficiency is achieved by
the best choice since they are optimized at 300kHz to 600kHz selecting a high side MOSFET that has the conduction losses
operation with low core loss. The core must be large enough equal to the switching losses. Ensure that ISL6255, ISL6255A
not to saturate at the peak inductor current IPeak: LGATE gate driver can supply sufficient gate current to prevent
it from conduction, which is due to the injected current into the
1
I Peak  I BAT ,MAX   IL drain-to-source parasitic capacitor (Miller capacitor Cgd), and
2
caused by the voltage rising rate at phase node at the time
Output Capacitor Selection instant of the high-side MOSFET turning on; otherwise, cross-
The output capacitor in parallel with the battery is used to conduction problems may occur. Reasonably slowing turn-on
absorb the high frequency switching ripple current and smooth speed of the high-side MOSFET by connecting a resistor
between the BOOT pin and gate drive supply source, and the

FN9203 Rev 2.00 Page 16 of 22

May 23, 2006
ISL6255, ISL6255A

high sink current capability of the low-side MOSFET gate driver because there is less stray inductance due to a short
help reduce the possibility of cross-conduction. connection. This Schottky diode is optional and may be
removed if efficiency loss can be tolerated. In addition, ensure
For the high-side MOSFET, the worst-case conduction losses
that the required total gate drive current for the selected
occur at the minimum input voltage:
MOSFETs should be less than 24mA. So, the total gate charge
VOUT 2 for the high-side and low-side MOSFETs is limited by the
PQ1,Conduction  I BAT R DSON
VIN following equation:

The optimum efficiency occurs when the switching losses

I GATE
QGATE 
equal the conduction losses. However, it is difficult to calculate fs
the switching losses in the high-side MOSFET since it must
Where IGATE is the total gate drive current and should be less
allow for difficult-to-quantify factors that influence the turn-on
than 24mA. Substituting IGATE = 24mA and fs = 300kHz into
and turn-off times. These factors include the MOSFET internal
the previous equation yields that the total gate charge should
gate resistance, gate charge, threshold voltage, stray
be less than 80nC. Therefore, the ISL6255, ISL6255A easily
inductance, pull-up and pull-down resistance of the gate driver.
drives the battery charge current up to 8A.
The following switching loss calculation provides a rough
estimate. Input Capacitor Selection
1 Qgd 1 Qgd The input capacitor absorbs the ripple current from the
PQ1,Switching  VIN ILV fs  VIN ILP fs  QrrVIN fs synchronous buck converter, which is given by:
2 Ig ,source 2 Ig ,sin k
VOUT VIN  VOUT 
Where Qgd: drain-to-gate charge, Qrr: total reverse recovery Irms  IBAT
VIN
charge of the body-diode in low side MOSFET, ILV: inductor valley
current, ILP: Inductor peak current, Ig,sink and Ig,source are the This RMS ripple current must be smaller than the rated RMS
peak gate-drive source/sink current of Q1, respectively. current in the capacitor datasheet. Non-tantalum chemistries
To achieve low switching losses, it requires low drain-to-gate (ceramic, aluminum, or OSCON) are preferred due to their
charge Qgd. Generally, the lower the drain-to-gate charge, the resistance to power-up surge currents when the AC adapter is
higher the on-resistance. Therefore, there is a trade-off plugged into the battery charger. For Notebook battery charger
between the on-resistance and drain-to-gate charge. Good applications, it is recommend that ceramic capacitors or
MOSFET selection is based on the Figure of Merit (FOM), polymer capacitors from Sanyo be used due to their small size
which is a product of the total gate charge and on-resistance. and reasonable cost.
Usually, the smaller the value of FOM, the higher the efficiency Table 2 shows the component lists for the typical application
for the same application. circuit in Figure 15.
For the low-side MOSFET, the worst-case power dissipation TABLE 2. COMPONENT LIST
occurs at minimum battery voltage and maximum input
PARTS PART NUMBERS AND MANUFACTURER
voltage:
C1, C10 10F/25V ceramic capacitor, Taiyo Yuden
 V  2 TMK325 MJ106MY X5R (3.2x2.5x1.9mm)
PQ2  1  OUT  I BAT R DSON

 VIN  C2, C4, C8 0.1F/50V ceramic capacitor

Choose a low-side MOSFET that has the lowest possible on- C3, C7, C9 1F/10V ceramic capacitor, Taiyo Yuden
resistance with a moderate-sized package like the SO-8 and is LMK212BJ105MG
reasonably priced. The switching losses are not an issue for C5 10nF ceramic capacitor
the low side MOSFET because it operates at zero-voltage-
C6 6.8nF ceramic capacitor
switching.
C11 3300pF ceramic capacitor
Choose a Schottky diode in parallel with low-side MOSFET Q2
D1 30V/3A Schottky diode, EC31QS03L (optional)
with a forward voltage drop low enough to prevent the low-side
MOSFET Q2 body-diode from turning on during the dead time. D2 100mA/30V Schottky Diode, Central Semiconductor
This also reduces the power loss in the high-side MOSFET L 10H/3.8A/26m, Sumida, CDRH104R-100
associated with the reverse recovery of the low-side MOSFET
Q1, Q2 30V/35m, FDS6912A, Fairchild
Q2 body diode.
Q3, Q4 -30V/30m, SI4835BDY, Siliconix
As a general rule, select a diode with DC current rating equal
to one-third of the load current. One option is to choose a Q5 Signal P-channel MOSFET, NDS352AP
combined MOSFET with the Schottky diode in a single Q6 Signal N-channel MOSFET, 2N7002
package. The integrated packages may work better in practice

FN9203 Rev 2.00 Page 17 of 22

May 23, 2006
ISL6255, ISL6255A

TABLE 2. COMPONENT LIST (Continued) Transfer function F2(S) from control to inductor current is:
PARTS PART NUMBERS AND MANUFACTURER S
1
z
F2 S  
Vin
î L
R1 40m, ±1%, LRC-LR2512-01-R040-F, IRC  1
d̂ Ro  RL S 2 S , where  z  .
 1 Ro Co
R2 20m, ±1%, LRC-LR2010-01-R020-F, IRC  o2  oQ p
R3 18, 5%, (0805)
Current loop gain Ti(S) is expressed as the following equation:
R4 2.2, 5%, (0805)
T i  S  = 0.25 R T F 2  S M
R5 100k, 5%, (0805)

R6 10k, 5%, (0805)

where RT is the trans-resistance in current loop. RT is usually
R7 100, 5%, (0805) equal to the product of the charging current sensing resistance
R8, R11 130k, 1%, (0805) and the gain of the current sense amplifier, CA2. For ISL6255,
ISL6255A, RT = 20R1.
R9 10.2k, 1%, (0805)
The voltage gain with open current loop is:
R10 4.7, 5%, (0805)
T v  S  = KM F 1  S A V  S 
R12 20k, 1%, (0805)
VFB
R13 1.87k, 1%, (0805) Where K  , VFB is the feedback voltage of the voltage
Vo
error amplifier. The Voltage loop gain with current loop closed
Loop Compensation Design is given by:
ISL6255, ISL6255A uses a constant frequency current mode
Tv S 
control architecture to achieve fast loop transient response. An Lv ( S ) 
1  Ti S 
accurate current sensing resistor in series with the output
inductor is used to regulate the charge current, and the sensed If Ti(S)>>1, then it can be simplified as follows:
current signal is injected into the voltage loop to achieve S
1 + ------------
current mode control to simplify the loop compensation design. 4 VF B  RO + RL   esr 1
L V  S  = --------------- ------------------------------ ------------------------ A V  S   P  -----------------
The inductor is not considered as a state variable for current VO RT S RO CO
1 + -------
mode control and the system becomes a single order system. P
It is much easier to design a compensator to stabilize the
voltage loop than voltage mode control. Figure 17 shows the From the above equation, it is shown that the system is a
small signal model of the synchronous buck regulator. single order system, which has a single pole located at  p
before the half switching frequency. Therefore, simple type II
PWM Comparator Gain Fm: compensator can be easily used to stabilize the system.
The PWM comparator gain Fm for peak current mode control
is given by: L
î in îL v̂ o
+

11
M = --------- .
V IN Vind̂
v̂ in ILd̂ 1:D
+ Rc
Power Stage Transfer Functions RT
Ro
Transfer function F1(S) from control to output voltage is:
VCA2 Co
S
1
 esr
F1 S   o  Vin
v̂
Ti(S)
d̂ S2 S
 1 d̂
 o2  oQ p K
11/Vin
1
, o 
1 Co
Where  esr  , Q p  Ro
LC o
Rc Co L
0.25VCA2 +
-
Tv(S)

v̂ comp
-Av(S)

FIGURE 17. SMALL SIGNAL MODEL OF SYNCHRONOUS

BUCK REGULATOR

FN9203 Rev 2.00 Page 18 of 22

May 23, 2006
ISL6255, ISL6255A

Vo
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
VFB As a general rule, power layers should be close together, either
- VCOMP on the top or bottom of the board, with signal layers on the
VREF gm opposite side of the board. As an example, layer arrangement
+
on a 4-layer board is shown below:
R1
1. Top Layer: signal lines, or half board for signal lines and the
C1 other half board for power lines
2. Signal Ground
3. Power Layers: Power Ground
FIGURE 18. VOLTAGE LOOP COMPENSATOR 4. Bottom Layer: Power MOSFET, Inductors and other Power
traces
Figure 17 shows the voltage loop compensator, and its transfer
function is expressed as follows: Separate the power voltage and current flowing path from the
control and logic level signal path. The controller IC will stay on
S
1 the signal layer, which is isolated by the signal ground to the
v̂ comp  cz
Av S    gm power signal traces.
v̂ FB SC1

1 Component Placement
where  cz 
R1C1 The power MOSFET should be close to the IC so that the gate
Compensator design goal: drive signal, the LGATE, UGATE, PHASE, and BOOT, traces
can be short.
• High DC gain
1 1  Place the components in such a way that the area under the IC
• Loop bandwidth fc:    fs
 5 20  has less noise traces with high dv/dt and di/dt, such as gate
• Gain margin: >10dB signals and phase node signals.
• Phase margin: 40° Signal Ground and Power Ground Connection
The compensator design procedure is as follows: At minimum, a reasonably large area of copper, which will
shield other noise couplings through the IC, should be used as
1. Put compensator zero at
signal ground beneath the IC. The best tie-point between the
cz  1  3 
1
signal ground and the power ground is at the negative side of
RoCo the output capacitor on each side, where there is little noise; a
2. Put one compensator pole at zero frequency to achieve noisy trace beneath the IC is not recommended.
high DC gain, and put another compensator pole at either
GND and VDD Pin
esr zero frequency or half switching frequency, whichever is
lower. At least one high quality ceramic decoupling cap should be
The loop gain Tv(S) at cross over frequency of fc has unity used to cross these two pins. The decoupling cap can be put
gain. Therefore, the compensator resistance R1 is determined close to the IC.
by: LGATE Pin
2 fcVo C o RT
8 This is the gate drive signal for the bottom MOSFET of the
R1 
11 g mVFB buck converter. The signal going through this trace has both
high dv/dt and high di/dt, and the peak charging and
where gm is the trans-conductance of the voltage loop error discharging current is very high. These two traces should be
amplifier. Compensator capacitor C1 is then given by: short, wide, and away from other traces. There should be no
1 other traces in parallel with these traces on any layer.
C1 
R1  cz
PGND Pin
Example: Vin = 20V, Vo = 16.8V, Io = 2.6A, fs = 300kHz, PGND pin should be laid out to the negative side of the
Co = 10F/10m, L = 10H, gm = 250s, RT = 0.8, relevant output cap with separate traces.The negative side of
VFB = 2.1V, fc = 20kHz, then compensator resistance the output capacitor must be close to the source node of the
R1 = 10k. Put the compensator zero at 1.5kHz. The bottom MOSFET. This trace is the return path of LGATE.
compensator capacitor is C1 = 6.5nF. Therefore, choose
voltage loop compensator: R1 = 10k, C1 = 6.5nF.

FN9203 Rev 2.00 Page 19 of 22

May 23, 2006
ISL6255, ISL6255A

PHASE Pin DCIN Pin

This trace should be short, and positioned away from other This pin connects to AC adapter output voltage, and should be
weak signal traces. This node has a very high dv/dt with a less noise sensitive.
voltage swing from the input voltage to ground. No trace
Copper Size for the Phase Node
should be in parallel with it. This trace is also the return path for
UGATE. Connect this pin to the high-side MOSFET source. The capacitance of PHASE should be kept very low to
minimize ringing. It would be best to limit the size of the
UGATE Pin PHASE node copper in strict accordance with the current and
This pin has a square shape waveform with high dv/dt. It thermal management of the application.
provides the gate drive current to charge and discharge the top
Identify the Power and Signal Ground
MOSFET with high di/dt. This trace should be wide, short, and
away from other traces similar to the LGATE. The input and output capacitors of the converters, the source
terminal of the bottom switching MOSFET PGND should
BOOT Pin connect to the power ground. The other components should
This pin’s di/dt is as high as the UGATE; therefore, this trace connect to signal ground. Signal and power ground are tied
should be as short as possible. together at one point.

CSOP, CSON Pins Clamping Capacitor for Switching MOSFET

The current sense resistor connects to the CSON and the It is recommended that ceramic caps be used closely
CSOP pins through a low pass filter. The CSON pin is also connected to the drain of the high-side MOSFET, and the
used as the battery voltage feedback. The traces should be source of the low-side MOSFET. This capacitor reduces the
away from the high dv/dt and di/di pins like PHASE, BOOT noise and the power loss of the MOSFET.
pins. In general, the current sense resistor should be close to
the IC. Other layout arrangements should be adjusted
accordingly.

EN Pin
This pin stays high at enable mode and low at idle mode and is
relatively robust. Enable signals should refer to the signal
ground.

FN9203 Rev 2.00 Page 20 of 22

May 23, 2006
ISL6255, ISL6255A

Quad Flat No-Lead Plastic Package (QFN) L28.5x5

Micro Lead Frame Plastic Package (MLFP) 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
2X (COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE I)
0.15 C A
A D MILLIMETERS

9 SYMBOL MIN NOMINAL MAX NOTES

D/2
A 0.80 0.90 1.00 -
D1
A1 - 0.02 0.05 -
D1/2
2X
A2 - 0.65 1.00 9
N 0.15 C B
6
INDEX A3 0.20 REF 9
AREA 1 E1/2 E/2 b 0.18 0.25 0.30 5,8
2
3 E1 D 5.00 BSC -
E
D1 4.75 BSC 9
9
2X D2 2.95 3.10 3.25 7,8
0.15 C B
E 5.00 BSC -
2X B
TOP VIEW E1 4.75 BSC 9
0.15 C A
E2 2.95 3.10 3.25 7,8
4X
0 A2
A / / 0.10 C e 0.50 BSC -
C
0.08 C
k 0.20 - - -
L 0.50 0.60 0.75 8
SEATING PLANE SIDE VIEW A3 A1
9 N 28 2
NX b 5 Nd 7 3
0.10 M C A B Ne 7 3
4X P
D2 7 8
P - - 0.60 9
(DATUM B) NX k
D2  - - 12 9
2 N
Rev. 1 11/04
4X P
1 NOTES:
(DATUM A) 2
3 (Ne-1)Xe 1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
6 E2 REF. 2. N is the number of terminals.
INDEX 7
AREA 3. Nd and Ne refer to the number of terminals on each D and E.
E2/2
NX L 8 4. All dimensions are in millimeters. Angles are in degrees.
N e 5. Dimension b applies to the metallized terminal and is measured
9
8 (Nd-1)Xe CORNER
between 0.15mm and 0.30mm from the terminal tip.
REF. OPTION 4X 6. The configuration of the pin #1 identifier is optional, but must be
BOTTOM VIEW located within the zone indicated. The pin #1 identifier may be
A1 either a mold or mark feature.
NX b
7. Dimensions D2 and E2 are for the exposed pads which provide
5 improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
SECTION "C-C"
C
L 9. Features and dimensions A2, A3, D1, E1, P &  are present when
C
L Anvil singulation method is used and not present for saw
singulation.
L L
10 10
L1 L1

e e
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE

FN9203 Rev 2.00 Page 21 of 22

May 23, 2006
ISL6255, ISL6255A

Shrink Small Outline Plastic Packages (SSOP)

Quarter Size Outline Plastic Packages (QSOP)

N M28.15
INDEX 28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
AREA H 0.25(0.010) M B M
(0.150” WIDE BODY)
E
GAUGE INCHES MILLIMETERS
-B- PLANE
SYMBOL MIN MAX MIN MAX NOTES

1 2 3 A 0.053 0.069 1.35 1.75 -

A1 0.004 0.010 0.10 0.25 -
L
SEATING PLANE 0.25 A2 - 0.061 - 1.54 -
0.010
-A- B 0.008 0.012 0.20 0.30 9
D A h x 45°
C 0.007 0.010 0.18 0.25 -
-C- D 0.386 0.394 9.81 10.00 3

A2
E 0.150 0.157 3.81 3.98 4
e A1
C e 0.025 BSC 0.635 BSC -
B 0.10(0.004)
H 0.228 0.244 5.80 6.19 -
0.17(0.007) M C A M B S
h 0.0099 0.0196 0.26 0.49 5
NOTES: L 0.016 0.050 0.41 1.27 6
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 N 28 28 7
of Publication Number 95.
 0° 8° 0° 8° -
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Rev. 1 6/04
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual in-
dex feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dam-
bar protrusion shall be 0.10mm (0.004 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.

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For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com

FN9203 Rev 2.00 Page 22 of 22

May 23, 2006