Advanced

Verification program
Course Curriculum

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 Advanced Verification Course - Module 1
SystemVerilog (Verification)
➢ SystemVerilog Overview
Live Session
➢ Standard Data types & Literals & Operators Theory & Labs
➢ User-Defined Data types & Structures
➢ Tb Architecture & Connectivity Hands on
Experience
➢ Testbench Components
➢ Static, Dynamic, Associative Arrays
➢ Queues Industry
➢ Tasks & Functions Guidance

➢ Interfaces, Virtual Interface

➢ Verification Features Live Doubt
➢ OOPs, Classes Discussion
➢ Polymorphism and Virtuality
Industry
➢ Inheritance, Encapsulation Applications
➢ Clocking Blocks
 Advanced Verification Course - Module 1
SystemVerilog (Verification)
➢ Clocking Blocks
Live Session
➢ Random Stimulus Theory & Labs
➢ Class-Based Random Stimulus
➢ Code Coverage Hands on
Performance Expectations
Experience
Of Employees & Superiors
➢ Deep into Functional coverage
➢ Assertion Based Verification(ABV)
➢ SystemVerilog Assertions Industry
➢ Direct Programming Interface(DPI) Guidance
➢ Interprocess Synchronization
➢ Testbench Components Setting Performance
LiveStandards
Doubt
➢ Testbench Examples Discussion
➢ Testplans, Testcases
Industry
Applications
 Advanced Verification Course - Module 2
UVM (Verification)
➢ Deep understanding of UVM in SOC | IP
Live Session
➢ Detailed explanation on UVC in SOC | IP Theory & Labs
➢ Introduction to UVM, Features
➢ Testbench Hierarchy, Components Hands on
Performance Expectations
Experience
Of Employees & Superiors
➢ UVM Sequence Item, Sequence, Sequencer
➢ Configuration, UVM config_db
➢ UVM Phases
Industry
➢ UVM Driver Guidance
➢ UVM Monitor
➢ UVM Agent Setting Performance
LiveStandards
Doubt
➢ UVM Scoreboard Discussion
➢ UVM Environment
➢ UVM Test Industry
Applications
➢ Creating all Components in a flow
 Advanced Verification Course - Module 2
UVM (Verification)
➢ Understanding of UVM RAL Model
Live Session
➢ Deep into UVM TLM Theory & Labs
➢ Callback
➢ Events Hands on
Performance Expectations
Experience
➢ UVM Test Of Employees & Superiors

➢ UVM Testbench Examples

➢ UVM Testplan Creation
Industry
➢ DTPs(Detailed Test Plan Exaplanation) Guidance
➢ Testcase scenarios
➢ Importance of Regressions Setting Performance
LiveStandards
Doubt
➢ How to Run the Regression Discussion
➢ How to check test pass or fail in SOC | IP
Level Industry
Applications
➢ Idea on debugging testcases, execution flow
 Advanced Verification Course - Module 3
Project | Protocols
➢ AMBA (APB, AHB, AXI) Protocols RTL Design
Live Session
& Verification in SV & UVM Theory & Labs
➢ Deep understand into Signal features of
AMBA Protocols Hands on
Performance Expectations
Experience
Of Employees & Superiors

➢ 1*3 Router Project in UVM Verification

➢ Detailed knowledge on Test plan
Industry
development, writing test cases Guidance

➢ 4 Port Calculator RTL Design & UVM Setting Performance

LiveStandards
Doubt
Verification Discussion

➢ DMA Controller Project with Coverage Industry

Applications
analysis, RTL design & Verification
 Advanced Verification Course - Module 4
Perl Scripting
➢ Importance of Perl Scripting
Live Session
➢ How to run the commands Theory & Labs
➢ Idea on Coverage analysis
➢ Upload and extract the coverage report Hands on
Performance Expectations
Experience
➢ Walk through perl concepts Of Employees & Superiors

➢ Coding standards
➢ Explanation of Data types, Arrays
Industry
➢ Hashes, Loops Guidance
➢ Operators, Subroutines
➢ Date & Time Setting Performance
LiveStandards
Doubt
➢ References, Formats Discussion
➢ Directories
➢ Error Handling Industry
Applications