Synchronous

Sequential Logic

Md. Zubair Alam Emon

https://youtu.be/fXeQxZqU_Bg
Sequential Circuits
• Output depends on current input and past history of inputs.

Inputs Outputs
Combinational
Circuit Memory
Elements
Sequential Circuits
• “State” contains all the information about the past needed to predict
current output based on current input.
• State variables, one or more bits of information.

Inputs Outputs
Combinational
Circuit Flip-flops

Clock pulses

Clock pulses
Real life examples
• A traffic light controller.
• A vending machine (the money acceptance and change return).
• A password checker (in an electronic door lock).
Clock signals
• Very important with most sequential circuits
• State variables change state at clock edge.
Clock
• Using a 555
timer IC /8038
IC
Bistable element
• The simplest sequential circuit
• Two states
• One state variable, say, Q

HIGH LOW

LOW HIGH
Bistable element
• The simplest sequential circuit
• Two states
• One state variable, say, Q

LOW HIGH

HIGH LOW
Metastability
• Metastability is inherent in any bistable circuit

Both transistors
are in saturation.
Huge current flow
causes huge
power loss.

• Two stable points, one metastable point

Figure: Butterfly curve
Another look at metastability
“sube y baja” behavior
Why all the harping on metastability?
• All real systems are subject to it
• Problems are caused by “asynchronous inputs” that do not
meet flip-flop setup and hold times.
• Especially severe in high-speed systems
• Since clock periods are so short, “metastability resolution
time” can be longer than one clock period.
• Many digital designers, products, and companies
have been burned by this phenomenon.
Back to the bistable….
• How to control it?
• Screwdriver
• Control inputs
• S-R latch

(reset)

(set)
SR Latch
S-R latch operation

Metastability is possible
if S and R are negated
simultaneously.
S-R latch timing parameters
• Propagation delay
• Minimum pulse width
S-R latch symbols
S-R latch using NAND gates
S-R latch with enable
D latch

• Level sensitive
D-latch operation

Propagation delay
D-latch timing parameters
• Propagation delay (from C or D)
• Setup time (D before C edge)
• Hold time (D after C edge)
Edge-triggered D flip-flop behavior

Value changes at Q after 1

• Edge sensitive
clk edge/ next state
D flip-flop timing parameters
• Propagation delay (from CLK)
• Setup time (D before CLK)
• Hold time (D after CLK)
Edge-triggered D circuit
• Preset and clear
inputs
• like S-R latch
• 3 feedback
loops
• interesting
analysis
• Light loading on
D and C
Positive Edge triggered D Flipflop
Other D flip-flop variations
• Negative-edge triggered

• Clock enable
Edge-triggered D circuit
• Preset and clear
inputs
• like S-R latch
• 3 feedback
loops
• interesting
analysis
• Light loading on
D and C
Dual D Flipflop
• CLR=0; Q=0
• PR=0;Q=1
Other D flip-flop variations
• Negative-edge triggered

• Clock enable
J-K flip-flops
• Not used
much
anymore

D = JQ’ + K’Q
T flip-flops
T flip-flops
• Important for counters
• D = EN Q

Characteristic Tables & Equations
JK Flip-Flop D Flip-Flop T Flip-Flop
J K Q(t+1) D Q (t+1) T Q (t+1)
0 0 Q(t) No change 0 0 Reset 0 Q (t) No change
0 1 0 Reset 1 1 Set 1 Q’ (t) Complement
1 0 1 Set
1 1 Q’(t) Comlement


Q (t + 1) = D

Q (t + 1) = JQ’ + K’Q
Q (t + 1) = T Q = TQ’ + T’Q

Q(t) represents present state and Q(t+1) represents next state

Analysis of Sequential Ckt
State Equations:
● D0
x ● D Q Q0

● Q(t+1) = D
C QN Q0’
Q0(t+1) = D0 = Q0.x + Q1.x
●
D1 Q1(t+1) = D1 = Q0’.x
● D Q Q1

CLK ● C QN Q1’ y = (Q0 + Q1).x’

y
Analysis of Sequential Ckt
Sate Table Present Next State
Present Next State (Q0*Q1*) Output (y)
State Input State Output (Q0Q1) x=0 x=1 x=0 x=1
Q0 Q1 x Q0 * Q1 * y 00 00 01 0 0

0 0 0 0 0 0 01 00 11 1 0
10 00 10 1 0
0 0 1 0 1 0
11 00 10 1 0
0 1 0 0 0 1
0 1 1 1 1 0 Next State Output
Present
1 0 0 0 0 1 State x=0 x=1 x=0 x=1
1 0 1 1 0 0 A A B 0 0
1 1 0 0 0 1 B A D 1 0
1 1 1 1 0 0 C A C 1 0
D A C 1 0
Q0(t+1) = Q0* = Q0 x + Q1 x
Q1(t+1) = Q1* = Q0’ x
Analysis of Sequential Ckt
• Step 1: Write state and output 0/0 1/0
0/1
equations 00 10
• Determine the flip-flop input eqn in
terms of present state and input 0/1
variables. 1/0 0/1 1/0

• Substitute input equation into flip-

flop characteristic equation to 01
1/0
11
obtain state equation
• Step 2: Generate state table 0/0 1/0
• Use the corresponding state 0/1
equations to determine the next A C
state values in the state table.
• Modify to name the states 1/0 0/1 0/1 1/0

• Step 3: Generate state diagram

1/0
B D
Analysis with D Flip-Flop

x D0
D Q Q● z
y 0

CLK C QN Q0’
Present Inputs Next State
State (Q0) x y (Q0*)
0 0 0 0
0 0 1 1
00, 11 00, 11 0 1 0 1
01, 10
0 1 0 1 1 0
1 0 0 1
01, 10 1 0 1 0
1 1 0 0
1 1 1 1
Practice Problem

x D Q ● F
1
CLK C QN
Analysis with JK Flip-Flop
J0
J Q ●
State Equations:
Q0
C Q0* = J0Q’0 + K’0Q0
x K0 Q’0
● ●
● K QN = Q1Q’0 + (Q1x’)’Q0

J1 = Q’0Q1 + Q0Q’1 + Q0x

J Q ●
Q1
CLK ● C
Q1* = J1Q’1 + K’1Q1
K1
K QN = x’Q’1 + (Q0  x)’Q1
Q’1

= Q’1x’ + Q0Q1x + Q’0Q1x’

J 0 = Q1 K0 = Q1 x’
J1 = x’ K1 = Q’0 x + Q0 x’ = Q0  x
 J0
J Q ●
Q0
C
x K0 Q’0
● ● K QN

J1
J Q ●
Q1
CLK ● C
K1
K QN
0 Q’1
Analysis with JK Flip-Flop
Present Next Flip-Flop 1
Input 1
State State Inputs
0
Q0 Q1 x Q0 * Q1 * J0 K0 J1 K1 00 11

0 0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0 1
0 0 0
0 1 0 1 1 1 1 1 0
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1 01 10
1
1 0 1 1 0 0 0 0 0
1
1 1 0 0 0 1 1 1 1
1 1 1 1 1 1 0 0 0
Analysis with T Flip-Flop
x ● T0
T Q Q y
0

C QN

T1
T Q ●
Q1
CLK ● C QN

State Equations:
T0 = Q1 x Q0* = T0  Q0 = T0Q’0 + T’0Q0 = Q’0Q1x + Q0Q’1 + Q0x’
T1 = x Q1* = T1  Q1 = T1Q’1 + T’1Q1 = Q’1x + Q1x’

y= Q0Q1
Analysis with T Flip-Flop
0
0
Present Next State 1
00/0 01/0
State (Q1*Q0*) Output
(Q1Q0) x=0 x=1 x=0 x=1
00 00 01 0 0 1 1
01 01 10 0 0
10 10 11 0 0
11/1 1
10/0
11 11 00 1 1
0 0

Mealy and Moore Models:

• In Mealy model, the output is a function of
both the present state and input.
• In Moore model, the output is a function of
the present state only.
Output sequence from state diagram

• Starting from state a, and the input sequence 0 1 0 1 0 1 1 0 1

0 0, determine the output sequence for the following state
diagram.
0/0
0/0
a
1/0 0/0

0/0
0/0 b c
1/0 1/0
g 0/0
d e
0/0
1/1
1/1
1/1
State a a b c d e f f g f g
f Input 0 1 0 1 0 1 1 0 1 0 0
1/1 Output 0 0 0 0 0 1 1 0 1 0 0
State Reduction
0/0 Present Next State Output
0/0 State x=0 x=1 x=0 x=1
a
a a b 0 0
1/0 0/0
b c d 0 0
0/0
0/0 b c c a d 0 0
d e f 0 1
1/0 1/0 e a f 0 1
g 0/0
d e f g f 0 1
0/0 g a f 0 1
1/1 1/1
1/1 Present Next State Output
f State x=0 x=1 x=0 x=1
1/1 a a b 0 0
b c d 0 0
c a d 0 0
Both ‘e’ and ‘g’ have same next state d e f 0 1
and same output. So can remove ‘g’ e a f 0 1
and replace all ‘g’ with ‘e’ f e f 0 1
State Reduction
Present Next State Output
0/0
State x=0 x=1 x=0 x=1
a
a a b 0 0
0/0 0/0
b c d 0 0 1/0
c a d 0 0 0/0
e b c
d e d 0 1
e a d 0 1 0/0 1/0
1/1 1/0

Both ‘d’ and ‘f’ have same next state d

and same output. So can remove ‘f’ 1/1
and replace all ‘f’ with ‘d’

Both ‘c’ and ‘e’ have same next state

but different output. So can’t remove
‘e’ and replace with ‘c’
State Assignment
Assignment 1 Assignment 2 Assignment 3
State
Binary Gray code One-hot 3 possible binary
a 000 000 00001 state assignments
b 001 001 00010
c 010 011 00100
d 011 010 01000
e 100 110 10000

Present Next State Output

State x=0 x=1 x=0 x=1
000 000 001 0 0
001 010 011 0 0
Reduced State Table 010 000 011 0 0
with
011 100 011 0 1
Binary Assignment 1
100 000 011 0 1
Design Procedure
• Recommended Steps:
• Derive a state diagram from the specification (i.e. word description)
• Reduce the number of states if necessary
• Assign binary values to the states
• Obtain binary coded state table
• Choose the type of flip-flop to be used
• Derive flip-flop input and output equations
• Draw the logic diagram
State Diagram, Table, Assignment
0 0

Design a circuit that detects A/0 B/0

1
3 or more consecutive 1’s
0 0
in a string of bits coming 1
1
through an input line. 1
D/1 C/0

State Table
Present Next State Output
Present Next State Output ( Q1*Q0* ) (y)
State
State x=0 x=1 x=0 x=1 ( Q1Q0 ) x=0 x=1 x=0 x=1
A A B 0 0 00 00 01 0 0
B A C 0 0 01 00 10 0 0
C A D 0 1 10 00 11 0 1
D A D 0 1 11 00 11 0 1
Next State Equations
Q0x Q0x
Q1 00 01 11 10 Q1 00 01 11 10
0 0 0 1 0 0 0 0 0 0

1 0 1 1 0 1 0 1 1 0

Q1 * = Q1 x + Q 0 x y = x Q1

Present Next State Output

Q0x
State ( Q1*Q0* ) (y)
Q1 00 01 11 10
( Q1Q0 ) x=0 x=1 x=0 x=1
0 0 1 0 0 00 00 01 0 0
01 00 10 0 0
1 0 1 1 0
10 00 11 0 1
Q0* = Q1 x + Q’0 x 11 00 11 0 1
Excitation Tables
Q* = D Q* = JQ’ + K’Q
Q* D Q Q* J K
0 0 0 0 0 X

1 1 0 1 1 X
1 0 X 1
1 1 X 0
Q* = T  Q = TQ’ + T’Q
Q Q* T
0 0 0
0 1 1
1 0 1
1 1 0
Circuit Diagram w/ D Flip-Flop
D Q ● ● Q0
x ● ● ● ●
C QN ● Q’0

y
D Q ● Q1

CLK ● C QN

Q0* = D0 = Q1 x + Q’0 x

Q1* = D1 = Q1 x + Q0 x

y = x Q1
 Circuit Diagram w/ JK Flip-Flop
Q0 x
Present Next 00 01 11 10
Q1
State Input State Flip-Flop Inputs
0 0 1 X X
Q1 Q0 x Q1 * Q0 * J1 K1 J0 K0
1 0 1 X X
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X J0 = x

0 1 0 0 0 0 X X 1
Q0x
0 1 1 1 0 1 X X 1 Q1 00 01 11 10
1 0 0 0 0 X 1 0 X X X 1 1
0
1 0 1 1 1 X 0 1 X
1 X X 0 1
1 1 0 0 0 X 1 X 1
1 1 1 1 1 X 0 X 0 K0 = Q1’ Q0 + Q0 x’

Q1Q0 Q0 x
x 00 01 11 10 Q1 00 01 11 10 Q Q* J K

0 0 0 X
0 0 0 1 0 0 X X X X
0 1 1 X
1 X X X X J1 = Q1 Q0 1 1 0 0 1 K1 = x’ 1 0 X 1
1 1 X 0
Circuit Diagram w/ JK Flip-Flop
x J0
J Q ●
Q0
C
.. K0
K QN
Q’0

J1
J Q ●
Q1
CLK ● C
K1
K QN .Q’ 1

J0 = x J1 = Q1 Q0
K0 = Q1’ Q0 + Q0 x’ K1 = x’
Design w/ T Flip-Flop
Present Flip-Flop Design a 3 000
bit
State Next State Inputs synchronous
001 111
Q2 Q1 Q0 Q2* Q1* Q0* T2 T1 T0 up counter
0 0 0 0 0 1 0 0 1
State
010 110
0 0 1 0 1 0 0 1 1 Diagram
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1 011 101
1 0 0 1 0 1 0 0 1 100
1 0 1 1 1 0 0 1 1 Q1Q0
Q2 00 01 11 10
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1 0 1 1 1 1

1 1 1 1 1 T0 = 1
Q1Q0 Q1Q0
Q2 00 01 11 10 Q2 00 01 11 10

0 0 0 1 0 0 0 1 1 0

1 0 0 1 0 T2 = Q1Q0 1 0 1 1 0 T1 = Q0
Circuit Diagram w/ T Flip-Flop
T2
T Q Q2

C QN

T1 ● T Q ● Q1

● C QN

T0 Q0
1 T Q ●

CLK ● C QN
HDL for Sequential Circuits
• There are 2 kinds of behavioral statements
• initial
• Executes only once beginning at time = 0
• always
• Execute repeatedly and re-executes until the simulation terminates
• A module may contain an arbitrary number of initial or always
statements.
• These statements execute concurrently with respect to each other at
time 0.
HDL for Sequential Circuits
initial initial
begin begin
clock = 0; clock = 0;
repeat (30) #300 $finish;
#10 clock = ~clock; end
end always
#10 clock = ~clock;

always @ (event control expression) A procedural assignment is an

Procedural assignment statement. assignment within an initial or
always statement
always @ (A or B or Reset)
Two kinds of procedural
always @ (posedge clock or negedge reset) assignments: blocking ( = )
and non-blocking ( <= )
Always Block
• Verilog syntax requires that procedural statement be
contained inside an always block.
• An always block can contain one or more statement(s).
• Statements inside an always block are evaluated in
the order given in the code.
• Continuous assignment statements are evaluated
concurrently.
• Part of always block after @ is called sensitivity list.
• The statements inside an always block are executed by the
simulator only when one or more of the signals in the
sensitivity list changes value.
Procedural Statement
• Procedural statement must be placed inside an always block
• e.g. for statement, if-else statement etc.
• Any signal that is assigned a value by a statement within an always
block must retain this value until it is re-evaluated.
• Such signals are declared to be of reg type
• Changes in the sensitivity variables given in the always statement
invokes the re-evaluation of the procedural statements
Latches & Flops
always @( Control or B ) What happens if Control = 0 ?
if( Control )
A=B

In the absence of an assigned value, the Verilog compiler assumes that the
value of A caused by the if statement must be maintained until the next time
this if statement is evaluated. This notion of implied memory is realized by
instantiating a latch in the circuit.

module D_latch ( Q, D, Clk ); module D_FF ( Q, D, Clk );

input D, Clk; input D, Clk;
output reg Q; output reg Q;

always @ (D, Clk) always @ (posedge Clk)

if( Clk ) Q = D;
Q = D; endmodule
endmodule
Flip-Flops
module TFF ( Q, T, CLK, RST ); module JKFF ( Q, J, K, CLK, RST );
output Q; output Q;
input T, CLK, RST; input J, K, CLK, RST;
wire DT; wire JK;
assign DT = Q ^ T; assign JK = (J & ~Q) | (~K & Q);
DFF TF1 ( Q, DT, CLK, RST ); DFF JK1 ( Q, JK, CLK, RST );
endmodule endmodule

module DFF ( Q, D, CLK, RST );

output reg Q;
input D, CLK, RST;
always @ (posedge CLK or negedge RST)
if (~RST) Q = 1’b0; D flip-flop with
else Q = D; asynchronous
endmodule reset
JK and T Flip-Flop
module JK_FF ( Q, Qn, J, K, CLK ); module T_FF ( Q, Qn, T, CLK );
output Q, Qn; output Q, Qn;
input J, K, CLK; input T, CLK;
reg Q; reg Q;
assign Qn = ~ Q; assign Qn = ~ Q;
always @ ( posedge CLK ) always @ ( posedge CLK )
case ( J, K ) if ( T ) Q = ~ Q;
2’b00 : Q = Q; else Q = Q;
2’b01 : Q = 1’b0; endmodule
2’b10 : Q = 1’b1;
2’b11 : Q = ~ Q;
endcase
endmodule
Blocking & Non-Blocking Assignment
• = creates a blocking assignment.
• If a variable is given a value by blocking assignment statement, then this new
value is used in evaluating all subsequent statements in the block.
• <= creates a non-blocking assignment
• All non-blocking assignment statements in an always block are evaluated
using the values that the variables have when the always block is entered.
• A given variable has the same value for all statements in the block.
• The meaning of non-blocking is that the result of each assignment is not seen
until the end of always block
Assignment
D D Q Q1
module non_shift_reg (D, Clk, Q1, Q2);
input D, Clk;
Clk
output reg Q1, Q2;
always @(posedge Clk)
D Q Q2
begin
Q1 = D;
Q2 = Q1;
end The synthesized ckt has 2 parallel flops, one of
endmodule which will likely get deleted during optimization

module shift_reg (D, Clk, Q1, Q2);

input D, Clk; Q1
D D Q D Q Q2
output reg Q1, Q2;
always @(posedge Clk)
begin Clk
Q1 <= D;
Q2 <= Q1; The synthesized ckt has 2 cascaded flops,
end which implements a shift register.
endmodule
Example
Consider the following statements assuming that RegA contains the
value of 50 initially.
(a) RegA = 125; (b) RegA <= 125;
RegB = RegA; RegB <= RegA;
What are the values of RegA and RegB after execution?

Solution:
(a) RegA=125;
RegB=125;

(b) RegA=125;
RegB=50;
HDL to Circuit (<= , =)
module Seq_Ckt ( input A, B, C, output reg Q,input CLK,);
reg E;
With non-blocking (<=)
always @ ( posedge CLK)
begin
E <= A && B;
Q <= E || C;
end
endmodule

Now draw the circuit of the

above HDL.
With blocking (=)
Also draw the circuit with
blocking assignment.
State Diagram in HDL
module Mealy_mdl ( y, x, CLK, RST ); 0/0 1/0
input x, CLK, RST;
0/1
output reg y; A C
reg [1:0] Prstate, Nxtstate;
parameter A=2’b00, B=2’b01, C=2’b10, D=2’b11; 1/0 0/1 0/1 1/0
always @ (posedge CLK or negedge RST)
if ( ~RST ) Prstate = A; // initialize 1/0
else Prstate = Nxtstate; B D
always @ (Prstate or x) // next state
case (Prstate)
A : Nxtstate = ( x ) ? B : A; always @ ( Prstate or x ) // output
B : Nxtstate = ( x ) ? D : A; case
C : Nxtstate = ( ~x ) ? A : C; A : y = 0;
D : Nxtstate = ( x ) ? C : A; B : y = ( x ) ? 1’b0 : 1’b1;
endcase C : y = ( x ) ? 1’b0 : 1’b1;
D : y = ( x ) ? 1’b0 : 1’b1;
endcase
endmodule
State Diagram in HDL
1
module Moore_mdl (x, AB, CLK, RST); 1
input x, CLK, RST; 0
00 11
output [1:0] AB;
reg [1:0] state;
parameter A=2’b00, B=2’b01, C=2’b10, D=2’b11;
0 0 0
always @ (posedge CLK or negedge RST)
if ( ~RST ) state = A; // initialize
else
case ( state )
01 1
10
A : state = ( ~x ) ? B : A;
B : state = ( x ) ? C : D; 1
C : state = ( ~x ) ? D : C;
D : state = ( ~x ) ? A : D;
endcase
assign AB = state; // output of flip-flop
endmodule
 Structural Description
x ● T0
T Q Q y
0

C module T_FF (Q, T, CLK);

input T, CLK;
output reg Q;
T1
T Q ●
Q1 always @ (posedge CLK)
Q = Q ^ T;
CLK ● C endmodule

module Tckt (x, y, Q0, Q1, CLK); module Tckt_tb;

input x, CLK; reg x, CLK;
output y, Q0, Q1; wire y, Q0, Q1;
wire T0, T1; initial begin
Tckt TC (x, y, Q0, Q1, CLK);
assign T1 = x, //input eqn x = 0;
T0 = x & Q1; initial begin #15 x = 1;
assign y = Q0 & Q1; CLK = 0; repeat (8)
T_FF TF0 (Q0, T0, CLK); repeat (16) #10 x = ~x;
T_FF TF1 (Q1, T1, CLK); #5 CLK = ~CLK; end
endmodule end endmodule
 A ●
T0 T Q Q F
0

RST ●
T Q ●
T1 Q1
CLK ● C
HW – text book: 4 th edition
• 5-2, 5-4, 5-6~5-10, 5-12, 5-13, 5-16, 5-18, 5-19(a), 5-22~5-24, 5-26, 5-
30, 5-31, 5-35, 5-36, 5-38, 5-40, 5-44