HING

UBLIS
AM P
INGR
D BY
ENSE
E LIC
IMAG
ND
GROU
BACK

Time-Encoding Georges G.E. Gielen,

Luis Hernandez,
and Pieter Rombouts

Analog-to-Digital
Converters
Bridging the analog gap to advanced digital CMOS—
Part 1: Basic principles

T
he scaling of CMOS large in area and have a high power ticular, to analog-to-digital converters
technology deep into consumption in spite of the process (ADCs) based on voltage-controlled
the nanometer range scaling. Analog circuits based on time oscillators (VCOs), one of the most
has created challenges encoding [1], [2] and hybrid analog/ successful time-encoding techniques
for the design of high- digital signal processing [3] have been to date.
performance analog ICs. The shrinking developed to overcome these issues. Although VCO-based ADCs have
supply voltage and presence of mis- Realizing analog circuit functionality been around for a long time [4], [5],
match and noise restrain the dynamic with highly digital circuits results in they really received a significant
range, causing analog circuits to be more scalable design solutions that boost in interest after Straayer and
can achieve excellent performance. Perrott’s highly cited 2008 paper
Digital Object Identifier 10.1109/MSSC.2020.2987536 This article reviews the basic princi- [6]. Since then, many other advance-
Date of current version: 24 June 2020 ples of time encoding applied, in par- ments from different research groups

1943-0582/20©2020IEEE IEEE SOLID-STATE CIRCUITS MAGAZINE SPRING 2020 47

Authorized licensed use limited to: Phanumas Khumsat. Downloaded on April 07,2023 at 14:04:28 UTC from IEEE Xplore. Restrictions apply.
 now be a simple flip-flop, as the signal
The main idea behind time encoding consists of
has only two values. From the sampled
representing an analog signal with a modulated square wave, a decoder can recon-
square wave, where the signal information struct a multibit approximation of the
analog input signal, which is typically
is encoded in the transitions instead of in done with a digital low-pass filter.
the instantaneous amplitude. Although early time-encoding ADCs
used PWM [1], [2], PWM may not be the
best option to replace analog circuits
worldwide have been published in circuits and robust against noise and in an ADC. Indeed, PWM modulators
application domains such as sensor distortion. Representing the analog sig- require sawtooth generators or analog
readout [7]–[10], telecom [11]–[13], nal information is, then, done through filters, which are still made of opera-
wideband wireless [14]–[18], the Inter- pulse modulations. Pulsewidth modu- tional amplifiers (op-amps) and other
net of Things [19], automotive [20], lation (PWM) is one of the best exam- highly linear circuits [28], [29]. VCO-
[21], and biomedical [22] –[24], to ples and is used extensively in, for based ADCs, on the other hand, can
name a few. Note that the integrat­­ instance, power electronics. The typi- be implemented very efficiently with
ing properties of VCOs have also cal block diagram of a time-encoding a ring oscillator, which is a simple
been used to implement continuous- ADC is shown in Figure 1. The analog digital circuit [30], [31]. To be precise,
time filters, time-to-digital converters, input signal is applied to a pulse mod- VCO-based ADCs need to be modeled
and other analog signal processing ulator that encodes the information using a different type of pulse modu-
blocks [25]–[27]. in the pulsewidth, frequency, or posi- lation, called pulse-frequency modu-
The main idea behind time encod- tion of a signal (or set of signals) with lation (PFM). PFM exhibits first-order
ing consists of representing an ana- two levels only. This two-level sig- noise shaping when sampled directly,
log signal with a modulated square nal, which is still analog, is sampled contrary to other pulse modulations,
wave, where the signal information is afterward at a sampling frequency fs , such as PWM. The hardware simplic-
encoded in the transitions instead of typically much larger than the input ity and digital nature of ring oscilla-
in the instantaneous amplitude. Such signal bandwidth ABW. Differing from tors and the noise-shaping properties
a signal is easy to handle with digital conventional ADCs, the sampler can of PFM have led to VCO-based ADCs’
wide popularity. We will, therefore,
concentrate most of our discussion on
VCO-based ADCs.

fs VCO-Based Analog-to-Digital
Decoder
Conversion: Basic Principles
Pulse D Q (Low-Pass So how do VCO-based ADCs digitize
Modulator Filter) an analog signal? We give an intuitive
explanation of this function with-
out detailed mathematics. Figure 2
FIGURE 1: The principle signal operations in a time-encoding ADC. depicts the simplest VCO-based ADC
architecture, which is also one of the
most used. A slowly varying input
signal modulates the frequency of
Sampling Clock
an oscillator (the VCO). The pulses of
Reset Clock the oscillator are then counted with a
digital counter. Assuming a sampling
D0 Y0 period Ts = 1/fs, the number of pulses
accumulated in the counter is dumped
D1 Y1 into a register every Ts seconds, and
the counter is reset. The value in the
VCO Counter . Register . ADC
. . register is therefore a measure of the
Output
. . VCO frequency and hence of the ana-
log input signal during that sample.
DN YN Clearly, the higher the oscillation
frequency compared to the sampling
frequency, the higher the resolution
FIGURE 2: The conceptual block diagram of an open-loop VCO-based ADC with a counter. that can be achieved. This defines

48 SPRING 2020 IEEE SOLID-STATE CIRCUITS MAGAZINE

Authorized licensed use limited to: Phanumas Khumsat. Downloaded on April 07,2023 at 14:04:28 UTC from IEEE Xplore. Restrictions apply.
an important design relation in VCO- f0, the SQNR is improved by 3 dB. similar square wave signals slightly
based ADCs: the resolution is pro- Therefore, the choice of the oscillator shifted in time. Figure 4(a) compares a
portional to the oscillator frequency and sampling frequencies enables the five-tap ring oscillator made of invert-
relative to the sampling frequency optimization of the SQNR. ers and oscillating at a frequency f0
(which corresponds to the number The typical VCO-based ADC circuit with an equifunctional circuit as in
of quantization bits in a traditional used in practice differs from the con- Figure 4(b), where an oscillator oscil-
amplitude-based ADC). ceptual circuit in Figure 2, although, in lating at 10f0 is connected to a five-
In addition, if the input signal is the end, it performs the same function. tap ring counter: the outputs of both
oversampled beyond Nyquist, the The difference lies in how the counter circuits are exactly the same signals.
sampling period Ts is shorter, and is implemented. Most VCO-based ADCs Therefore, the ring oscillator itself
there will apparently be fewer counts are implemented with a ring oscillator, suffices to implement the whole sys-
in the counter, resulting in a lower which is a circuit that produces many tem in Figure 2 in a very compact and
resolution. However, the reality is
the opposite: the error introduced
by quantizing the frequency of the
oscillator into an integer number (the Output
VCO

count) is first-order noise-shaped: the

error obtained after and before sam-
pling in the middle of a VCO cycle
always adds to one cycle. This fact is
Sampling

Sampling
Clock

illustrated in Figure 3, which shows Edge

that the quantization error e[n] can be
written as the first-order difference
of a finite-power sequence. This first-
order noise shaping, in combination
y [n ]

with oversampling and digital deci- 0

mation after the counter, improves
the signal-to-quantization-noise ratio
(SQNR) much more than if the oscilla- efinal [n–1] + einitial [n] = 1 → e [n] = einitial [n] + efinal [n] – 1 → e [n] = efinal [n] – efinal [n–1]
tor frequency is increased.
The following approximate eq­­
FIGURE 3: The signal behavior in the VCO-based ADC in Figure 2, with an illustration of the
uation gives the ma x imum SQNR noise shaping. The latter is due to the fact that the error efinal injected at the end of a count-
of a VCO-based ADC with analog ing cycle, combined with the error einitial at the beginning of the next counting cycle, always
signal bandwidth ABW, sampling adds up to 1 least significant bit.
frequency fs, and oscillator rest
frequency f0 [32]:

SQNR [dB] .
6 log 2 c m - 5.17 + 9 log 2 c m.
2f0 fs
fs 2ABW
(1) f0

This equation shows that the SQNR

φ0 φ1 φ2 φ3 φ4
improves by 6 dB every time the
(a)
VCO frequency f0 is doubled relative
to the sampling frequency fs, as the φ0 φ1 φ2 φ3 φ4
quantization resolution is increased
by one bit. If the oversampling ratio
is doubled as well as the quantiza-
D Q D Q D Q D Q D Q
tion resolution, i.e., the sampling fre- 10f0
quency fs is doubled together with
the oscillator frequency f0, the SQNR VCO
improvement is 9 dB. An additional
consequence of this dependency is (b)
that, if the sampling frequency fs is
doubled for a fixed oscillator frequency FIGURE 4: The comparison of (a) a ring oscillator and (b) an oscillator and counter.

IEEE SOLID-STATE CIRCUITS MAGAZINE SPRING 2020 49

Authorized licensed use limited to: Phanumas Khumsat. Downloaded on April 07,2023 at 14:04:28 UTC from IEEE Xplore. Restrictions apply.
 phase (see Figure 6) in a way that
resembles the equations of a multi-
bit, first-order delta–sigma modula-
w1 (t) tor [14], [32]. In Figure 6, a VCO with
D Q DQ conversion gain k VCO is modulated in
frequency by the input signal x (t) .
fs
The phase of the VCO, z (t), has a lin-
early growing component due to the
w2 (t)
rest angular frequency ~ 0 (the dotted
D Q DQ y [n ]

fs
+ line in Figure 6) and a slowly varying
additive component representing the
integral of x (t) . The physical out-
x (t )
put of the VCO, however, is a square
... signal (or a set of square signals in a
ring oscillator); therefore, only phase
... advancement in discrete steps can be
noticed, coincident with the square
wM (t ) signal edges. The VCO output is then
DQ DQ sampled into a discrete sequence by a
flip-flop with sampling period Ts . The
fs quantized and sampled phase z q [n]
can therefore be modeled by adding a
quantization noise component q [n] .
The effect of the exclusive-OR (XOR)
gates in Figure 5 is equivalent to
M-Phases Ring Oscillator Readout Circuit (×M ) computing the first-order difference
of z q [n] . Hence, the following equa-
tions are obtained:
FIGURE 5: The practical implementation of an open-loop ring-oscillator VCO-based ADC with
multiphase readout. nTs
z q [n] = ~ 0 nTs + k VCO
x (x)dx + q [n], #- 3
(2)
y [n] = zq [n] - zq [n - 1](3)
φ = ∫(ω0 + kVCOx(t ))dt
x (t ) φq [n ] y (n ) = q [n] - q [n - 1] + ~ 0 Ts
φ (t ) nTs
+ k VCO #(n - 1)T x (x) dx.
s
(4)
t t n n
As can be seen, the output sequence
fs
y [n] contains the input signal x [t]
x (t ) φ (t ) φq [n ] y (n )
VCO 1-z-1 averaged across each sampling period
as well as the quantization noise that
Quantizer is, indeed, first-order shaped.

FIGURE 6: The phase-referenced model of a VCO-based ADC. VCO-Based Analog-to-Digital

­Conversion: Diving Deeper
power-efficient way. Fortunately, as first-order, noise-shaped sequence is There are, however, some tricky ques-
a practical implementation, the circuit obtained with only a few digital logic tions that trigger a deeper dive. For
in Figure 5 facilitates a very easy way gates and no op-amps. instance, how does the VCO rest
to measure the count increment with- Since early VCO-based ADC con- fre­­quency f0 affect the quantiza-
out the need to reset the counter at verters were seen as a lter native tion noise? Also, the behavior of
every sampling clock cycle. Thanks to implementations of delta–sigma mo­­ the VCO-based ADC is poorly mod-
modulo arithmetic, this circuit encodes, dulators, the explanation given for eled for large signals, due to dis-
with minimal hardware, the number of the functioning of VCO-based ADCs crete tones in the output spectrum,
both the rising and the falling edges of can also be deduced from common similar to a first-order delta–sigma
the oscillator in a thermometric code delta–sigma modulator understanding. modulator. A different point of view
at every clock instance. And here is the The block diagram in Figure 2 can be is obtained by going back to the
beauty of VCO-based ADCs: a many-bit, described in terms of the oscillator basics of pulse-modulation theory

50 SPRING 2020 IEEE SOLID-STATE CIRCUITS MAGAZINE

Authorized licensed use limited to: Phanumas Khumsat. Downloaded on April 07,2023 at 14:04:28 UTC from IEEE Xplore. Restrictions apply.
[33], [34]. Figure 7 illustrates how a
VCO-based ADC can be expressed
as the reference model of the time- x (t )
encoding ADC in Figure 1. The ana-
log input signal x(t) modulates the
frequency of the VCO that generates w (t )
the square wave w(t). The signal w(t)
is applied to the monostable circuit
that generates the signal d(t), having
d (t )
a square pulse of fixed width Ts at
every time instance where w(t) has
an edge. According to [35], the signal (a)
d(t) is a pulse-frequency-modulated fs
representation of x(t). In case x(t) is
w (t ) d (t ) y [n]
a sine wave, the spectrum of d(t) can x (t )
VCO
be calculated analytically. Figure 7 Ts
also shows a possible implementa-
tion of the monostable circuit that Monostable
produces d(t). It consists of the XOR
(b)
operation between w(t) and is itself
delayed through Ts seconds. This
FIGURE 7: The time-encoding equivalent of a VCO-based ADC: (a) time-domain waveforms
circuit, in the end, is the same as of the analog signal x(t), the VCO output w(t), and the PFM modulation signal d(t) and (b)
the one used in Figure 4 if we move conceptual model of a VCO-based ADC.
the flip-flops that implement the
first-order difference immediately
Analog Signal

before the sampling operation. Fig-

ure 7 therefore reveals how the PFM
analysis is connected to the phase-
referenced model. t
The spectrum of a pulse-modulated (a)
signal has a quite similar structure
across different modulation types: it Ts = 1/fs
is composed of the input signal plus a
PWM

PFM

modulated carrier at high frequency,

with modulation sidebands repeated t t
around the harmonics of the carrier. For
instance, Figure 8(a) shows (part of) a (b) (c)
slow sinusoidal input signal. Figure 8(b)
presents the PWM-encoded signal as
fs 2fs
a function of time, and Figure 8(d)
PWM

PFM

shows the corresponding frequency

spectrum, where the modulation f f
sidebands have a spectrum envelope fo 2fo 3fo fo 2fo 3fo
described by Bessel functions, as in (d) (e)
analog frequency modulation. If the FIGURE 8: The time-domain waveforms and frequency spectra of a PWM- and a PFM-modulated
PWM signal is sampled, these modula- analog signal: (a) input analog signal; (b) PWM time-domain representation; (c) PFM time-domain
tion sidebands alias to lower frequen- representation; (d) frequency spectrum of PWM signal; and (e) frequency spectrum of PFM signal.
cies in the form of quantization noise.
VCO-based ADCs can be seen as pulse- PFM has a very special property: the The PFM time signal has many copies of
frequency modulators, as described modulation sidebands have periodic the same pulsewidth Ts, occurring very
previously, because the frequency nulls in the frequency spectrum. Fig- frequently or only sparsely, depending
of the oscillator is modulated with ure 8(c) displays the same sinusoidal on the input signal amplitude. As long
the input and the edges are detected signal that is in Figure 8(a), encoded as the pulsewidth is always the same,
with the counter or an XOR function with PFM in the time domain, and its signal theory predicts preperiodic
(Figure 7). The carrier in this case is corresponding spectrum in the fre- nulls in the spectrum at ­frequencies
the rest oscillation frequency of the VCO. quency domain is shown in Figure 8(e). ­c orresponding to multiples of the

IEEE SOLID-STATE CIRCUITS MAGAZINE SPRING 2020 51

Authorized licensed use limited to: Phanumas Khumsat. Downloaded on April 07,2023 at 14:04:28 UTC from IEEE Xplore. Restrictions apply.
 resistors and transistors used in the
φn (f ) VCO. Phase noise is displayed as an
ω0 φn (t )
additive component U n (t) in the block
VVCO(t ) 1/f 3 diagram in Figure 9(a), representing
Vin (t)
+ 1/f 2
+ 1 sin(φ (t )) an oscillator modulated by a signal
kVCO f Vin (t). Powerful simulation methods
(a) (b) based on periodic noise analysis have
been developed to predict the phase
Vn (t)~dφn /dt ω0
noise of an oscillator circuit, which
Vin (t) VVCO(t ) Vn (f ) typically has the shape of the Leeson
+ + 1 sin(φ (t )) 1/f model [see Figure 9(b)] [36]. Since it
kVCO is difficult to infer how such a noise
Noiseless Oscillator
spectrum affects the signal-to-noise
f
(c) (d) ratio (SNR) of the ADC, the VCO phase
noise should be referenced to the VCO
input [as in Figure 9(c)]. Referenc-
FIGURE 9: The output- and input-referred modeling and corresponding spectra of phase
noise in a VCO: (a) a conventional phase noise model of a VCO and (b) the corresponding ing the VCO phase noise to the input
phase noise spectrum; (c) an input-referred noise model of a VCO; and (d) the corresponding makes the design process similar to
input-referred noise spectrum. that of any analog block [38], as the
VCO’s input-referred noise shows
thermal and flicker noise components
Vdd in the same way that any conventional
analog circuit does. A more straight-
Ipreamp
forward approach is to use transient
+ IADC = Ipreamp noise simulations, but this makes the
Sensor design process very long and nonin-
– tuitive and hence should be done only
Ring Oscillator in the final design iteration [38].
SF/Transconductor VCO ADC To better understand the thermal
noise tradeoffs in the design of a
VCO-based ADC system, consider, as
an illustration, the VCO-based instru-
FIGURE 10: The VCO-based instrumentation system as an application illustration. SF: source
follower. mentation system in Figure 10. Here,
the VCO is driven by a transistor pre-
in­­­verse of the pulsewidth 1/Ts . These mentation, in particular, noise and amplifier either in current mode (by
periodic nulls arise from the sinc-shaped distortion as well as the impact on a transconductor Gm) or in voltage
spectrum of the pulses ­composing the design flow. mode [by a source follower (SF)]. Now,
the PFM signal. If this pulsewidth is suppose that the system is functional
forced to be the sampling period, Noise (with a correctly biased preamplifier
then all first-order nulls in the PFM Analog ADC designers are used to cal- and so on) but that the noise of the
spectrum of Figure 8(e) are aliased to culate the input-referred noise of an system has to be reduced. This can be
dc, creating the first-order noise shap- ADC and balance it properly with the achieved by increasing the width of
ing. This insight enables an accurate quantization noise to optimize the the input transistor and, additionally,
description of the more subtle be­­ power consumption of the ADC. This increasing the widths of all the tran-
havior of VCO-based ADCs beyond the balance, however, tends to be a bit sistors in the ring oscillator. In this
predictions of delta–sigma theory. For trickier in VCO-based ADCs because way, well-established analog imped-
instance, it fully enables an under- the dominant noise typically comes ance-scaling techniques are followed,
standing of large-signal behavior and from the VCO, and noise in VCOs man- sacrificing a factor of two in power
the occurrence of spurious base- ifests itself as (output) phase noise for a 3-dB reduction in circuit noise
band tones [34]. [36]. Phase noise is described as the (and hence a 3-dB improvement in the
random fluctuation of the phase of an SNR in a circuit-noise-limited design).
Circuit Design Guidelines oscillator. Phase noise in ring oscil- This is exactly the same scaling law
With the basic principles and func- lators has been the subject of many as in conventional analog circuits, as
tioning of a VCO-based ADC explained, publications, including [30], [36], and is also reflected in the typical figure
we can now describe the major design [37]. The root cause for phase noise is of merit (FoM) used for ADCs [FoM =
requirements for the circuit imple- the thermal and flicker noise in the SNDR + 10 log10(bandwidth/power)].

52 SPRING 2020 IEEE SOLID-STATE CIRCUITS MAGAZINE

Authorized licensed use limited to: Phanumas Khumsat. Downloaded on April 07,2023 at 14:04:28 UTC from IEEE Xplore. Restrictions apply.
As an additional perk of most VCO- signals. This structure also has the good practice is to think of the VCO
based ADCs, the circuit in Figure 10 benefit of achieving excellent power- as if it were an amplifier for the input
shows that the main current driven supply rejection ratio (PSRR) values signal. If you want good noise in the
by the Gm stage or SF also supplys way above common belief [9]. Alter- ring oscillator, use large transistors
the ring oscillator, which means that native solutions aim at limiting the [37]. If you want improved linearity,
the biasing current in the preampli- signal swing using canceling feed- use a differential circuit. Two oscil-
fiers is shared by the active portion forward paths or closed-loop feed- lators with large transistors may cost
of the ADC, hence improving the pow­­ back structures, as will be discussed power to obtain a high oscillation
er efficiency. in part 2. frequency, but, then again, this is a
Flicker noise is also a major concern way to save lots of biasing circuits,
in low-bandwidth instrumentation Design Process power -hung r y op -a mps, c ap ac-
applications. Detailed analysis of the This takes us to a final challenge: a itors, and switches. ADC designers
noise in ring oscillators [30], [36], [37] key problem for VCO-based ADCs is the have also gotten used to minimiz-
has shown that flicker noise decreases design process itself. ADC designers ing the importance of digital hard-
proportionally to the number of oscil- usually have a background in analog ware in the power budget, but, in
lator taps. Loosely speaking, it is as circuits (e.g., capacitor-based succes- VCO-based ADCs, the digital power
though flicker noise is produced by a sive-approximation-register converters is really significant, and there may
very large transistor, adding all areas or delta–sigma modulators) but typi- be digital logic running much faster
of the inverters in the ring. Therefore, cally have little experience with ring than the sampling rate. In summary,
if low flicker noise is desired, many oscillators. Phase-locked loop (PLL) designing time-encoding VCO-based
taps must be used in the ring oscil- designers might be better prepared for ADCs is quite different from design-
lator. This, however, complicates the the job, but the kind of VCOs that they ing standard ADCs and therefore
digital circuitry because more digi- are used to designing may not be the requires some open-mindedness from
tal signals need to be sampled and best suited for VCO-based ADCs. A ADC designers.
processed. This shows how power is
traded off between the analog and dig-
ital portions of the ADC. An important
fs
design option to reduce the impact of
Differential
flicker noise in a sensing application VCO p 1 – z –1
Signal +
is to use chopping [39], as will be dis- y [n]
cussed in part 2 of this article to be Gm/SF +
published in a later issue. fs
–
VCO n 1 – z –1
Distortion
A huge challenge for VCO-based ADC
design is the nonlinearity of the VCO FIGURE 11: The pseudodifferential VCO-based ADC configuration.
characteristic. Differing from closed-
loop feedback systems, such as delta–
sigma modulators, any nonlinearity in
the voltage-to-frequency translation
of the VCO used in a structure such
fs
as Figure 5 immediately degrades
w1 (t)
the SNDR of the ADC. Most of the
different VCO-based ADC architec- ...
x(t)
tures that will be reviewed in part 2
of this article have as their purpose
Encoder

fs
desensitizing the ADC with respect wM–1 (t)
to the VCO nonlinearity. If the input
swing is small, in many cases a ring fs y [n ]
oscillator VCO can already be suffi- wM (t) + 1–z –1
ciently linear. A standard practice to
improve the distortion performance
by removing even-order distortion Counter
is to use a pseudodifferential VCO
configuration (see Figure 11) driving FIGURE 12: The practical realization of an open-loop VCO-based ADC structure with a multi-
twin VCOs with differential input phase readout based on coarse/fine phase quantization.

IEEE SOLID-STATE CIRCUITS MAGAZINE SPRING 2020 53

Authorized licensed use limited to: Phanumas Khumsat. Downloaded on April 07,2023 at 14:04:28 UTC from IEEE Xplore. Restrictions apply.
Practical Design Example digital circuits and frequency-en- [3] Y. Tsividis, “Mixed-domain systems and
signal processing based on input decom-
To illustrate the preceding concepts, coded square wave signals rather position,” IEEE Trans. Circuits Syst. I, Reg.
and as example of the different design than voltage or current linear cir- Papers, vol. 53, no. 10, pp. 2145–2156, Oct.
2006. doi: 10.1109/TCSI.2006.882822.
methodology needed for VCO-based cuits, resulting in a small area and [4] M. Hovin, A. Olsen, T. S. Lande, and C.
ADCs, we now describe the circuit given good power efficiency. Toumazou, “Delta-sigma modulators us-
ing frequency-modulated intermediate
in [9], which is intended for audio ■■ Open-loop VCO-based ADCs resem- values,” IEEE J. Solid-State Circuits, vol. 32,
applications. It is a very simple VCO- ble closed-loop delta–sigma modu- no. 1, pp. 13–22, Jan. 1997. doi: 10.1109/
4.553171.
based ADC, yet it shows the full poten- lators in the sense that they behave [5] R. Naiknaware, H. Tang, and T. S. Fiez,
tial of time encoding. The core of the as first-order, multibit delta–sigma “Time-referenced single-path multi-bit DR
ADC using a VCO-based quantizer,” IEEE
ADC consists of two twin VCOs imple- modulators. The key system-level Trans. Circuits Syst. II, Analog Digit. Signal
mented with 11-phase ring oscillators. design parameters to achieve a tar- Process., vol. 47, no. 7, pp. 596–602, July
2000. doi: 10.1109/82.850418.
The VCOs are driven by a differential get SQNR performance are the rest [6] M. Z. Straayer and M. H. Perrott, “A 12-
transconductor that isolates them oscillation frequency and sampling bit, 10 MHz bandwidth, continuous-time
sigma-delta ADC with a 5-bit, 950-MS/s
from the input, which, in this case, is frequency. Here, the phase-domain VCO-based quantizer,” IEEE J. Solid-State
a high-output-impedance microelec- model (Figure 6) and correspond- Circuits, vol. 43, no. 4, pp. 805–814, Apr.
2008. doi: 10.1109/JSSC.2008.917500.
tromechanical system microphone. ing SNR (1) should be the start of [7] T. Anand, K. A. A. Makinwa, and P. K. Hanu-
All current used by the transconduc- your first design iteration. molu, “A VCO based highly digital tempera-
ture sensor with 0.034 C/mV supply sensi-
tor is, at the same time, powering the ■■ To understand more subtle sys- tivity,” IEEE J. Solid-State Circuits, vol. 51, no.
VCOs (see Figure 10). The transistors in tem-level effects (such as over- 11, pp. 2651–2663, Nov. 2016. doi: 10.1109/
JSSC.2016.2598765.
the ring oscillator have widths on the loading and spurious baseband [8] C. Tu, Y. Wang, and T. Lin, “A low-noise ar-
order of 30 nm. This large transistor tones), PFM theory is needed. ea-efficient chopped VCO-based CTDSM for
sensor applications in 40-nm CMOS,” IEEE J.
size, compared to what would be used ■■ To get good distortion and PSRR Solid-State Circuits, vol. 52, no. 10, pp. 2523–
for this frequency in a PLL, is needed performance, a twin setup with 2532, Oct. 2017. doi: 10.1109/JSSC.2017.
2724025.
to satisfy the input-referred noise re­­ two pseudodifferentially driven [9] A. Quintero et al., “A coarse-fine VCO-ADC
quirement relative to the quantization VCOs should always be used in for MEMS microphones with sampling
synchronization by data scrambling,” IEEE
noise of the converter (on the order the basic configuration. In part 2 Solid-State Circuits Lett., vol. 3, pp. 29–32,
of a few microvolts). of this article to be published in 2020. doi: 10.1109/LSSC.2020.2964158.
[10] J. Van Rethy, H. Danneels, V. De Smedt, W.
The chip uses the multiphase read- a later issue, more complex archi- Dehaene, and G. E. Gielen, “Supply-noise-
out circuit in Figure 12 to count the tectures for even better perfor- resilient design of a BBPLL-based force-
balanced wheatstone bridge interface in
edges in the ring oscillator phases mance will be discussed. 130-nm CMOS,” IEEE J. Solid-State Circuits,
W 1 ...W M with as little power as pos- ■■ To design the core VCO, a PLL ar- vol. 48, no. 11, pp. 2618–2627, Nov. 2013.
doi: 10.1109/JSSC.2013.2274831.
sible. The multiphase readout circuit chitecture style is not the best [11] S. Huang, N. Egan, D. Kesharwani, F. Op-
is implemented with a Gray counter approach. Instead, it is important teynde, and M. Ashburn, “28.3 A 125 MHz-
BW 71.9 dB-SNDR VCO-based CT SD ADC
connected to a reference phase, pro- to think in terms of the input-re- with segmented phase-domain ELD com-
viding a coarse quantization code ferred noise of the VCO, leading to pensation in 16nm CMOS,” in Proc. IEEE Int.
Solid-State Circuits Conf. (ISSCC), Feb. 2017,
and an encoder block that refines the large devices in the VCO core. De- pp. 470 – 471. doi: 10.1109/ISSCC.2017.
total edge count from samples of the signing the VCO mixes traditional 7870465.
[12] J. Daniels, W. Dehaene, M. Steyaert, and
ring oscillator state. The encoder analog amplifier design and VCO A. Wiesbauer, “A 0.02 mm2 65 nm CMOS
block operates at the sampling clock design for PLLs. Hence, it is a craft 30 MHz BW all-digital differential VCO-
based ADC with 64 dB SNDR,” in Proc.
(2.4 MHz in this case), much slower of its own. Symp. VLSI Circuits, June 2010, pp. 155–
than the coarse counter (approximately 156. doi: 10.1109/VLSIC.2010.5560314.
[13] X. Xing and G. G. E. Gielen, “A 42 fJ/Step-
50 MHz). The digital and analog power Acknowledgments FoM two-step VCO-based delta-sigma ADC
in 40 nm CMOS,” IEEE J. Solid-State Circuits,
consumption is each roughly half This work was supported by Spanish
vol. 50, no. 3, pp. 714–723, Mar. 2015. doi:
the varchitecture pays off in distortion Ministry of Science and Innovation proj- 10.1109/JSSC.2015.2393814.
[14] G. Taylor and I. Galton, “A mostly-digital
mitigation (the peak SNDR is 70 dB in ect TEC2017-82653-R and the Fund for
variable-rate continuous-time delta-sig-
20 kHz of bandwidth without feed- Scientific Research Flanders (Research ma modulator ADC,” IEEE J. Solid-State Cir-
cuits, vol. 45, no. 12, pp. 2634–2646, Dec.
back) and very good power-supply Foundation–Flanders), Belgium. 2010. doi: 10.1109/JSSC.2010.2073193.
rejection (which exceeds 80 dB in [15] F. Opteynde, “A maximally-digital radio
spite of the poor inherent power-sup- References receiver front-end,” in Proc. IEEE Int. Sol-
[1] E. Roza, “Analog-to-digital conversion via id-State Circuits Conf. (ISSCC), Feb. 2010,
ply rejection of a single VCO channel). duty-cycle modulation,” IEEE Trans. Cir- pp. 450 – 451. doi: 10.1109/ISSCC.2010.
cuits Syst. II, Analog Digit. Signal Process., 5433952.
vol. 44, no. 11, pp. 907–914, Nov. 1997. [16] T. Wu and M. S. Chen, “A noise-shaped
Takeaway Points doi: 10.1109/82.644044. VCO-based nonuniform sampling ADC
[2] A. A. Lazar and L. T. Toth, “Perfect recov- with phase-domain level crossing,” IEEE J.
■■ Time-encoding VCO-based ADCs Solid-State Circuits, vol. 54, no. 3, pp. 623–
ery and sensitivity analysis of time en-
are an interesting ADC architec- coded bandlimited signals,” IEEE Trans. 635, Mar. 2019. doi: 10.1109/JSSC.2019.
Circuits Syst. I, Reg. Papers, vol. 51, no. 10, 2892426.
ture in deeply scaled CMOS tech- [17] A. Mukherjee et al., “A 1-GS/s 20 MHz-BW
pp. 2060–2073, Oct. 2004. doi: 10.1109/
nologies, as they generally use TCSI.2004.835026. capacitive-input continuous-time∆∑ ADC

54 SPRING 2020 IEEE SOLID-STATE CIRCUITS MAGAZINE

Authorized licensed use limited to: Phanumas Khumsat. Downloaded on April 07,2023 at 14:04:28 UTC from IEEE Xplore. Restrictions apply.
 using a novel parasitic pole-mitigated ful- [32] J. Kim, T. K. Jang, Y. G. Yoon, and S. Cho, Van Valkenburg Award in 2015. He is
ly differential VCO,” IEEE Solid-State Cir- “Analysis and design of voltage-con-
cuits Lett., vol. 2, no. 1, pp. 1–4, Jan 2019. trolled oscillator based analog-to-digital a 1997 laureate of the Belgian Royal
doi: 10.1109/LSSC.2019.2911874. converter,” IEEE Trans. Circuits Syst. I, Reg. Academy of Sciences, Literature, and
[18] M. Baert and W. Dehaene, “A 5-GS/s 7.2-ENOB Papers, vol. 57, no. 1, pp. 18–30, Jan. 2010.
time-interleaved VCO-based ADC achieving doi: 10.1109/TCSI.2009.2018928. Arts in the discipline of engineering.
30.5 fJ/cs,” IEEE J. Solid-State Circuits, to be [33] L. Hernandez and E. Gutierrez, “Analyti- Luis Hernandez received his M.S.
published. doi: 10.1109/JSSC.2019.2959484. cal evaluation of VCO-ADC quantization
[19] V. Nguyen, F. Schembari, and R. B. Stasze- noise spectrum using pulse frequency and Ph.D. degrees in telecommunica-
wski, “A 0.2-V 30-MS/s 11b-ENOB open- modulation,” IEEE Signal Process. Lett., tions engineering from the Polytech-
loop VCO-based ADC in 28-nm CMOS,” vol. 22, no. 2, pp. 249–253, Feb. 2015. doi:
IEEE Solid-State Circuits Lett., vol. 1, no. 10.1109/LSP.2014.2357071. nic University of Madrid, in 1989 and
9, pp. 190–193, Sept. 2018. doi: 10.1109/ [34] E. Gutierrez, L. Hernandez, F. Cardes, and 1995, respectively. He completed a
LSSC.2019.2906777. P. Rombouts, “A pulse frequency modula-
[20] T. Watanabe, T. Mizuno, and Y. Makino, tion interpretation of VCOs enabling VCO- postdoctoral stay in the United States
“An all-digital analog-to-digital converter ADC architectures with extended noise during 1996 at the Department of
with 12-uV/LSB using moving-average fil- shaping,” IEEE Trans. Circuits Syst. I, Reg.
tering,” IEEE J. Solid-State Circuits, vol. 38, Papers, vol. 65, no. 2, pp. 444–457, Feb. Electrical and Computer ­Engineering,
no. 1, pp. 120–125, Jan. 2003. doi: 10.1109/ 2018. doi: 10.1109/TCSI.2017.2737830. Oregon State University. In 1997, he
JSSC.2002.806263. [35] E. Fitch, “The spectrum of modulated
[21] S. Tajima, Y. Okuda, T. Watanabe, H. Aoya- pulses,” J. Inst. Elect. Eng. IIIA, Radiocom- joined University Carlos III of Madrid,
ma, M. Yamamoto, and T. Uchiyama, “High- mun., vol. 94, no. 13, pp. 556–564, Mar. where he is currently a full professor
resolution magneto-impedance sensor 1947. doi: 10.1049/ji-3a-2.1947.0065.
with TAD for low noise signal process- [36] B. Razavi, “A study of phase noise in CMOS in the Department of Electronic Tech-
ing,” IEEE Trans. Magn., vol. 50, no. 11, pp. oscillators,” IEEE J. Solid-State Circuits, nology and leads the mixed-signal
1–4, Nov. 2014. doi: 10.1109/TMAG.2014. vol. 31, no. 3, pp. 331–343, Mar. 1996. doi:
2332178. 10.1109/4.494195. Microelectronic Design and Applica-
[22] P. Yeon, M. S. Bakir, and M. Ghovanloo, [37] F. Pepe and P. Andreani, “An accurate tions research group. His research
“Towards a 1.1 mm2 free-floating wire- analysis of phase noise in CMOS ring
less implantable neural recording SoC,” in oscillators,” IEEE Trans. Circuits Syst. II, interests include signal theory, mixed-
Proc. IEEE Custom Integrated Circuits Conf. Express Briefs, vol. 66, no. 8, pp. 1292– signal microelectronics, and, spe-
(CICC), Apr. 2018, pp. 1–4. doi: 10.1109/CICC. 1296, Aug. 2019. doi: 10.1109/TCSII.2018.
2018.8357048. 2884569. cifically, data acquisition using
[23] W. Jiang, V. Hokhikyan, H. Chandrakumar, [38] F. Cardes, A. Quintero, E. Gutierrez, C. sigma–delta modulation. He has pub-
V. Karkare, and D. Markovic, “A ± 50-mV Buffa, A. Wiesbauer, and L. Hernandez,
linear-input-range VCO-based neural-re- “SNDR limits of oscillator-based sen- lished more than 150 scientific articles
cording front-end with digital nonlinear- sor readout circuits,” Sensors, vol. 18, and holds 20 international patents.
ity correction,” IEEE J. Solid-State Circuits, no. 2, pp. 445, Feb. 2018. doi: 10.3390/
vol. 52, no. 1, pp. 173–184, Jan. 2017. doi: s18020445. He is a member of the IEEE Circuits
10.1109/JSSC.2016.2624989. [39] J. Marin, E. Sacco, J. Vergauwen, and G. and Systems Society Analog Signal
[24] J. Huang et al., “A 0.01-mm2 mostly digital Gielen, “A robust BBPLL-based 0.18-μm
capacitor-less AFE for distributed autono- CMOS resistive sensor interface with Processing Technical Committee and
mous neural sensor nodes,” IEEE Solid- high drift resilience over a −40°C–175°C for eight years has been an associate
State Circuits Lett., vol. 1, no. 7, pp. 162– temperature range,” IEEE J. Solid-State Cir-
165, July 2018. doi: 10.1109/LSSC.2019. cuits, vol. 54, no. 7, pp. 1862–1873, July editor of IEEE Transactions on Cir-
2894932. 2019. doi: 10.1109/JSSC.2019.2911888. cuits and Systems—I: Regular Papers
[25] L. B. Leene and T. G. Constandinou, “Time do-
main processing techniques using ring oscil- and IEEE Transactions on Circuits and
lator-based filter structures,” IEEE Trans. Cir-
cuits Syst. I, Reg. Papers, vol. 64, no. 12, pp.
About the Authors Systems—II: Express Briefs.
3003–3012, Dec. 2017. doi: 10.1109/TCSI.2017. Georges G.E. Gielen (gielen@kuleuven Pieter Rombouts received his
2715885. .be) received his M.Sc. and Ph.D. de­­ engineering degree in applied phys-
[26] B. Drost, M. Talegaonkar, and P. K. Hanu-
molu, “Analog filter design using ring os- grees in electrical engineering from ics and his Ph.D. degree in electron-
cillator integrators,” IEEE J. Solid-State Cir- KU Leuven, Belgium, in 1986 and ics from Ghent University, Belgium,
cuits, vol. 47, no. 12, pp. 3120–3129, Dec.
2012. doi: 10.1109/JSSC.2012.2225738. 1990, respectively. In 1990, he was a in 1994 and 2000, respectively. In
[27] S. Tannirkulam C h a n d r a s e k a r a n , A. postdoctoral research assistant and 1994, he joined the Department of
Jayaraj, M. Danesh, and A. Sanyal, “A
highly digital second-order oversampling visiting lecturer in the Department Electronics and Information Sys-
TDC,” IEEE Solid-State Circuits Lett., vol. 1, of Electrical Engineering and Com- tems, Ghent University, where he
no. 5, pp. 114–117, May 2018. doi: 10.1109/
LSSC.2018.2875818. puter Science, University of Califor- has been a professor of analog elec-
[28] E. Prefasi, S. Paton, and L. Hernandez, “A nia, Berkeley. Since 1991, he has been tronics since 2005. His research
7 mW 20 MHz BW time-encoding overs-
ampling converter implemented in a in the MICAS research group with the interests include signal processing,
0.08 mm2 65 nm CMOS circuit,” IEEE J. Sol- Department of Electrical Engineering, circuits and systems theory, analog
id-State Circuits, vol. 46, no. 7, pp. 1562–
1574, July 2011. doi: 10.1109/JSSC.2011. KU Leuven, where he currently is a circuit design, and sensor systems.
2143790.
full professor. His research interests The main focus of his research has
[29] V. Dhanasekaran et al., ”A continuous
time multi-bit∆∑ADC using time domain include the design and design automa- been on analog-to-digital and digital-
quantizer and feedback element,” IEEE
tion of analog and mixed‐signal ICs, to-analog conversion. He has served
J. Solid-State Circuits, vol. 46, no. 3, pp.
639 – 650, Mar. 2011. doi: 10.1109/JSSC. including data converters and sensor or currently serves as an associate
2010.2099893.
[30] A. A. Abidi, “Phase noise and jitter in CMOS
readout circuits. He has coauthored editor of IEEE Transactions on Cir-
ring oscillators,” IEEE J. Solid-State Circuits, 10 books and more than 600 papers cuits and Systems—I: Regular Papers,
vol. 41, no. 8, pp. 1803–1816, Aug. 2006.
doi: 10.1109/JSSC.2006.876206.
in edited books, international jour- IEEE Transactions on Circuits and
[31] B. Razavi, “The ring oscillator [a circuit nals, and conference proceedings. He Systems—II: Express Briefs, and Elec-
for all seasons],” IEEE Solid State Circuits
Mag., vol. 11, no. 4, pp. 10–81, Fall 2019.
is a Fellow of the IEEE and received the tronics Letters.
doi: 10.1109/MSSC.2019.2939771. IEEE Circuits and Systems Society Mac 

IEEE SOLID-STATE CIRCUITS MAGAZINE SPRING 2020 55

Authorized licensed use limited to: Phanumas Khumsat. Downloaded on April 07,2023 at 14:04:28 UTC from IEEE Xplore. Restrictions apply.