uP9505

4/3/2/1+2/1/0-Phase PWM Controller

with SMBus Digital Interface for FM2+ CPU Core Power
General Description Features
The uP9505 is an AMD SVI2 compliant desktop CPU voltage † AMD SVI2 CPU Compliant
regulator controller that integrates a 4-phase PWM † RCOT+TM Control Topology
controller for VDD and a 2-phase controller for VDDA. The „ Easy Setting
VDD controller can be configured as 4/3/2/1-phase, and the „ Smooth Mode Transition
VDDA controller can be configured as 2/1/0-phase (0 „ Fast Transition Response
denotes VDDA controller is disabled) for platform power † Flexible Operation Phase Configuration
design flexibility. For the typical 4+2-phase application, the „ 4/3/2/1-Phase PWM Controller for VDD
4-phase VDD controller has 4 PWM outputs. The 2-phase „ 2/1/0-Phase PWM Controller for VDDA
VDDA controller has 2 PWM outputs. The controller provides „ Support Operation Phase Disable Function
further flexible operating phase configurations to support „ Support 6+0 or 5+1 Phase Application
6+0 or 5+1 phase application (0 denotes VDDA controller † SMBus Interface for Performance and Efficiency
is disabled). The integrated SMBus interface Optimization
programmability makes this part with high performance and „ Dynamic Programmable VR Parameters
easy design. Designer can define different power scenario „ Programmable Protection Thresholds
for different current states to optimize the performance and „ VR Output Reporting
efficiency. „ Programmable Loop Gain
† Programmable Operation Frequency
The uP9505 combines true differential output voltage sense,
† Inductor DCR Current Sensing for Droop/
differential inductor DCR current sense, input voltage feed- Channel OCP/ Total OCP
forward sense and adaptive voltage positioning to provide † Differential Current Sense Amplifier for Current
accurately regulated power for desktop CPU. It adopts uPI Balance
proprietary RCOT+TM (Robust Constant On-Time) topology † Differential Remote Output Voltage Sense
to have fast transient response and smooth mode † Transient Boost for Fast Transient Response
transition. Similar to digital based PWM controller, the loop † High Accuracy DAC
gain is also programmable by SMBus interface to achieve † OCP/UVP/OVP/Thermal Shutdown
design flexibility. † RoHS Compliant and Halogen Free
The uP9505 has built-in serial interface to communicate
with AMD SVI2 compliant CPU. It supports mode transition Applications
function with various operating states. This part provides
† AMD FM2+ Desktop CPU Power Supplies
two different VID on-the-fly slew rates, which can be
programmed by the SMBus register. † AMD VGA Card GPU Power Supplies
The uP9505 provides power good indicator and selectable Pin Configuration
VR parameters, such as SMBus device address and Vboot
voltage. It also provides complete fault protection functions,
FBRTN
PWM1

PWM2

PWM3

PWM4
CSN3

CSN2

CSN1
CSP2
CSP3

CSP1

including over voltage, under voltage, over current, over

DAC
POK

temperature and under voltage lockout. The uP9505 is 39 38 37 36 35 34 33 32 31 30 29 28 27

available in VQFN6x6-52L package. CSP4 40 26 EAP

CSN4 41 25 FB

CSP 42 24 TP

Ordering Information CSN 43

CSNA 44
23

22
COMP

TONSET

CSPA 45 21 IMON
Order Number P a ck a g e Remark CSN1A 46 53 GND 20 IMONA

CSP1A 47 19 VRHOT#
uP9505PQGW VQFN6x6-52L
CSN2A 48 18 TSEN

CSP2A 49 17 TSENA
Note: PWROK 50 16 VINSEN
(1) Please check the sample/production availability with PWM1A 51 15 EN
uPI representatives. PWM2A 52 14 VCC5

(2) uPI products are compatible with the current IPC/JEDEC 1 2 3 4 5 6 7 8 9 10 11 12 13

SDA

SCL
FBRTNA

DACA

COMPA

SVD

SVT

SVC
EAPA

FBA

TPA

VDDIO

PROG

J-STD-020 requirement. They are halogen-free, RoHS

compliant and 100% matte tin (Sn) p lating that are suitable
for use in SnPb or Pb-free soldering processes.

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 uP9505
Typical Application Circuit
4+2 Phase Application

12V 12V
uP1962 uP1962
51 32
VIN BOOT PWM PWM1A PWM1 PWM BOOT VIN

EN EN
VDDA_1 PH1A UG UG PH1 VDD_1
VDDA PH VCC VCC PH VDD

LG GND GND LG

12V 12V
uP1962 uP1962
52 31
BOOT PWM PWM2A PWM2 PWM BOOT

EN EN
VDDA_2 PH2A UG UG PH2 VDD_2
PH VCC VCC PH

LG GND GND LG

12V
47
PH1A CSP1A uP1962
46 30
VDDA_1 CSN1A PWM3 PWM BOOT
49
PH2A CSP2A EN
UG PH3 VDD_3
48
VDDA_2 CSN2A VCC PH

GND LG
45
CSPA
12V
44
VDDA_1 CSNA
uP1962
VDDA_2 0.1uF
29
PWM4 PWM BOOT
6
COMPA
EN
4
UG PH4 VDD_4
VDDA_SENSE FBA VCC PH

3
EAPA GND LG
2
DACA
1 34
VSSA_SENSE FBRTNA CSP1 PH1
35
CSN1 VDD_1
5 36
VCC5 TPA CSP2 PH2
37
CSN2 VDD_2
17
TSENA 38
CSP3 PH3
39
18
TSEN CSN3 VDD_3
53
GND CSP4 40
PH4
0.1uF
14 41
5V VCC5 CSN4 VDD_4
24
TP
13
PROG
42
CSP
22
TONSET 43
21
IMON CSN VDD_1
20
IMONA 0.1uF VDD_2
VDD_3
VIN 16
VINSEN VDD_4
23
8
COMP
SVT
7 25
SVD FB VDD_SENSE
9
SVC
10 26
VDDIO EAP
15 27
EN DAC
28
50
PWROK FBRTN VSS_SENSE
33 12
POK SCL
19 11
VRHOT# SDA

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 uP9505
Typical Application Circuit
5+1 Phase Application

12V 12V
uP1962 uP1962
51 32
VIN BOOT PWM PWM1A PWM1 PWM BOOT VIN

EN EN
VDDA_1 PH1A UG UG VDD_1
PH1
VDDA PH VCC VCC PH VDD

LG GND GND LG

47
PH1A CSP1A 12V
uP1962
*Note 1 VDDA_1
31
PWM2 PWM BOOT
46
5V CSN1A EN
PH1A 45
CSPA UG VDD_2
PH2
VCC PH
44
VDDA_1 CSNA
0.1uF GND LG
6
COMPA
4
12V
VDDA_SENSE FBA
uP1962
30
3
PWM3 PWM BOOT
EAPA
2
DACA EN
UG VDD_3
VSSA_SENSE 1
FBRTNA PH3
VCC PH

GND LG

VCC5 5 TPA 12V

uP1962
17
TSENA PWM4 29
PWM BOOT

EN
18
TSEN UG VDD_4
PH4
53
GND VCC PH
0.1uF
5V 14
VCC5 GND LG
24
TP
*Note 1:
13
PROG 12V
Use 1kohm resistor to pull up CSN1A to 5V. uP1962
CSP1A should be in normal connection. 22
TONSET 52
21 PWM2A PWM BOOT
IMON
20
IMONA EN
UG VDD_5
PH5
16
VCC PH
VIN VINSEN
8
SVT GND LG
7
SVD
9 34
SVC CSP1 PH1
10
VDDIO CSN1 35
VDD_1
15
EN 36
50
CSP2 PH2
PWROK
37
33
POK CSN2 VDD_2
19 38
VRHOT# CSP3 PH3
12
SCL CSN3 39
VDD_3
11
SDA
40
CSP4 PH4
41
23
CSN4 VDD_4
COMP
49
CSP2A PH5
25
VDD_SENSE FB 48
CSN2A VDD_5

26 42
EAP CSP
27
DAC CSN 43
VDD_1
28
VSS_SENSE FBRTN 0.1uF VDD_2
VDD_3
VDD_4
VDD_5

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 uP9505
Typical Application Circuit
6+0 Phase Application
12V
44
5V CSNA uP1962
*Note 1
45 32
CSPA PWM1 PWM BOOT VIN
6
Left Floating COMPA EN
4
FBA UG PH1 VDD_1
3
VCC PH VDD
EAPA
2
Left Floating DACA GND LG
1
FBRTNA
5
12V
Left Floating TPA
uP1962
31
17
PWM2 PWM BOOT
TSENA
EN
UG PH2 VDD_2
18
TSEN VCC PH
53
GND
0.1uF GND LG
14
5V VCC5
24
TP 12V
13
PROG uP1962
30
22
TONSET PWM3 PWM BOOT
21
IMON EN
20
IMONA UG PH3 VDD_3
16
VCC PH
VIN VINSEN
8
SVT SVT GND LG
7
SVD SVD
12V
9
SVC SVC
uP1962
10
VDDIO 29
PWM4 PWM BOOT
15
EN
50
PWROK EN
UG PH4 VDD_4
33
POK VCC PH
19
VRHOT#
GND LG
12
SCL
11
SDA 12V
34 uP1962
PH1 CSP1
51
35
PWM1A PWM BOOT
VDD_1 CSN1
36
EN
PH2 CSP2 UG PH5 VDD_5
37
VCC PH
VDD_2 CSN2

PH3 38
CSP3 GND LG

39
VDD_3 CSN3 12V
40 uP1962
PH4 CSP4
52
41
PWM2A PWM BOOT
VDD_4 CSN4
47
EN
PH5 CSP1A UG PH6 VDD_6
46
VCC PH
VDD_5 CSN1A

PH6 49
CSP2A GND LG

48
VDD_6 CSN2A
23
COMP
42
CSP FB 25
VDD_SENSE
43
VDD_1 CSN
VDD_2 0.1uF 26
EAP
VDD_3 27
DAC
VDD_4 28
FBRTN VSS_SENSE
VDD_5
VDD_6

*Note 1:
Use 1kΩ resistor to pull up CSNA to 5V.
Connect CSPA to ground.

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 uP9505
Functional Pin Description
N o. Name Pin Function
Output Voltage Feedback Return for VDDA. Inverting input to the differential voltage
sense amplifier. FBRTNA is the reference point in DACA output voltage measurement.
1 FBRTNA
Connect this pin directly to the processor output voltage feedback return sense point,
namely VSSA_SENSE.
DAC Output for VDDA. The output voltage of this pin is the reference voltage for the
2 D AC A VDDA rail. DACA voltage is measured with respect to FBRTNA. Connect a capacitor
from this pin to FBRTNA.
Non-Inverting Input of the Error Amplifier for VDDA. Connect a resistor between this
3 EAPA
pin and DACA to set the droop (load line) function.
4 FB A Inverting Input of the Error Amplifier for VDDA.
5 TPA Test Pin for VDDA. Reserved for VDDA internal testing purpose.
Output of Control Loop Error Amplifier for VDDA. Connect a resistor in series with a
6 COMPA
capacitor from this pin to GND for voltage control loop compensation.
Serial VID Data. SVD is a push-pull with high-Z output of the processor. SVD can be
7 SVD
driven by the VR during the Acknowledgement phase.
8 SVT Serial VID Telemetry. SVT is a push-pull output of the processor.
9 SVC Serial VID Clock. SVC is a push-pull output of the processor.
The reference for the processor for the memory interface. Connect a capacitor
10 VDDIO
between VDDIO and GND to power and reference the SVC, SVD, SVT pins.
11 SD A SMBus Data Input. This pin is input or output of serial bus data signal.
12 SC L SMBus Clock Input. This pin receives serial bus clock signal input.
Function Setting Pin. Connect a resistor voltage divider from VCC5 to GND to set the
13 PROG
initial start up voltage (Vboot) for VDDA and SMBus device address.
Supply Input for Logic Control Circuit. Connect this pin to a 5V voltage source via an
14 VC C 5
RC filter. VCC5 is the supply input for the logic control circuit.
Chip Enable Control Input. Pull this pin above 2V enables the chip. Pull this pin below
15 EN
0.8V to disable the chip.
Pow er Stage Input Voltage Sense. Directly connect this pin to the power stage input
16 VINSEN VIN. The controller senses the voltage on this pin for power stage input voltage VIN
detection. The VINSEN voltage is also used for PWM on-time calculation.
Thermal Sensing for VDDA. Connect NTC network to this pin for thermal sensing. The
controller uses specific nonlinear A/D converter in thermal reporting. The recommended
17 TSENA
NTC thermistor is 10kΩ / β = 3380 by Murata (NCP18XH103F03RB), and the
recommended lower dividing resistor is 6kΩ.
Thermal Sensing for VDD. Connect NTC network to this pin for thermal sensing. The
controller uses specific nonlinear A/D converter in thermal reporting. The recommended
18 TSEN
NTC thermistor is 10kΩ / β = 3380 by Murata (NCP18XH103F03RB), and the
recommended lower dividing resistor is 6kΩ.
VRHOT# Output. This pin is an open-drain output. The controller asserts VRHOT# when
19 VRHOT# the sensed temperature is higher than the value of SMBus register 0x29h
(TEMP_VRHOT), in which the default value is 05h (106oC)

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 uP9505
Functional Pin Description
N o. Name Pin Function
Over Current Protection Threshold Setting and Sensing for VDDA. Connect a resistor
from this pin to GND to set the over current protection threshold. Do not connect any capacitor
to this pin. The output current of this pin is proportional to the total load current. The total load
20 IMONA
current is sensed and flows out of this pin, and a resistor from this pin to GND makes the
IMONA voltage proporti onal to the total output current. When the voltage on IMONA pi n
exceeds 2.56V, the over current protection will be tripped to shutdown the controller.
Over Current Protection Threshold Setting and Sensing for VDD. Connect a resistor
from this pin to GND to set the over current protection threshold. Do not connect any capacitor
to this pin. The output current of this pin is proportional to the total load current. The total load
21 IMON
current is sensed and flows out of this pin, and a resistor from this pin to GND makes the
IMON voltage proportional to the total output current. When the voltage on IMON pin exceeds
2.56V, the over current protection will be tripped to shutdown the controller.
PWM On-Time Setting. Connect a resistor from this pin to GND to set the PWM on-time.
22 TONSET
The VDD VR and VDDA VR share the same PWM on-time setting.
Output of Control Loop Error Amplifier for VDD . Connect a resistor in series with a
23 COMP
capacitor from this pin to GND for voltage control loop compensation.
24 TP Test Pin for VDD. Reserved for VDD internal testing purpose.
25 FB Inverting Input of the Error Amplifier for VDD.
Non-Inverting Input of the Error Amplifier for VDD. Connect a resistor between this pin
26 EAP
and DAC to set the droop (load line) function.
DAC Output for VDD. The output voltage of this pin is the reference voltage for the VDD
27 D AC rail. DAC voltage is measured with respect to FBRTN. Connect a capacitor from this pin to
FBRTN.
Output Voltage Feedback Return for VDD. Inverting input to the differential voltage sense
amplifier. FBRTN is the reference point in DAC output voltage measurement. Connect this
28 FBRTN
p i n d i r e c t l y t o t h e p r o c e s s o r o u t p u t vo l t a g e f e e d b a c k r e t u r n s e n s e p o i n t , n a m e l y
VSS_SENSE.
VDD Phase 4 PWM Output. Connect this pin to the PWM input of external MOSFET driver.
29 PWM4
This pin outputs a PWM logic signal for external discrete MOSFET driver for VDD rail
VDD Phase 3 PWM Output. Connect this pin to the PWM input of external MOSFET driver.
30 PWM3
This pin outputs a PWM logic signal for external discrete MOSFET driver for VDD rail.
VDD Phase 2 PWM Output. Connect this pin to the PWM input of external MOSFET driver.
31 PWM2
This pin outputs a PWM logic signal for external discrete MOSFET driver for VDD rail
VDD Phase 1 PWM Output. Connect this pin to the PWM input of external MOSFET driver.
32 PWM1
This pin outputs a PWM logic signal for external discrete MOSFET driver for VDD rail.
Pow er OK Indication. This pin is an open-drain output that indicates the VDD/VDDA start
33 POK
up to output voltage Vboot and no fault happens.
34 C SP1 Positive Differential Current Sense Input for VDD Phase 1.
35 CSN1 Negative Differential Current Sense Input for VDD Phase 1.
Positive Differential Current Sense Input for VDD Phase 2. When VDD phase 2 is not
36 C SP2
used, short this pin to GND when VDD VR is configured in single-phase configuration.
Negative Differential Current Sense Input for VDD Phase 2. When VDD phase 2 is
37 CSN2 not used, pull high this pin to VCC5 through a 1kΩ resistor to disable PWM2 to let VDD
VR operate in single-phase configuration.

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 uP9505
Functional Pin Description
N o. Name Pin Function
Positive Differential Current Sense Input for VDD Phase 3. When VDD phase 3 is not
38 C SP3
used, short this pin to GND when VDD VR is configured in 2-phase configuration.
Negative Differential Current Sense Input for VDD Phase 3. When VDD phase 3 is
39 CSN3 not used, pull high this pin to VCC5 tthrough a 1kΩ resistor to disable PWM3 to let VDD
VR operate in 2-phase configuration.
Positive Differential Current Sense Input for VDD Phase 4. When VDD phase 4 is not
40 C SP4
used, short this pin to GND when VDD VR is configured in 3-phase configuration.
Negative Differential Current Sense Input for VDD Phase 4. When VDD phase 4 is
41 CSN4 not used, pull high this pin to VCC5 through a 1kΩ resistor to disable PWM4 to let VDD
VR operate in 3-phase configuration.
42 C SP Non-Inverting Input of Total Current Sense Amplifier for VDD.
43 C SN Inverting Input of Total Current Sense Amplifier for VDD.
44 CSNA Inverting Input of Total Current Sense Amplifier for VDDA.
45 CSPA Non-Inverting Input of Total Current Sense Amplifier for VDDA.
Negative Differential Current Sense Input for VDDA Phase 1. When VDDA phase 1 is
46 CSN1A not used, pull high this pin to VCC5 through a 1kΩ resistor to disable PWM1A to let VDDA
VR operate in zero-phase configuration.
Positive Differential Current Sense Input for VDDA Phase 1. When VDDA phase 1 is
47 C S P 1A
not used, short this pin to GND when VDDA VR is configured in zero-phase configuration.
Negative Differential Current Sense Input for VDDA Phase 2. When VDDA phase 2 is
48 CSN2A not used, pull high this pin to VCC5 through a 1kΩ resistor to disable PWM2A to let VDDA
VR operate in single-phase configuration.
Positive Differential Current Sense Input for VDDA Phase 2. When VDDA phase 2 is
49 C S P 2A
not used, short this pin to GND when VDDA VR is configured in single-phase configuration.
System Pow er OK Indication. This pin is the active high that indicates the system power
50 PWROK is ok. When PWROK is asserted, it indicates that all voltage planes and free-running clocks
are within specification.
VDDA Phase 1 PWM Output. Connect this pin to the PWM input of external MOSFET
51 PWM1A driver. This pin outputs a PWM logic signal for external discrete MOSFET driver for VDDA
rail.
VDDA Phase 2 PWM Output. Connect this pin to the PWM input of external MOSFET
52 PWM2A driver. This pin outputs a PWM logic signal for external discrete MOSFET driver for VDDA
rail.
Ground. The exposed pad is the ground of all logic control circuits, and it must be
Exposed Pad
soldered to a large PCB and connected to GND.

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 uP9505
Functional Block Diagram

TONSET
VRHOT#

VINSEN
TSENA

VDDIO
PROG
TSEN

VCC5
SDA

SVD

SVC
SCL

SVT

POK
EN
PWROK SVI2/SMBus/ADC POR Power OK

ICSN
D/A
DAC
BUF
FBRTN

ICSNA PWM1
D/A
DACA
BUF Ramp
FBRTNA Generation On Time
PWM2
Generation
and
PWM
Control
PWM3
Logic

COMP
PWM4
EAP
GM
FB

TP TP

CSN ICSN CSP1

GM
CSP CSN1

UVP OVP CSP2

Per-Phase Current GM
OCP Balance CSN2
EAP - 325mV EAP + 325mV

CSP3
GM
CSN3

ICSN

IMON CSP4
GM
CSN4

Operation
ICSNA Phase
Selection
IMONA
TONSET
VINSEN
PWM1A
On Time
Generation
Ramp and
Generation PWM
TONSET
Control
COMPA Logic PWM2A

EAPA
GM
FBA

TPA TPA

CSNA ICSNA
CSP1A
CSPA GM
CSN1A
Per-Phase Current
OCP Balance
UVP OVP CSP2A
GM
CSN2A
EAPA - 325mV EAPA + 325mV
Operation
Phase
Selection
GND

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 uP9505
Functional Description
Power Input and Power On Reset
The uP9505 has a single power input VCC5. VCC5 is the
TA TB
5V supply input for control logic circuit of the controller. VCC5
RC filter to VCC5 is required for locally bypassing this
VDDIO
supply input. The controller monitors the VINSEN voltage Boot-VID
Startup
VID

for PWM on-time calculation. EN is the chip enable input SVC

pin. Logic high to this pin enables the controller, and logic SVD
low to this pin disables the controller. The above three inputs SVT VOTF
Telemory Telemory

(VCC5, VINSEN and EN) are monitored to determine Complete

whether the controller is ready for operation. EN

Figure 1 shows the power ready detection circuit. The VCC5 VDD & VDDA

voltage is monitored for power on reset with typically 4.3V POK

threshold at its rising edge.The VINSEN voltage is
PWROK
monitored for power on reset with typically 6V threshold at
its rising edge. The VDDIO voltage is monitored for power
on reset with typically 0.8V threshold at its rising edge. Figure 2. Power Up Sequence Timing
When VCC5, VDDIO and VINSEN are all ready, the Initial Start Up Voltage (Vboot) and SMBus Device
controller waits for EN to start up. When EN pin is driven Address (PROG)
above 2V, the controller begins its start up sequence. When Refer to the Table 1. The uP9505 determines the Vboot
EN pin is driven below 0.8V, the controller will be turned voltage upon the SVC and SVD status during POR.
off, and it will clear all fault states to prepare to next start Table 1. Vboot Voltage for both VDD and VDDA
up once the controller is re-enabled. Note that only VCC5
or EN toggle will clear all fault state, VDDIO or VINSEN SVC SVD V boot
toggle is not used for clearing fault state. Anytime any one
0 0 1.1V
of the four inputs falls below their power on reset level will
shutdown the controller. 0 1 1.0V
1 0 0.9V
4.3V 1 1 0.8V
VCC5
The uP9505 features selectable initial start up voltage
2V (Vboot) and SMBus device address for design flexibility.
EN PROG is a function setting pin, which is used to set the
6V two essential parameters. Refer to Figure 3, connect a
POR
VINSEN resistor voltage divider to the PROG pin to set the initial
start up voltage (Vboot) for VDDA and SMBus device
0.8V
address. The VDDA Vboot can be set to 1.55V, 1.5V,
VDDIO
1.35V, and follow SVI2 connections. The SMBus device
address can be set to 0x88h, or 0x8Ah. Table 2 shows
the recommended resistance value for PROG function
Figure 1. Circuit for Power Ready Detection setting.
Power-up Sequence
VCC5
Figure 2 shows a typical power-up sequence of uP9505.
When VCC5, VDDIO and VINSEN inputs are all ready, the
R1
controller waits for the EN signal to initiate the power on
PROG
sequence. After EN goes high, the controller waits for a
delay time TA (<1ms) then the output voltage starts to ramp R2

up to Vboot. The time interval TB is determined by the VID

upward slew rate. The uP9505 asserts POK when VDD/
VDDA rails are in regulation of the voltage (Vboot). Figure 3 Initial Parameter Setting

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 uP9505
Functional Description
Table 2.PROG Resistor Setting

R1/R2 Resistor Value (kΩ)

VD D A SMBus
4+2 Phase 5+1 Phase 6+0 Phase
Vboot (V) Address
R1 R2 R1 R2 R1 R2
1.55 88 4.92 3.37 24.61 16.84 NA NA
1.5 88 4.27 3.77 21.33 18.83 NA NA
1.35 88 3.76 4.27 18.82 21.34 NA NA
Follow SVI2
Connections 88 3.37 4.92 16.84 24.62 30.31 44.31
(Table 1)
1.55 8A 3.05 5.82 15.24 29.1 NA NA
1.5 8A 2.78 7.11 13.91 35.56 NA NA
1.35 8A 2.56 9.14 12.8 45.72 NA NA
Follow SVI2
Connections 8A 2.37 12.8 11.85 64.02 21.33 115.24
(Table 1)

Operation Phase Disable Function

The uP9505 supports operation phase disable function to further increase the design flexibility. Platform designer can
choose to disable some phases to meet their design requirement. Both VDD and VDDA rail support operation phase
disable function. The minimum operation phase number is 1+0-phase. In general, to disable a specific phase, pull up
CSNx to VCC5 through 1kΩ resistor and tie CSPx to ground for that phase. The controller detects all the CSNx voltage
at VCC5 power on reset to determine operation phase number.
Note that there is an exception for VDDA rail phase disable function. To let VDDA rail in zero-phase operation, pull up
CSNA to VCC5 through 1kΩ resistor and tied CSPA to ground. Table 4 shows the operation phase number setting.
In addition, the operating phase number is governed by the SVI2 command. The SVI2 command and operating phase
number are shown as Table 3.
Table 3. SVI2 Command and VDD & VDDA Operating Phase Number

PSI0_L PSI1_L Set VDD Phase Number Set VDDA Phase Number
1 1 Full Phase CCM Full Phase CCM
1 0 Full Phase CCM Full Phase CCM
0 1 1 Phase CCM 1 Phase CCM
0 0 1 Phase PSM 1 Phase PSM

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 uP9505
Functional Description
Table 4. Operation Phase Number Setting

Supported Pin connection, Pull High/ Pull Low to Target

Operation
Configuration
P h ase
Number CSPA CSNA CSP4 CSN4 CSP3 CSN3 CSP2 CSN2 CSP2A CSN2A CSP1A CSN1A

4+2 -- -- -- -- -- -- -- -- -- -- -- --

5+1 -- -- -- -- -- -- -- -- -- -- (Note 5) VC C 5

6+0 GND VCC5 -- -- -- -- -- -- -- -- -- --

3+2 GND VCC5 -- -- -- -- -- -- -- --

5+0 GND VCC5 -- -- -- -- -- -- -- -- GND VC C 5

4+1 -- -- -- -- -- -- -- -- GND VC C 5 -- --

4+0 GND VCC5 -- -- -- -- -- -- GND VC C 5 GND VC C 5

4+2-Phase
3+1 -- -- GND VCC5 -- -- -- -- GND VC C 5 -- --

2+2 -- -- GND VCC5 GND VCC5 -- -- -- -- -- --

3+0 GND VCC5 GND VCC5 -- -- -- -- GND VC C 5 GND VC C 5

2+1 -- -- GND VCC5 GND VCC5 -- -- GND VC C 5 -- --

2+0 GND VCC5 GND VCC5 GND VCC5 -- -- GND VC C 5 GND VC C 5

1+1 -- -- GND VCC5 GND VCC5 GND VCC5 GND VC C 5 -- --

1+0 GND VCC5 GND VCC5 GND VCC5 GND VCC5 GND VC C 5 GND VC C 5

Note 1. "--" denotes normal connection.

Note 2. Use 1kΩ pull up resistor when pull-up to VCC5
Note 3. Pay attention to the CSNA connection when using phase disable function of VDDA rail in zero phase
configuration.
Note 4. Strictly follow the table for phase disable. Incorrect PROG setting and incorrect pin pull up/down connection
will cause catastrophic fault during start-up.
Note 5. For 5+1 phase operation. CSP1A should be in normal connection.

PWM On-Time Setting Table 5. Switching Frequency and Resistor RTON

The PWM on-time is set by an external resistor RTON
connected between TONSET pin and GND. The controller Switching Frequency Recommended Resistor RTON
senses VINSEN voltage to obtain input voltage information (kHz) (kΩ)
for PWM on-time calculation. Both the VDD rail and VDDA 200 49.9
rail share the same PWM on-time setting. The PWM on
time can be calculated as below equation. 300 33

⎛ VOUT ⎞ 400 24.9

TON = ⎜ ⎟ × RTON × 100
⎝ VIN ⎠ 500 20
600 16
where TON is in ns, RTON is in kΩ.
Note: The minimum of resistor RTON value is 10kΩ.
Table 5 lists the switching frequency and the recommended
resistor RTON value (with condition: VIN = 12V, VOUT = 1.2V).
For example, given VIN = 12V, VOUT = 1.2V, RTON = 49.9kΩ,
TON is about 500ns by above equation. The PWM frequency
is about 200kHz. Note that the resistance value of RTON
value must be greater than 10kΩ to ensure the PWM on
time calculation circuit in normal operation.

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 uP9505
Functional Description
DAC Reference Voltage The error amplifier compares the VFB with VEAP (=VDAC - IMON
The uP9505 embeds separate precise bandgap reference x RDRP) to regulate the output voltage.
voltage generation circuits for VDD and VDDA controllers.
Figure 4 shows the reference voltage generation circuit. RCOMP_INT
VDD_SENSE FB
The output voltage of bandgap reference circuit is 1.55V Positive voltage remote RFB Gm COMP

sense pin of CPU

with respect to FBRTN (FBRTNA for VDDA). EAP RCOMP
RDRP
The uP9505 utilizes plural resistors to generate precise DAC Reference CCOMP
Voltage
reference voltages ranging from 6.25mV to 1.55V, with CDAC
CSP
6.25mV step. All the voltages connect to a multiplexer VSS_SENSE
Negative voltage remote
FBRTN
CCSN

(MUX). According to SVI2 command, the MUX outputs the sense pin of CPU CSN
IMON RCSN
selected VID (VDAC) to the current limit buffer input. The
DAC voltage is generated as the reference voltage to the
DAC pin (DACA pin for VDDA). The DAC voltage for VDDA Figure 5. Output Voltage Differential Sense
is generated by the same method except that it is referred
to FBRTNA pin. Table 6 shows the VID voltage and the Total Load Current Sense
SVI2 code. The uP9505 uses a low input offset current sense amplifier
(CSA) to sense the total load current flowing through
1.55V inductors for droop function by CSP and CSN (CSPA and
VBG
+ CSNA for VDDA) as shown in Figure 6.
R1

1.55V
R2 RPH1
PH1
- 6.25mV~1.55V
Step=6.25mV
RPH2
PH2
RPH3
FBRTN 6.25mV VDAC PH3
MUX CSP RPH4
PH4
RN Current
Limited CCSN
Buffer CSN 1ohm
VDD_1
IMON RCSN 1ohm
FBRTN
VDD_2
SVI2
Interface
1ohm
VDD_3
1ohm
Figure 4. Reference Voltage Generation Circuit VDD_4
Dynamic VID Change and Slew Rate
The controller accepts SetVID command via SVI2 bus for Figure 6.Total Load Current Sense
output voltage change during normal operation. This allows The voltage across CCSN is proportional to the total load
the output voltage to change while the DC/DC converter is current, and the output current of CSA (IMON) is also
running and supplying current to the load. This is commonly proportional to the total load current of the voltage regulator.
referred to as VID on-the-fly (VID OTF). A VID OTF event The sensed current IMON represents the total output current
may occur under either light or heavy load condition. This of the regulator, and it is directly used for droop function,
voltage change direction can be upward or downward. The total output over current protection, and output current
default value of VID upward slew rate is 12mV/us. The value reporting. IMON is calculated as follows.
of VID downward slew rate is 1/3 of VID upward slew rate.
The upward slew rate of VDD and VDDA can be separately
RDC
IOUT ×
further programmed by the controllers SMBus register IMON = P
0x26h. The upward slew rate can be set from 8mV/us to RCSN
22mV/us with a total of 7 steps and 2mV/LSB resolution. In this inductor current sensing topology, RPH and CCSN must
The default value of upward slew rate is 12mV/us. be selected according to the equation below:
Output Voltage Differential Sense
The uP9505 uses differential sense by a high-gain low offset L RPH × CCSN
k× =
error amplifier for output voltage differential sense as shown RDC P
in Figure 5. The CPU voltage is sensed by the FB and where RDC is the DCR of the output inductor L, P is the
FBRTN pins (FBA and FBRTNA for VDDA). FB pin is operation phase number. Theoretically, k should be equal
connected to the positive remote sense pin VDD_SENSE to 1 to sense the instantaneous total load current. But in
of the CPU via the resistor RFB. FBRTN pin is connected to real application, k is usually between 1.2 to 1.8 for better
the negative remote sense pin VSS_SENSE of CPU load transient response. Note that the resistance value of
directly. (VDDA_SENSE and VSSA_SENSE for VDDA). RCSN must be less than 2kΩ to ensure the current sensing
circuit in normal operation.

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 uP9505
Functional Description
Table 6. VID Table

SVID[7:0] Voltage(V) SVID[7:0] Voltage(V) SVID[7:0] Voltage(V) SVID[7:0] Voltage(V)

0000_0000 1.55000 001 0_0000 1.35000 01 00_0000 1.15000 0110_0000 0.95000
0000_0001 1.54375 001 0_0001 1.34375 01 00_0001 1.14375 0110_0001 0.94375
0000_001 0 1.53750 001 0_001 0 1.33750 01 00_001 0 1.13750 0110_0010 0.93750
0000_0011 1.53125 0010_0011 1.33125 0100_0011 1.13125 0110_0011 0.93125
0000_01 00 1.52500 001 0_01 00 1.32500 01 00_01 00 1.12500 0110_0100 0.92500
0000_01 01 1.51875 001 0_01 01 1.31875 01 00_01 01 1.11875 0110_0101 0.91875
0000_0110 1.51250 0010_0110 1.31250 0100_0110 1.11250 0110_0110 0.91250
0000_0111 1.50625 0010_0111 1.30625 0100_0111 1.10625 0110_0111 0.90625
0000_1 000 1.50000 001 0_1 000 1.30000 01 00_1 000 1.10000 0110_1000 0.90000
0000_1 001 1.49375 001 0_1 001 1.29375 01 00_1 001 1.09375 0110_1001 0.89375
0000_1 01 0 1.48750 001 0_1 01 0 1.28750 01 00_1 01 0 1.08750 0110_1010 0.88750
0000_1011 1.48125 0010_1011 1.28125 0100_1011 1.08125 0110_1011 0.88125
0000_1100 1.47500 0010_1100 1.27500 0100_1100 1.07500 0110_1100 0.87500
0000_1101 1.46875 0010_1101 1.26875 0100_1101 1.06875 0110_1101 0.86875
0000_1110 1.46250 0010_1110 1.26250 0100_1110 1.06250 0110_1110 0.86250
0000_1111 1.45625 0010_1111 1.25625 0100_1111 1.05625 0110_1111 0.85625
0001 _0000 1.45000 0011_0000 1.25000 01 01 _0000 1.05000 0111_0000 0.85000
0001 _0001 1.44375 0011_0001 1.24375 01 01 _0001 1.04375 0111_0001 0.84375
0001 _001 0 1.43750 0011_0010 1.23750 01 01 _001 0 1.03750 0111_0010 0.83750
0001_0011 1.43125 0011_0011 1.23125 0101_0011 1.03125 0111_0011 0.83125
0001 _01 00 1.42500 0011_0100 1.22500 01 01 _01 00 1.02500 0111_0100 0.82500
0001 _01 01 1.41875 0011_0101 1.21875 01 01 _01 01 1.01875 0111_0101 0.81875
0001_0110 1.41250 0011_0110 1.21250 0101_0110 1.01250 0111_0110 0.81250
0001_0111 1.40625 0011_0111 1.20625 0101_0111 1.00625 0111_0111 0.80625
0001 _1 000 1.40000 0011_1000 1.20000 01 01 _1 000 1.00000 0111_1000 0.80000
0001 _1 001 1.39375 0011_1001 1.19375 01 01 _1 001 0.99375 0111_1001 0.79375
0001 _1 01 0 1.38750 0011_1010 1.18750 01 01 _1 01 0 0.98750 0111_1010 0.78750
0001_1011 1.38125 0011_1011 1.18125 0101_1011 0.98125 0111_1011 0.78125
0001_1100 1.37500 0011_1100 1.17500 0101_1100 0.97500 0111_1100 0.77500
0001_1101 1.36875 0011_1101 1.16875 0101_1101 0.96875 0111_1101 0.76875
0001_1110 1.36250 0011_1110 1.16250 0101_1110 0.96250 0111_1110 0.76250
0001_1111 1.35625 0011_1111 1.15625 0101_1111 0.95625 0111_1111 0.75625

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 uP9505
Functional Description
SVID[7:0] Voltage(V) SVID[7:0] Voltage(V) SVID[7:0] Voltage(V) SVID[7:0] Voltage(V)
1 000_0000 0.75000 1 01 0_0000 0.55000 1100_0000 0.35000 1110_0000 0.15000
1 000_0001 0.74375 1 01 0_0001 0.54375 1100_0001 0.34375 1110_0001 0.14375
1 000_001 0 0.73750 1 01 0_001 0 0.53750 1100_0010 0.33750 1110_0010 0.13750
1000_0011 0.73125 1010_0011 0.53125 1100_0011 0.33125 1110_0011 0.13125
1 000_01 00 0.72500 1 01 0_01 00 0.52500 1100_0100 0.32500 1110_0100 0.12500
1 000_01 01 0.71875 1 01 0_01 01 0.51875 1100_0101 0.31875 1110_0101 0.11875
1000_0110 0.71250 1010_0110 0.51250 1100_0110 0.31250 1110_0110 0.11250
1000_0111 0.70625 1010_0111 0.50625 1100_0111 0.30625 1110_0111 0.10625
1 000_1 000 0.70000 1 01 0_1 000 0.50000 1100_1000 0.30000 1110_1000 0.10000
1 000_1 001 0.69375 1 01 0_1 001 0.49375 1100_1001 0.29375 1110_1001 0.09375
1 000_1 01 0 0.68750 1 01 0_1 01 0 0.48750 1100_1010 0.28750 1110_1010 0.08750
1000_1011 0.68125 1010_1011 0.48125 1100_1011 0.28125 1110_1011 0.08125
1000_1100 0.67500 1010_1100 0.47500 1100_1100 0.27500 1110_1100 0.07500
1000_1101 0.66875 1010_1101 0.46875 1100_1101 0.26875 1110_1101 0.06875
1000_1110 0.66250 1010_1110 0.46250 1100_1110 0.26250 1110_1110 0.06250
1000_1111 0.65625 1010_1111 0.45625 1100_1111 0.25625 1110_1111 0.05625
1 001 _0000 0.65000 1011_0000 0.45000 1101_0000 0.25000 1111_0000 0.05000
1 001 _0001 0.64375 1011_0001 0.44375 1101_0001 0.24375 1111_0001 0.04375
1 001 _001 0 0.63750 1011_0010 0.43750 1101_0010 0.23750 1111_0010 0.03750
1001_0011 0.63125 1011_0011 0.43125 1101_0011 0.23125 1111_0011 0.03125
1 001 _01 00 0.62500 1011_0100 0.42500 1101_0100 0.22500 1111_0100 0.02500
1 001 _01 01 0.61875 1011_0101 0.41875 1101_0101 0.21875 1111_0101 0.01875
1001_0110 0.61250 1011_0110 0.41250 1101_0110 0.21250 1111_0110 0.01250
1001_0111 0.60625 1011_0111 0.40625 1101_0111 0.20625 1111_0111 0.00625

1 001 _1 000 0.60000 1011_1000 0.40000 1101_1000 0.20000 1111_1000 OFF

1 001 _1 001 0.59375 1011_1001 0.39375 1101_1001 0.19375 1111_1001 OFF
1 001 _1 01 0 0.58750 1011_1010 0.38750 1101_1010 0.18750 1111_1010 OFF
1001_1011 0.58125 1011_1011 0.38125 1101_1011 0.18125 1111_1011 OFF
1001_1100 0.57500 1011_1100 0.37500 1101_1100 0.17500 1111_1100 OFF
1001_1101 0.56875 1011_1101 0.36875 1101_1101 0.16875 1111_1101 OFF
1001_1110 0.56250 1011_1110 0.36250 1101_1110 0.16250 1111_1110 OFF
1001_1111 0.55625 1011_1111 0.35625 1101_1111 0.15625 1111_1111 OFF

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 uP9505
Functional Description
Droop (Load Line) Setting and LGx will be held low, and all PWM outputs will in high
As shown in Figure 5, the current IMON denotes the sensed impedance state to let driver turns off all MOSFETs to
total load current, which is mirrored to the EAP pin. When shutdown the regulator. The other unaffected voltage
load current increases, IMON also increases and creates a regulator will also shut down. The total output OCP is a
voltage drop across RDRP, and makes VEAP lower than the latch-off type protection, and it can only be reset by VCC5
VDAC as follows. or EN toggling. The total output OCP delay time can be
further programmed by the SMBus register. Avoid adding
⎛ IOUT × RDC ⎞
VEAP = VDAC − IMON × RDRP = VDAC − ⎜ ⎟ × RDRP capacitor to the IMON pin. Additional capacitance to this
⎝ RCSN × P ⎠ pin will affect the total output OCP. The default output
where RDC is the DCR of output inductor, P is the operation current level of triggering total output OCP is calculated
phase number, and IOUT denotes the total load current. In as follows.
steady state, the output voltage is regulated to VEAP. As the 2.56 P × RCSN
total load current I OUT increases, I MON increases IOUT _ OCP = ×
proportionally, making VEAP decreases accordingly. This RIMON RDC
makes the output voltage also decreases linearly as the
total output current increases, which is also known as active CSP
voltage positioning (AVP). The slope of output voltage CCSN
decrease to total load current increase is referred to as CSN
load line. The load line is defined as follows 2.56V
IMON RCSN
OCP IMON
∆VOUT RDC × RDRP
Load Line = = RIMON
∆IOUT RCSN × P
Total Output OCP and Operating Phase Number Figure 7. Total Output OCP
As shown in Figure 7, the sensed current IMON is mirrored The total output OCP level is usually designed for the
internally and fed to IMON pin (IMONA for VDDA) for total voltage regulator that is operated in full phase condition
output over current protection (OCP). A resistor RIMON is by hardware setting. The actual operating phase number
connected from IMON pin to GND. This current flows through is controlled by the SVI2 command or the SMBus Auto
the resistor RIMON, creating voltage drop across it. As the Phase setting. When the operating phase number is
total load current increases, the voltage on IMON pin (VIMON) decreased, the total output OCP level is decreased as well.
increases proportionally. When the IMON pin voltage further The total output OCP level is changed per actual operating
increases to greater than the OCP threshold (2.56V) for a phase number. Table 7 shows the total output OCP ratio
specific delay time, the total output current protection will per actual operating phase number and the hardware
be triggered. POK will be pulled low immediately, both UGx configuration

Table 7. Total Output OCP and Operating Phase Number

Operating Condition
Total Output OCP Ratio
6-Phase 5-Phase 4-Phase 3-Phase 2-Phase 1-Phase
6-Phase 1 10/12 9/12 8/12 5/12 4/12
5-Phase -- 1 10/12 8/12 5/12 4/12

Hardware 4-Phase -- -- 1 9/12 8/12 5/12

Configuration 3-Phase -- -- -- 1 9/12 5/12
2-Phase -- -- -- -- 1 8/12
1-Phase -- -- -- -- -- 1

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 uP9505
Functional Description
Per-Phase Over Current Protection Over Voltage Protection (OVP)
In addition to the total output current OCP, the controller The controller monitors the voltage on FB pin (FBA for VDDA)
provides per-phase current OCP to protect the voltage for over voltage protection. After output voltage ramps up to
regulator. The controller uses DCR current sensing Vboot, the controller initiates OVP function. Once VFB
technique to sense the inductor current in each phase for exceeds VEAP + OVP threshold for a specific delay time,
per-phase over current protection and current balance as OVP is triggered. POK will be pulled low immediately, UGx
shown in Figure 8. In this inductor current sensing topology, will be held low, LGx will be held high, and PWM outputs
the time constant can expressed as follows. will be low to let driver turns on low side MOSFET and turns
off high side MOSFET to protect CPU. Since the low side
L MOSFET is turned on, the regulator output capacitor will
k× = RCSPx × CCSx
RDC be discharged and output voltage decreases as well. When
where L is the output inductor, RDC is its parasitic resistance FB pin voltage decreases to lower than typical 0.5V, LGx
and k is a constant. Theoretically, if k = 1, the sensed will be held low (PWM outputs turns to high impedance
current signal ICSNx can be expressed as follows. state) to turn off the low side MOSFET to avoid negative
output voltage. The other unaffected voltage regulator will
ILX × RDC also shut down. The OVP is a latch-off type protection, and
ICSNx =
RCSNx it can only be reset by VCC5 or EN toggling. The OVP
detection circuit has a fixed delay time to prevent false
VIN
trigger. The OVP threshold can be further programmed by
the SMBus register.
L RDC
Under Voltage Protection (UVP)
VDD
ILx The controller monitors the voltage on FB pin (FBA for VDDA)
for under voltage protection. After output voltage ramps up
to Vboot, the controller initiates UVP function. Once VFB is
lower than VEAP - UVP threshold for a specific delay time,
UVP is triggered. POK will be pulled low immediately, both
UGx and LGx will be held low, and all PWM outputs will in
CSPx RCSPx high-impedance state to let driver turns off all MOSFETs to
CCSx
shutdown the regulator. The other unaffected voltage
CSNx regulator will also shut down. The UVP is a latch-off type
ICSNx RCSNx protection, and it can only be reset by VCC5 or EN toggling.
The UVP detection circuit has a fixed delay time to prevent
false trigger. The UVP threshold can be further programmed
Figure 8. Phase Current Sense by the SMBus register.
The sensed current ICSNx represents the current in each Thermal Monitoring and VRHOT#
phase, and it is compared to a current (default = 100uA, The TSEN pin (TSENA for VDDA) is used for voltage regulator
SMBus programmable) for per-phase OCP. If the inductor thermal monitoring. Connect a negative temperature
current of any of the active operating phase exceeds the coefficient ( NTC) thermistor network to this pin for sensing
threshold for a specific delay time, the per-phase OCP is VR temperature. The curve of TSEN (TSENA for VDDA) pin
triggered. POK will be pulled low immediately, both UGx voltage and the sensed temperature is shown in Figure 9.
and LGx will be held low, and all PWM outputs will in high- The NTC thermistor is placed close to the hottest point of
impedance state to let driver turns off all MOSFETs to the regulator, normally close to the inductor and low-side
shutdown the regulator. The other unaffected voltage MOSFET of phase 1. The controller asserts VRHOT# when
regulator will also shut down. The per-phase OCP is a latch- the sensed temperature is higher than the value of SMBus
off type protection, and it can only be reset by VCC5 or EN register 0x29h (TEMP_VRHOT), in which the default value
toggling. The per-phase OCP threshold and its delay time is 05h (106oC). Either VDD or VDDA regulator can trigger
can be further programmed by the SMBus register. Note the VRHOT# as long as the temperature of any of the two
that the resistance value of RCSNx must be less than 2kΩ to regulators exceeds the maximum temperature threshold.
ensure the current sensing circuit in normal operation. The The threshold of VRHOT# assertion can be further
resistance of RCSNx and the default per-phase OCP level can programmed by SMBus register. The recommended NTC
be obtained using equation as follows: thermistor is 10kΩ/β = 3380 by Murata (NCP18XH103F03RB)
and the recommended lower dividing resistor is 6kΩ.
IOCP _ perphase × RDC
RCSNx =
100uA
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 uP9505
Functional Description
as Table 8. The main function is to dynamically change the
4.6
offset voltage, switching frequency, operating phase number,
4.55 and load line according to the total load current. This function
is referred to as Auto Phase, and it provides user the
TSEN/TSENA Pin Voltage (V)

4.5
maximal flexibility in the platform design to maximize
4.45
voltage regulator’s efficiency and the processor performance
4.4 as well. For the 4-phase VDD regulator, there are four load
4.35 current states (LCS) to set. The switching frequency, offset
4.3
voltage, operating phase number and load line in each LCS
can be programmed independently. For the 2-phase VDDA
4.25 regulator, there are two load current states (LCS) to set.
4.2 The switching frequency, offset voltage and operating phase
4.15 number in each LCS can also be programmed
independently.
4.1
VM0~ VM4 (AVM0 for VDDA): Define the thresholds for
90 95 100 105 110 115 120 125
six load current states (LCS0~LCS5) for VDD. The VDD
Sensed Temperature (oC)
controller converts IMON pin voltage VIMON to a digital
Figure 9. TSEN/TSENA Pin Voltage and Sensed Temperature content, which represents the total output current. The VMx
Power OK Indication setting is defined as the ratio of IMON pin voltage to 2.56V
The uP9505 has a power ok indication pin for VDD/VDDA (2.56V denotes when VDD output current reaches its
controllers. The VDD/VDDA controller monitors DAC/DACA summed total current). It takes 2.56V as the full scale, and
voltage for power ok indication. When DAC/DACA voltage 6-bits means that there are 64 steps for user to choose
ramps to the target output voltage, the controller asserts from. Each load current state register has 6-bits to set the
POK. The POK is pulled low immediately if any of the faults level of output current that the load current state is entered.
(OCP, OVP and UVP) occurs. The controller compares the VMx content and the IMON (refer
Control Loop to the section of Total Output Over Current Protection)
to determine which load current state should be entered
The uP9505 adopts the uPI proprietary RCOT+TM control and executes the corresponding operating parameter
technology. The RCOT uses the constant on-time settings (frequency, offset and operating phase number).
modulator. The output voltage is sensed to compare with
the internal high accurate reference voltage. The reference LCS0: VIMON > VM0, highest load current state
voltage is commanded by CPU through the SVI2 interface LCS1: VM0 > VIMON > VM1
or by system through SMBus interface. The amplified error LCS2: VM1 > VIMON > VM2
signal VCOMP is compared to the internal ramp to initiate a
PWM on-time. The RCOT+TM features easy design, fast LCS3: VM2 > VIMON > VM3
transient response and is smooth mode transition and LCS4: VM3 > VIMON > VM4
especially suitable for powering the microprocessor LCS5: VM4 > VIMON, lowest load current state.
Serial VID Interface 2.0 (SVI2) VM0_Hys~ VM4_Hys (AVM0_Hys for VDDA):
Serial VID Interface 2.0 (SVI2) is a three wire (SVC, SVD Define the hysteresis of VM0~VM4. The hysteresis is also
and SVT) serial synchronous interface defined by AMD to defined as the ratio of IMON pin voltage to 2.56V.
transfer power management information between the CPU
and the VR controller. The SVI2 bus operates at a maximum VOFS0~VOFS5 (AVOFS0, AVOFS1 for VDDA):
frequency of 21MHz. CPU is always the master, and the Define the offset voltage in each load current state. 8-bits
VR controller is always the slave. SVC, SVD and SVT pins content setting with 6.25mV/step.
are both in push-pull structure. SVC is source synchronous
IICF0~ IICF5 (AIICF0, AIICF1 for VDDA):
clock signal from the CPU. Only PWROK is asserted, SVC
and SVD can be used to serially transmit data from the Define the switching frequency in each load current state.
CPU to VR. The switching frequency is defined as the ratio to current
setting per RTONSET and VIN. The default is 1000 for 100%.
SMBus Interface
0000 = 60%; 0001 = 65%; 0010 = 70%;0011 = 75%; 0100
The uP9505 features an SMBus interface and data registers = 80%; 0101 = 85%; 0110 = 90%; 0111 = 95%; 1000 =
to allow user to adjust various platform operating parameters 100%; 1001=125%; 1010 = 150%; 1011 = 175%; 1100 =
for VDD and VDDA. The supported operating parameters 200%; 1101 = 225%; 1110 = 250%; 1111 = 275%.
that can be adjusted through the SMBus are summarized

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 uP9505
Functional Description
IICP0~IICP5 (AIICP0, AIICP1 for VDDA): OC/UV/OV:
Define the operating phase number in each load current OC/UV/OV is used for the threshold adjustment of per-
state. The operating phase number can be full-phase to phase OCP, UVP and OVP, respectively.
single phase OCP Delay: For total OCP threshold and per-phase OCP
IICLL0~ IICLL5 (AIICLL0, AIICLL1 for VDDA): delay time setting.
Define the load line value in each load current state. The LCHVID (ALCHVID for VDDA):
load line adjustment is defined as the ratio to current droop This register stores the 8-bits VID code. When latch VID
setting. The default is 0110 for 100%. 0000 = 0%; 0001 = function is enabled, controller will ignore the SetVID
40%; 0010 = 60%;0011 = 70%; 0100 = 80%; 0101 = 90%; command from CPU and move output voltage to the
0110 = 100%; 0111 =110%; 1000 = 120%;1001=130%; targeted value.
1010 = 140%; 1011 = 150%; 1100 = 160%; 1101 =170%;
1110 = 180%; 1111 = 190%. IMON (IMONA for VDDA):
RCOMP1, RCOMP2 (ARCOMP1, ARCOMP2 for VDDA): The register reports real IMON value (FFh when VIMON =
Define the compensation resistor value. The compensation 2.56V).
resistor value for the regulator operating in single-phase VFB (VFBA for VDDA):
operation and multi-phase operation can be adjusted
This register reports the output voltage that is converted
separately.
by the internal ADC with 6.25mV/LSB.
GCOMP (AGCOMP for VDDA):
For OTA transconductance setting for voltage control loop.
It is defined as the ratio to the default value of 2020 uA/V.

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 uP9505
Functional Description
Table 8. SMBus Configuration Register

R eg . F o cu s
Reg. Name Access Default Description
Addr. Rail
Set internal IMON voltage level 0
VIMON > Level 0 => LCS0 (highest current state)
0x01 VD D VM0[7:2] R/W 00h Bit[1:0] : Don't care
VM0 = (Bit[7:2]/64) x 2.56
VM0 setting is defined as the ratio to IMON voltage to 2.56V
Set internal IMON voltage level 1
VIMON > Level 1 => LCS1
VIMON < Level 1 => LCS2
0x02 VD D VM1[7:2] R/W 00h
Bit[1:0] : Don't care
VM1 = (Bit[7:2]/64) x 2.56
VM1 setting is defined as the ratio to IMON voltage to 2.56V
Set internal IMON voltage level 2
VIMON > Level 2 => LCS2
VIMON < Level 2 => LCS3
0x03 VD D VM2[7:2] R/W 00h
Bit[1:0] : Don't care
VM2 = (Bit[7:2]/64) x 2.56
VM2 setting is defined as the ratio to IMON voltage to 2.56V
Set internal IMON voltage level 3
VIMON > Level 3 => LCS3
VIMON < Level 3 => LCS4
0x04 VD D VM3[7:2] R/W 00h
Bit[1:0] : Don't care
VM3 = (Bit[7:2]/64) x 2.56
VM3 setting is defined as the ratio to IMON voltage to 2.56V
Set internal IMON voltage level 4
VIMON > Level 4 => LCS4
VIMON < Level 4 => LCS5
0x05 VD D VM4[7:2] R/W 00h
Bit[1:0] : Don't care
VM4 = (Bit[7:2]/64) x 2.56
VM4 setting is defined as the ratio to IMON voltage to 2.56V
VBit[7]: Don't care
Bit[6:4] : Set VM0 Hysteresis, 8 steps
Hys = (2.56 / 100) x (2 + bit[6:4])
VM0_Hys[6:4]
0x06 VD D R/W 00h Bit[3]: Don't care
VM1_Hys[2:0]
Bit[2:0] : Set VM1 Hysteresis, 8 steps
Hys = (2.56 / 100) x (2 + bit[2:0])
Hysteresis is defined as the ratio of IMON pin voltage to 2.56V
Bit[7]: Don't care
Bit[6:4] : Set VM2 Hysteresis, 8 steps
Hys = (2.56 / 100) x (2 + bit[6:4])
VDD VM2_Hys[6:4]
0x07 R/W 00h Bit[3]: Don't care
VDDA AVM0_Hys[2:0] Bit[2:0] : Set AVM0 Hysteresis, 8 steps
Hys= (2.56 / 100) x (2+bit[2:0])
Hysteresis is defined as the ratio of IMON pin voltage to 2.56V
Bit[7]: Don't care
Bit[6:4] : Set VM3 Hysteresis, 8 steps
VM3_Hys[6:4] Hys = (2.56 / 100) x (2 + bit[6:4])
0x08 VD D R/W 00h
VM4_Hys[2:0] Bit[3]: Don't care Bit[2:0] : Set VM4 Hysteresis, 8 steps
Hys = (2.56 / 100) x (2 + bit[2:0])
Hysteresis is defined as the ratio of IMON pin voltage to 2.56V

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 uP9505
Functional Description
R eg . F o cu s
Reg. Name Access Default Description
Addr. Rail
VDD Operation Phase Number Setting
Bit[6:4] : Phase Number of VDD LCS0
IICP0[6:4]
0x09 VD D R/W 66h Bit[2:0] : Phase Number of VDD LCS1
IICP1[2:0]
110 : 6 Phase; 101 : 5 Phase; 100 : 4 Phase; 011 : 3 Phase;
010 : 2 Phase; 001 : 1 Phase CCM; 000 : 1 Phase PSM
VDD Operation Phase Number Setting
Bit[6:4] : Phase Number of VDD LCS2
IICP2[6:4]
0x0A VD D R/W 66h Bit[2:0] : Phase Number of VDD LCS3
IICP3[2:0]
110 : 6 Phase; 101 : 5 Phase; 100 : 4 Phase; 011 : 3 Phase;
010 : 2 Phase; 001 : 1 Phase CCM; 000 : 1 Phase PSM
VDD Operation Phase Number Setting
Bit[6:4] : Phase Number of VDD LCS4
IICP4[6:4]
0x0B VD D R/W 66h Bit[2:0] : Phase Number of VDD LCS5
IICP5[2:0]
110 : 6 Phase; 101 : 5 Phase; 100 : 4 Phase; 011 : 3 Phase;
010 : 2 Phase; 001 : 1 Phase CCM; 000 : 1 Phase PSM
Voltage offset of VDD LCS0. (6.25mV / step)
Bit7 is sign bit, "0"=positive offset; "1"=negative offset
Upper and lower limits = +/-750mV
00000000 = +0mV
00000001 = +6.25mV
00111100 = +375mV
0x0C VD D VOFS0[7:0] R/W 00h 01111000 = +750mV
01111111 = +750mV
10000000 = -0mV
10000001 = -6.25mV
10111100 = -375mV
11111000 = -750mV
11111111 = -750mV
Voltage offset of VDD LCS1. (6.25mV / step)
Bit7 is sign bit, "0"=positive offset; "1"=negative offset
Upper and lower limits = +/-750mV
00000000 = +0mV
00000001 = +6.25mV
00111100 = +375mV
0x0D VD D VOFS1[7:0] R/W 00h 01111000 = +750mV
01111111 = +750mV
10000000 = -0mV
10000001 = -6.25mV
10111100 = -375mV
11111000 = -750mV
11111111 = -750mV
Voltage offset of VDD LCS2. (6.25mV / step)
Bit7 is sign bit, "0"=positive offset; "1"=negative offset
Upper and lower limits = +/-750mV
00000000 = +0mV
00000001 = +6.25mV
00111100 = +375mV
0x0E
VD D VOFS2[7:0] R/W 00h 01111000 = +750mV
01111111 = +750mV
10000000 = -0mV
10000001 = -6.25mV
10111100 = -375mV
11111000 = -750mV
11111111 = -750mV

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 uP9505
Functional Description
R eg . F o cu s
Reg. Name Access Default Description
Addr. Rail
Voltage offset of VDD LCS3. (6.25mV / step)
Bit7 is sign bit, "0"=positive offset; "1"=negative offset
Upper and lower limits = +/-750mV
00000000 = +0mV
00000001 = +6.25mV
00111100 = +375mV
0x0F VD D VOFS3[7:0] R/W 00h 01111000 = +750mV
01111111 = +750mV
10000000 = -0mV
10000001 = -6.25mV
10111100 = -375mV
11111000 = -750mV
11111111 = -750mV
Voltage offset of VDD LCS4. (6.25mV / step)
Bit7 is sign bit, "0"=positive offset; "1"=negative offset
Upper and lower limits = +/-750mV
00000000 = +0mV
00000001 = +6.25mV
00111100 = +375mV
0x10 VD D VOFS4[7:0] R/W 00h 01111000 = +750mV
01111111 = +750mV
10000000 = -0mV
10000001 = -6.25mV
10111100 = -375mV
11111000 = -750mV
11111111 = -750mV
Voltage offset of VDD LCS5. (6.25mV / step)
Bit7 is sign bit, "0"=positive offset; "1"=negative offset
Upper and lower limits = +/-750mV
00000000 = +0mV
00000001 = +6.25mV
00111100 = +375mV
0x11 VD D VOFS5[7:0] R/W 00h 01111000 = +750mV
01111111 = +750mV
10000000 = -0mV
10000001 = -6.25mV
10111100 = -375mV
11111000 = -750mV
11111111 = -750mV
VDD Operation Frequency Setting
Bit[7:4] : Phase Number of VDD LCS0, default = 100%
Bit[3:0] : Phase Number of VDD LCS1, default = 100%
IICF0[7:4]
0x12 VD D R/W 88h 0000 = 60%; 0001 = 65%; 0010 = 70%;0011 = 75%;
IICF1[3:0]
0100 = 80%; 0101 = 85%; 0110 = 90%; 0111 = 95%;
1000 = 100%(default); 1001=125%; 1010 = 150%; 011 = 175%;
1100 = 200%; 1101 = 225%; 1110 = 250%; 1111 = 275%
VDD Operation Frequency Setting
Bit[7:4] : Phase Number of VDD LCS2, default = 100%
Bit[3:0] : Phase Number of VDD LCS3, default = 100%
IICF2[7:4]
0x13 VD D R/W 88h 0000 = 60%; 0001 = 65%; 0010 = 70%;0011 = 75%;
IICF3[3:0]
0100 = 80%; 0101 = 85%; 0110 = 90%; 0111 = 95%;
1000 = 100%(default); 1001=125%; 1010 = 150%; 011 = 175%;
1100 = 200%; 1101 = 225%; 1110 = 250%; 1111 = 275%

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 uP9505
Functional Description
R eg . F o cu s
Reg. Name Access Default Description
Addr. Rail
VDD Operation Frequency Setting
Bit[7:4] : Phase Number of VDD LCS4, default = 100%
Bit[3:0] : Phase Number of VDD LCS5, default = 100%
IICF4[7:4]
0x14 VD D R/W 88h 0000 = 60%; 0001 = 65%; 0010 = 70%;0011 = 75%;
IICF5[3:0]
0100 = 80%; 0101 = 85%; 0110 = 90%; 0111 = 95%;
1000 = 100%(default); 1001=125%; 1010 = 150%; 011 = 175%;
1100 = 200%; 1101 = 225%; 1110 = 250%; 1111 = 275%
VDD Load Line Setting
Bit[7:4] : Load line setting of VDD LCS0, default = 100%
Bit[3:0] : Load line setting of VDD LCS1, default = 100%
IICLL0[7:4]
0x15 VD D R/W 66h 0000 = 0%; 0001 = 40%; 0010 = 60%; 0011 = 70%; 0100 = 80%;
IICLL1[3:0]
0101 = 90%; 0110 = 100%(default); 0111 =110%; 1000 = 120%;
1001 =130%; 1010 = 140%; 1011 = 150%; 1100 = 160%;
1101 =170%; 1110 = 180%; 1111 = 190%
VDD Load Line Setting
Bit[7:4] : Load line setting of VDD LCS2, default = 100%
Bit[3:0] : Load line setting of VDD LCS3, default = 100%
IICLL2[7:4]
0x16 VD D R/W 66h 0000 = 0%; 0001 = 40%; 0010 = 60%; 0011 = 70%; 0100 = 80%;
IICLL3[3:0]
0101 = 90%; 0110 = 100%(default); 0111 =110%; 1000 = 120%;
1001 =130%; 1010 = 140%; 1011 = 150%; 1100 = 160%;
1101 =170%; 1110 = 180%; 1111 = 190%
VDD Load Line Setting
Bit[7:4] : Load line setting of VDD LCS4, default = 100%
Bit[3:0] : Load line setting of VDD LCS5, default = 100%
IICLL4[7:4]
0x17 VD D R/W 66h 0000 = 0%; 0001 = 40%; 0010 = 60%; 0011 = 70%; 0100 = 80%;
IICLL5[3:0]
0101 = 90%; 0110 = 100%(default); 0111 =110%; 1000 = 120%;
1001 =130%; 1010 = 140%; 1011 = 150%; 1100 = 160%;
1101 =170%; 1110 = 180%; 1111 = 190%
Bit[7]: On/Off control of VDD current balance function,
default = ON, "0" = ON, "1" = OFF
Bit[6:4] : VDD Phase 1 current balance gain adjust, default = 100%
CB_EN[7] 000 = 50%; 001 = 62.5%; 010 = 75%; 011 = 87.5%; 100 = 100%
0x18 VD D PH1_IGAIN[6:4] R/W 44h (default); 101 = 112.5%; 110 = 125%; 111 = 137.5%
PH2_IGAIN[2:0] Bit[3] : Don't care
Bit[2:0] : VDD Phase 2 current balance gain adjust, default = 100%
000 = 50%; 001 = 62.5%; 010 = 75%; 011 = 87.5%; 100 = 100%
(default); 101 = 112.5%; 110 = 125%; 111 = 137.5%
Bit[7] : Don't care
Bit[6:4] : VDD Phase 3 current balance gain adjust, default = 100%
000 = 50%; 001 = 62.5%; 010 = 75%; 011 = 87.5%; 100 = 100%
PH3_IGAIN[6:4] (default) ; 101 = 112.5%; 110 = 125%; 111 = 137.5%
0x19 VD D R/W 44h
PH4_IGAIN[2:0] Bit[3] : Don't care
Bit[2:0] : VDD Phase 4 current balance gain adjust, default = 100%
000 = 50%; 001 = 62.5%; 010 = 75%; 011 = 87.5%; 100 = 100%
(default); 101 = 112.5%; 110 = 125%; 111 = 137.5%
Bit[7]: Don't care
Bit[6:4] : VDD Phase 1 current balance offset, default = 0uA
000 = 0uA(default); 001 = 2uA; 010 = 4uA; 011 = 6uA; 100 = 8uA;
0x1B PH1_IOS[6:4] 101 = 10uA; 110 = 12uA; 111 = 14uA
VD D R/W 00h
PH2_IOS[2:0] Bit[3]: Don't care
Bit[2:0] : VDD Phase 2 current balance offset, default = 0uA
000 = 0uA(default); 001 = 2uA; 010 = 4uA; 011 = 6uA; 100 = 8uA;
101 = 10uA; 110 = 12uA; 111 = 14uA

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 uP9505
Functional Description
R eg . F o cu s
Reg. Name Access Default Description
Addr. Rail
Bit[7]: Don't care
Bit[6:4] : VDD Phase 3 current balance offset, default = 0uA
000 = 0uA(default); 001 = 2uA; 010 = 4uA; 011 = 6uA; 100 = 8uA;
PH3_IOS[6:4] 101 = 10uA; 110 = 12uA; 111 = 14uA
0x1C VD D R/W 00h
PH4_IOS[2:0] Bit[3]: Don't care
Bit[2:0] : VDD Phase 4 current balance offset, default = 0uA
000 = 0uA(default); 001 = 2uA; 010 = 4uA; 011 = 6uA; 100 = 8uA;
101 = 10uA; 110 = 12uA; 111 = 14uA
RCOMP Resistor Setting
Bit[7:4] : Single-phase operation RCOMP
RCOMP1[7:4]
0x1E VD D R/W 73h RCOMP = 2.5K x (1+[7:4]), default = 20K
RCOMP2[3:0]
Bit[3:0] : Multi-phase operation RCOMP
RCOMP = 2.5K x (1+[3:0]), default = 10K
VDD OTA Gm value selection
GCOMP[3] : VDD OTA Gm value selection
0 = force to use default value (2020uA/V), GCOMP[2:0] setting will
be ignored(default);
0x1F VD D GCOMP[3:0] R/W 80h 1 = use the value set in GCOMP[2:0]
GCOMP[2:0] : VDD transconductance Gm setting, applied to all
operating phase number, defined as the ratio to default (=2020uA/V)
000 = 1X(default); 001 = 1.17X; 010 = 1.31X; 011 = 1.45X;
100 = 1.69X; 101 = 0.81X; 110 = 0.6X; 111 = 0.33X

0x20 VD D LCHVID[7:0] R/W 48h VDD Latch VID Register. Default = 48h = 1.1V

0x21 VD D IMON[7:0] RO -- VDD IMON reporting

VDD voltage Reading
0x22 VD D VFB[7:0] RO -- Voltage reading values in VFB[7:0] is from A/D result of actual output
voltage by default.
VDD protection indicator, indicating which protection is triggered
Bit[7] : Don't care
Bit[6] : OVP Indicator
"0" = Not Active, "1" = Active
Bit[5] : UVP Indicator
"0" = Not Active, "1" = Active
Bit[4] : OCP Indicator
0x23 VD D Protect_Ind[6:0] RO 00h
"0" = Not Active, "1" = Active
Bit[3] : Per Phase OCP Indicator
"0" = Not Active, "1" = Active
Bit[2:0]: Per Phase OCP Indicator if Bit[3]=1
001 = PH1; 010 = PH2; 011 = PH3
100 = PH4; 101 = PH5; 110 = PH6
Report value of Bit[2:0] is valid only when Bit[3]=1
Both VDD and VDDA share the same setting
Bit[7] : Don't care
Bit[6:4] : Total OCP Delay Time
000 = 5us; 001 = 10us; 010 = 15us; 011 = 20us(default);
OCP Delay
0x24 shared R/W 32h 100 = 25us; 101 = 30us; 110 = 35us; 111 = 40us
[6:0]
Bit[3] : Don't care
Bit[2:0] : Per Phase OCP Delay Time
000 = 2us; 001 = 4us; 010 = 6us(default) ; 011 = 8us; 100 = 10us;
101 = 12us; 110 = 14us; 111 = 16us

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 uP9505
Functional Description
R eg . F o cu s
Reg. Name Access Default Description
Addr. Rail
Both VDD and VDDA share the same setting
Bit[7] : Don't care
Bit[5:4] : Per Phase OCP Current
OC/UV/OV 00 = 100uA(default); 01 = 120uA; 10 = 140uA; 11 = 160uA
0x25 shared R/W 00h
[5:0] Bit[3:2] : UVP Threshold
00 = 325mV(default); 01 = 405mV; 10 = 485mV; 11 = 570mV
Bit[1:0] : OVP Threshold
00 = 325mV(default); 01 = 405mV; 10 = 485mV; 11 = 570mV
Bit[7] : Don't care
Bit [6:4] : VDD d-VID upward slew rate selection
Bit [2:0] : VDDA d-VID upward slew rate selection
AVR_SR[6:4] DVID upward slew rate selection. Setting range from 8 to 22 mV/uS.
0x26 shared R/W 22h
VR_SR[2:0] Total 7 steps and 2mV/us per-LSB. Default is 12mV/us.
000 = 8mV/us; 001 = 10mV/us; 010 = 12mV/us(default);
011 = 14mV/us; 100 = 16mV/us; 101 = 18mV/us; 110 = 20mV/us;
111 = 22mV/us;
Bit[7] :OFS control 2
Report value of Bit[7] is valid only when Bit[4]=1
"0" =Only SMBus, "1" = SVI2+ SMBus
Bit[6] : VDAC Control
"0" = Follow SVI2, "1" = Ignore SVI2
Bit[5] : PWR State Control
"0" = Follow SVI2, "1" = Ignore SVI2
Bit[4]: OFS control1
0x27 VD D Misc1[7:0] R/W 0F h "0" = Follow SVI2, "1" = Follow Bit[7]
Bit[3]: Total OCP Control
"0" = Disable, "1" = Enable(default)
Bit[2]: Per-phase OCP Control
"0" = Disable, "1" = Enable(default)
Bit[1]: OVP Control
"0" = Disable, "1" = Enable(default)
Bit[0]: UVP Control
"0" = Disable, "1" = Enable(default)
Bit[7] : Load Line Control
"0" = Follow SVI2
"1" = Ignore SVI2
Bit[6] : Spread Spectrum for switching frequency
"0" = Disable Spread Spectrum(default)
"1" = Enable Spread Spectrum
Bit[5]: Selection of the data source of SMBus Reg.
0x22h VDD output voltage reading(VFB [7:0])
"0" = From A/D(default)
"1" = From SVI2
Bit[4] : Auto Phase Enable Control
0x28 VD D Misc2[7:0] R/W 04h
"0" = Disable Auto Phase(default)
"1" = Enable Auto Phase
Bit[3] : Load Line Enable Control
"0" = Enable Load Line(default)
"1" = Disable Load Line (LL = 0)
Bit[2] : PSM Enable Control
"0" = Disable PSM
"1" = Enable PSM(default)
Bit[1:] : USM Enable Control
"0" = Disable USM(default)
"1" = Enable USM

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 uP9505
Functional Description
R eg . F o cu s
Reg. Name Access Default Description
Addr. Rail
Bit[7] : OTP Shutdown Enable Control (TSEN/TSENA)
"0" = Disable(default), "1" = Enable
Bit[6] : OTP(internal) Enable Control (controller thermal shutdown)
"0"= Disable, "1" = Enable(default)
Bit[5] : Don't care
OTPEN1[7]
Bit[4] : VRHOT# Enable Control
VD D , OTPEN2[6]
0x29 R/W 45h "0" = Enable(default), "1" = Disable
shared TEMP_VRHOT Bit[3:0] : Shift left by LSB, Temp range from 91oC to 121oC, default =
[4:0]
106oC, 3oC/LSB
0000 = No Shift; 0001 = Shift 1LSB; 0010 = Shift 2LSB;
0011 = Shift 3LSB; 0100 = Shift 4LSB; 0101 = Shift 5LSB (default) ;
0110 = Shift 6LSB; 0111 = Shift 7LSB; 1000 = Shift 8LSB;
1001 = Shift 9LSB; 1010 = Shift 10LSB
Watchdog Timer
Bit[7] : "1" = Enable ; "0" = Disable(default)
Bit[6] : Watchdog status
"0" = SMBus transactions occurred within watchdog period
"1" = time between SMBus transaction exceeds watchdog period
When the watchdog function is enabled, if no SMBus transactions
WD[7:5]
occur within a selected period (600ms or 1200ms), all register
0x2A shared SVC_Timeout R/W 05h
contents will be reset to default value. This bit is cleared by SMBus
[2:0]
read from this register.
Bit[5] : Watchdog period
"0" = 600ms(default)
"1" = 1200ms
SVC_Timeout: Bit[2:0] : 000 = 0.5us; 001 = 1us; 010 = 2us; ... ;
110 = 32us; 111 = 64us
Ramp_COMP[7:4] is for multi-phase operation, default = 100%
0000=60%; 0001=65%; 0010=70%; 0011=75%; 0100=80%;
0101=85%; 0110=90%; 0111=95%; 1000=100%(default);
1001=105%; 1010=110%; 1011=115%; 1100=120%; 1101=125%;
Ramp_COMP 1110=130%; 1111=135%
0x2E VD D R/W 88h
[7:0] Ramp_COMP[3:0] is for single-phase operation, default = 100%
0000=60%; 0001=65%; 0010=70%; 0011=75%; 0100=80%;
0101=85%; 0110=90%; 0111=95%; 1000=100%(default);
1001=105%; 1010=110%; 1011=115%; 1100=120%; 1101=125%;
1110=130%; 1111=135%
VDD SMBus Thermal Monitor Value Reading.
0x2F VD D TM[7:0] R/W --
This register stores the value of A/D conversion for TSEN pin
VDDA Operation Phase Number Setting
AIICP0[3:2] Bit[3:2] : Phase Number of VDDA LCS0
0x30 VD D A R/W 05h
AIICP1[1:0] Bit[1:0] : Phase Number of VDDA LCS1
01: 2 Phase; 00: 1 Phase
Voltage offset of VDDA LCS0. (6.25mV / step)
Bit7 is sign bit, "0"=positive offset; "1"=negative offset
Upper and lower limits = +/-750mV
00000000 = +0mV
00000001 = +6.25mV
00111100 = +375mV
0x31 VD D A AVOFS0[7:0] R/W 00h 01111000 = +750mV
01111111 = +750mV
10000000 = -0mV
10000001 = -6.25mV
10111100 = -375mV
11111000 = -750mV
11111111 = -750mV

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 uP9505
Functional Description
R eg . F o cu s
Reg. Name Access Default Description
Addr. Rail
Voltage offset of VDDA LCS1. (6.25mV / step)
Bit7 is sign bit, "0"=positive offset; "1"=negative offset
Upper and lower limits = +/-750mV
00000000 = +0mV
00000001 = +6.25mV
00111100 = +375mV
0x32 VD D A AVOFS1[7:0] R/W 00h 01111000 = +750mV
01111111 = +750mV
10000000 = -0mV
10000001 = -6.25mV
10111100 = -375mV
11111000 = -750mV
11111111 = -750mV
VDDA Operation Frequency Setting
Bit[7:4] : Phase Number of VDDA LCS0, default = 100%
Bit[3:0] : Phase Number of VDDA LCS1, default = 100%
AIICF0[3:2]
0x33 VD D A R/W 88h 0000 = 60%; 0001 = 65%; 0010 = 70%;0011 = 75%; 0100 = 80%;
AIICF1[1:0]
0101 = 85%; 0110 = 90%; 0111 = 95%; 1000 = 100%(default);
1001=125%; 1010 = 150%; 1011 = 175%; 1100 = 200%;
1101 = 225%; 1110 = 250%; 1111 = 275%
VDDA Load Line Setting
Bit[7:4] : Load line setting of VDDA LCS0, default = 100%
Bit[3:0] : Load line setting of VDDA LCS1, default = 100%
AIICLL0[3:2]
0x34 VD D A R/W 66h 0000 = 0%; 0001 = 40%; 0010 = 60%;0011 = 70%; 0100 = 80%;
AIICLL1[1:0]
0101 = 90%; 0110 = 100%(default); 0111 =110%; 1000 = 120%;
1001=130%; 1010 = 140%; 1011 = 150%; 1100 = 160%;
1101 =170%; 1110 = 180%; 1111 = 190%
Bit[7]: On/Off control of VDDA current balance function, default = ON,
"0" = ON, "1" = OFF
ACB_EN[7] Bit[6:4] : VDDA Phase 1 current balance gain adjust, default = 100%
APH1_IGAIN 000 = 50%; 001 = 62.5%; 010 = 75%; 011 = 87.5%; 100 = 100%
0x35 VD D A [6:4] R/W 44h (default); 101 = 112.5%; 110 = 125%; 111 = 137.5%
APH2_IGAIN Bit[3] : Don't care
[2:0] Bit[2:0] : VDDA Phase 2 current balance gain adjust, default = 100%
000 = 50%; 001 = 62.5%; 010 = 75%; 011 = 87.5%; 100 = 100%
(default); 101 = 112.5%; 110 = 125%; 111 = 137.5%
Bit[7]: Don't care
Bit[6:4] : VDDA Phase 1 current balance offset, default = 0uA
000 = 0uA(default); 001 = 2uA; 010 = 4uA; 011 = 6uA; 100 = 8uA;
APH1_IOS[6:4] 101 = 10uA; 110 = 12uA; 111 = 14uA
0x36 VD D A R/W 00h
APH2_IOS[2:0] Bit[3]: Don't care
Bit[2:0] : VDDA Phase 2 current balance offset, default = 0uA
000 = 0uA(default); 001 = 2uA; 010 = 4uA; 011 = 6uA; 100 = 8uA;
101 = 10uA; 110 = 12uA; 111 = 14uA
ARCOMP Resistor Setting
Bit[7:4]: single-phase operation ARCOMP
ARCOMP1[7:4]
0x37 VD D A R/W 73h ARCOMP = 2.5K x (1+[7:4]), default = 20K
ARCOMP2[3:0]
Bit[3:0]: multi-phase operation ARCOMP
ARCOMP = 2.5K x (1+[3:0]), default = 10K

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 uP9505
Functional Description
R eg . F o cu s
Reg. Name Access Default Description
Addr. Rail
VDDA OTA Gm value selection
AGCOMP[3] : VDDA OTA Gm value selection
0 = force to use default value (2020uA/V), AGCOMP[2:0] setting will
be ignored(default);
1 = use the value set in AGCOMP[2:0]
0x38 VD D A AGCOMP[3:0] R/W 00h
AGCOMP[2:0] : VDDA transconductance Gm setting, applied to all
operating phase number, defined as the ratio to default
(=2020uA/V)
000 = 1X(default); 001 = 1.17X; 010 = 1.31X; 011 = 1.45X;
100 = 1.69X; 101 = 0.81X; 110 = 0.6X;111 = 0.33X
ARamp_COMP[7:4] is for multi-phase operation, default = 100%
0000=60%; 0001=65%; 0010=70%; 0011=75%; 0100=80%;
0101=85%; 0110=90%; 0111=95%; 1000=100%(default);
1001=105%; 1010=110%; 1011=115%; 1100=120%; 1101=125%;
ARamp_COMP 1110=130%; 1111=135%
0x39 VD D A R/W 88h
[7:0] ARamp_COMP[3:0] is for single-phase operation, default = 100%
0000=60%; 0001=65%; 0010=70%; 0011=75%; 0100=80%;
0101=85%; 0110=90%; 0111=95%; 1000=100%(default);
1001=105%; 1010=110%; 1011=115%; 1100=120%; 1101=125%;
1110=130%; 1111=135%

0x3A VD D A IMONA[7:0] RO -- VDDA IMONA reporting

VDDA Voltage Reading
0x3B VD D A VFBA[7:0] RO -- Voltage reading values in VFBA[7:0] is from A/D result of actual
output voltage by default.

Bit[7] :OFS control 2

Report value of Bit[7] is valid only when Bit[4]=1
"0" =Only SMBus , "1" = SVI2+ SMBus
Bit[6] : VDAC Control
"0" = Follow SVI2, "1" = Ignore SVI2
Bit[5] : PWR State Control
"0" = Follow SVI2, "1" = Ignore SVI2
Bit[4]: OFS control1
0x3C VD D A AMisc1[7:0] R/W 0F h "0" = Follow SVI2, "1" = Follow Bit[7]
Bit[3]: Total OCP Control
"0" = Disable, "1" = Enable(default)
Bit[2]: Per-phase OCP Control
"0" = Disable, "1" = Enable(default)
Bit[1]: OVP Control
"0" = Disable, "1" = Enable(default)
Bit[0]: UVP Control
"0" = Disable, "1" = Enable(default)

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 uP9505
Functional Description
R eg . F o cu s
Reg. Name Access Default Description
Addr. Rail
Bit[7] : Load Line Control
"0" = Follow SVI2, "1" = Ignore SVI2
Bit[6] : Spread Spectrum for switching frequency
"0" = Disable Spread Spectrum(default)
"1" = Enable Spread Spectrum
Bit[5]: Selection of the data source of SMBus Reg.
0x3Bh VDDA output voltage reading(VFBA[7:0])
"0" = From AD (default)
"1" = From SVI2
Bit[4] : Auto Phase Enable Control
0x3D VD D A AMisc2[7:0] R/W 04h "0" = Disable Auto Phase(default)
"1" = Enable Auto Phase
Bit[3] : Load Line Enable Control
"0" = Enable Load Line(default)
"1" = Disable Load Line (LL = 0)
Bit[2] : PSM Enable Control
"0" = Disable PSM
"1" = Enable PSM(default)
Bit[1:] : USM Enable Control
"0" = Disable USM(default)
"1" = Enable USM
Bit[7] : Don't care
Bit[6] : Don't care
Bit[5] : Don't care
Bit[4] : VRHOT# Enable Control
ATEMP_VRH- 0" = Enable(default), "1" = Disable
0x3E VD D A OT R/W 05h Bit[3:0] : Shift left by LSB, Temp range from 91oC to 121oC
[4:0] default = 106oC, 3oC/LSB
0000 = No Shift; 0001 = Shift 1LSB; 0010 = Shift 2LSB;
0011 = Shift 3LSB; 0100 = Shift 4LSB;0101 = Shift 5LSB (Default)
0110 = Shift 6LSB; 0111 = Shift 7LSB; 1000 = Shift 8LSB;
1001 = Shift 9LSB; 1010 = Shift 10LSB

0x3F VD D A ALCHVID[7:0] R/W 48h VDDA Latch VID Register, Default = 48h = 1.1V
VIMONA > Level 0 => LCS0
VIMONA < Level 0 => LCS1 (lowest current state) (For 2-phase
operation of VDDA)
0x44 VD D A AVM0[7:0] R/W 00h
Bit[1:0] : Don't care
AVM0 = (Bit[7:2]/64) x2.56
AVM0 setting is defined as the ratio to IMON voltage to 2.56V
VDDA SMBus Thermal Monitor Value Reading.
0x45 VD D A ATM[7:0] RO 00h
This register stores the value of A/D conversion for TSENA pin
VDDA protection indicator, indicating which protection is triggered
Bit[7] : Don't care
Bit[6] : OVP Indicator
"0" = Not Active, "1" = Active
Bit[5] : UVP Indicator
"0" = Not Active, "1" = Active
AProtect_Ind
0x46 VD D A RO 00h Bit[4] : OCP Indicator
[6:0]
"0" = Not Active, "1" = Active
Bit[3] : Per Phase OCP Indicator
"0" = Not Active, "1" = Active
Bit[2:1]: Don't care
Bit[0]: "0" = PH2, "1" = PH1
Report value of Bit[0] is valid only when Bit[3]=1

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 uP9505
Functional Description
R eg . F o cu s
Reg. Name Access Default Description
Addr. Rail
VDD PWM controller OTP shutdown threshold setting
Bit[7:4]: 16 steps, 2oC/step
VRSD[7:4] VR_SHDN = 111oC + (Bit[7:4])x2,
0x47 VD D VRSD Hys R/W 70h temp range from 111oC to 141oC, default = 125oC
[3:0] VR_SHDN Hysteresis Setting
Bit[3:0]: 16 steps , 2oC/step
VR_SHDN Hys = (Bit[3:0])x2
VDD PWM controller OTP shutdown threshold setting
Bit[7:4]: 16 steps, 2oC/step
AVRSD[7:4] VR_SHDN = 111oC + (Bit[7:4])x2,
0x48 VD D A AVRSD Hys R/W 70h temp range from 111oC to 141oC, default = 125oC
[3:0] VR_SHDN Hysteresis Setting
Bit[3:0]: 16 steps , 2oC/step
VR_SHDN Hys = (Bit[3:0])x2

0x4A shared CHIP ID RO 29h

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 uP9505
Absolute Maximum Rating
(Note 1)
Supply Input Voltage VCC5 to GND ------------------------------------------------------------------------------------------------ -0.3V to +6V
VINSEN ----------------------------------------------------------------------------------------------------------------------------------------- -0.3V to +30V
Other Pins to GND -------------------------------------------------------------------------------------------------------------------------- -0.3V to +6V
Storage Temperature Range ----------------------------------------------------------------------------------------------------------- -65oC to +150oC
Junction Temperature ------------------------------------------------------------------------------------------------------------------------------------ 150oC
Lead Temperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260oC
ESD Rating (Note 2)
HBM (Human Body Mode) --------------------------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------------------------------------------- 200V

Thermal Information
Package Thermal Resistance (Note 3)
VQFN6x6 - 52L θJA ---------------------------------------------------------------------------------------------------------------------- 35oC/W
VQFN6x6 - 52L θJC ----------------------------------------------------------------------------------------------------------------------- 3oC/W
Power Dissipation, PD @ TA = 25oC
VQFN6x6 - 52L ---------------------------------------------------------------------------------------------------------------------------------- 2.86W

Recommended Operation Conditions

(Note 4)
Operating Junction Temperature Range ------------------------------------------------------------------------------------------- -40oC to +125oC
Operating Ambient Temperature Range ------------------------------------------------------------------------------------------- -40oC to +85oC
Supply Input Voltage VCC5 ------------------------------------------------------------------------------------------------------------- 4.5V to 5.5V

Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. θJA is measured in the natural convection at TA = 25oC on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.

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 uP9505
Electrical Characteristics
(VCC5 = 5V, TA = 25oC, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Units

Supply Input
VCC5 POR Threshold PORVCC5 VCC5 rising 4.1 4.3 4.5 V
VCC5 POR Hysteresis HYSVCC5POR -- 0.3 -- V
EN = 5V, VDD and VDDA VID = 0V,
Supply Current IVCC5 -- 10 -- mA
PWM no switching
Shutdown Current IVCC5_SHDN E N = 0V -- 60 -- uA
VIN Sense
VINSEN POR Threshold PORVINSEN_r VINSEN rising -- 6 -- V
VINSEN POR Threshold PORVINSEN_f VINSEN falling -- 4.5 -- V
Input Current IVINSEN EN = 5V, VINSEN = 12V -- 30 -- uA
EN Input
Input Low VIL -- -- 0.8 V
Input High VIH 2 -- -- V
Pull-Low Current IEN_PL 1 2 3 uA
SVI2 Bus Timing Parameters (Guaranteed by design)
SVC Period TPERIOD 47.6 -- -- ns
SVC Frequency FSVC 0.1 -- 21 MHz
SVC High Time THIGH 20 -- -- ns
SVC Low Time TLOW 30 -- -- ns
SVD,SVT Setup Time to SVC
TSetup 5 -- -- ns
rising edge
SVD,SVT Hold Time from SVC
THold 5 -- -- ns
falling edge
SVD,SVT Start Time to SVC
TSTART 15 -- -- ns
falling edge
SVD,SVT Stop Time from SVC
TSTOP 5 -- -- ns
rising edge
SVC, SVD, SVT, Fall Time TFALL VOH_DC to VOL_DC -- -- 1 ns
SVC, SVD, SVT, Rise Time TRISE VOL_DC to VOH_DC -- -- 1 ns

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 uP9505
Electrical Characteristics
Parameter Symbol Test Conditions Min Typ Max Units
SVI2
SVC,SVD,SVT and PWROK input 0.35*
VIL_DC 0 -- VDDIO
V
Low Voltage
SVC,SVD,SVT and PWROK input 0.7*
VIH_DC VDDIO
-- VDDIO V
High Voltage
SVC,SVD,SVT and PWROK 0.1*
VHYST VDDIO
-- -- V
Hysteresis Voltage
SVC,SVD,SVT Low Level Output
VOL 0 -- 0.2 V
Voltage
SVC,SVD,SVT High Level Output VDDIO
VOH -0.2
-- VDDIO V
Voltage
SVC,SVD,SVT Output Current IOH when driving VOH 4 -- -- mA
SVC,SVD,SVT, PWROK Input
IL -100 -- 100 uA
Leakage Current
SVD High Z Output Leakage
IOZ -100 -- 100 uA
Current
SVC,SVD,SVT Input Capacitances CIN Guaranteed by design -- -- 5 pF
Telemetry and ADC
0.8V to 1.2V -1 -- 1
ADC Accuracy LS B
>1.2V or < 0.8V -2 -- 2

DAC Voltage Accuracy (DAC, DACA)

_ 0.8V
0.5V < VID < -15 -- 15 mV
DAC Voltage Accuracy V D AC _ 1.0V
0.8V < VID < -10 -- 10 mV
1.0V < VID <
_ 1.55V -1 -- 1 %
Slew Rate (DAC, DACA)
mV/
Slew Rate SR 10 12 --
us
Error Amplifier
Offset Voltage VOS(EA) -1 -- 1 mV
Trans-Conductance GM -- 2020 -- uA/V
Gain Bandwidth Product GBW(EA) Guaranteed by Design -- 10 -- MHz
PWM On-Time Setting
VINSEN = 12V, VID = 1.2V,
PWM On Time TON -- 500 -- ns
RTONSET = 50kΩ , Fsw=200kHz
Minimum Off-Time TOFF_MIN Single phase operation -- 300 -- ns
Current Sense Amplifier for Total Current Summing
Offset Voltage VOS(CSA) -1 -- 1 mV
Input Bias Current IBC(CSA) VCSPx = 1.2V, guaranteed by design -10 -- 10 nA

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 uP9505
Electrical Characteristics
Parameter Symbol Test Conditions Min Typ Max Units
Current Sense Amplifier for Total Current Summing (cont'd)
Maximum Sourcing Current IMAXSRC 100 -- -- uA
Gain Bandwidth Product GBW(CSA) Guaranteed by Design -- 10 -- MHz
Current Sense Amplifier for Phase Current Balance
Offset Voltage VOS(CSA) -1 -- 1 mV
Input Bias Current IBC(CSA) VCSPx = 1.2V, guaranteed by design -10 -- 10 nA
Maximum Sourcing Current IMAXSRC 100 -- -- uA
Gain Bandwidth Product GBW(CSA) Guaranteed by Design -- 10 -- MHz
PWM Output
Output Low Voltage VOL(PWM) ISINK = 4mA -- -- 0.2 V
Output High Voltage VOH(PWM) ISOURCE = 4mA 4.7 -- -- V
IPWM_leak0 VPWM = 0V -1 -- 0 uA
High Impedance State Leakage
IPWM_leak1 VPWM = 5V 0 -- 1 uA
Current Monitoring for Droop
Current Mirror Ratio for VDD IEAP to ICSN ratio 95 100 105 %
Current Mirror Ratio for VDDA IEAPA to ICSNA ratio 95 100 105 %
VRHOT#, POK
Output Low Voltage VOL ISINK = 4mA -- -- 0.2 V
Output Leakage Current IL Pull up to 5V -- -- 1 uA
Over Current Protection
Current Mirror Ratio for VDD IMON to ICSN ratio 95 100 105 %
Current Mirror Ratio for VDDA IMONA to ICSNA ratio 95 100 105 %
Total Current OCP Threshold VIMON_OCP 2.54 2.56 2.58 V
Total Current OCP Delay Time TOCP1_DELAY -- 20 -- us
Over Current Protection (cont'd)
Per-Phase OCP Threshold IOCP2 Measure ICSNX current -- 100 -- uA
Per-Phase OCP Delay Time TOCP2_DELAY -- 6 -- us
Under Voltage Protection
UVP Threshold VUVP VEAP - VFB; VEAPA - VFBA 300 325 350 mV
UVP Delay Time TUVP -- 8 -- us
Over Voltage Protection
OVP Threshold VOVP VFB - VEAP; VFBA - VEAPA 300 325 350 mV
OVP Delay Time TOVP -- 6 -- us

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 uP9505
Electrical Characteristics
Parameter Symbol Test Conditions Min Typ Max Units
Thermal Shutdow n Protection
o
OTP Threshold TOTP -- 160 -- C
Thermal Monitoring
Temperature ADC result = 106oC,
VRHOT# Assert Threshold VTSEN_R -- 4.383 -- V
measure TSEN/TSENA voltage
Temperature ADC result = 102oC,
VRHOT# De-Assert Threshold VTSEN_F -- 4.326 -- V
measure TSEN/TSENA voltage

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 uP9505
Typical Operation Characteristics
Power On from EN Power Off from EN

EN (5V/Div)

EN (5V/Div)

POK (5V/Div) POK (5V/Div)

VDD (500mV/Div) VDD (500mV/Div)

VDDA (500mV/Div) VDDA (500mV/Div)

Time : 100us/Div Time : 1ms/Div

VIN = 12V, no load VIN = 12V, IOUT = 1A

VDD VR Dynamic VID Up VDD VR Dynamic VID Up

SVC (2V/Div) SVC (2V/Div)

SVD (2V/Div) SVD (2V/Div)

SVT (2V/Div) SVT (2V/Div)

VDD (500mV/Div) VDD (500mV/Div)

Time : 10us/Div Time : 10us/Div

VID = 0.4V to 1V, ILOAD = 9A VID = 1V to 1.06875V, ILOAD = 45A

VDD VR Dynamic VID Up VDD VR Dynamic VID Up

SVC (2V/Div) SVC (2V/Div)

SVD (2V/Div) SVD (2V/Div)

SVT (2V/Div) SVT (2V/Div)

VDD (500mV/Div) VDD (500mV/Div)

Time : 10us/Div Time : 10us/Div

VID = 1V to 1.1V, ILOAD = 45A VID = 1V to 1.2V, ILOAD = 45A

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 uP9505
Typical Operation Characteristics
VDD VR Dynamic VID Up VDD VR Load Transient

SVC (2V/Div)

SVD (2V/Div)

SVT (2V/Div) VDD (100mV/Div)

VDD (500mV/Div)

Time : 10us/Div Time : 10us/Div

VID = 1V to 1.4V, ILOAD = 45A FLOAD = 10kHz, VDD = 1V, ILOAD = 35A ~ 120A

VDD VR OVP VDD VR OCP

UGATE1
UGATE1 (20V/Div) (20V/Div)

LGATE1 (10V/Div)
POK
VDD (1V/Div) (5V/Div)

POK (5V/Div)

VFB (1V/Div)

IOUT
(50A/Div)

Time : 4us/Div Time : 200us/Div

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 uP9505
Typical Operation Characteristics
VDDA VR Dynamic VID Up VDDA VR Dynamic VID Up

SVC (2V/Div) SVC (2V/Div)

SVD (2V/Div) SVD (2V/Div)

SVT (2V/Div) SVT (2V/Div)

VDDA (500mV/Div) VDDA (500mV/Div)

Time : 10us/Div Time : 10us/Div

VID = 0.4V to 1V, ILOAD = 4.1A VID = 1V to 1.06875V, ILOAD = 20.5A

VDDA VR Dynamic VID Up VDDA VR Dynamic VID Up

SVC (2V/Div) SVC (2V/Div)

SVD (2V/Div) SVD (2V/Div)

SVT (2V/Div) SVT (2V/Div)

VDDA (500mV/Div) VDDA (500mV/Div)

Time : 10us/Div Time : 10us/Div

VID = 1V to 1.1V, ILOAD = 20.5A VID = 1V to 1.2V, ILOAD = 20.5A

VDDA VR Dynamic VID Up VDDA VR Load Transient

SVC (2V/Div)

SVD (2V/Div)

SVT (2V/Div) VDDA (100mV/Div)

VDDA (500mV/Div)

Time : 10us/Div Time : 10us/Div

VID = 1V to 1.4V, ILOAD = 20.5A FLOAD = 10kHz, VDDA = 1V, ILOAD = 20A ~ 60A

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 uP9505
Typical Operation Characteristics
VDDA VR OVP VDDA VR OCP

UGATE1A
UGATE1A (20V/Div) (20V/Div)

LGATE1A (10V/Div)
POK (5V/Div)

POK (5V/Div)
VDDA (1V/Div)

VFBA (1V/Div)

IOUT (50A/Div)

Time : 4us/Div Time : 200us/Div

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 uP9505
Package Information
VQFN6x6 - 52L Package
5.90 - 6.10 4.40 - 4.60 0.35 - 0.45

0.31 - 0.41
0.13 - 0.23

5.90 - 6.10 0.15 - 0.25

Bottom View - Exposed Pad

Pin 1 mark

0.80 -1.00

0.00 - 0.05 0.20 REF

Note
1.Package Outline Unit Description:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm.

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 uP9505

Important Notice
uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other
changes to its products and services at any time and to discontinue any product or service without notice. Customers
should obtain the latest relevant information before placing orders and should verify that such information is current and
complete.
uPI products are sold subject to the taerms and conditions of sale supplied at the time of order acknowledgment.
However, no responsibility is assumed by uPI or its subsidiaries for its use or application of any product or circuit; nor
for any infringements of patents or other rights of third parties which may result from its use or application, including but
not limited to any consequential or incidental damages. No uPI components are designed, intended or authorized for
use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. No license
is granted by implication or otherwise under any patent or patent rights of uPI or its subsidiaries.
COPYRIGHT (C) 2016, UPI SEMICONDUCTOR CORP.

uPI Semiconductor Corp. uPI Semiconductor Corp.

Headquarter Sales Branch Office
9F.,No.5, Taiyuan 1st St. Zhubei City, 12F-5, No. 408, Ruiguang Rd. Neihu District,
Hsinchu Taiwan, R.O.C. Taipei Taiwan, R.O.C.
TEL : 886.3.560.1666 FAX : 886.3.560.1888 TEL : 886.2.8751.2062 FAX : 886.2.8751.5064

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