LABORATORY 1 – MOS DEVICE CHARACTERIZATION

LABORATORY 1
MOS DEVICE CHARACTERIZATION

OBJECTIVES
No. Objectives Requirements
1 I/V characteristics of NMOS transistor ▪ Drawing curves 𝐼𝐷𝑆 = 𝑓(𝑉𝐺𝑆 ), and
𝐼𝐷𝑆 = 𝑓(𝑉𝐷𝑆 )
▪ Determine the threshold voltage and
operation region of the NMOS device.
2 The effects on I/V characteristics when ▪ Drawing curves 𝐼𝐷𝑆 = 𝑓(𝑉𝐷𝑆 ) when
𝑉𝐺𝑆 , width, and length vary of NMOS these parameters vary.
transistor ▪ Consider curves drawn.
3 Second order effects (body effect, ▪ Drawing curves 𝐼𝐷𝑆 = 𝑓(𝑉𝐺𝑆 ), and
channel-length modulation) of NMOS 𝐼𝐷𝑆 = 𝑓(𝑉𝐷𝑆 ) when these effects
transistor occur.
▪ Consider curves drawn.
4 The effects on I/V characteristics when ▪ Drawing curves 𝐼𝑆𝐷 = 𝑓(𝑉𝑆𝐷 ) when
𝑉𝑆𝐺 , width, and length vary of PMOS these parameters vary.
transistor ▪ Consider curves drawn.

PREPARATION FOR LAB 1

➢ Finished Lab 0 at home. Requirement:
▪ Create library, schematic cellview and symbol of INV with tsmc65 technology.
▪ Simulate transient analysis with ADE-L.

EXPERIMENT 1

Objective: Known NMOS operations and I-V characteristics

Requirements: Simulate and draw curves 𝐼𝐷𝑆 = 𝑓(𝑉𝐺𝑆 ) and 𝐼𝐷𝑆 = 𝑓(𝑉𝐷𝑆 ) of NMOS currently used.
Instruction: Assemble the circuit as shown in Figure 1, setting parameters for power supplies (using
vdc source), with 𝐿 = 60𝑛𝑚, 𝑊 = 120𝑛𝑚, 𝑉𝑆𝐵 = 0V.
Note: Consider “nch_lvt” device in tsmc65 technology for all lab experiments.

Department of Electronics Page | 1

Analog and Mixed Signal IC Design Laboratory
LABORATORY 1 – MOS DEVICE CHARACTERIZATION

Figure 1. Circuit diagram for characterizing NMOS characteristics

Check: Your report must show these results and explain the NMOS operation region based on
waveform.

➢ Draw a curve when fixing the value 𝑉𝐺𝑆 = 1.0𝑉, and sweeping variable 𝑉𝐷𝑆 from 0V to 1.2V
to characterize the change of 𝐼𝐷𝑆 with respect to 𝑉𝐷𝑆 .

Figure 2. Waveform 𝐼𝐷𝑆 = 𝑓(𝑉𝐷𝑆 ) example

➢ Draw a curve when fixing the value 𝑉𝐷𝑆 = 1.0𝑉, and sweeping variable 𝑉𝐺𝑆 from 0V to 1.2V
with step = 0.01V to characterize the change of 𝐼𝐷𝑆 with respect to 𝑉𝐺𝑆 .

Department of Electronics Page | 2

Analog and Mixed Signal IC Design Laboratory
LABORATORY 1 – MOS DEVICE CHARACTERIZATION

Figure 3. Waveform 𝐼𝐷𝑆 = 𝑓(𝑉𝐺𝑆 ) example

▪ Question: Propose at least one method to determine the threshold voltage of NMOS nch_lvt
device.

EXPERIMENT 2

Objective: The effects on I/V characteristics of NMOS when 𝑉𝐺𝑆 , width and length vary.

Requirements: Simulate and draw curves when 𝑉𝐺𝑆 , width and length vary.

Instruction:

➢ Setting parameters W, L, 𝑉𝐺𝑆 , 𝑉𝑆𝐵 and 𝑉𝐷𝑆 for convenience when characterizing the circuit
shown in Figure 1.

➢ Sweep multiple variables in parallel using ADE-L: Tools → Parametric Analysis → Sweeps
& Ranges Type (Figure 4 is an example for setting multiple sweeping variables)

➢ You can refer to the setting in Figure 4, and observe the result shown in Figures 5 and 6.

Figure 4. Setting parameters for characterizing 𝐼𝐷𝑆 = 𝑓(𝑉𝐷𝑆 ) at 𝑉𝐺𝑆 = {0, 0.25,0.5, 0.75,1.0} 𝑉

Department of Electronics Page | 3

Analog and Mixed Signal IC Design Laboratory
LABORATORY 1 – MOS DEVICE CHARACTERIZATION

Figure 5. 𝐼𝐷𝑆 = 𝑓(𝑉𝐷𝑆 ) waveform with 𝑉𝐺𝑆 = {0, 0.25,0.5, 0.75,1.0} 𝑉

Figure 6. 𝐼𝐷𝑆 = 𝑓(𝑉𝐷𝑆 ) waveform with 𝐿 = {90,180,270,360} 𝑛𝑚

Check: Your result must show these results and summarize the conclusion of the current and
operation region of NMOS with the width, length, and 𝑣𝑔𝑠 variation.

➢ Choose 𝐿 = 60𝑛𝑚, 𝑊 = 120𝑛𝑚 and 𝑉𝑆𝐵 = 0V. Draw curves 𝐼𝐷𝑆 = 𝑓(𝑉𝐷𝑆 ), sweeping variable
𝑉𝐷𝑆 from 0V to 1.2V with step = 0.01V and sweeping 𝑉𝐺𝑆 from 0.4V to 1.0V with step =
0.2V.

➢ Choose 𝐿 = 60𝑛𝑚, 𝑉𝐺𝑆 = 1.0𝑉 and 𝑉𝑆𝐵 = 0V. Draw curves 𝐼𝐷𝑆 = 𝑓(𝑉𝐷𝑆 ) sweeping variable
𝑉𝐷𝑆 from 0V to 1.2V with step = 0.01V and 𝑊 = {120, 240, 360, 480} 𝑛𝑚

➢ Choose W = 240𝑛𝑚, 𝑉𝐺𝑆 = 1.0𝑉 and 𝑉𝑆𝐵 = 0V. Draw curves 𝐼𝐷𝑆 = 𝑓(𝑉𝐷𝑆 ) sweeping
variable 𝑉𝐷𝑆 from 0V to 1.2V with step = 0.01V and 𝐿 = {60, 120, 180, 240} 𝑛𝑚

Department of Electronics Page | 4

Analog and Mixed Signal IC Design Laboratory
LABORATORY 1 – MOS DEVICE CHARACTERIZATION

EXPERIMENT 3

Objective: Known second order effect of MOS transistor in library currently used.

The ideal I-V model neglects many effects that are important to moder device. It is useful to have a
qualitative understanding of second order effects to predict their impact on circuit behavior and to
be able to anticipate how devices will change in future process generations.

These effects are listed as follows.

No. Name of second order effect (Nonlinear I-V Effects)

1 Mobility degradation and Velocity saturation

2 Channel length modulation

3 Threshold voltage effect Body effect

Drain-Induced Barrier Lowering

Short Channel Effect

4 Leakage Subthreshold Leakage

Gate Leakage

Junction Leakage

5 Temperature Dependence

6 Geometry Dependence
Table 1. Some second-order effects in MOS transistors.

In fact, body effect and channel length modulation are important when analyzing the small
signal, and the expression determined 𝐼𝐷𝑆 . Assemble the testbench circuit as shown in Figure 1. In
Experiment 2, we have already considered channel length modulation so in Experiment 3 we
investigate the body effect of NMOS only.

Requirements:

Instruction:

Department of Electronics Page | 5

Analog and Mixed Signal IC Design Laboratory
LABORATORY 1 – MOS DEVICE CHARACTERIZATION

➢ Setting parameters W, L, 𝑉𝐺𝑆 , 𝑉𝑆𝐵 and 𝑉𝐷𝑆 for convenience when characterizing circuit
shown in Figure 1.

➢ Sweep multiple variables in parallel using ADE-L: Tools → Parametric Analysis

Check: Your report must show the results

➢ Draw curves 𝐼𝐷𝑆 = 𝑓(𝑉𝐺𝑆 ) when fixing 𝐿 = 60𝑛𝑚, 𝑊 = 120𝑛𝑚, 𝑉𝐷𝑆 = 1.2𝑉, and
sweeping 𝑉𝐺𝑆 from 0V to 1.0V at 𝑉𝑆𝐵 = {0.15,0.30,0.45} 𝑉.

Figure 7. 𝐼𝐷𝑆 = 𝑓(𝑉𝐺𝑆 ) waveform with 𝑉𝑆𝐵 = {0.15,0.30,0.45} 𝑉

Questions:

➢ 𝑉𝑇𝐻 can also be obtained from Figure 7 or using DCOP report in DC analysis.

➢ Explain the body effect based on 𝐼𝐷𝑆 = 𝑓(𝑉𝐺𝑆 ) characteristic and 𝑉𝑇𝐻 measured in the
previous step.

EXPERIMENT 4

Objective: The effects on I/V characteristics of PMOS when 𝑉𝑆𝐺 , width and length vary.

Requirements: Know how to create a testbench and consider the I/V characteristics of PMOS.

Instruction:

➢ Based on the NMOS I/V characteristics in Figure 1, you propose a testbench to consider the
I/V characteristics of PMOS pch_lvt device in tsmc65 technology.

Check: Your result must show these results and summarize the conclusion of the current and

Department of Electronics Page | 6

Analog and Mixed Signal IC Design Laboratory
LABORATORY 1 – MOS DEVICE CHARACTERIZATION

operation region of PMOS with the width, length, and 𝑉𝑆𝐺 variation.

➢ Choose 𝐿 = 60𝑛𝑚, 𝑊 = 120𝑛𝑚 and 𝑉𝐵𝑆 = 0V. Draw curves 𝐼𝑆𝐷 = 𝑓(𝑉𝑆𝐷 ), sweeping variable
𝑉𝑆𝐷 from 0V to 1.2V with step = 0.01V and sweeping 𝑉𝑆𝐺 from 0.4V to 1.0V with step =
0.2V.

➢ Choose 𝐿 = 60𝑛𝑚, 𝑉𝑆𝐺 = 1.0𝑉 and 𝑉𝐵𝑆 = 0V. Draw curves 𝐼𝑆𝐷 = 𝑓(𝑉𝑆𝐷 ) sweeping variable
𝑉𝑆𝐷 from 0V to 1.2V with step = 0.01V and 𝑊 = {120, 240, 360, 480} 𝑛𝑚

➢ Choose W = 240𝑛𝑚, 𝑉𝑆𝐺 = 1.0𝑉 and 𝑉𝐵𝑆 = 0V. Draw curves 𝐼𝑆𝐷 = 𝑓(𝑉𝑆𝐷 ) sweeping
variable 𝑉𝑆𝐷 from 0V to 1.2V with step = 0.01V and 𝐿 = {60, 120, 180, 240} 𝑛𝑚

Department of Electronics Page | 7

Analog and Mixed Signal IC Design Laboratory