8 7 6 5 4 3 2 1

1. Schematic Page Description :

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01

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Origins Schematic Ver :

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D D

SoC I2C table

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Function Channel Read Write
Touch Screen I2C0 0x?

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Audio Codec I2C1 0x? 0x?
VNN (reserve) I2C4
Track Pad I2C5

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EC I2C6

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EC SMBus/I2C table

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C
Function Channel Address C

Battery/Thermal SMB0
NA SMB1

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G-Sensor I2C1
PCH I2C2
VNN I2C3

USB3/2 port mapping

a C Current sensor address

Function Channel Function Channel

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+VBATA 0x47 +VCC_OUT 0x40
B
USB3 Port No# Usage USB2 Port No# Usage +V5A 0x43 +VGG 0x44 B

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USB3P0 NA USB2P0 I/O(2.0) +V3P3A 0x4B +VNN 0x45
USB3P1 NA USB2P1 LTE +V1P05A 0x46 +VDDQ_OUT 0x41
USB3P2 I/O USB2P2 I/O(3.0) +V1P8A 0x49

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USB3P3 NA USB2P3 CCD
USB2P4 BT

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PCIe port mapping

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PCIe port No# Usage PCIe CLK# Usage
PCIe_0 Video Codec PCIe_CLK0 Video Codec
PCIe_1 Video Codec PCIe_CLK1 NA
A
PCIe_2 WLAN PCIe_CLK2 WLAN A

PCIe_3 NA PCIe_CLK3 NA

Quanta Computer Inc.

PROJECT : ZHR
Size Document Number Rev
1A
Sch Page description
Date: Monday, September 14, 2015 Sheet 1 of 47
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 5 4 3 2 1

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ZHRA/Origins_T 02

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Intel Braswell Platform Block Diagram

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For ZHRA_DVT SKU1 AJ0QJ4VVT04--CPU(1170)BSWN3050 1.6G QJ4V(FCBGA)STNBSQ BQ24770 PS51716
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For ZHRA_SKU2/3 AJ0QJ4TVT03--CPU(1170)BSWN3150 1.6G QJ4T(FCBGA)STNBSQ NVDC Battery Charger VDDQ

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PAGE 36 PAGE 40
Default BOM is SKU2
RT7291A/RT7290A RT8171B

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+V5A/+V3P3A +VCC0_CPU/+VGG

DDR3L 1600 X2 LANES

PAGE 37 PAGE 38,39
DDR3L DDI 1
Memory down LCD Conn

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2 Channel 1Rx16 32.768KHz
RT5041A RT8171B
PAGE 20 +V1P8A/+V1P05A
PAGE 6 +VNN
PAGE 17,18
PAGE 42 PAGE 41

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Intel Braswell
19.2 Mhz Thermal Protection
PAGE 6

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Discharger
PAGE 43
Power : TDP 6 Watt
DDI 2

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C HDMI Conn PAGE 22 C
Package : FCBGA 1170
eMMC 5.0 Size : 25 x 27 (mm) I2C Interface
MMC
16G/32G

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Port0 Port1 Port5 Port6
PAGE 19
Touch Screen Audio Codec Track Pad KBC
USB 3.0 Interface
MAX98090 MEC1322

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SD Card Port2 PAGE 33 PAGE 26 PAGE 29 PAGE 30
SD Card 3.0
USB3.0 Port x 1
PAGE 19 Port2
PAGE 28
CCD
PAGE 6~15 USB 2.0 Interface Port3

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Int
1.8V BIOS+TXE Port4 Port1 Port0
SPI ROM(64Mb) SPI Interface PAGE 20
I2S+I2C(PORT1)

W25Q64FWSSIG
PAGE 9
B B

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LPC Interface PCIE Gen 2 x 1 Lane
Port0/1 Port2

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TPM KBC Audio Codec Kepler NGFF M.2 2230-E NGFF M.2 3042-B
SLB9655TT1.2 MEC1322-LZY MAX98090 USB port3
FW4.32GOOG

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Video Codec
WLAN / BT Combo LTE
Package : DQFN132 Package : TQFN-40

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PCIE CLK PORT 0 PCIE CLK PORT 2 USB2.0 Port x 1
Size : 11 x 11 (mm) Size : 5 x 5 (mm) BOM value option:
PAGE 27 3G@ => LTE
PAGE 30 PAGE 26 PAGE 32 PAGE 24 PAGE 25 PAGE 27
SMB0 I2C1 SMB0 I2C3 GD@ =>Google debug
Daughter Board CHB@ =>DRAM sec channel

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Battery Thermal IC Keyboard VC@ =>Video Codec
TMP432 Speaker GS@ =>G-sensor
PAGE 29 PAGE 26 TS@ =>Touch screen
PAGE 36 PAGE 33
A VN@ =>VNN A
MIC SW Combo Jack NVN@ =>Non VNN
G-Sensor LTE UART COEXISTENCE
TS3A227 Headphone + MIC 360@ => Convertible SKU (Yoga)
KXCJ9-1008 PAGE 27 PAGE 27

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PAGE 33 Daughter Board
Quanta Computer Inc.
DMIC
PAGE 20 PROJECT : ZHR
Size Document Number Rev
Block Diagram 1A

Date: Monday, September 14, 2015 Sheet 2 of 47

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Quanta Computer Inc.
PROJECT : ZHR
Rev
A

1A
Power Sequence
Date: Monday, September 14, 2015 Sheet 3 of 47
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Quanta Computer Inc.
PROJECT : ZHR

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Size Document Number Rev
1A
SMBUS_I2C
Date: Monday, September 14, 2015 Sheet 4 of 47
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Q u Quanta Computer Inc.

PROJECT : ZHR
A

Size Document Number Rev

1A
BSW PWR TREE
Date: Monday, September 14, 2015 Sheet 5 of 47
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 5 4 3 2 1

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SoC (CPU) BRASWELL SOC - MEMORY DDR3L CHANNEL A
06

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BSW_MCP_EDS
?
U10A

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M_A_DQ[63:0] (17)
(17) M_A_A[15:0]
M_A_A15 BD49 BG33 M_A_DQ63
D M_A_A14 BD47 DDR3_M0_MA_15 DDR3_M0_DQ_63 BH28 M_A_DQ62 D

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M_A_A13 BF44 DDR3_M0_MA_14 DDR3_M0_DQ_62 BJ29 M_A_DQ61
DDR0
M_A_A12 BF48 DDR3_M0_MA_13 DDR3_M0_DQ_61 BG28 M_A_DQ60
M_A_A11 BB49 DDR3_M0_MA_12 DDR3_M0_DQ_60 BG32 M_A_DQ59
M_A_A10 BJ45 DDR3_M0_MA_11 DDR3_M0_DQ_59 BH34 M_A_DQ58
M_A_A9 BE52 DDR3_M0_MA_10 DDR3_M0_DQ_58 BG29 M_A_DQ57

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M_A_A8 BD44 DDR3_M0_MA_9 DDR3_M0_DQ_57 BJ33 M_A_DQ56
M_A_A7 BE46 DDR3_M0_MA_8 DDR3_M0_DQ_56 BD28 M_A_DQ55
M_A_A6 BB46 DDR3_M0_MA_7 DDR3_M0_DQ_55 BF30 M_A_DQ54
M_A_A5 BH48 DDR3_M0_MA_6 DDR3_M0_DQ_54 BA34 M_A_DQ53
M_A_A4 BD42 DDR3_M0_MA_5 DDR3_M0_DQ_53 BD34 M_A_DQ52

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M_A_A3 BH47 DDR3_M0_MA_4 DDR3_M0_DQ_52 BD30 M_A_DQ51
M_A_A2 BJ48 DDR3_M0_MA_3 DDR3_M0_DQ_51 BA32 M_A_DQ50
M_A_A1 BC42 DDR3_M0_MA_2 DDR3_M0_DQ_50 BC34 M_A_DQ49
M_A_A0 BB47 DDR3_M0_MA_1 DDR3_M0_DQ_49 BF34 M_A_DQ48
DDR3_M0_MA_0 DDR3_M0_DQ_48 AV32 M_A_DQ47

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M_A_BS2 BF52 DDR3_M0_DQ_47 AV34 M_A_DQ46
(17) M_A_BS2 DDR3_M0_BS_2 DDR3_M0_DQ_46
M_A_BS1 AY40 BD36 M_A_DQ45
(17) M_A_BS1 DDR3_M0_BS_1 DDR3_M0_DQ_45
(17) M_A_BS0 M_A_BS0 BH46 BF36 M_A_DQ44

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DDR3_M0_BS_0 DDR3_M0_DQ_44 AU32 M_A_DQ43
M_A_CAS# BG45 DDR3_M0_DQ_43 AU34 M_A_DQ42
(17) M_A_CAS# DDR3_M0_CASB DDR3_M0_DQ_42
M_A_RAS# BA40 BA36 M_A_DQ41
(17) M_A_RAS# DDR3_M0_RASB DDR3_M0_DQ_41
M_A_WE# BH44 BC36 M_A_DQ40

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(17) M_A_WE# DDR3_M0_WEB DDR3_M0_DQ_40
AU38 BH38 M_A_DQ39
C DDR3_M0_CSB_1 DDR3_M0_DQ_39 C
M_A_CS#0 AY38 BH36 M_A_DQ38
(17) M_A_CS#0 DDR3_M0_CSB_0 DDR3_M0_DQ_38 BJ41 M_A_DQ37
BD38 DDR3_M0_DQ_37 BH42 M_A_DQ36
BF38 DDR3_M0_CK_1 DDR3_M0_DQ_36 BJ37 M_A_DQ35

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AY42 DDR3_M0_CKB_1 DDR3_M0_DQ_35 BG37 M_A_DQ34
DDR3_M0_CKE_1 DDR3_M0_DQ_34 BG43 M_A_DQ33
M_A_CLKP0 BD40 DDR3_M0_DQ_33 BG42 M_A_DQ32
(17) M_A_CLKP0 DDR3_M0_CK_0 DDR3_M0_DQ_32
M_A_CLKN0 BF40 BB51 M_A_DQ31
(17) M_A_CLKN0 DDR3_M0_CKB_0 DDR3_M0_DQ_31
M_A_CKE0 BB44 AW53 M_A_DQ30
(17) M_A_CKE0 DDR3_M0_CKE_0 DDR3_M0_DQ_30

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BC52 M_A_DQ29
AT30 DDR3_M0_DQ_29 AW51 M_A_DQ28
AU30 RSVD1 DDR3_M0_DQ_28 AV51 M_A_DQ27
RSVD2 DDR3_M0_DQ_27 BC53 M_A_DQ26
M_A_ODT0 AV36 DDR3_M0_DQ_26 AV52 M_A_DQ25
(17) M_A_ODT0 DDR3_M0_ODT_0 DDR3_M0_DQ_25
BA38 BD52 M_A_DQ24
DDR3_M0_ODT_1 DDR3_M0_DQ_24 AV42 M_A_DQ23
DDR3_M0_DQ_23

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TP_M0_OCAVREF AT28 AP41 M_A_DQ22
TP_M0_ODQVREF AU28 DDR3_M0_OCAVREF DDR3_M0_DQ_22 AV41 M_A_DQ21
DDR3_M0_ODQVREF DDR3_M0_DQ_21 AT44 M_A_DQ20
BA42 DDR3_M0_DQ_20 AP40 M_A_DQ19
(17) M_A_DRAMRST# DDR3_M0_DRAMRSTB DDR3_M0_DQ_19
AV28 AT38 M_A_DQ18
(31) DDR3_DRAM_PWROK DDR3_DRAM_PWROK DDR3_M0_DQ_18 AP42 M_A_DQ17
DDR3_M0_DQ_17
DDR3_M0_RCOMPPD BA28
DDR3_M0_RCOMPPD DDR3_M0_DQ_16
AT40 M_A_DQ16 PLACE CA CAP NEAR SOC
AV45 M_A_DQ15

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B B
M_A_DM7 BH30 DDR3_M0_DQ_15 AY50 M_A_DQ14 DDR3_DRAM_PWROK
(17) M_A_DM7 BD32 DDR3_M0_DM_7 DDR3_M0_DQ_14 AT50 M_A_DQ13
R488 M_A_DM6
(17) M_A_DM6 DDR3_M0_DM_6 DDR3_M0_DQ_13
182/F_4 M_A_DM5 AY36 AP47 M_A_DQ12 CA

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(17) M_A_DM5 BG41 DDR3_M0_DM_5 DDR3_M0_DQ_12 AV50 M_A_DQ11
M_A_DM4 C294
(17) M_A_DM4 BA53 DDR3_M0_DM_4 DDR3_M0_DQ_11 AY48 M_A_DQ10
M_A_DM3
(17) M_A_DM3 DDR3_M0_DM_3 DDR3_M0_DQ_10
M_A_DM2 AP44 AT47 M_A_DQ9 0.1U/16V_4
(17) M_A_DM2 AT48 DDR3_M0_DM_2 DDR3_M0_DQ_9 AP48 M_A_DQ8
M_A_DM1
(17) M_A_DM1 DDR3_M0_DM_1 DDR3_M0_DQ_8
M_A_DM0 AP52 AP51 M_A_DQ7
(17) M_A_DM0 DDR3_M0_DM_0 DDR3_M0_DQ_7

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AR53 M_A_DQ6
M_A_DQSP7 BH32 DDR3_M0_DQ_6 AK52 M_A_DQ5
(17) M_A_DQSP7 DDR3_M0_DQS_7 DDR3_M0_DQ_5
(17) M_A_DQSN7 M_A_DQSN7 BG31 AL53 M_A_DQ4
M_A_DQSP6 BC30 DDR3_M0_DQSB_7 DDR3_M0_DQ_4 AR51 M_A_DQ3
(17) M_A_DQSP6 DDR3_M0_DQS_6 DDR3_M0_DQ_3
M_A_DQSN6 BC32 AT52 M_A_DQ2

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(17) M_A_DQSN6 DDR3_M0_DQSB_6 DDR3_M0_DQ_2
M_A_DQSP5 AT32 AL51 M_A_DQ1
(17) M_A_DQSP5 DDR3_M0_DQS_5 DDR3_M0_DQ_1
M_A_DQSN5 AT34 AK51 M_A_DQ0
(17) M_A_DQSN5 DDR3_M0_DQSB_5 DDR3_M0_DQ_0
(17) M_A_DQSP4 M_A_DQSP4 BH40
M_A_DQSN4 BG39 DDR3_M0_DQS_4
(17) M_A_DQSN4 DDR3_M0_DQSB_4
(17) M_A_DQSP3 M_A_DQSP3 AY52
DDR3_M0_DQS_3

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M_A_DQSN3 BA51
(17) M_A_DQSN3 DDR3_M0_DQSB_3
M_A_DQSP2 AT42
(17) M_A_DQSP2 DDR3_M0_DQS_2
(17) M_A_DQSN2 M_A_DQSN2 AT41
M_A_DQSP1 AV47 DDR3_M0_DQSB_2
(17) M_A_DQSP1 DDR3_M0_DQS_1
(17) M_A_DQSN1 M_A_DQSN1 AV48
A M_A_DQSP0 AM52 DDR3_M0_DQSB_1 A
(17) M_A_DQSP0 DDR3_M0_DQS_0
M_A_DQSN0 AM51
(17) M_A_DQSN0 DDR3_M0_DQSB_0

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BSW_MCP_EDS
REV = 1 1 OF 13 ? Quanta Computer Inc.
PROJECT : ZHR
Size Document Number Rev
1A
BSW 1/10 (DDRA)
Date: Monday, September 14, 2015 Sheet 6 of 47
5 4 3 2 1
 5 4 3 2 1

BRASWELL - MEMORY DDR3L CHANNEL B

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SoC (CPU)

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M_B_DQ[63:0] (18)

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?
U10B BSW_MCP_EDS

D (18) M_B_A[15:0] DDR1 D

M_B_A15 BD5 BG21 M_B_DQ63

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M_B_A14 BD7 DDR3_M1_MA_15 DDR3_M1_DQ_63 BH26 M_B_DQ62
M_B_A13 BF10 DDR3_M1_MA_14 DDR3_M1_DQ_62 BJ25 M_B_DQ61
M_B_A12 BF6 DDR3_M1_MA_13 DDR3_M1_DQ_61 BG26 M_B_DQ60
M_B_A11 BB5 DDR3_M1_MA_12 DDR3_M1_DQ_60 BG22 M_B_DQ59
M_B_A10 BJ9 DDR3_M1_MA_11 DDR3_M1_DQ_59 BH20 M_B_DQ58

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M_B_A9 BE2 DDR3_M1_MA_10 DDR3_M1_DQ_58 BG25 M_B_DQ57
M_B_A8 BD10 DDR3_M1_MA_9 DDR3_M1_DQ_57 BJ21 M_B_DQ56
M_B_A7 BE8 DDR3_M1_MA_8 DDR3_M1_DQ_56 BD26 M_B_DQ55
M_B_A6 BB8 DDR3_M1_MA_7 DDR3_M1_DQ_55 BF24 M_B_DQ54
M_B_A5 BH6 DDR3_M1_MA_6 DDR3_M1_DQ_54 BA20 M_B_DQ53

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M_B_A4 BD12 DDR3_M1_MA_5 DDR3_M1_DQ_53 BD20 M_B_DQ52
M_B_A3 BH7 DDR3_M1_MA_4 DDR3_M1_DQ_52 BD24 M_B_DQ51
M_B_A2 BJ6 DDR3_M1_MA_3 DDR3_M1_DQ_51 BA22 M_B_DQ50
M_B_A1 BC12 DDR3_M1_MA_2 DDR3_M1_DQ_50 BC20 M_B_DQ49
M_B_A0 BB7 DDR3_M1_MA_1 DDR3_M1_DQ_49 BF20 M_B_DQ48

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DDR3_M1_MA_0 DDR3_M1_DQ_48 AV22 M_B_DQ47
M_B_BS2 BF2 DDR3_M1_DQ_47 AV20 M_B_DQ46
(18) M_B_BS2 DDR3_M1_BS_2 DDR3_M1_DQ_46
(18) M_B_BS1 M_B_BS1 AY14 BD18 M_B_DQ45

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M_B_BS0 BH8 DDR3_M1_BS_1 DDR3_M1_DQ_45 BF18 M_B_DQ44
(18) M_B_BS0 DDR3_M1_BS_0 DDR3_M1_DQ_44 AU22 M_B_DQ43
M_B_CAS# BG9 DDR3_M1_DQ_43 AU20 M_B_DQ42
(18) M_B_CAS# DDR3_M1_CASB DDR3_M1_DQ_42
M_B_RAS# BA14 BA18 M_B_DQ41

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(18) M_B_RAS# DDR3_M1_RASB DDR3_M1_DQ_41
(18) M_B_WE# M_B_WE# BH10 BC18 M_B_DQ40
C DDR3_M1_WEB DDR3_M1_DQ_40 C
AU16 BH16 M_B_DQ39
M_B_CS#0 AY16 DDR3_M1_CSB_1 DDR3_M1_DQ_39 BH18 M_B_DQ38
(18) M_B_CS#0 DDR3_M1_CSB_0 DDR3_M1_DQ_38 BJ13 M_B_DQ37
BD16 DDR3_M1_DQ_37 BH12 M_B_DQ36

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BF16 DDR3_M1_CK_1 DDR3_M1_DQ_36 BJ17 M_B_DQ35
AY12 DDR3_M1_CKB_1 DDR3_M1_DQ_35 BG17 M_B_DQ34
DDR3_M1_CKE_1 DDR3_M1_DQ_34 BG11 M_B_DQ33
M_B_CLKP0 BD14 DDR3_M1_DQ_33 BG12 M_B_DQ32
(18) M_B_CLKP0 DDR3_M1_CK_0 DDR3_M1_DQ_32
M_B_CLKN0 BF14 BB3 M_B_DQ31
(18) M_B_CLKN0 DDR3_M1_CKB_0 DDR3_M1_DQ_31

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(18) M_B_CKE0 M_B_CKE0 BB10 AW1 M_B_DQ30
DDR3_M1_CKE_0 DDR3_M1_DQ_30 BC2 M_B_DQ29
AT24 DDR3_M1_DQ_29 AW3 M_B_DQ28
AU24 RSVD1 DDR3_M1_DQ_28 AV3 M_B_DQ27
RSVD2 DDR3_M1_DQ_27 BC1 M_B_DQ26
M_B_ODT0 AV18 DDR3_M1_DQ_26 AV2 M_B_DQ25
(18) M_B_ODT0 DDR3_M1_ODT_0 DDR3_M1_DQ_25
BA16 BD2 M_B_DQ24
DDR3_M1_ODT_1 DDR3_M1_DQ_24

C
AV12 M_B_DQ23
TP_M1_OCAVREF AT26 DDR3_M1_DQ_23 AP13 M_B_DQ22
TP_M1_ODQVREF AU26 DDR3_M1_OCAVREF DDR3_M1_DQ_22 AV13 M_B_DQ21
DDR3_M1_ODQVREF DDR3_M1_DQ_21 AT10 M_B_DQ20
BA12 DDR3_M1_DQ_20 AP14 M_B_DQ19
(18) M_B_DRAMRST# DDR3_M1_DRAMRSTB DDR3_M1_DQ_19
AV26 AT16 M_B_DQ18
(31) DDR3_VCCA_PWROK DDR3_VCCA_PWROK DDR3_M1_DQ_18 AP12 M_B_DQ17
DDR3_M1_RCOMPPD BA26 DDR3_M1_DQ_17 AT14 M_B_DQ16

a
B B
DDR3_M1_RCOMPPD DDR3_M1_DQ_16 AV9 M_B_DQ15
M_B_DM7 BH24 DDR3_M1_DQ_15 AY4 M_B_DQ14
(18) M_B_DM7 DDR3_M1_DM_7 DDR3_M1_DQ_14
R473 M_B_DM6 BD22 AT4 M_B_DQ13

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(18) M_B_DM6 AY18 DDR3_M1_DM_6 DDR3_M1_DQ_13 AP7 M_B_DQ12
182/F_4 M_B_DM5
(18) M_B_DM5 BG13 DDR3_M1_DM_5 DDR3_M1_DQ_12 AV4 M_B_DQ11
M_B_DM4
(18) M_B_DM4 DDR3_M1_DM_4 DDR3_M1_DQ_11
M_B_DM3 BA1 AY6 M_B_DQ10
(18) M_B_DM3 AP10 DDR3_M1_DM_3 DDR3_M1_DQ_10 AT7 M_B_DQ9
M_B_DM2
(18) M_B_DM2 DDR3_M1_DM_2 DDR3_M1_DQ_9
M_B_DM1 AT6 AP6 M_B_DQ8
(18) M_B_DM1 DDR3_M1_DM_1 DDR3_M1_DQ_8

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M_B_DM0 AP2 AP3 M_B_DQ7
(18) M_B_DM0 DDR3_M1_DM_0 DDR3_M1_DQ_7 AR1 M_B_DQ6
M_B_DQSP7 BH22 DDR3_M1_DQ_6 AK2 M_B_DQ5
(18) M_B_DQSP7 DDR3_M1_DQS_7 DDR3_M1_DQ_5
M_B_DQSN7 BG23 AL1 M_B_DQ4
(18) M_B_DQSN7 DDR3_M1_DQSB_7 DDR3_M1_DQ_4
M_B_DQSP6 BC24 AR3 M_B_DQ3

a
(18) M_B_DQSP6 DDR3_M1_DQS_6 DDR3_M1_DQ_3
M_B_DQSN6 BC22 AT2 M_B_DQ2
(18) M_B_DQSN6 DDR3_M1_DQSB_6 DDR3_M1_DQ_2
M_B_DQSP5 AT22 AL3 M_B_DQ1
(18) M_B_DQSP5 DDR3_M1_DQS_5 DDR3_M1_DQ_1
(18) M_B_DQSN5 M_B_DQSN5 AT20 AK3 M_B_DQ0
M_B_DQSP4 BH14 DDR3_M1_DQSB_5 DDR3_M1_DQ_0
(18) M_B_DQSP4 DDR3_M1_DQS_4
(18) M_B_DQSN4 M_B_DQSN4 BG15
DDR3_M1_DQSB_4

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M_B_DQSP3 AY2
(18) M_B_DQSP3 DDR3_M1_DQS_3
M_B_DQSN3 BA3
(18) M_B_DQSN3 DDR3_M1_DQSB_3
(18) M_B_DQSP2 M_B_DQSP2 AT12
M_B_DQSN2 AT13 DDR3_M1_DQS_2
(18) M_B_DQSN2 DDR3_M1_DQSB_2
(18) M_B_DQSP1 M_B_DQSP1 AV7
A M_B_DQSN1 AV6 DDR3_M1_DQS_1 A
(18) M_B_DQSN1 DDR3_M1_DQSB_1
M_B_DQSP0 AM2
(18) M_B_DQSP0 DDR3_M1_DQS_0
(18) M_B_DQSN0 M_B_DQSN0 AM3

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DDR3_M1_DQSB_0
2 OF 13 Quanta Computer Inc.
BSW_MCP_EDS
REV = 1 ?
PROJECT : ZHR
Size Document Number Rev
1A
BSW 2/10 (DDRB)
Date: Monday, September 14, 2015 Sheet 7 of 47
5 4 3 2 1
 5 4 3 2 1

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BRASWELL SOC - DISPLAY, XDP, EMMC, SD
SoC (CPU)
08

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?

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BSW_MCP_EDS
DISPLAY MAPPING U10C

D SD MAPPING D

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DDI0 NA
M44 SDMMC1 EMMC
DDI1 eDP RSVD15 K44
RSVD12
K48 SDMMC2 NC
D50 RSVD14 K47

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DDI2 HDMI TP73
DDI0_TXP_0 RSVD13
TP72 C51
DDI0_TXN_0
MCSI_1_CLKP
T44 SDMMC3 SD card
TP63 H49 T45
TP66 H50 DDI0_TXP_1 MCSI_1_CLKN
DDI0_TXN_1 Y47

MCSI and Camera interface

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+V1P8A TP75 F53 DDI0 MCSI_1_DP_0 Y48
TP77 F52 DDI0_TXP_2 MCSI_1_DN_0 V45
DDI0_TXN_2 MCSI_1_DP_1 V47
TP71 G53 MCSI_1_DN_1 V50
R202 TP74 G52 DDI0_TXP_3 MCSI_1_DP_2 V48
DDI0_TXN_3 MCSI_1_DN_2 T41
*10K_4

d
TP67 H47 MCSI_1_DP_3 T42
TP69 H46 DDI0_AUXP MCSI_1_DN_3
DDI0_AUXN P50
MCSI_2_CLKP

i
DP_USB_C_HPD W51 P48
HV_DDI0_HPD MCSI_2_CLKN
Y51 P47
Y52 HV_DDI0_DDC_SCL MCSI_2_DP_0 P45
HV_DDI0_DDC_SDA MCSI_2_DN_0

f
M48
V52 MCSI_2_DP_1 M47
C V51 PANEL0_BKLTEN MCSI_2_DN_1 C
W53 PANEL0_BKLTCTL T50
R544 402/F_4 DDI0_PLLOBS_DP F38 PANEL0_VDDEN RSVD17 T48
DDI0_PLLOBS_DN G38 DDI0_PLLOBS_P RSVD16
DDI0_PLLOBS

n
P44
J51 MCSI_COMP
(20) EDP_TXP0_DP DDI1_TXP_0
H51 AB41 OBSDATA_C0 (16)
(20) EDP_TXN0_DN K51 DDI1_TXN_0 GP_CAMERASB00 AB45
+V1P8A (20) EDP_TXP1_DP DDI1_TXP_1 GP_CAMERASB01 OBSDATA_C1 (16)
K52 AB44 OBSDATA_C2 (16)
(20) EDP_TXN1_DN DDI1_TXN_1 GP_CAMERASB02 AC53
GP_CAMERASB03 OBSDATA_C3 (16)
L53 AB51

o
DDI1 OBSDATA_D0 (16)
L51 DDI1_TXP_2 GP_CAMERASB04 AB52
DDI1_TXN_2 GP_CAMERASB05 OBSDATA_D1 (16)
M52 AA51 OBSDATA_D2 (16)
R492 M51 DDI1_TXP_3 GP_CAMERASB06 AB40
DDI1_TXN_3 GP_CAMERASB07 OBSDATA_D3 (16)
10K_4 M42 Y44 OBSFN_C0 (16,23)
(20) EDP_AUXP_DP DDI1_AUXP GP_CAMERASB08
K42
(20) EDP_AUXN_DN DDI1_AUXN Y42
GP_CAMERASB09 TP_RSVD_STRAP1 (23)
EDP_HPD_L R51 Y41
HV_DDI1_HPD GP_CAMERASB10 V40 TP_RSVD_STRAP2

C
GP_CAMERASB11 TP_RSVD_STRAP2 (23)
3

EDP_BKLTEN P51
(35) EDP_BKLTEN PANEL1_BKLTEN
EDP_BKLTCTL P52
(35) EDP_BKLTCTL PANEL1_BKLTCTL
EDP_HPD 2 EDP_VDDEN R53 M7 EMMC_CLK
(20) EDP_HPD (35) EDP_VDDEN F47 PANEL1_VDDEN SDMMC1_CLK EMMC_CLK (19)
R511 402/F_4 DDI1_PLLOBS_DP
Q55 DDI1_PLLOBS_DN F49 DDI1_PLLOBS_P P6 EMMC_CMD
DDI1_PLLOBS SDMMC1_CMD EMMC_CMD (19)
2N7002K
R478 F40 M6 EMMC_D0 EMMC_D0 (19)

a
(22) INT_HDMITX2P_DP
1

100K/F_4 G40 DDI2_TXP_0 SDMMC1_D0 M4 EMMC_D1

B (22) INT_HDMITX2N_DN DDI2_TXN_0 SDMMC1_D1 EMMC_D1 (19) B
P9 EMMC_D2
SDMMC1_D2 EMMC_D2 (19)
J40 SDMMC1 P7 EMMC_D3
(22) INT_HDMITX1P_DP DDI2_TXP_1 SDMMC1_D3_CD_B EMMC_D3 (19)

t
K40 T6 EMMC_D4
(22) INT_HDMITX1N_DN DDI2_TXN_1 MMC1_D4_SD_WE EMMC_D4 (19)
F42 T7 EMMC_D5 EMMC_D5 (19)
(22) INT_HDMITX0P_DP G42 DDI2_TXP_2 DDI2 MMC1_D5 T10 EMMC_D6 EMMC_D6 (19)
(22) INT_HDMITX0N_DN DDI2_TXN_2 MMC1_D6 T12 EMMC_D7 EMMC_D7 (19)
D44 MMC1_D7 T13 EMMC_RCLK_R R245 *Short_4
(22) INT_HDMICLK_DP DDI2_TXP_3 MMC1_RCLK EMMC_RCLK (19)
F44 P13 EMMC_RCOMP R521 100/F_4
(22) INT_HDMICLK_DN DDI2_TXN_3 SDMMC1_RCOMP

n
D48
C49 DDI2_AUXP K10
DDI2_AUXN SDMMC2_CLK K9
INT_HDMI_HPD U51 SDMMC2_CMD
(22) INT_HDMI_HPD HV_DDI2_HPD M12

a
HDMI_DDCCLK_SW T51 SDMMC2_D0 M10
(22) HDMI_DDCCLK_SW HV_DDI2_DDC_SCL SDMMC2_D1
HDMI_DDCDATA_SW T52 K7
(22) HDMI_DDCDATA_SW HV_DDI2_DDC_SDA SDMMC2_D2
SDMMC2 K6
B53 SDMMC2_D3_CD_B
A52 RSVD6 F2 SD3_CLK
RSVD3 SDMMC3_CLK SD3_CLK (19)
E52 D2

u
RSVD9 SDMMC3_CMD SD3_CMD (19)
D52 K3
RSVD8 SDMMC3_CD_B SD3_CD# (19,21)
B50
B49 RSVD5 NC's J1
RSVD4 SDMMC3_D0 SD3_D0 (19)
E53 J3 SD3_D1 (19)
C53 RSVD10 SDMMC3_D1 H3
RSVD7 SDMMC3_D2 SD3_D2 (19)
A51 G2
RSVD2 SDMMC3_D3 SD3_D3 (19)
A49
G44 RSVD1 K2
A SDMMC3 A
RSVD11 SDMMC3_1P8_EN SDMMC3_1P8_EN (19)
L3

Q
SDMMC3_PWR_EN_B P12 SDMMC3_PWR_EN_N (19)
SDIO3_RCOMP R504 80.6/F_4
SDMMC3_RCOMP

SD3_CLK
Quanta Computer Inc.
C150
BSW_MCP_EDS
3 OF 13
*33P/50V_4 PROJECT :ZHR
REV = 1 ? Size Document Number Rev
1A
BSW 3/10 (DDI,SD,EMMC)
Date: Monday, September 14, 2015 Sheet 8 of 47
5 4 3 2 1
 5 4 3 2 1

09

l
PCIe MAPPING
BSW SOC - SATA, PCIe, SPI, I2S PCIE0 Video Codec

a
PCIE1 Video Codec
SoC (CPU)

i
PCIE2 WIFI (StP)

t
D U10D
?
BSW_MCP_EDS
PCIE3 NC D

0818 unstuffed related RC components of Kepler

C31 C24 PCIE_TX0_IMAGE_C_DP C154 *[email protected]/16V_4
SATA_TXP0 PCIE_TXP0 PCIE_TX0_IMAGE_DP (32)
B30 B24 PCIE_TX0_IMAGE_C_DN C153 *[email protected]/16V_4
SATA_TXN0 PCIE_TXN0 PCIE_TX0_IMAGE_DN (32)

n
N28 G20 PCIE_RX0_IMAGE_DP
SATA_RXP0 PCIE_RXP0 PCIE_RX0_IMAGE_DP (32)
M28 J20 PCIE_RX0_IMAGE_DN
SATA_RXN0 PCIE_RXN0 PCIE_RX0_IMAGE_DN (32)
C29
A29 SATA_TXP1 A25 PCIE_TX1_IMAGE_C_DP C158 *[email protected]/16V_4 Video Codec
SATA_TXN1 PCIE_TXP1 PCIE_TX1_IMAGE_DP (32)
J28 C25 PCIE_TX1_IMAGE_C_DN C159 *[email protected]/16V_4
SATA_RXP1 PCIE_TXN1 PCIE_TX1_IMAGE_DN (32)

e
K28 D20 PCIE_RX1_IMAGE_DP
SATA_RXN1 PCIE_RXP1 PCIE_RX1_IMAGE_DP (32)
F20 PCIE_RX1_IMAGE_DN
PCIE_RXN1 PCIE_RX1_IMAGE_DN (32)
(35) EC_IN_RW_Q EC_IN_RW_Q AH3
AH2 SATA_LEDN B26 PCIE_TX2_WLAN_C_DP C163 0.1U/16V_4
(35) WIFI_DISABLE# SATA_GP0 PCIE_TXP2 PCIE_TX2_WLAN_DP (24)
AG3 C26 PCIE_TX2_WLAN_C_DN C161 0.1U/16V_4
(35) TOUCH_INT#
AG1 SATA_GP1 SATA PCIe PCIE_TXN2 D22 PCIE_RX2_WLAN_DP
PCIE_TX2_WLAN_DN (24) WLAN
SATA_GP2 PCIE_RXP2 PCIE_RX2_WLAN_DP (24)

d
RAMID0 AF3 F22 PCIE_RX2_WLAN_DN
(10) RAMID0 SATA_GP3/SATA_DEVSLP1 PCIE_RXN2 PCIE_RX2_WLAN_DN (24)
R501 402/F_4 SATA_RCOMP_DP N30 A27
SATA_RCOMP_DN M30 SATA_RCOMP_P PCIE_TXP3 C27

i
SATA_RCOMP_N PCIE_TXN3 G24
FAST_SPI_CLK W3 PCIE_RXP3 J24
FST_SPI_CLK PCIE_RXN3
FAST_SPI_CS0 V4 AM10 PCIE_CLKREQ_IMAGE#

f
FST_SPI_CS0_B PCIE_CLKREQ0B PCIE_CLKREQ_IMAGE# (32)
V6 AM12 LTE_WAKE#
FST_SPI_CS1_B PCIE_CLKREQ1B LTE_WAKE# (35) pullup at level shifter side
(35) LTE_DISABLE# LTE_DISABLE# V7 AK14 PCIE_CLKREQ_WLAN#
FST_SPI_CS2_B PCIE_CLKREQ2B PCIE_CLKREQ_WLAN# (24)
AM14 AUDIO_CODEC_IRQ
PCIE_CLKREQ3B AUDIO_CODEC_IRQ (26)
FAST_SPI_D0 V2
FAST_SPI_D1 V3 FST_SPI_D0 A21
FST_SPI_D1 FAST SPI CLK_DIFF_P_0 CLK_PCIE_IMAGEP_DP (32)
U1 C21
C
Video Codec C

n
FST_SPI_D2 CLK_DIFF_N_0 CLK_PCIE_IMAGEN_DN (32)
U3 C19
FST_SPI_D3 CLK_DIFF_P_1 B20
AF13 CLK_DIFF_N_1 C18
MF_HDA_RSTB CLK_DIFF_P_2 CLK_PCIE_WLANP_DP (24)
AD6 B18
AD9 MF_HDA_SDI1 CLK_DIFF_N_2 C17
CLK_PCIE_WLANN_DN (24) WLAN
AD7 MF_HDA_CLK CLK_DIFF_P_3 A17

o
AF12 MF_HDA_SDI0 CLK_DIFF_N_3 C16
AF14 MF_HDA_SYNC RSVD_C16 B16 +V1P8A
pullup at level shifter side MF_HDA_SDO RSVD_B16
(27) AJACK_MICPRES_L
AB9
AB7 MF_HDA_DOCKENB D26 SOC_PCIE_COMP_DP R520 402/F_4
(27) AUDIO_SWITCH_INT_N MF_HDA_DOCKRSTB PCIE_RCOMP_P F26 SOC_PCIE_COMN_DN PCIE_CLKREQ_IMAGE# R450 *VC@10K_4
H4 SATA_RCOMP PCIE_CLKREQ_WLAN# R449 *10K_4
pullup at level shifter side SPKR AUDIO
V14 EC_IN_RW_Q R455 10K_4
AK9 SPI1_CLK Y13 AUDIO_CODEC_IRQ R448 *10K_4

C
(26) I2S_BCLK_R GP_SSP_2_CLK SPI1_CS0_B
(26) I2S_LRCLK_R AK10 SPI Y12
AK12 GP_SSP_2_FS SPI1_CS1_B V13
(26) I2S_DOUT_R GP_SSP_2_TXD SPI1_MISO
(26) I2S_DIN_R AK13 V12
GP_SSP_2_RXD SPI1_MOSI

4 OF 13
BSW_MCP_EDS
REV = 1 ?

ta
B BIOS ROM(CPU) +V1P8A +V1P8A_ME +V1P8A_ME
B

n
+V1P8A_ME Q60
PJA138K FAST_SPI_CS0 R212 3.3K/F_4
SOC_SPI_WP# R246 *3.3K/F_4
1 3 SOC_SPI_HOLD# R260 3.3K/F_4
SOC_SPI_MOSI_R R278 *3.3K/F_4
+V1P8A_ME SOC_SPI_MISO_R R243 *3.3K/F_4

a
R591 +V3P3A C345 SOC_SPI_CLK_R R238 *3.3K/F_4

100K_4 C148 0.1u/10V_4 2 0.1U/16V_4

5

2 SPI NOR FLASH

u
4 SOC_SPI_WP# SOC_SPI_WP# (34) soic8-7_9-1_27
(21) GPIO_SPI_WP R292 *Short_4 SPI_WP_ME R242 *Short_4 SPI_WP_ME_ROM_Q 1 AKE5EZN0N00
U13 IC FLASH (8P) W25Q64FWSSIG (SOIC)
U12 R252 8 5 SOC_SPI_MOSI_R R268 10_4 FAST_SPI_D0
From debug header
3

74LVC1G34 VCC SPI_SI 2 SOC_SPI_MISO_R R224 10_4 FAST_SPI_D1

100K_4 SPI_SO 1 SOC_SPI_CS#_R R219 10_4 FAST_SPI_CS0
SOC_SPI_WP# 3 CS# 6 SOC_SPI_CLK_R R237 10_4 FAST_SPI_CLK
W P# SPI_SCK

Q
SOC_SPI_HOLD# 7 4
SPI_HOLD GND
Q
(21) SPI_HOLD#_BIOS R261 *Short_4 SOC_SPI_HOLD# SPI_FLASH
R263 10K_4 +V1P8A R269 GD@0_4 GD_SPI_SI_R (21)
R233 GD@0_4
Q26 From debug header R209 GD@0_4
GD_SPI_SO_R (21)
GD_SPI_CS0#_R (21)
A PJA138K R239 GD@0_4 GD_SPI_CLK_R (21) A

1 3 PCH_SPI_WP_D PCH_SPI_WP_D (10)

CAD note: Place near to SPI flash
to SoC
2

(28,30) SPI_WP_ME
Quanta Computer Inc.
From Screw
PROJECT : ZHR
Size Document Number Rev
1A
BSW 4/10 (PCIE/SATA/SPI)
Date: Monday, September 14, 2015 Sheet 9 of 47
5 4 3 2 1
 5 4 3 2 1

l
SoC (CPU)
BRASWELL - I2C, XDP, SM BUS
10

ia
?
U10E BSW_MCP_EDS

D
RESERVED ISH GPIOs - RSVD for type C GPIOs D

t
XTAL19_2_IN P24
XTAL19_2_OUT M22 OSCIN C11 TP_HOST_DETECT TP34
OSCOUT RSVD3 B10 TP_DEVICE_DETECT TP29
J26 RSVD2 F12 TP_POL_DETECT TP70
N26 RSVD13 RSVD9 F10 TP_WAKE_ALERT# TP68

n
R293 2.49K/F_4 ICLK_ICOMP P20 RSVD17 RSVD8
R295 49.9/F_4 ICLK_RCOMP N20 ICLKICOMP iCLK RESERVED D12
ICLKRCOMP RSVD5 PCH_SPI_WP_D (9)
P26 E8
K26 RSVD18 RSVD7 C7
M26 RSVD14 RSVD4 D6

e
AH45 RSVD16 RSVD6
RSVD1 J12
I2S_MCLK_R A9 RSVD11 F7
(26) I2S_MCLK_R C9 MF_PLT_CLK0 RSVD10 J14
RAMID2

PLTFM CLK's
B8 MF_PLT_CLK1 RSVD12 L13

d
B7 MF_PLT_CLK2 RSVD15
B5 MF_PLT_CLK3 AK6 I2C_0_SCL R471 *Short_4 I2C_0_SCL_R
B4 MF_PLT_CLK4 I2C0_SCL AH7 I2C_0_SDA R464 *Short_4 I2C_0_SDA_R
I2C_0_SCL_R (35) Touch panel
I2C_0_SDA_R (35) Level shifter is un-stuffed

i
MF_PLT_CLK5 I2C0_SDA
Level shifter of Touch screen INT is un-stuffed
AF6 I2C_1_SCL (35)
AM40 I2C1_SCL AH6
(16) XDP_GPIO_DFX0 AM41 GPIO_DFX0 I2C1_SDA I2C_1_SDA (35) Audio
Level shifter is stuffed for Audio codec and MIC switch

f
(16) XDP_GPIO_DFX1 GPIO_DFX1
AM44 AF9 I2C_NFC_SCL TP7

GPIO_DFX
C (16) XDP_GPIO_DFX2 AM45 GPIO_DFX2 I2C2_SCL AF7
C
I2C_NFC_SDA TP6
(16) XDP_GPIO_DFX3 GPIO_DFX3 I2C I2C2_SDA
AM47
(16) XDP_GPIO_DFX4 AK48 GPIO_DFX4 AE4 RAMID1
(16) XDP_GPIO_DFX5 AM48 GPIO_DFX5 I2C3_SCL AD2 RAMID3

n
(16) XDP_GPIO_DFX6 GPIO_DFX6 I2C3_SDA
AK41
(16) XDP_GPIO_DFX7 AK42 GPIO_DFX7 AC1 I2C_4_SCL_C TP9
(16) XDP_GPIO_DFX8 GPIO_DFX8 I2C4_SCL AD3 I2C_4_SDA_C TP8
AD51 I2C4_SDA
(23,34) SOC_WAKE_SCI_N GPIO_SUS0
AD52 AB2 Level shifter of Track Pad INT is stuffed
(23,35) MUX_AUD_INT1# GPIO_SUS1 I2C5_SCL I2C_5_SCL (35)

o
AH50 AC3 I2C_5_SDA (35) Track pad Level shifter is stuffed
(23,34) EC_SMI_L AH48 GPIO_SUS2 I2C5_SDA TP38

GPIO_SUS
(23,34) KBD_IRQ# GPIO_SUS3
DFX_SUS_DBG_STRAP AH51 AA1 I2C_6_SCL_C
AH52 GPIO_SUS4 I2C6_SCL AB3 SDCARD_WP (19)
EC_KBD_ALERT_SOC SDCARD_WP
AG51 GPIO_SUS5 I2C6_SDA
(16,23) SOC_RUNTIME_SCI GPIO_SUS6
TRACKPAD_INT# AG53 AA3
(23) TRACKPAD_INT# AF52 GPIO_SUS7 RSVD_AA3 Y2
(23) NFC_FW_RESET# SEC_GPIO_SUS9 RSVD_Y2 +V1P8A

C
(23) TP_RSVD_STRAP3 AF51
AE51 SEC_GPIO_SUS8 AM6 SMB_SOC_CLK
(23) NFC_PWR_MANAGE SEC_GPIO_SUS10 MF_SMB_CLK SMB_SOC_CLK (16,35)
AC51 SMBUS AM7 SMB_SOC_DATA
(35) SIM_DET_C SEC_GPIO_SUS11 MF_SMB_DATA SMB_SOC_DATA (16,35)
R193 100/F_4 SOC_GPIO_RCOMP AH40 AM9 TP_GPIO_2_SOC TP55 R166 4.7K_4 SOC_WAKE_SCI_N
DET_TRIGGER Y3 GPIO0_RCOMP MF_SMB_ALERTB R153 *10K_4 KBD_IRQ#
(35) DET_TRIGGER GPIO_ALERT R157 *10K_4 EC_SMI_L
pullup at level shifter side
RAMID +V1P8A

a
B 5 OF 13 RAMID0 (9) B
BSW_MCP_EDS
R173 *Short_4 DFX_SUS_DBG_STRAP REV = 1 ?
(23) SOC_KBC_SMI
R460 *10K_4 RAMID0 R454 10K_4
0819 Changed the PU of RAMID back to 10K

t
R178 *10K_4 RAMID1 R184 10K_4
19.2MHz X'tal EC_KBD_ALERT_SOC
EC_KBD_ALERT_SOC (23)

n
R271 10K_4 RAMID2 R281 *10K_4
3

C164 15P/50V_4 XTAL19_2_OUT

R195 10K_4 RAMID3 R192 *10K_4

2 Q95

a
(30) EC_KBD_ALERT
PJA138K
2
1

Y2
1

R310 TRACKPAD_INT# R827 33_4

TRACKPAD_INT#_R (29)

u
19.2MHZ +-20PPM 200K/F_4
4
3

Vender RAM_ID Q PN Mfr. PN Freq. Size Total C423

Size
180p/50V_4
Samsung 0000 AKD5PGST514 K4B4G1646Q-HYK0 1600MHz 4Gb 4GB
A A
C171 15P/50V_4 XTAL19_2_IN Hynix 0001 AKD5PGSTW13 H5TC4G63CFR-PBA 1600MHz 4Gb 4GB
ZHRA DVT SKU2/3

Q
2nd source:BG619200014 (TXC) Samsung 0010 AKD5PGST514 K4B4G1646Q-HYK0 1600MHz 4Gb 2GB
ZHRA DVT SKU1 Quanta Computer Inc.
Hynix 0011 AKD5PGSTW13 H5TC4G63CFR-PBA 1600MHz 4Gb 2GB
PROJECT : ZHR
Size Document Number Rev
1A
BSW 5/10 (I2C/DFX/GPIO)
Date: Monday, September 14, 2015 Sheet 10 of 47
5 4 3 2 1
 5 4 3 2 1

l
BRASWELL - USB INTERFACE
11

a
SoC (CPU)

i
D D

t
BSW_MCP_EDS

n
U10F ?

B48 TP_USB_OTG_ID TP76

TP28 B32 USB_OTG_ID C42
TP24 C32 USB3_TXP0 USB_DP0 B42
USBP0_DP (27) USB2.0_DB

e
F28 USB3_TXN0 USB_DN0 USBP0_DN (27)
TP26
TP27 D28 USB3_RXP0 C43
USB3_RXN0 USB_DP1 B44
USBP1_DP (25) LTE
A33 USB_DN1 USBP1_DN (25)
TP22
TP23 C33 USB3_TXP1 C41
USBP2_DP (28) USB3.0_1

d
TP31 F30 USB3_TXN1 USB_DP2 A41
D30 USB3_RXP1 USB_DN2 USBP2_DN (28)
TP32
USB3_RXN1 C45 CCD

i
C34 USB_DP3 A45 USBP3_DP (20)
(28) USB3_TXP2_DP USB3_TXP2 USB_DN3 USBP3_DN (20)
B34
(28) USB3_TXN2_DN G32 USB3_TXN2 B40
(28) USB3_RXP2_DP J32 USB3_RXP2 USB_DP4 C40 USBP4_DP (24) BT

f
(28) USB3_RXN2_DN USB3_RXN2 USB_DN4 USBP4_DN (24)

USB3.0

USB2.0
C
C35 P16 USB_OC1# (27,34) C
USB_OC1# R335 10K_4
A35 USB3_TXP3 USB_OC1_B P14 USB_OC0# R339 10K_4
USB3_TXN3 USB_OC0_B +V1P8A
G34
J34 USB3_RXP3 B46 USB_OC0# (28,34)

n
USB3_RXN3 USB_RCOMP1 B47 USB_VBUSSNS R270 10K_4
USB3_OBSP_DP D34 USB_VBUSSNS A48 USB_RCOMP R274 113/F_4
F34 USB3_RCOMP_P USB_RCOMP
R527 USB3_OBSN M36
C37 USB_HSIC_0_STROBE N36
402/F_4 RSVD4 USB_HSIC_0_DATA

o
A37

HSIC
F36 RSVD1 K38
USB3_OBSN_DN D36 RSVD7 USB_HSIC_1_STROBE M38
RSVD6 USB_HSIC_1_DATA

RESERVED
M34 N38 USB_HSIC_RCOMP R543 *49.9/F_4
M32 RSVD11 USB_HSIC_RCOMP
RSVD10 AD10 SOC_UART_TX
C38 UART1_TXD AD12 SOC_UART_TX (21)
SOC_UART_RX
RSVD5 UART1_RXD SOC_UART_RX (21)

C
B38 AD13
G36 RSVD2 UART1_CTS_B AD14

UART
J36 RSVD8 UART1_RTS_B
RSVD9 Y6
SOC_UART_TX R200 *0_4 SOC_UART_RX N34 UART2_TXD Y7
P34 RSVD12 UART2_RXD V9
RSVD13 UART2_CTS_B V10
UART2_RTS_B

a
B B
Un-Stuff for Test Only
6 OF 13

t
BSW_MCP_EDS
REV = 1 ?

an
u
A A

Q
Quanta Computer Inc.
PROJECT : ZHR
Size Document Number Rev
1A
BSW 6/10 (USB)
Date: Monday, September 14, 2015 Sheet 11 of 47
5 4 3 2 1
 5 4 3 2 1

l
BRASWELL - JTAG, LPC, THERMAL, PMU 12

a
RTC 32.768KHz X'tal

i
Y3 32.768KHZ
SoC (CPU) 1 2 RTC_X2

t
D ? D
U10G BSW_MCP_EDS R309 10M_4

(16) XDP_H_TCK AF42 M18 RTC_X1 C169 C175

AD47 TCK BRTCX1_PAD K18 RTC_X2 15P/50V_4 15P/50V_4

n
(16) XDP_H_TDI

JTAG/ITP
AF40 TDI RTCX2_PAD F16 BRTC_EXTPAD C170 0.1U/16V_4
(16) XDP_H_TDO TDO RTC_EXTPAD
(16) XDP_H_TMS AD48
AB48 TMS D18 SRTCRST#

RTC
(16) XDP_H_TRST# TRST_B SRTCRST_B G16 CORE_PWROK_R
COREPWROK CORE_PWROK_R (16,30,31)
F18 SOC_RSMRST#

e
RSMRST_B SOC_RSMRST# (16,34)
AD45 J16 SOC_RTEST#
(16) XDP_H_PRDY_N CX_PRDY_B RTC_TEST
(16) XDP_H_PREQ_N AF41 G18 RSVD_VSS_G18 R307 10K/F_4
RSVD_M13 M13 CX_PREQ_B RSVD_VSS
RSVD5 AE3 PMC_SUSPWRDNACK
SUSPWRDNACK PMC_SUSPWRDNACK (34)
CLK_PCI_EC R506 10_4 CLK_PCI_EC_SOC P2 D14 PMC_SUS_STAT#
MF_LPC_CLKOUT0 SUS_STAT_B PMC_SUS_STAT# (34)

d
TP13 TP_L_CLKOUT1 R3 C15 PMC_SUSCLK0
MF_LPC_CLKOUT1 PMU_SUSCLK PMC_SUSCLK0 (35)
T3 C12 SLP_S4#
(30) LPC_CLKRUN_L LPC_CLKRUNB PMU_SLP_S4_B SLP_S4# (34)
P3 B14 SLP_S3#
(27,30) LPC_LFRAME# LPC_FRAMEB PMU_SLP_S3_B SLP_S3# (22,34,42,43)

i
AF2 SOC_REST_BTN#

PMU
SOC_REST_BTN# (16,21,34)

LPC
M3 PMU_RESETBUTTON_B F14 SOC_PLTRST#
(27,30) LPC_LAD0 MF_LPC_AD0 PMU_PLTRST_B SOC_PLTRST# (12,16,19,34)
M2 C14 PMC_BATLOW#
(27,30) LPC_LAD1 MF_LPC_AD1 PMU_BATLOW_B
N3 C13 ACPRESENT
(27,30) LPC_LAD2 ACPRESENT (35)

f
N1 MF_LPC_AD2 PMU_AC_PRESENT A13 SLP_S0IX#
(27,30) LPC_LAD3 MF_LPC_AD3 PMU_SLP_S0IX_B SLP_S0IX# (34,42)
B12 TP_SOC_SLP_LAN#
R500 100/F_4 RCOMP_LPC_HVT T4 PMU_SLP_LAN_B N16 SOC_PMC_WAKE# R312 *Short_4 TP25
LPC_HVT_RCOMP PMU_WAKE_B PCH_WAKE_L (34)
ILB_SERIRQ T2 M16 SOC_PWRBTN#
(34) ILB_SERIRQ ILB_SERIRQ PMU_PWRBTN_B SOC_PWRBTN# (34)
C P18 TP_PMU_WAKE_LAN_B C
H5 PMU_WAKE_LAN_B TP60

PWM
n
H7 RSVD_H5 AD42 SVID_CLK
RSVD_H7 SVID0_CLK SVID_CLK (31)
AD41 SVID_DATA

SVID
SVID0_DATA SVID_DATA (31)
AD40 SVID_ALERT#
SVID0_ALERT_B SVID_ALERT# (31)
P28
P30 RSVD6

o
RSVD7 AG32 +VCORE_VCC0_SENSEP_DP R160 100/F_4
AF50 +VCC_SENSEP_DP (38)

Voltage sense
CORE_VCC0_SENSE AJ32 +VCORE_VCC0_SENSEN_DN R161 100/F_4
AF48 RSVD4 +VCC_SENSEN_DN (38)

Reserved
CORE_VSS0_SENSE AD29 +VCORE_VCC1_SENSEP_DP R266 100/F_4
AF44 RSVD3
CORE_VCC1_SENSE
AF45 RSVD1
CORE_VSS1_SENSE
AF27 +VCORE_VCC1_SENSEN_DN R272 100/F_4 SENSEP and SENSEN differential routing
+VGG_SENSEP_DP (39) SENSEP and SENSEN differential routing
RSVD2 AD24
AD50 DDI_VGG_SENSE
PROCHOT_B AD22
UNCORE_VSS_SENSE2 +VGG_SENSEN_DN (39)
PROCHOT# AC27
(21,30) PROCHOT# UNCORE_VSS_SENSE1 +VNN_SENSEP_R R493 100/F_4

C
+VNN_SENSEP (41,42)
CC 7 OF 13
+V1P8A
C122 BSW_MCP_EDS
CLK_PCI_EC
CLK_PCI_EC (27,30)
PLACE 'CC' CAP NEAR SOC 0.1U/16V_4 REV = 1 ?
PMC_SUSPWRDNACK R458 10K_4
SOC_PMC_WAKE# (35)
SOC_PMC_WAKE# R311 10K_4
+V1P8A ACPRESENT R302 2.2K_4 O_1.8VA

a
PMC_BATLOW# R587 10K_4
PROCHOT# R152 20K_4 SOC_REST_BTN# R447 10K_4 SOC_PLTRST#
SOC_PLTRST# (12,16,19,34)

t
B VCC_VR_HOT_N R162 *Short_4 PROCHOT# CORE_PWROK_R B
(38) VCC_VR_HOT_N

(39) VGG_VR_HOT_N
VGG_VR_HOT_N R163 *Short_4 PLACE 'CB' CAP NEAR SOC
CB

n
VNN_VR_HOT_N R148 *Short_4 C357 R306 10K_4 RSVD_M13
(41) VNN_VR_HOT_N
0.1U/16V_4

VBATA_VR_HOT_N R156 *Short_4

(36) VBATA_VR_HOT_N

a
TEMP_ALERT# R155 *Short_4
(33) TEMP_ALERT#

u
RTC Circuitry(RTC) +VRTC +VRTC

RTC CIRCUIT
R583 R581 +V3P3A_LDO +VRTC

Q
20K_4 20K_4

SRTCRST# SOC_RTEST#
3

A R364 A
*SHORT_6

(12,30) EC_STRAP_GPIO1 2 (12,30) EC_STRAP_GPIO1 2

C358 C359
Q19 1u/6.3V_4 Q20 1u/6.3V_4
2N7002K 2N7002K Quanta Computer Inc.
Imax support up to 100uA
1

Estimate 1.5mW Ploss at Imax PROJECT : ZHR

Size Document Number Rev
1A
BSW 7/10 (JTAG/LPC//PMU)
Date: Monday, September 14, 2015 Sheet 12 of 47
5 4 3 2 1
 5 4 3 2 1

BRASWELL - POWER 1

l
SoC (CPU)
PLACE THESE CAPS CLOSE TO
AA18, AA19, AA21, AA22, AA24, AA25,
13

a
+VCC0_CPU AC18, AC19, AC21, AC22, AC24, AC25,
U10H ?
BSW_MCP_EDS AD25 AND AD27 +VCCSOCVID_1P05

i
AA18
C141 C139 C300 C308 C315 AF36 UNCORE_VNN_S41 AA19 C321 C327 C329 C316 C342 C340 C341

t
D 4.7U/6.3V_4 4.7U/6.3V_4 4.7U/6.3V_4 AG33 CORE_VCC1_S0IX3 UNCORE_VNN_S42 AA21 1U/10V_4 22uF/6.3V_6 22uF/6.3V_6 22uF/6.3V_6 D
22uF/6.3V_6 22uF/6.3V_6 CORE_VCC1_S0IX7 UNCORE_VNN_S43 1U/10V_4 1U/10V_4 1U/10V_4
AG35 AA22
AG36 CORE_VCC1_S0IX8 UNCORE_VNN_S44 AA24
AG38 CORE_VCC1_S0IX9 UNCORE_VNN_S45 AA25
AJ33 CORE_VCC1_S0IX10 UNCORE_VNN_S46 AC18
AJ36 CORE_VCC1_S0IX14 UNCORE_VNN_S47 AC19

n
AJ38 CORE_VCC1_S0IX15 UNCORE_VNN_S48 AC21
+VCC0_CPU CORE_VCC1_S0IX16 UNCORE_VNN_S49 AC22
UNCORE_VNN_S410 AC24
AF30 UNCORE_VNN_S411 AC25
AG27 CORE_VCC1_S0IX2 UNCORE_VNN_S412 AD25

e
CORE_VCC1_S0IX4 UNCORE_VNN_S413
AG29
CORE_VCC1_S0IX5 UNCORE_VNN_S414
AD27 PLACE THESE CAPS CLOSE TO
C140 C142 C310 C301 C307 AG30
4.7U/6.3V_4 4.7U/6.3V_4 4.7U/6.3V_4 AJ27 CORE_VCC1_S0IX6 AA30 +V1P05A_R_SOC V33, AA32, AA33, AA35, AA36,
22uF/6.3V_6 22uF/6.3V_6
AJ29 CORE_VCC1_S0IX11 RSVD1 V33 AC32, Y30, Y32, Y33 AND Y35
AJ30 CORE_VCC1_S0IX12 VCCSRAMSOCIUN_1P056 AA32
AF29 CORE_VCC1_S0IX13 VCCSRAMSOCIUN_1P051 AA33

d
CORE_VCC1_S0IX1 VCCSRAMSOCIUN_1P052 AA35 C167 C324 C318 C335 C166
VCCSRAMSOCIUN_1P053 AA36 1U/10V_4
VCCSRAMSOCIUN_1P054 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4
AD16 AC32

i
+VGG AD18 DDI_VGG_S0IX1 VCCSRAMSOCIUN_1P055 Y30
AD19 DDI_VGG_S0IX2 VCCSRAMSOCIUN_1P057 Y32 +V1P05A_R_SOC
DDI_VGG_S0IX3 VCCSRAMSOCIUN_1P058
AF16
DDI_VGG_S0IX4 VCCSRAMSOCIUN_1P059
Y33 PLACE THIS CAP CLOSE TO V19 AND V18
C305 C306 C311 C312 AF18 Y35

f
DDI_VGG_S0IX5 VCCSRAMSOCIUN_1P0510
AF19
DDI_VGG_S0IX6 PLACE THESE CAPS CLOSE TO
1U/10V_4 10u/6.3V_4 10u/6.3V_6 10u/6.3V_6 AF21 V19 C333
DDI_VGG_S0IX7 ICLK_GND_OFF2 AM21, AM33, AM22, AN22, AN32

iCLK
AF22 V18 1U/10V_4
AJ19 DDI_VGG_S0IX8 ICLK_GND_OFF1 +V1P05A_R_SOC AND AM32
AG16 DDI_VGG_S0IX15 AM21
C C
DDI_VGG_S0IX9 DDR_V1P05A_G31

n
AG18 AM33
AG19 DDI_VGG_S0IX10 DDR_V1P05A_G34 AM22 C415
DDI_VGG_S0IX11 DDR_V1P05A_G32

DDR
AG21 AN22 C295 C123 C127 C404 C405 C406 C407 C409 C408 C410 C414
AG22 DDI_VGG_S0IX12 DDR_V1P05A_G35 AN32 1U/10V_4 22uF/6.3V_6 22uF/6.3V_6 1U/10V_4 1U/10V_4 22uF/6.3V_6 22uF/6.3V_6 *1U/10V_4 *1U/10V_4 *22uF/6.3V_6 *22uF/6.3V_6 10u/6.3V_6
AG24 DDI_VGG_S0IX13 DDR_V1P05A_G36 AM32
AJ21 DDI_VGG_S0IX14 DDR_V1P05A_G33
DDI_VGG_S0IX16

o
AJ22 V22
DDI_VGG_S0IX17 PCIE_V1P05A_G31

PCIe
AJ24 V24 +V1P05A_R_SOC
AK24 DDI_VGG_S0IX18 PCIE_V1P05A_G32
+V1P15A DDI_VGG_S0IX19
U24
SATA_V1P05A_G32

SATA
AK30
AK35 CORE_V1P15_S0IX1 SATA_V1P05A_G31
U22 C351
1U/10V_4
C173
1U/10V_4
C343
1U/10V_4
PLACE THESE CAPS CLOSE TO
C304 C299 C298 C302 C126 C125 AK36 CORE_V1P15_S0IX2 V22, V24, U24, U22, V27 AND U27

C
1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 AM29 CORE_V1P15_S0IX3 V27
CORE_V1P15_S0IX4 USB3_V1P05A_G32 U27

USB
USB3_V1P05A_G31
PLACE THESE CAPS CLOSE TO +V1P15A USBSSIC_V1P05A_G3
V29 +V1P05A_SSIC_SOC R253 *Short_4 +V1P05A_R_SOC
AK33
AK30, AK35, AK38 AND AM29 AJ35 FUSE_V1P15_S0IX2 N18 +V1P05A_R_SOC

FUSE
+V1P15A FUSE_V1P15_S0IX1 FUSE3_V1P05A_G5
AM19
AK21 VCCSRAMGEN_1P152 FUSE_V1P05A_G3
U19 PLACE THIS C397
1U/10V_4
C398
1U/10V_4
PLACE THESE CAPS CLOSE TO VCCSRAMGEN_1P151 CAP CLOSE TO

a
AM19 AND AK21 C130 C303 C131
8 OF 13 C336 N18
BSW_MCP_EDS 1U/10V_4
1U/10V_4 1U/10V_4 1U/10V_4 REV = 1 ?

t
+V1P05A_R_SOC

B B

C338 C344
PLACE THESE CAPS CLOSE TO U19
1U/10V_4 1U/10V_4

an
u
+VDDQ_M0_M1_R +VCCSFRPLLDDR_1P24_1P35
+V1P05A R258 *SHORT_8 +V1P05A_R_SOC +V1P05A R650 *SHORT_6 +V1P05A_R_SOC

R78 *SHORT_6 R227 *SHORT_8 R651 *SHORT_6

R244 *SHORT_8 R652 *SHORT_6

+VDDQ_M0_M1_R +VCCCLKDDR_1P24_1P35

Q
R79 *SHORT_6
+V1P05A_R_SOC

A A

+VNN R211 *SHORT_8 +VCCSOCVID_1P05 C144 C177 C176

22uF/6.3V_6 22uF/6.3V_6 22uF/6.3V_6
R503 *SHORT_8

R210 *SHORT_8 Quanta Computer Inc.

CAD NOTE: PLACE CLOSE TO PIN AM21, PROJECT : ZHR
AM33, AM22, AN22, AN32 AND AM32 POWER PLANE
Size Document Number Rev
BSW 8/10 (Power 1) 1A

Date: Monday, September 14, 2015 Sheet 13 of 47

5 4 3 2 1
 5 4 3 2 1

+V1P24A_R_SOC

BRASWELL - POWER 2

l
SoC (CPU)

PLACE THESE CAPS

C326
PLACE
1U/10V_4 THESE CAPS
14

a
CLOSE TO V36 & Y36
CLOSE TO AM25 PLACE THESE CAPS CLOSE TO AN27 +V1P24A_MIPI_SOC

+VCCSFRPLLDDR_1P24_1P35

i
+VCCCLKDDR_1P24_1P35 +V1P24A_R_SOC R663 *Short_4 +V1P24A_R_SOC

PLACE THESE CAPS R662 *0_4

t
C399 C400
D
C71 C297 C66 C296 U10I
?
BSW_MCP_EDS C330
CLOSE TO Y27 & Y25 D
1U/10V_4 1U/10V_4
22uF/6.3V_6 1U/10V_4 22uF/6.3V_6 1U/10V_4 1U/10V_4
AN27 V36
AM25 DDRSFR_VDDQ_G_S4 DDI_VDDQ_G31 Y36 +V1P24A_R_SOC
DDR_VDDQ_G_S42 DDI_VDDQ_G32

n
BE1
DDR_VDDQ_G_S416 MIPI_V1P2A_G32
T40 PLACE THESE CAPS
PLACE THESE CAPS BE53
DDR_VDDQ_G_S419 MIPI_V1P2A_G31
P40
CLOSE TO P38, V30 & AC30
BJ2 C331 C317
CLOSE TO THE +VDDQ_M0_M1_R BJ3 DDR_VDDQ_G_S426 Y27 1U/10V_4 1U/10V_4
DDR_VDDQ_G_ PINS BJ49 DDR_VDDQ_G_S427 ICLK_VSFR_G32 Y25 +V1P24A_R_SOC
DDR_VDDQ_G_S428 ICLK_VSFR_G31

e
BJ5
DDR_VDDQ_G_S429
BH50
DDR_VDDQ_G_S425 CORE_VSFR_G35
P38 PLACE THESE CAPS
C94 C95 C108 C107 BH5 V30
BH49 DDR_VDDQ_G_S424 CORE_VSFR_G36 AC30 C319
CLOSE TO AF35, AD35, AD38 & AC36
22uF/6.3V_6 22uF/6.3V_6 22uF/6.3V_6 22uF/6.3V_6 DDR_VDDQ_G_S423 CORE_VSFR_G31

DDR
BH4 1U/10V_4
BE3 DDR_VDDQ_G_S422
DDR_VDDQ_G_S417

d
PLACE THESE CAPS +VCCPADCF3SI0_1P8_3P3
BG51
DDR_VDDQ_G_S421 CORE_VSFR_G34
AF35
BG3 AD35
CLOSE TO E1 AND E2 BJ51 DDR_VDDQ_G_S420 CORE_VSFR_G32 AD38 USBHNSSIC_V1P24A_M41_P41 R661 *Short_4
DDR_VDDQ_G_S430 CORE_VSFR_G33 +V1P24A_R_SOC
BJ52 AC36

i
+VCCPADCF1SI0_1P8_3P3 AY10 DDR_VDDQ_G_S431 CORE_VSFR_G31_AC36 +V1P24A_R_SOC
C350 AY44 DDR_VDDQ_G_S414 C401 C402
AV44 DDR_VDDQ_G_S415 M41 +V1P24A_R_SOC
1U/10V_4 DDR_VDDQ_G_S413 USBHSIC_V1P2A_G3 1U/10V_4 1U/10V_4
AV10 U35 C325

f
DDR_VDDQ_G_S410 USB_VDDQ_G32
PLACE THESE CAPS C149 BE51
DDR_VDDQ_G_S418 USB_VDDQ_G33
V35 C349 1U/10V_4
1U/10V_4 AV38 H44
CLOSE TO G1

USB
AV16 DDR_VDDQ_G_S412 USB_VDDQ_G31 P41 USBHNSSIC_V1P24A_M41_P41 1U/10V_4
AU36 DDR_VDDQ_G_S411 USBSSIC_V1P2A_G3
AU18 DDR_VDDQ_G_S49 AA29
+VCCCFIOAZA_1P80 AN36 DDR_VDDQ_G_S48 USB_V1P8A_G3
C C

n
AN35 DDR_VDDQ_G_S47 C23 +VCCUSB2_3P3
AN19 DDR_VDDQ_G_S46 USB_V3P3A_G32 B22 +V1P8A_R_SOC
AN18 DDR_VDDQ_G_S45 USB_V3P3A_G31
PLACE THESE CAPS DDR_VDDQ_G_S44 +VCCRTC_3P3
C309 AM36 C5
CLOSE TO AH4 AND AF4 1U/10V_4 AM18 DDR_VDDQ_G_S43 RTC_V3P3RTC_G52 B6 C156
DDR_VDDQ_G_S41 RTC_V3P3RTC_G51 D4 +VCCRTCSUS_3P3 C143 C328

o
RTC_V3P3A_G51 1U/10V_4
E1 E3 C160

RTC
SDIO_V3P3A_V1P8A_G31 RTC_V3P3A_G52 1U/10V_4 1U/10V_4
E2 1U/10V_4
G1 SDIO_V3P3A_V1P8A_G32 +V1P8A_R_SOC
AH4 SDIO_V3P3A_V1P8A_G33 U16 C155
+V1P8A_R_SOC AF4 VCCCFIOAZA_1P802 FUSE_V1P8A_G3 H10 +V1P05A_R_SOC
VCCCFIOAZA_1P801 FUSE1_V1P05A_G4 1U/10V_4
Y18 G10
AD33 GPIO_V1P8A_G35 FUSE0_V1P05A_G3 A3

FUSE
RSVD_VSS_A3
+V1P8A_R_SOC AK18 GPIO_V1P8A_G31 RSVD_VSS K20

C
C334 C145 AF33 GPIO_V1P8A_G33 RSVD1 M20
AK19 GPIO_V1P8A_G32 RSVD2 R265
1U/10V_4 1U/10V_4 GPIO_V1P8A_G34
C337 C339
10K_4 PLACE THESE CAPS
1U/10V_4 1U/10V_4 CLOSE TO THEIR PINS
PLACE THESE CAPS
PLACE THESE CAPS CLOSE TO AD33, AK18, 9 OF 13
CLOSE TO Y18

a
BSW_MCP_EDS
AF33 AND AK19 REV = 1 ?

t
B B
+VSDIO +VCCPADCF3SI0_1P8_3P3

n
R549 *SHORT_6
+V1P24A
+V3P3A_PRIME SD3 IO SUPPLY
+VCCRTCSUS_3P3 +V1P24A_R_SOC
R300 *SHORT_8

a
R545 *SHORT_6 R299 *SHORT_8
R298 *SHORT_6

C353 +V3P3A_PRIME
0.1U/16V_4 +VCCPADCF1SI0_1P8_3P3

u
PLACE CAPS NEAR SOC R530 *SHORT_6

+VRTC LPC IO SUPPLY

+VCCRTC_3P3

R282 *SHORT_6

Q
C157
0.1U/16V_4 +V1P8A +VCCCFIOAZA_1P80
+V1P8A_R_SOC +V1P05A_R_SOC
R487 *SHORT_6

AUDIO IO SUPPLY
C346 C174
A 1U/10V_4 1U/10V_4 A
+V1P8A R518 *SHORT_6
+V1P8A_R_SOC
R509 *SHORT_6
PLACE THIS CAP PLACE THIS CAP
R505 *SHORT_6
CLOSE TO U16 CLOSE TO G10 & H10 +V3P3A_PRIME +VCCUSB2_3P3

R283 *SHORT_6
Quanta Computer Inc.
PROJECT : ZHR
Size Document Number Rev
1A
BSW 9/10 (Power 2)
Date: Monday, September 14, 2015 Sheet 14 of 47
5 4 3 2 1
 5 4 3 2 1

l
SoC (CPU)
BRASWELL - GND
15

ia
?
U10K BSW_MCP_EDS ?
U10L BSW_MCP_EDS
D D

t
Power-VSS Power-VSS
?
U10J BSW_MCP_EDS
Power-VSS AN21 AY9 AN33 Y24
BG30 VSS5 VSS61 AY28 P32 VSS2 VSS102 G30
AN3 AF38 BG27 VSS101 VSS52 AY26 P27 VSS99 VSS53 G28
AN29 VSS98 VSS51 AF32 BG24 VSS100 VSS51 AY24 P22 VSS98 VSS52 G26 ?
U10MBSW_MCP_EDS

n
AN25 VSS97 VSS50 AF25 BG20 VSS99 VSS50 AY22 P19 VSS97 VSS51 G22 Power-VSS
AN24 VSS96 VSS49 AF10 BG19 VSS98 VSS49 AY20 AF24 VSS96 VSS50 G14 F1 W1
AN16 VSS95 VSS48 AE9 BG18 VSS97 VSS48 AW35 N53 VSS1 VSS49 G12 C1 VSS_NCTF18 VSS57 V44
AN14 VSS94 VSS47 AE8 BG16 VSS96 VSS47 AW27 N51 VSS95 VSS48 F5 BH53 VSS_NCTF17 VSS56 V42
AN12 VSS93 VSS46 AE6 BG14 VSS95 VSS46 AW19 N32 VSS94 VSS47 F35 BH52 VSS_NCTF16 VSS55 V41

e
AN11 VSS92 VSS45 AE53 BF42 VSS94 VSS45 AM13 N24 VSS93 VSS46 F32 BH2 VSS15 VSS54 V38
AN1 VSS91 VSS44 AE50 BF32 VSS93 VSS4 AK29 N22 VSS92 VSS45 F27 BH1 VSS_NCTF14 VSS53
AM50 VSS90 VSS43 AE48 BF28 VSS92 VSS3 AK22 M9 VSS91 VSS44 F24 BG53 VSS_NCTF13 V32
AM42 VSS89 VSS42 AE46 BF27 VSS91 VSS2 AV40 VSS90 VSS43 F19 BG1 VSS_NCTF12 VSS52 V21
AM4 VSS88 VSS41 AE45 BF26 VSS90 VSS44 AV35 K45 VSS42 E51 B52 VSS_NCTF10 VSS51 V16

d
AM38 VSS87 VSS40 AE43 BF22 VSS89 VSS43 AV30 M40 VSS77 VSS41 E35 B2 VSS_NCTF5 VSS50 U9
AM35 VSS86 VSS39 AE42 BF12 VSS88 VSS42 AV27 M35 VSS87 VSS39 E19 VSS_NCTF4 VSS49 U8
AH44 VSS85 VSS38 AE40 BE35 VSS87 VSS41 AV24 M27 VSS86 VSS38 D42 A6 VSS48 U6

i
AM30 VSS60 VSS37 AE14 BE19 VSS86 VSS40 AV19 AW13 VSS85 VSS37 D40 A5 VSS_NCTF2 VSS47 U53
AM27 VSS84 VSS36 AE12 C20 VSS85 VSS39 AV14 M19 VSS3 VSS36 D38 VSS_NCTF1 VSS46 U5
U25 VSS83 VSS35 AE11 BD53 VSS103 VSS38 AJ18 M14 VSS84 VSS35 D32 M24 VSS45 U49
P10 VSS100 VSS34 AE1 BG7 VSS84 VSS1 AU53 L35 VSS83 VSS34 D27 A7 VSSA VSS44 U48

f
AM16 VSS99 VSS33 AD44 BD35 VSS102 VSS37 AU51 L27 VSS82 VSS33 D24 BF50 VSS3 VSS43 U46
C VSS81 VSS32 VSS83 VSS36 VSS81 VSS32 VSS9 VSS42 C
AD4 AD36 BD27 AU3 L19 D16 BF4 U45
AK7 VSS31 VSS30 AC29 BD19 VSS82 VSS35 AU1 L1 VSS80 VSS31 D10 BB50 VSS8 VSS41 U43
AK50 VSS80 VSS23 AD32 BD1 VSS81 VSS34 AT9 K50 VSS79 VSS30 J42 VSS7 VSS40 U42
AK47 VSS79 VSS29 AD30 BC44 VSS80 VSS33 AT51 T47 VSS78 VSS65 C47 BB4 VSS39 U40

n
AK45 VSS78 VSS28 AD21 BC40 VSS79 VSS32 AT45 K4 VSS100 VSS29 C39 VSS6 VSS38 U38
AK44 VSS77 VSS27 AC38 BC38 VSS78 VSS31 AT36 K36 VSS76 VSS28 C36 BG47 VSS37
AK40 VSS76 VSS26 AC35 BC28 VSS77 VSS30 AT35 K34 VSS75 VSS27 C30 Y9 VSS11 U33
AK4 VSS75 VSS25 AC33 BC26 VSS76 VSS29 AT3 K32 VSS74 VSS26 C3 Y50 VSS70 VSS35 U32
AK38 VSS74 VSS24 AC16 BC16 VSS75 VSS28 AT27 K30 VSS73 VSS25 C28 Y45 VSS69 VSS34 U30
VSS73 VSS22 VSS74 VSS27 VSS72 VSS24 VSS68 VSS33

o
AK32 AB6 BC14 AT19 K24 C22 Y40 U29
AK27 VSS72 VSS21 AB50 BC10 VSS73 VSS26 AT18 K22 VSS71 VSS23 AW41 Y4 VSS67 VSS32
AK25 VSS71 VSS20 AB47 BB35 VSS72 VSS25 AP9 K16 VSS70 VSS4 BJ7 Y38 VSS66 U21
AM24 VSS70 VSS19 AB42 BB27 VSS71 VSS24 AP50 K14 VSS69 VSS22 BJ47 Y29 VSS65 VSS31 U18
AK16 VSS82 VSS18 AB4 BB19 VSS70 VSS23 AP45 K12 VSS68 VSS21 BJ43 Y22 VSS64 VSS30 U36
AJ53 VSS69 VSS17 AB14 BA35 VSS69 VSS22 AP4 J53 VSS67 VSS20 BJ39 Y21 VSS63 VSS36 U14
AJ51 VSS68 VSS16 AB13 BA30 VSS68 VSS21 AN9 M45 VSS66 VSS19 BJ35 Y19 VSS62 VSS29 U12
VSS67 VSS15 VSS67 VSS20 VSS88 VSS18 VSS61 VSS28

C
AJ3 AB12 BA27 AN8 J38 BJ31 Y16 U11
AJ25 VSS66 VSS14 AB10 BA24 VSS66 VSS19 AN6 J35 VSS64 VSS17 BJ27 Y14 VSS60 VSS27 T9
AJ16 VSS65 VSS13 AA53 BA19 VSS65 VSS18 AN53 J30 VSS63 VSS16 BJ23 Y10 VSS59 VSS26 P42
AJ1 VSS64 VSS12 AA38 B36 VSS64 VSS17 AN51 J27 VSS62 VSS15 BJ19 VSS58 VSS23 T14
AH9 VSS63 VSS11 AA27 B28 VSS63 VSS16 AN5 J22 VSS61 VSS14 BJ15 P4 VSS25 R1
AH47 VSS62 VSS10 AA16 AY7 VSS62 VSS15 AN49 J19 VSS60 VSS13 BJ11 L41 VSS22 VSS24
AH42 VSS61 VSS9 A47 AY51 VSS60 VSS14 AN48 J18 VSS59 VSS12 BG5 P36 VSS19 P35
AH41 VSS59 VSS8 A43 AY47 VSS59 VSS13 AN46 H8 VSS58 VSS11 BG49 VSS21 VSS20

a
B 13 OF 13 B
AH14 VSS58 VSS7 A39 AY34 VSS58 VSS12 AN45 E46 VSS57 VSS10 BG40
VSS57 VSS6 VSS56 VSS11 VSS40 VSS9 BSW_MCP_EDS
AH13 A31 AY32 AN43 H35 BG38 REV = 1 ?
AH12 VSS56 VSS5 A23 AY30 VSS55 VSS10 AN42 H27 VSS56 VSS8 BG36

t
AH10 VSS55 VSS4 A19 AY3 VSS54 VSS9 AN40 H19 VSS55 VSS7 BG35
AG25 VSS54 VSS3 A15 AN30 VSS53 VSS8 AN38 M50 VSS54 VSS6 BG34
AF47 VSS53 VSS2 A11 AY45 VSS6 VSS7 V25 VSS89 VSS5
VSS52 VSS1 VSS57 VSS101
10 OF 13

n
BSW_MCP_EDS 11 OF 13 12 OF 13
REV = 1 ?
BSW_MCP_EDS BSW_MCP_EDS
REV = 1 ? REV = 1 ?

ua A

Q
Quanta Computer Inc.
PROJECT : ZHR
Size Document Number Rev
1A
BSW 10/10 (GND)
Date: Monday, September 14, 2015 Sheet 15 of 47
5 4 3 2 1
 5 4 3 2 1

l
60 PIN XDP CN8

31 1 GND GND 2 30
16

a
32 31 3 OBSFN_A0 OBSFN_C0 4 30 29
(12) XDP_H_PREQ_N 33 32 5 OBSFN_A1 OBSFN_C1 6 29 28 OBSFN_C0 (8,23)
XDP (DBG) (12) XDP_H_PRDY_N 33 7 GND GND 8 28
34 27

i
35 34 9 OBSDATA_A_0 OBSDATA_C_0 10 27 26
(10) XDP_GPIO_DFX0 35 26 OBSDATA_C0 (8)
36 11 OBSDATA_A_1 OBSDATA_C_1 12 25
D (10) XDP_GPIO_DFX1 36 25 OBSDATA_C1 (8) D
37 13 GND GND 14 24

t
38 37 15 OBSDATA_A_2 OBSDATA_C_2 16 24 23
(10) XDP_GPIO_DFX2 38 23 OBSDATA_C2 (8)
39 17 OBSDATA_A_3 OBSDATA_C_3 18 22
(10) XDP_GPIO_DFX3 39 22 OBSDATA_C3 (8)
40 19 GND GND 20 21
41 40 21 OBSFN_B0 OBSFN_D_0 22 21 20
(10) XDP_GPIO_DFX8 41 23 OBSFN_B1 OBSFN_D_1 24 20
42 19

n
43 42 25 GND GND 26 19 18
44 43 27 OBSDATA_B_0 OBSDATA_D_0 28 18 17
(10) XDP_GPIO_DFX4 44 17 OBSDATA_D0 (8)
45 29 OBSDATA_B_1 OBSDATA_D_1 30 16
(10) XDP_GPIO_DFX5 45 16 OBSDATA_D1 (8)
46 31 GND GND 32 15
47 46 33 OBSDATA_B_2 OBSDATA_D_2 34 15 14

e
(10) XDP_GPIO_DFX6 47 14 OBSDATA_D2 (8)
(10) XDP_GPIO_DFX7 48 35 OBSDATA_B_3 OBSDATA_D_3 36 13
48 13 OBSDATA_D3 (8)
49 37 GND GND 38 12
R29 *1K_4 XDP_RSMRST# 50 49 39 HOOK0 ITPCLK/HOOK4 40 12 11
(12,34) SOC_RSMRST# 50 11
R25 *Short_4XDP_PMU_PWRBTN# 51 41 HOOK1 ITPCLK#/HOOK5 42 10
(30,34) PCH_PWRBTN_L 51 43 VCC_OBS_AB VCC_OBS_CD 44 10
+VPP1800_XDP_AB 52 9 +VPP1800_XDP_CD

d
R37 *10K_4 XDP_COREPWROK 53 52 45 HOOK2 RESET#/HOOK6 46 9 8 XDP_PMU_PLTRST# R34 *1K_4
(12,30,31) CORE_PWROK_R 53 8 SOC_PLTRST# (12,19,34)
R459 *1K_4 XDP_RTEST# 54 47 HOOK3 DBR#/HOOK7 48 7 XDP_PMU_RSTBTN# R48 *Short_4
(10,23) SOC_RUNTIME_SCI 54 49 GND GND 50 7 SOC_REST_BTN# (12,21,34)
C27 55 6

i
SMB_XDP_SDA 56 55 51 SDA TDO 52 6 5
*0.1U/10V_4 56 5 XDP_H_TDO (12)
SMB_XDP_SCL 57 53 SCL TRSTn 54 4
(35) SMB_XDP_SDA 57 4 XDP_H_TRST# (12)
R380 **0_4 58 55 TCK1 TDI 56 3 C24
(10,35) SMB_SOC_DATA 58 3 XDP_H_TDI (12)
R379 **0_4 XDP_H_TCK 59 57 TCK0 TMS 58 2 *0.1U/10V_4

f
(10,35) SMB_SOC_CLK 59 2 XDP_H_TMS (12)
60 59 GND GND_XDP_PRESENT 60 1 XDP_PRESENT_N R54 *Short_4
C (35) SMB_XDP_SCL 60 1 C

*SEC_BSH-030-01-L-D-A-TR
(12) XDP_H_TCK

n
+V1P8A R10 *0_6 +VPP1800_XDP_AB
+V1P8S R28 *0_4 +VPP1800_XDP_CD

o
0818 unstuffed related RC components of ITP header

APS

C
PULL-UPS AND DOWNS FOR XDP SIGNALS
+VPP1800_XDP_AB
+V1P8A

a
B B

+V3P3A PLACE 'RA' RESISTOR WITHIN 0.25" FROM XDP PIN

RA

t
C2 0.1U/16V_4
XDP_H_TDO R431 *51/F_4

PLACE THIS CAP CLOSE TO LAYER TRANSITION OF

RE R50
RB XDP_H_TCK SIGNAL TRANSITION

n
2.2K_4 PLACE' RB','RC' RESISTORS WITHIN 1" FROM SoC PIN
XDP_H_TMS R191 *51/F_4
XDP_H_TDI R190 *51/F_4

XDP_PMU_PWRBTN# RC

a
+V1P8A +V1P8A

RD CA
C9 XDP_H_PREQ_N R179 *51/F_4 C271 0.1U/16V_4 XDP_RTEST#R466 *4.7K_4

u
0.1U/16V_4
PLACE 'RD' RESISTOR WITHIN 1" FROM SoC PIN PLACE 'CA' capacitor closed to PIN 47

XDP_H_TCK R99 *51/F_4

+V1P8A
A
XDP_H_TRST# R46 *51/F_4 RF A

C30 0.1U/16V_4 XDP_PMU_RSTBTN#R38 **1K_4

Q
Quanta Computer Inc.
PROJECT : ZHR
Size Document Number Rev
1A
XDP
Date: Monday, September 14, 2015 Sheet 16 of 47
5 4 3 2 1
 1 2 3 4 5 6 7 8

On board memory(OBM)
DDR3L MEMORY CHANNEL A
17

l
BYTE3_0-7
BYTE0_8-15 BYTE4_32-39 BYTE5_40-47
BYTE0_16-23
U2 U24 BYTE3_24-31 U3 BYTE6_48-55 U25 BYTE7_56-63
M8 E3 M8 E3 +V_SMDDR_VREF_DIMMM8 E3 +V_SMDDR_VREF_DIMMM8 E3

a
+V_SMDDR_VREF_DIMM M_A_DQ3 +V_SMDDR_VREF_DIMM M_A_DQ9 M_A_DQ50 M_A_DQ45
VREFCA DQL0 M_A_DQ3 (6) VREFCA DQL0 M_A_DQ9 (6) VREFCA DQL0 M_A_DQ50 (6) VREFCA DQL0 M_A_DQ45 (6)
+V_SMDDR_VREF_DQ0 H1 F7 M_A_DQ1 +V_SMDDR_VREF_DQ0 H1 F7 M_A_DQ14 +V_SMDDR_VREF_DQ0 H1 F7 M_A_DQ52 +V_SMDDR_VREF_DQ0 H1 F7 M_A_DQ42
VREFDQ DQL1 M_A_DQ1 (6) VREFDQ DQL1 M_A_DQ14 (6) VREFDQ DQL1 M_A_DQ52 (6) VREFDQ DQL1 M_A_DQ42 (6)
F2 M_A_DQ2 F2 M_A_DQ13 F2 M_A_DQ51 F2 M_A_DQ40
(6) M_A_A[15:0] DQL2 M_A_DQ2 (6) DQL2 M_A_DQ13 (6) DQL2 M_A_DQ51 (6) DQL2 M_A_DQ40 (6)
M_A_A0 N3 F8 M_A_DQ4 M_A_A0 N3 F8 M_A_DQ10 M_A_A0 N3 F8 M_A_DQ53 M_A_A0 N3 F8 M_A_DQ46
A0 DQL3 M_A_DQ4 (6) A0 DQL3 M_A_DQ10 (6) A0 DQL3 M_A_DQ53 (6) A0 DQL3 M_A_DQ46 (6)
M_A_A1 P7 H3 M_A_DQ6 M_A_A1 P7 H3 M_A_DQ8 M_A_A1 P7 H3 M_A_DQ54 M_A_A1 P7 H3 M_A_DQ41
M_A_DQ6 (6) M_A_DQ8 (6) M_A_DQ54 (6) M_A_DQ41 (6)

i
M_A_A2 P3 A1 DQL4 H8 M_A_DQ5 M_A_A2 P3 A1 DQL4 H8 M_A_DQ15 M_A_A2 P3 A1 DQL4 H8 M_A_DQ49 M_A_A2 P3 A1 DQL4 H8 M_A_DQ47
A2 DQL5 M_A_DQ5 (6) A2 DQL5 M_A_DQ15 (6) A2 DQL5 M_A_DQ49 (6) A2 DQL5 M_A_DQ47 (6)
M_A_A3 N2 G2 M_A_DQ7 M_A_A3 N2 G2 M_A_DQ12 M_A_A3 N2 G2 M_A_DQ55 M_A_A3 N2 G2 M_A_DQ44
A3 DQL6 M_A_DQ7 (6) A3 DQL6 M_A_DQ12 (6) A3 DQL6 M_A_DQ55 (6) A3 DQL6 M_A_DQ44 (6)
M_A_A4 P8 H7 M_A_DQ0 M_A_A4 P8 H7 M_A_DQ11 M_A_A4 P8 H7 M_A_DQ48 M_A_A4 P8 H7 M_A_DQ43
A4 DQL7 M_A_DQ0 (6) A4 DQL7 M_A_DQ11 (6) A4 DQL7 M_A_DQ48 (6) A4 DQL7 M_A_DQ43 (6)
M_A_A5 P2 M_A_A5 P2 M_A_A5 P2 M_A_A5 P2
M_A_A6 R8 A5 M_A_A6 R8 A5 M_A_A6 R8 A5 M_A_A6 R8 A5

t
A A
M_A_A7 R2 A6 D7 M_A_DQ19 M_A_A7 R2 A6 D7 M_A_DQ24 M_A_A7 R2 A6 D7 M_A_DQ33 M_A_A7 R2 A6 D7 M_A_DQ61
A7 DQU0 M_A_DQ19 (6) A7 DQU0 M_A_DQ24 (6) A7 DQU0 M_A_DQ33 (6) A7 DQU0 M_A_DQ61 (6)
M_A_A8 T8 C3 M_A_DQ21 M_A_A8 T8 C3 M_A_DQ30 M_A_A8 T8 C3 M_A_DQ39 M_A_A8 T8 C3 M_A_DQ59
A8 DQU1 M_A_DQ21 (6) A8 DQU1 M_A_DQ30 (6) A8 DQU1 M_A_DQ39 (6) A8 DQU1 M_A_DQ59 (6)
M_A_A9 R3 C8 M_A_DQ16 M_A_A9 R3 C8 M_A_DQ26 M_A_A9 R3 C8 M_A_DQ36 M_A_A9 R3 C8 M_A_DQ60
A9 DQU2 M_A_DQ16 (6) A9 DQU2 M_A_DQ26 (6) A9 DQU2 M_A_DQ36 (6) A9 DQU2 M_A_DQ60 (6)
M_A_A10 L7 C2 M_A_DQ18 M_A_A10 L7 C2 M_A_DQ28 M_A_A10 L7 C2 M_A_DQ34 M_A_A10 L7 C2 M_A_DQ63
A10/AP DQU3 M_A_DQ18 (6) A10/AP DQU3 M_A_DQ28 (6) A10/AP DQU3 M_A_DQ34 (6) A10/AP DQU3 M_A_DQ63 (6)
M_A_A11 R7 A7 M_A_DQ17 M_A_A11 R7 A7 M_A_DQ31 M_A_A11 R7 A7 M_A_DQ37 M_A_A11 R7 A7 M_A_DQ57
A11 DQU4 M_A_DQ17 (6) A11 DQU4 M_A_DQ31 (6) A11 DQU4 M_A_DQ37 (6) A11 DQU4 M_A_DQ57 (6)
M_A_A12 N7 A2 M_A_DQ23 M_A_A12 N7 A2 M_A_DQ25 M_A_A12 N7 A2 M_A_DQ38 M_A_A12 N7 A2 M_A_DQ58
A12/BC DQU5 M_A_DQ23 (6) A12/BC DQU5 M_A_DQ25 (6) A12/BC DQU5 M_A_DQ38 (6) A12/BC DQU5 M_A_DQ58 (6)
M_A_A13 T3 B8 M_A_DQ22 M_A_A13 T3 B8 M_A_DQ29 M_A_A13 T3 B8 M_A_DQ32 M_A_A13 T3 B8 M_A_DQ62
A13 DQU6 M_A_DQ22 (6) A13 DQU6 M_A_DQ29 (6) A13 DQU6 M_A_DQ32 (6) A13 DQU6 M_A_DQ62 (6)
M_A_A14 T7 A3 M_A_DQ20 M_A_A14 T7 A3 M_A_DQ27 M_A_A14 T7 A3 M_A_DQ35 M_A_A14 T7 A3 M_A_DQ56

n
A14 DQU7 M_A_DQ20 (6) A14 DQU7 M_A_DQ27 (6) A14 DQU7 M_A_DQ35 (6) A14 DQU7 M_A_DQ56 (6)
M_A_A15 M7 M_A_A15 M7 M_A_A15 M7 M_A_A15 M7
A15 +VDDQ_M0_M1_R A15 +VDDQ_M0_M1_R A15 +VDDQ_M0_M1_R A15 +VDDQ_M0_M1_R
(6) M_A_BS[2:0]
M_A_BS0 M2 B2 M_A_BS0 M2 B2 M_A_BS0 M2 B2 M_A_BS0 M2 B2
M_A_BS1 N8 BA0 VDD#B2 D9 M_A_BS1 N8 BA0 VDD#B2 D9 M_A_BS1 N8 BA0 VDD#B2 D9 M_A_BS1 N8 BA0 VDD#B2 D9
M_A_BS2 M3 BA1 VDD#D9 G7 M_A_BS2 M3 BA1 VDD#D9 G7 M_A_BS2 M3 BA1 VDD#D9 G7 M_A_BS2 M3 BA1 VDD#D9 G7
BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2

e
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
M_A_CLKP0 J7 VDD#N1 N9 M_A_CLKP0 J7 VDD#N1 N9 M_A_CLKP0 J7 VDD#N1 N9 M_A_CLKP0 J7 VDD#N1 N9
(6) M_A_CLKP0 M_A_CLKN0 K7 CK VDD#N9 R1 M_A_CLKN0 K7 CK VDD#N9 R1 M_A_CLKN0 K7 CK VDD#N9 R1 M_A_CLKN0 K7 CK VDD#N9 R1
(6) M_A_CLKN0 M_A_CKE0 K9 CK VDD#R1 R9 M_A_CKE0 K9 CK VDD#R1 R9 M_A_CKE0 K9 CK VDD#R1 R9 M_A_CKE0 K9 CK VDD#R1 R9
(6) M_A_CKE0 CKE VDD#R9 CKE VDD#R9 CKE VDD#R9 CKE VDD#R9

M_A_ODT0 K1 A1 M_A_ODT0 K1 A1 M_A_ODT0 K1 A1 M_A_ODT0 K1 A1

d
(6) M_A_ODT0 M_A_CS#0 L2 ODT VDDQ#A1 A8 M_A_CS#0 L2 ODT VDDQ#A1 A8 M_A_CS#0 L2 ODT VDDQ#A1 A8 M_A_CS#0 L2 ODT VDDQ#A1 A8
(6) M_A_CS#0 M_A_RAS# J3 CS VDDQ#A8 C1 M_A_RAS# J3 CS VDDQ#A8 C1 M_A_RAS# J3 CS VDDQ#A8 C1 M_A_RAS# J3 CS VDDQ#A8 C1
(6) M_A_RAS# M_A_CAS# K3 RAS VDDQ#C1 C9 M_A_CAS# K3 RAS VDDQ#C1 C9 M_A_CAS# K3 RAS VDDQ#C1 C9 M_A_CAS# K3 RAS VDDQ#C1 C9
(6) M_A_CAS# M_A_WE# L3 CAS VDDQ#C9 D2 M_A_WE# L3 CAS VDDQ#C9 D2 M_A_WE# L3 CAS VDDQ#C9 D2 M_A_WE# L3 CAS VDDQ#C9 D2
(6) M_A_WE# WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9

i
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
M_A_DQSP0 F3 VDDQ#F1 H2 M_A_DQSP1 F3 VDDQ#F1 H2 M_A_DQSP6 F3 VDDQ#F1 H2 M_A_DQSP5 F3 VDDQ#F1 H2
(6) M_A_DQSP0 M_A_DQSP2 C7 DQSL VDDQ#H2 H9 (6) M_A_DQSP1 M_A_DQSP3 C7 DQSL VDDQ#H2 H9 (6) M_A_DQSP6 M_A_DQSP4 C7 DQSL VDDQ#H2 H9 (6) M_A_DQSP5 M_A_DQSP7 C7 DQSL VDDQ#H2 H9
(6) M_A_DQSP2 DQSU VDDQ#H9 (6) M_A_DQSP3 DQSU VDDQ#H9 (6) M_A_DQSP4 DQSU VDDQ#H9 (6) M_A_DQSP7 DQSU VDDQ#H9

f
M_A_DM0 E7 A9 M_A_DM1 E7 A9 M_A_DM6 E7 A9 M_A_DM5 E7 A9
(6) M_A_DM0 M_A_DM2 D3 DML VSS#A9 B3 (6) M_A_DM1 M_A_DM3 D3 DML VSS#A9 B3 (6) M_A_DM6 M_A_DM4 D3 DML VSS#A9 B3 (6) M_A_DM5 M_A_DM7 D3 DML VSS#A9 B3
(6) M_A_DM2 DMU VSS#B3 E1 (6) M_A_DM3 DMU VSS#B3 E1 (6) M_A_DM4 DMU VSS#B3 E1 (6) M_A_DM7 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
M_A_DQSN0 G3 VSS#G8 J2 M_A_DQSN1 G3 VSS#G8 J2 M_A_DQSN6 G3 VSS#G8 J2 M_A_DQSN5 G3 VSS#G8 J2
B B
(6) M_A_DQSN0 M_A_DQSN2 B7 DQSL VSS#J2 J8 (6) M_A_DQSN1 M_A_DQSN3 B7 DQSL VSS#J2 J8 (6) M_A_DQSN6 M_A_DQSN4 B7 DQSL VSS#J2 J8 (6) M_A_DQSN5 M_A_DQSN7 B7 DQSL VSS#J2 J8
(6) M_A_DQSN2 DQSU VSS#J8 M1 (6) M_A_DQSN3 DQSU VSS#J8 M1 (6) M_A_DQSN4 DQSU VSS#J8 M1 (6) M_A_DQSN7 DQSU VSS#J8 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9

n
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
M_A_DRAMRST# T2 VSS#P1 P9 M_A_DRAMRST# T2 VSS#P1 P9 M_A_DRAMRST# T2 VSS#P1 P9 M_A_DRAMRST# T2 VSS#P1 P9
(6) M_A_DRAMRST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
M_A_ZQ1 L8 VSS#T1 T9 M_A_ZQ2 L8 VSS#T1 T9 M_A_ZQ3 L8 VSS#T1 T9 M_A_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9

B1 B1 B1 B1
VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9
VSSQ#B9 VSSQ#B9 VSSQ#B9 VSSQ#B9

o
R62 D1 R396 D1 R47 D1 R415 D1
VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8
240/F_4 VSSQ#D8 E2 240/F_4 VSSQ#D8 E2 240/F_4 VSSQ#D8 E2 240/F_4 VSSQ#D8 E2
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
RAM _DDR3L RAM _DDR3L RAM _DDR3L RAM _DDR3L

C
DE-CAPS FOR MEMORY CHANNEL A VTT TERMINATIONS VOLTAGE MERGE

a
+VDDQ_VTT_M0_M1_R

+VDDQ_M0_M1_R
CAD note: Distributed around all DRAM devices (CHA) M_A_RAS# R76 80.6/F_4

t
C C
M_A_CAS# R89 80.6/F_4
M_A_WE# R420 80.6/F_4 +VDDQ_VTT +VDDQ_VTT_M0_M1_R
M_A_BS0 R418 80.6/F_4
C18 C77 C217 C21 C252 C216 M_A_BS1 R412 80.6/F_4 R382 *SHORT_6
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 M_A_BS2 R40 80.6/F_4
+V_SMDDR_VREF_DIMM PLACE 2 CAPS NEAR EACH DDR3L IC M_A_CKE0 R59 80.6/F_4
M_A_CS#0 R63 80.6/F_4
M_A_A0 R45 80.6/F_4

VREF_CA AND DQ CIRCUITS

n
M_A_A1 R409 80.6/F_4
M_A_A2 R41 80.6/F_4
C37 C227 C230 C228 M_A_A3 R400 80.6/F_4
CAD NOTE: Place these Caps near each X16 Memory Down 0.047U/10V_4 0.047U/10V_4 0.047U/10V_4 0.047U/10V_4 M_A_A4 R405 80.6/F_4
M_A_A5 R35 80.6/F_4 +VDDQ_M0_M1_R
M_A_A6 R391 80.6/F_4 +VDDQ_M0_M1_R
M_A_A7 R385 80.6/F_4

a
C16 C20 C43 C64 C82 C69 C91 C215 M_A_A8 R384 80.6/F_4
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 +V_SMDDR_VREF_DQ0 M_A_A9 R30 80.6/F_4 Vref_DQ
M_A_A10 R72 80.6/F_4 Vref_CA R75
M_A_A11 R27 80.6/F_4 R67 4.7K/F_4 +V_SMDDR_VREF_DQ0
M_A_A12 R57 80.6/F_4 4.7K/F_4 +V_SMDDR_VREF_DIMM PLACE 'CA' CAPACITOR
M_A_A13 R393 80.6/F_4 AT GENERATION POINT
C62 C51 C233 C235 M_A_A14 R397 80.6/F_4

2
0.047U/10V_4 0.047U/10V_4 0.047U/10V_4 0.047U/10V_4 M_A_A15 R71 80.6/F_4

2
u
C221
1U/6.3V_4
C214
1U/6.3V_4
C85
1U/6.3V_4
C237
1U/6.3V_4
C245
1U/6.3V_4
C259
1U/6.3V_4
C42
1U/6.3V_4 C44 R422
C232
CA
0.1U/16V_4

1
R56 0.1U/16V_4 4.7K/F_4

1
+VDDQ_VTT_M0_M1_R 4.7K/F_4
Place these Caps near Memory Down CA & DQ pin
M_A_ODT0 R81 80.6/F_4

C74 C223 C239 C244 C58 C10

1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4

+VDDQ_M0_M1_R

Q
+VDDQ_VTT_M0_M1_R

D D
C234 C92 C68 C5
0.1U/10V_4 *1U/6.3V_4 *1U/6.3V_4 *1U/6.3V_4
+VDDQ_VTT_M0_M1_R

M_A_CLKP0 R433 80.6/F_4 M_A_CLKP0_N0_C

M_A_CLKN0 R432 80.6/F_4

C26 C13 C48 C205 C208 C210 C209 C202 C200

1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 10U/6.3V_6

Quanta Computer Inc.

M_A_CLKP0 M_A_CLKN0
C238 0.2P/50V_4
PROJECT :ZHR
Size Document Number Rev
DDR3L MEMORY DOWNx16 CHA 1A

Date: Monday, September 14, 2015 Sheet 17 of 47

1 2 3 4 5 6 7 8
 5 4 3 2 1

On board memory(OBM)
DDR3L MEMORY CHANNEL B
18

l
BYTE2_16-23 BYTE0_8-15
BYTE6_48-55 BYTE5_40-47
BYTE3_24-31 BYTE1_0-7
+V_SMDDR_VREF_DIMM BYTE4_32-39 BYTE7_56-63

a
U27 U5 U4 U26

+V_SMDDR_VREF_DIMM M8 E3 M_B_DQ20 +V_SMDDR_VREF_DIMMM8 E3 M_B_DQ15 +V_SMDDR_VREF_DIMMM8 E3 M_B_DQ52 +V_SMDDR_VREF_DIMMM8 E3 M_B_DQ42

VREFCA DQL0 M_B_DQ20 (7) VREFCA DQL0 M_B_DQ15 (7) VREFCA DQL0 M_B_DQ52 (7) VREFCA DQL0 M_B_DQ42 (7)
+V_SMDDR_VREF_DQ1 H1 F7 M_B_DQ16 +V_SMDDR_VREF_DQ1 H1 F7 M_B_DQ8 +V_SMDDR_VREF_DQ1 H1 F7 M_B_DQ54 +V_SMDDR_VREF_DQ1 H1 F7 M_B_DQ44
VREFDQ DQL1 M_B_DQ16 (7) VREFDQ DQL1 M_B_DQ8 (7) VREFDQ DQL1 M_B_DQ54 (7) VREFDQ DQL1 M_B_DQ44 (7)
F2 M_B_DQ21 F2 M_B_DQ10 F2 M_B_DQ53 F2 M_B_DQ46
(7) M_B_A[15:0] M_B_DQ21 (7) M_B_DQ10 (7) M_B_DQ53 (7) M_B_DQ46 (7)

i
M_B_A0 N3 DQL2 F8 M_B_DQ19 M_B_A0 N3 DQL2 F8 M_B_DQ14 M_B_A0 N3 DQL2 F8 M_B_DQ50 M_B_A0 N3 DQL2 F8 M_B_DQ45
A0 DQL3 M_B_DQ19 (7) A0 DQL3 M_B_DQ14 (7) A0 DQL3 M_B_DQ50 (7) A0 DQL3 M_B_DQ45 (7)
M_B_A1 P7 H3 M_B_DQ23 M_B_A1 P7 H3 M_B_DQ9 M_B_A1 P7 H3 M_B_DQ48 M_B_A1 P7 H3 M_B_DQ47
A1 DQL4 M_B_DQ23 (7) A1 DQL4 M_B_DQ9 (7) A1 DQL4 M_B_DQ48 (7) A1 DQL4 M_B_DQ47 (7)
M_B_A2 P3 H8 M_B_DQ22 M_B_A2 P3 H8 M_B_DQ12 M_B_A2 P3 H8 M_B_DQ51 M_B_A2 P3 H8 M_B_DQ40
A2 DQL5 M_B_DQ22 (7) A2 DQL5 M_B_DQ12 (7) A2 DQL5 M_B_DQ51 (7) A2 DQL5 M_B_DQ40 (7)
M_B_A3 N2 G2 M_B_DQ18 M_B_A3 N2 G2 M_B_DQ11 M_B_A3 N2 G2 M_B_DQ49 M_B_A3 N2 G2 M_B_DQ43
A3 DQL6 M_B_DQ18 (7) A3 DQL6 M_B_DQ11 (7) A3 DQL6 M_B_DQ49 (7) A3 DQL6 M_B_DQ43 (7)
M_B_A4 P8 H7 M_B_DQ17 M_B_A4 P8 H7 M_B_DQ13 M_B_A4 P8 H7 M_B_DQ55 M_B_A4 P8 H7 M_B_DQ41

t
A4 DQL7 M_B_DQ17 (7) A4 DQL7 M_B_DQ13 (7) A4 DQL7 M_B_DQ55 (7) A4 DQL7 M_B_DQ41 (7)
D M_B_A5 P2 M_B_A5 P2 M_B_A5 P2 M_B_A5 P2 D
M_B_A6 R8 A5 M_B_A6 R8 A5 M_B_A6 R8 A5 M_B_A6 R8 A5
M_B_A7 R2 A6 D7 M_B_DQ30 M_B_A7 R2 A6 D7 M_B_DQ6 M_B_A7 R2 A6 D7 M_B_DQ35 M_B_A7 R2 A6 D7 M_B_DQ56
A7 DQU0 M_B_DQ30 (7) A7 DQU0 M_B_DQ6 (7) A7 DQU0 M_B_DQ35 (7) A7 DQU0 M_B_DQ56 (7)
M_B_A8 T8 C3 M_B_DQ24 M_B_A8 T8 C3 M_B_DQ4 M_B_A8 T8 C3 M_B_DQ37 M_B_A8 T8 C3 M_B_DQ57
A8 DQU1 M_B_DQ24 (7) A8 DQU1 M_B_DQ4 (7) A8 DQU1 M_B_DQ37 (7) A8 DQU1 M_B_DQ57 (7)
M_B_A9 R3 C8 M_B_DQ25 M_B_A9 R3 C8 M_B_DQ2 M_B_A9 R3 C8 M_B_DQ38 M_B_A9 R3 C8 M_B_DQ63
A9 DQU2 M_B_DQ25 (7) A9 DQU2 M_B_DQ2 (7) A9 DQU2 M_B_DQ38 (7) A9 DQU2 M_B_DQ63 (7)
M_B_A10 L7 C2 M_B_DQ31 M_B_A10 L7 C2 M_B_DQ0 M_B_A10 L7 C2 M_B_DQ36 M_B_A10 L7 C2 M_B_DQ60
A10/AP DQU3 M_B_DQ31 (7) A10/AP DQU3 M_B_DQ0 (7) A10/AP DQU3 M_B_DQ36 (7) A10/AP DQU3 M_B_DQ60 (7)
M_B_A11 R7 A7 M_B_DQ28 M_B_A11 R7 A7 M_B_DQ3 M_B_A11 R7 A7 M_B_DQ39 M_B_A11 R7 A7 M_B_DQ59
A11 DQU4 M_B_DQ28 (7) A11 DQU4 M_B_DQ3 (7) A11 DQU4 M_B_DQ39 (7) A11 DQU4 M_B_DQ59 (7)
M_B_A12 N7 A2 M_B_DQ29 M_B_A12 N7 A2 M_B_DQ5 M_B_A12 N7 A2 M_B_DQ33 M_B_A12 N7 A2 M_B_DQ62

n
A12/BC DQU5 M_B_DQ29 (7) A12/BC DQU5 M_B_DQ5 (7) A12/BC DQU5 M_B_DQ33 (7) A12/BC DQU5 M_B_DQ62 (7)
M_B_A13 T3 B8 M_B_DQ27 M_B_A13 T3 B8 M_B_DQ7 M_B_A13 T3 B8 M_B_DQ34 M_B_A13 T3 B8 M_B_DQ58
A13 DQU6 M_B_DQ27 (7) A13 DQU6 M_B_DQ7 (7) A13 DQU6 M_B_DQ34 (7) A13 DQU6 M_B_DQ58 (7)
M_B_A14 T7 A3 M_B_DQ26 M_B_A14 T7 A3 M_B_DQ1 M_B_A14 T7 A3 M_B_DQ32 M_B_A14 T7 A3 M_B_DQ61
A14 DQU7 M_B_DQ26 (7) A14 DQU7 M_B_DQ1 (7) A14 DQU7 M_B_DQ32 (7) A14 DQU7 M_B_DQ61 (7)
M_B_A15 M7 M_B_A15 M7 M_B_A15 M7 M_B_A15 M7
A15 +VDDQ_M0_M1_R A15 +VDDQ_M0_M1_R A15 +VDDQ_M0_M1_R A15 +VDDQ_M0_M1_R
(7) M_B_BS[2:0]
M_B_BS0 M2 B2 M_B_BS0 M2 B2 M_B_BS0 M2 B2 M_B_BS0 M2 B2
M_B_BS1 N8 BA0 VDD#B2 D9 M_B_BS1 N8 BA0 VDD#B2 D9 M_B_BS1 N8 BA0 VDD#B2 D9 M_B_BS1 N8 BA0 VDD#B2 D9

e
M_B_BS2 M3 BA1 VDD#D9 G7 M_B_BS2 M3 BA1 VDD#D9 G7 M_B_BS2 M3 BA1 VDD#D9 G7 M_B_BS2 M3 BA1 VDD#D9 G7
BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
M_B_CLKP0 J7 VDD#N1 N9 M_B_CLKP0 J7 VDD#N1 N9 M_B_CLKP0 J7 VDD#N1 N9 M_B_CLKP0 J7 VDD#N1 N9
(7) M_B_CLKP0 M_B_CLKN0 K7 CK VDD#N9 R1 M_B_CLKN0 K7 CK VDD#N9 R1 M_B_CLKN0 K7 CK VDD#N9 R1 M_B_CLKN0 K7 CK VDD#N9 R1
(7) M_B_CLKN0 M_B_CKE0 K9 CK VDD#R1 R9 M_B_CKE0 K9 CK VDD#R1 R9 M_B_CKE0 K9 CK VDD#R1 R9 M_B_CKE0 K9 CK VDD#R1 R9
(7) M_B_CKE0 CKE VDD#R9 CKE VDD#R9 CKE VDD#R9 CKE VDD#R9

d
M_B_ODT0 K1 A1 M_B_ODT0 K1 A1 M_B_ODT0 K1 A1 M_B_ODT0 K1 A1
(7) M_B_ODT0 M_B_CS#0 L2 ODT VDDQ#A1 A8 M_B_CS#0 L2 ODT VDDQ#A1 A8 M_B_CS#0 L2 ODT VDDQ#A1 A8 M_B_CS#0 L2 ODT VDDQ#A1 A8
(7) M_B_CS#0 M_B_RAS# J3 CS VDDQ#A8 C1 M_B_RAS# J3 CS VDDQ#A8 C1 M_B_RAS# J3 CS VDDQ#A8 C1 M_B_RAS# J3 CS VDDQ#A8 C1
(7) M_B_RAS# K3 RAS VDDQ#C1 C9 K3 RAS VDDQ#C1 C9 K3 RAS VDDQ#C1 C9 K3 RAS VDDQ#C1 C9

i
M_B_CAS# M_B_CAS# M_B_CAS# M_B_CAS#
(7) M_B_CAS# M_B_WE# L3 CAS VDDQ#C9 D2 M_B_WE# L3 CAS VDDQ#C9 D2 M_B_WE# L3 CAS VDDQ#C9 D2 M_B_WE# L3 CAS VDDQ#C9 D2
(7) M_B_WE# WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
M_B_DQSP2 F3 VDDQ#F1 H2 M_B_DQSP1 F3 VDDQ#F1 H2 M_B_DQSP6 F3 VDDQ#F1 H2 M_B_DQSP5 F3 VDDQ#F1 H2
(7) M_B_DQSP2 M_B_DQSP3 C7 DQSL VDDQ#H2 H9 (7) M_B_DQSP1 M_B_DQSP0 C7 DQSL VDDQ#H2 H9 (7) M_B_DQSP6 M_B_DQSP4 C7 DQSL VDDQ#H2 H9 (7) M_B_DQSP5 M_B_DQSP7 C7 DQSL VDDQ#H2 H9

f
(7) M_B_DQSP3 DQSU VDDQ#H9 (7) M_B_DQSP0 DQSU VDDQ#H9 (7) M_B_DQSP4 DQSU VDDQ#H9 (7) M_B_DQSP7 DQSU VDDQ#H9

M_B_DM2 E7 A9 M_B_DM1 E7 A9 M_B_DM6 E7 A9 M_B_DM5 E7 A9

(7) M_B_DM2 M_B_DM3 D3 DML VSS#A9 B3 (7) M_B_DM1 M_B_DM0 D3 DML VSS#A9 B3 (7) M_B_DM6 M_B_DM4 D3 DML VSS#A9 B3 (7) M_B_DM5 M_B_DM7 D3 DML VSS#A9 B3
(7) M_B_DM3 DMU VSS#B3 E1 (7) M_B_DM0 DMU VSS#B3 E1 (7) M_B_DM4 DMU VSS#B3 E1 (7) M_B_DM7 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
M_B_DQSN2 G3 VSS#G8 J2 M_B_DQSN1 G3 VSS#G8 J2 M_B_DQSN6 G3 VSS#G8 J2 M_B_DQSN5 G3 VSS#G8 J2
(7) M_B_DQSN2 M_B_DQSN3 B7 DQSL VSS#J2 J8 (7) M_B_DQSN1 M_B_DQSN0 B7 DQSL VSS#J2 J8 (7) M_B_DQSN6 M_B_DQSN4 B7 DQSL VSS#J2 J8 (7) M_B_DQSN5 M_B_DQSN7 B7 DQSL VSS#J2 J8

n
C
(7) M_B_DQSN3 DQSU VSS#J8 M1 (7) M_B_DQSN0 DQSU VSS#J8 M1 (7) M_B_DQSN4 DQSU VSS#J8 M1 (7) M_B_DQSN7 DQSU VSS#J8 M1 C
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
M_B_DRAMRST# T2 VSS#P1 P9 M_B_DRAMRST# T2 VSS#P1 P9 M_B_DRAMRST# T2 VSS#P1 P9 M_B_DRAMRST# T2 VSS#P1 P9
(7) M_B_DRAMRST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
M_B_ZQ1 L8 VSS#T1 T9 M_B_ZQ2 L8 VSS#T1 T9 M_B_ZQ3 L8 VSS#T1 T9 M_B_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9

o
B1 B1 B1 B1
VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9
R399 VSSQ#B9 D1 R26 VSSQ#B9 D1 R70 VSSQ#B9 D1 R398 VSSQ#B9 D1
VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8
CHB@240/F_4 VSSQ#D8 E2 CHB@240/F_4 VSSQ#D8 E2 CHB@240/F_4 VSSQ#D8 E2 CHB@240/F_4 VSSQ#D8 E2
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL

C
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
CHB@RAM _DDR3L CHB@RAM _DDR3L CHB@RAM _DDR3L CHB@RAM _DDR3L

Hynix AKD5JGETW00--H5TC4G63AFR-PBA

DE-CAPS FOR MEMORY CHANNEL B VTT TERMINATIONS VREF_DQ CIRCUIT

a
+VDDQ_VTT_M0_M1_R

t
M_B_RAS# R77 [email protected]/F_4
+VDDQ_M0_M1_R PLACE 2 CAPS NEAR EACH DDR3L IC M_B_CAS# R423 [email protected]/F_4
+V_SMDDR_VREF_DIMM M_B_WE# R69 [email protected]/F_4
Distributed around all DRAM devices (CHB) M_B_BS0 R413 [email protected]/F_4
M_B_BS1 R408 [email protected]/F_4
B M_B_BS2 B
R407 [email protected]/F_4
M_B_CKE0 R74 [email protected]/F_4

n
C19 C219 C23 C93 C212 C240 C47 C226 C229 C46 M_B_CS#0 R43 [email protected]/F_4
CHB@10U/6.3V_6 CHB@10U/6.3V_6 CHB@10U/6.3V_6 CHB@10U/6.3V_6 CHB@10U/6.3V_6 CHB@10U/6.3V_6 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 M_B_A0 R42 [email protected]/F_4
M_B_A1 R404 [email protected]/F_4
M_B_A2 R33 [email protected]/F_4
M_B_A3 R39 [email protected]/F_4
M_B_A4 R36 [email protected]/F_4
Place these Caps near Memory Down CA & DQ pin M_B_A5 R395 [email protected]/F_4 +VDDQ_M0_M1_R
Place these Caps near each X16 Memory Down

a
M_B_A6 R392 [email protected]/F_4
M_B_A7 R386 [email protected]/F_4
M_B_A8 R388 [email protected]/F_4
C31 C52 C39 C255 C260 M_B_A9 R389 [email protected]/F_4 Vref_DQ
CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4 C220 CHB@1U/6.3V_4 CHB@1U/6.3V_4 M_B_A10 R53 [email protected]/F_4 R61
CHB@1U/6.3V_4 M_B_A11 R390 [email protected]/F_4 [email protected]/F_4 +V_SMDDR_VREF_DQ1
M_B_A12 R51 [email protected]/F_4
M_B_A13 R394 [email protected]/F_4 PLACE 'CA' CAPACITOR

u
M_B_A14 R387 [email protected]/F_4 AT GENERATION POINT

2
M_B_A15 R58 [email protected]/F_4
C53
C22 C57 C72 C70 C67 C98 +V_SMDDR_VREF_DQ1 R64 [email protected]/16V_4

1
CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4 [email protected]/F_4
CA
+VDDQ_VTT_M0_M1_R
C56 C54 C231 C236
[email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4
M_B_ODT0 R68 [email protected]/F_4
C222 C211 C224 C241 C254 C218

Q
CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4

+VDDQ_VTT_M0_M1_R

C75 C15 C29 C8

CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4
22uF/6.3V_6 C65
[email protected]/10V_4
A A

M_B_CLKP0 R90 [email protected]/F_4 M_B_CLKP0_N0_C

M_B_CLKN0 R83 [email protected]/F_4

+VDDQ_VTT_M0_M1_R

C12 C28 C225 C204 C206 C201 C25 C203 C207

CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@1U/6.3V_4 CHB@10U/6.3V_6
M_B_CLKP0 C63 [email protected]/50V_4 M_B_CLKN0 Quanta Computer Inc.
PROJECT :ZHR
Size Document Number Rev
DDR3L MEMORY DOWNx16 CHB 1A

Date: Monday, September 14, 2015 Sheet 18 of 47

5 4 3 2 1
 5 4 3 2 1

+VSDIO
SD/MMC CARD READER CONNECTOR
19

l
SDMMC3_PWR_EN_N SDMMC3_1P8_EN VSDIO (V)
1 0 0V
1 1 0V
0 0 3.3V

a
0 1 1.8V
Notes:
Card Reader(CRD)
Imax: 100 mA SD SLOT POWER SUPPLY

i
+V3P3A_PRIME +V3P3A
Rise time: 150 uSec +VSDIO
Card Reader(CRD)
D D
+V1P8A

t
C360
R574
1U/6.3V_4 +V3P3S +V3P3S_PD_EN_CARD
100K_4
C361 U30 C356 C355
4.7U/6.3V_4
1U/6.3V_4 A1 B1 *2.2U/6.3V_4
VIN1 VOUT +V3P3S +V3P3S

n
A2 B2
Q30 VIN2 GND
PJA138K A3 B3 1 3
R234 *Short_4 VSDIO_EN_G_N 2 EN SEL R617
(8,19) SDMMC3_PWR_EN_N
VSDIO_EN VSDIO_SEL R553 100K_4 R637 100K_4 Q82
SDMMC3_1P8_EN (8,19)
R248 100K_4 BD2204GUL-E2 10K_4 AO3415

2
e
PWR_SD_GATE_EN R615 1K_4 PWR_SD_GATE_EN_R

3
+VSDIO
SDMMC3_PWR_EN_N_G 5 R590
C379 *22_8
Q81A 0.1U/16V_4

4
6
R802 PJ4N3KDW
2
(8,19) SDMMC3_PWR_EN_N

d
240/F_4

3
Q81B

1
VSDIO_DISC_D PJ4N3KDW Q74

3
*PJA138K
Q85 R614 *0_4 2

i
C419 0.1U/16V_4 VSDIO_3P3_1P8_T_CKT 2
(8,19) SDMMC3_1P8_EN

1
R803 PJA138K

f
47K_4

1
C C

n
eMMC (MMC)

Card Reader(CRD)
SD SLOT/EMI This is full size SD card (push-push type)
eMMC

o
CN5

SD3_CD#_CONN 11 +V1P8S
CD for host interface
SD_WP_R 10
WP NC
16 CAD note: PLACE THE SERIES RESISTORS NEAR EMMC
SD3_D1_CONN SD3_D1_CONN 9 17 U28
SD3_D0_CONN 8 DATA1 NC R528 *Short_4 EMMC_R_D0 A3 C6 VCCQ_EMMC R176 *Short_4
SD3_D0_CONN DATA0 (8) EMMC_D0 DAT0 VCCQ1
7 (8) EMMC_D1 R526 *Short_4 EMMC_R_D1 A4 M4
SD3_CLK_CONN 6 VSS2 R523 *Short_4 EMMC_R_D2 A5 DAT1 VCCQ2 N4
SD3_CLK_CONN CLK SD3_CD#_CONN NORMAL CLOSE (8) EMMC_D2 DAT2 VCCQ3
+V3P3S_PD_EN_CARD R605 *SHORT_6 +V3P3S_PD_EN_CARD_R 5 (8) EMMC_D3 R517 *Short_4 EMMC_R_D3 B2 P3 C132 C133 C147
VCC DAT3 VCCQ4

C
4 SD_WP_R NORMAL CLOSE (8) EMMC_D4 R541 *Short_4 EMMC_R_D4 B3 P5 0.1U/10V_4 0.1U/10V_4 4.7U/6.3V_4
SD3_CMD_CONN SD3_CMD_CONN 3 VSS R525 *Short_4 EMMC_R_D5 B4 DAT4 VCCQ5
CMD (8) EMMC_D5 DAT5
SD3_D3_CONN 2 R522 *Short_4 EMMC_R_D6 B5 E6

GND
GND
GND
GND
SD3_D3_CONN DATA3 (8) EMMC_D6 DAT6 VCC1 +V3P3S
SD3_D2_CONN 1 R524 *Short_4 EMMC_R_D7 B6 F5 for internal flash memory, 250mA
SD3_D2_CONN DATA2 (8) EMMC_D7 DAT7 VCC2 J10
M5 VCC3 K9
PLACE RES CLOSE TO SD CARD CONNECTOR TAS_5-251301001000-6 (8) EMMC_CMD R508 *Short_4 EMMC_CMD_R VCC_EMMC R187 *SHORT_6

12
13
14
15
R519 *Short_4 EMMC_CLK_R M6 CMD VCC4
(8) EMMC_CLK CLK C2 EMMC_VDDI
R189 *Short_4EMMC_RST# K5 VDDI
(12,16,34) SOC_PLTRST# RST_n E7
0 OHM SERIES TERMINATIONS ARE PLACEHOLDERS. VALUE MAY CHANGE. VSS1 G5 iNAND's C137 C138

a
R551 *0_4 R558 *0_4 VSS2 H10 internal 0.1U/10V_4 4.7U/6.3V_4
E9 VSS3 K8 power node
B VSF1 VSS4 B
+V1P8S +V1P8S E10 A6
+V3P3S F10 VSF2 VSS5 J5
VSF3 VSS6

t
+V3P3S_PD_EN_CARD K10
R554 R567 VSF4 C4
VSSQ1 N2 C348
10K_4 *10K_4 VSSQ2 N5 0.1U/10V_4
SD3_CD#_Q R555 1K_4 VSSQ3 P4
SD3_CD# (8,21) VSSQ4
R547 SD3_WP R557 *Short_4 (8) EMMC_RCLK R203 *Short_4 EMMC_RCLK_R_Q H5 P6
SDCARD_WP (10) RCLK VSSQ5
3

4.7K_4 R562
10K_4

n
3

Q64 H26M64103EMR
SD3_CD#_CONN 2 eMMC16G-S100-A06
Q72
2N7002K
SD_WP_R 2
conn side : insert--> open, non-insert-->low 2N7002K
chip side: insert--> low, non-insert --> high
1

conn side : WP -->low, non WP-->open 16G

a
chip side: WP -->high, non WP-->low Samsung-->KLMAG2WEMB-B031-AKE2RF-T505-- IC FLASH(153)KLMAG2WEMB-B031(FBGA)STNBSQ
1

Hynix--> H26M52103FMR (0x03)--AR0ZHQR1000--PROG IC FLASH(153P)H26M52103FMR STNBSQ

R604 *Short_4 SD3_CLK_CONN
(8) SD3_CLK
32G
R641 *Short_4 SD3_CMD_CONN
(8) SD3_CMD Samsung-->KLMBG4WEBC-B031--AKE3SZ-T500--IC FLASH(153)KLMBG4WEBC-B031(FBGA)STNBSQ
Hynix--> H26M64103EMR (0x03)--AR0ZHQR1001--PROG IC FLASH(153P)H26M64103EMR STNBSQ

u
(8) SD3_D0 R569 *Short_4 SD3_D0_CONN

(8) SD3_D1 R580 *Short_4 SD3_D1_CONN

(8) SD3_D2 R649 *Short_4 SD3_D2_CONN

(8) SD3_D3 R647 *Short_4 SD3_D3_CONN

C372
A C364 A
12p/50V_4 C391

Q
+V3P3S_PD_EN_CARD 12p/50V_4 C396
12p/50V_4
30mils 12p/50V_4
C363
C370 C395
C368 12p/50V_4
10U/6.3V_4 0.1U/10V_4 12p/50V_4

Quanta Computer Inc.

PROJECT : ZHR
Size Document Number Rev
SDIO/eMMC 1A

Date: Monday, September 14, 2015 Sheet 19 of 47

5 4 3 2 1
 1 2 3 4 5 6 7 8

l
eDP
eDP PANEL CONTROL 20

a
LCD(LDS)
LCD(LDS)
eDP CONNECTOR

i
(35) EDP_BKLTCTL_CONN EDP_BKLTCTL_CONN 50406-03071-001
A +VBATA C277 0.1u/50V_6 CN9 A

t
R117 C101
F1 Max 1.5A
*100K_4 *0.1U/10V_4 1 2 +VBATA_EDP G_4
30
29
KMC5S150RY24
+V3P3DX_EDP 28 eDP
27 (VGA)

n
Max 1.5A 26
25
LCD_Self_Test 24
TP52 23
EDP_BKLTCTL_CONN
22

e
EDP_BL_EN_CONN
EDP_HPD_CONN 21
R134 *Short_4 EDP_BL_EN_CONN 20 G_2
(35) EDP_BKLTEN_CONN 19
(8) EDP_AUXN_DN C287 0.1U/16V_4 EDP_AUXN_C_DN
+VBATA_EDP C282 0.1U/16V_4 EDP_AUXP_C_DP 18
(8) EDP_AUXP_DP 17
D3
16

d
(30) EC_BL_DISABLE_L (8) EDP_TXP0_DP C283 0.1U/16V_4 EDP_TXP0_C_DP
R129 C284 0.1U/16V_4 EDP_TXN0_C_DN 15
(8) EDP_TXN0_DN 14
RB500V-40 C289 C293 C273
13
*100K_4 CH2 is reserved C285 0.1U/16V_4 EDP_TXP1_C_DP

i
(8) EDP_TXP1_DP 12
10u/25V_8 *10u/25V_8 1000P/50V_4 (8) EDP_TXN1_DN C286 0.1U/16V_4 EDP_TXN1_C_DN
11
10 G_1
+V3P3S R107
150mA
*SHORT_6 +V3P3S_CAMERA
9 CCD USB

f
B
C90 0.1U/10V_4 8
7
(CCD) B

USBP3_R_DN
USBP3_R_DP 6
5
4
(26) DMIC_DAT R476
R477
600,0.3A
600,0.3A
DMIC_DAT_R
DMIC_CLK_R 3 DMIC

n
(26) DMIC_CLK 2

G_5
(8) EDP_HPD R828 33_4 EDP_HPD_CONN +V1P8S R479 *Short_4
1

G_0
C424 C113 C112
180p/50V_4
*150p/50V_4 *150p/50V_4

C
LCD(LDS)

Co CAMERA - POWER AND USB CMC C

a
Front Camera(FCM) +V3P3S

eDP Power

t
0.5A
C87 C88 C89

1U/6.3V_4 10P/50V_4 1000P/50V_4

+V3P3A

n
+V3P3DX_EDP
C121 R474 *Short_4
U8 R123 *SHORT_8

a
1U/6.3V_4
6 1 LCDVCC_1 R114 *SHORT_8
IN OUT
4 2 C105 C100 C83 C84 (11) USBP3_DN USBP3_R_DN
IN GND
CA (11) USBP3_DP USBP3_R_DP
EDP_ON 3 5 CHECK SLEW RATE

u
R112 33_4 0.1U/10V_4 0.01U/50V_4 22U/6.3V_8 *22U/6.3V_8
(35) PCH_DISP_ON ON/OFF GND

D G5245AT11U Based on validation result to D

R111 sot23-5 stuff CA? R475 *Short_4

C425 *100K_4
0901 removed CMC L6 for SMT
180p/50V_4
request "no co-layout" Quanta Computer Inc.

Q
PROJECT : ZHR
Size Document Number Rev
1A
eDP/CCD/DMIC/Touch-panel
Date: Monday, September 14, 2015 Sheet 20 of 47
1 2 3 4 5 6 7 8
 5 4 3 2 1

l
Google debug(DBG)
GOOGLE DEBUG PORT
21

ia
D D

t
PIN7 OD PIN39 OD PIN49 OD
PIN14 OD PIN41 OD PIN50 OD
PIN19 OD PIN43 OD
PIN22 OD PIN44 OD

n
PIN28 OD PIN45 OD
PIN30 OD PIN46 OD
PIN37 OD PIN47 OD
PIN38 OD PIN48 OD

d e
CN10
1
1 2
2 GD_SPI_CLK_R
GD_SPI_CLK_R (9) SOC SPI TO FLASH

i
GD_SPI_CS0#_R 3 4 GD_SPI_SI_R
(9) GD_SPI_CS0#_R 3 4 GD_SPI_SI_R (9)
SOC SPI TO FLASH (9) GD_SPI_SO_R
GD_SPI_SO_R 5
5 6
6
+V1P8A_ME
+V3P3A_EC_GD SPI_HOLD#_BIOS 7 8
(9) SPI_HOLD#_BIOS 7 8

f
C EC_SPI_CLK 9 10 EC_SPI_CS# C
(30) EC_SPI_CLK 9 10 EC_SPI_CS# (30)
EC_SPI_MOSI 11 12 EC_SPI_MISO
(30) EC_SPI_MOSI 11 12 EC_SPI_MISO (30)
13 14 GPIO_EC_RST# R539 GD@200/F_4
13 14 SLG_EC_RST# (29)
15 16 SOC_UART_RX_R
15 16
SOC_UART_TX_R 17 18 SOC_UART_PWR SOC UART

n
R560 GD@0_4 GPIO_SD_DECT 19 17 18 20
(8,19) SD3_CD# 19 20
21 22 GPIO_PWR_BTN# R535 GD@10_4
(30) EC_JTAG_TCK 21 22 PWR_BTN_L (29,30,31)
EC JTAG (30) EC_JTAG_TMS
23
23 24
24
EC_JTAG_TDI (30)
25 26 EC_JTAG_RTCK R534 GD@0_4 EC_JTAG_TCK
(30) EC_JTAG_TDO 25 26
27 28 SYS_RESET# R546 GD@0_4

o
(30) EC_SERVO_JTAG_RST_N 27 28 SOC_REST_BTN# (12,16,34)
29 30
+V3P3A 29 30
31 32 EC_UART_RXD R533 GD@0_4
31 32 EC_UART0_RX (21,30)
EC UART (21,30) EC_UART0_TX R603 GD@0_4 EC_UART_TXD 33
33 34
34
+V3P3A
R602 GD@0_4 PP3300_INA_R 35 36
+V3P3_INA 35 36
R600 GD@0_4 I2C_SDA_INA 37 38 I2C_SCL_INA R531 GD@0_4
I2C_SDA_INA_R 37 38 I2C_SCL_INA_R
R599 GD@10_4 GPO_HPD 39 40 GPIO_SPI_WP

C
(22) HP_DET_CN 39 40 GPIO_SPI_WP (9)
R598 *GD@10_4 GPIO_PROC_HOT# 41 42
(12,30) PROCHOT# 41 42
R305 GD@10_4 TP_USB_MCU_BOOT 43 44
(27,30) LID_OPEN_OUT2_L 43 44 LID_OPEN_OUT1_L (27,30)
USBPD_MCU_RST 45 46
TP39 47 45 46 48
B
49 47 48 50 B
49 50

a
GD@AXK750147G

n t
R595 GD@0_4 SOC_UART_TX_R +V3P3_INA
(11) SOC_UART_TX
R532 [email protected]_4 I2C_SCL_INA_R
(21,30) EC_UART0_TX R606 *GD@0_4
R601 [email protected]_4 I2C_SDA_INA_R

a
R537 GD@0_4 SOC_UART_RX_R
(11) SOC_UART_RX

(21,30) EC_UART0_RX R538 *GD@0_4

u
A SOC_UART_PWR R536 *GD@0_4 +V3P3A A
R529 GD@0_4 +V1P8A
Quanta Computer Inc.
PROJECT : ZHR

Q
Size Document Number Rev
1A
Google Debug & FP header
Date: Monday, September 14, 2015 Sheet 21 of 47
5 4 3 2 1
 5 4 3 2 1

HDMI INTERFACE

l
HDMI(HDM)

HDMI CONNECTOR
22

a
HDMI LEVEL SHIFTER

ti
D D

C103 0.1U/16V_4 INT_HDMITX2N_C

(8) INT_HDMITX2N_DN INT_HDMITX2P_C
C106 0.1U/16V_4
(8) INT_HDMITX2P_DP
C110 0.1U/16V_4 INT_HDMITX1N_C

n
(8) INT_HDMITX1N_DN INT_HDMITX1P_C
C111 0.1U/16V_4
(8) INT_HDMITX1P_DP
C86 0.1U/16V_4 INT_HDMITX0N_C
(8) INT_HDMITX0N_DN
C96 0.1U/16V_4 INT_HDMITX0P_C
(8) INT_HDMITX0P_DP
INT_HDMICLK+_C

e
C81 0.1U/16V_4 CN2
(8) INT_HDMICLK_DP INT_HDMICLK-_C 20
C78 0.1U/16V_4
(8) INT_HDMICLK_DN 1 SHELL1 22
R102 *Short_4 INT_HDMITX2P_C
R446 R445 R470 R463 R457 R451 2 D2+SHELL3
INT_HDMITX2N_C 3 D2 Shield
Layout Notes: 619/F_4 619/F_4 619/F_4 619/F_4 619/F_4 619/F_4 INT_HDMICLK+_C INT_HDMITX1P_C 4 D2-
D1+
Place decoupling CAPs INT_HDMICLK-_C 5

d
INT_HDMITX1N_C 6 D1 Shield
close to Connector INT_HDMITX0P_C 7 D1-
8 D0+
D0 Shield
3
R98 *Short_4 INT_HDMITX0N_C 9

i
Q54 INT_HDMICLK+_CONN 10 D0-
11 CK+
PJA138K R443 619/F_4 INT_HDMICLK+_CONN 0901 removed CMC L1 for SMT CK Shield
2 INT_HDMICLK-_CONN 12
(12,34,42,43) SLP_S3# request "no co-layout" 13 CK-

f
R441 619/F_4 INT_HDMICLK-_CONN 14 CE Remote
+V5S HDMI_DDCCLK_MB 15 NC
HDMI_DDCDATA_MB 16 DDC CLK
1

Q47 17 DDC DATA

3 1 HDMI_5V 18 GND
IN OUT 2 HP_DET_CN_CONN 19 +5V 23
GND HP DET
SHELL4

n
C 21 C
AP2331SA-7 SHELL2

1
C243 D13 R93 C128F4-K1909-L
*220P/50V_4 *14V/38V/100P_4 RV5
*Short_4
*5V/0.2P_4 C247 *1000P/50V_4

2
o
C253 *1000P/50V_4

HP_DET_CN

a C
t
B
LEVEL TRANSLATOR/ EMI B

n
EMI +V1P8A

a
+V1P8A R146 *Short_4 PP1800_PCH_HDMI
INT_HDMITX2P_C
+V1P8S R147 *0_4 R462
R116 *100/F_4 10K_4
D14 RB500V-40 HDMI_5V
PP1800_PCH_HDMI INT_HDMITX2N_C

u
PP1800_PCH_HDMI R125 *4.7K_4 R480 (8) INT_HDMI_HPD
2

4.7K_4 INT_HDMITX1P_C

3
R126 *Short_4 HDMI_DDCCLK_COM 1 3 HDMI_DDCCLK_MB R130 *100/F_4
(8) HDMI_DDCCLK_SW
INT_HDMITX1N_C 2 HP_DET_CN
HP_DET_CN (21)
Q11 FDV301N

Q
Q51
2N7002K
INT_HDMITX0P_C R94 100K/F_4

1
D2 RB500V-40 HDMI_5V R108 *100/F_4
PP1800_PCH_HDMI
INT_HDMITX0N_C
PP1800_PCH_HDMI R136 *4.7K_4 R135
A A
2

4.7K_4
INT_HDMICLK+_CONN
R137 *Short_4 HDMI_DDCDATA_COM 1 3 HDMI_DDCDATA_MB
(8) HDMI_DDCDATA_SW
R101 *100/F_4

Q14 FDV301N INT_HDMICLK-_CONN

Quanta Computer Inc.

PROJECT : ZHR
Size Document Number Rev
HDMI 1A

Date: Monday, September 14, 2015 Sheet 22 of 47

5 4 3 2 1
 5 4 3 2 1

STRAPS SETTINGS
23
l
SoC (CPU)

a
+V1P8A

i
D R196 D

t
R182 R167 R159 R142 R139 R133
BSW Strapping Table (based on EDS V1.0), sampled 4.7K_4 4.7K_4 *10K_4 4.7K_4 4.7K_4 2.7K/F_4
100K_4

on the rising edge of PMU_RSMRST_N

n
Pin Name Strap description Configuration (10,35) MUX_AUD_INT1#
(10,34) EC_SMI_L
0 = DDI0 not detected
GPIO_SUS0 DDI0 Detect (10,34) KBD_IRQ#
1 = DDI0 detected

e
(10) TRACKPAD_INT#
0 = DDI1 not detected (10) EC_KBD_ALERT_SOC
GPIO_SUS1 DDI1 Detect (10,16) SOC_RUNTIME_SCI
1 = DDI1 detected (10) SOC_KBC_SMI

d
0 = change boot loader address
GPIO_SUS2 Top Swap (A16 Override)
1 = Normal operation

i
R181 R158 R154 R143 R131 R183
*100K_4 *100K_4 *100K_4 *100K_4 *100K_4 *100K_4
DSI Display Detect

f
GPIO_SUS3 0 = DSI not detected
C (Leave floating if GPIO functionality C
is not used, it is not POR) 1 = DSI detected
0 = No SPI
GPIO_SUS4 BIOS Boot Selection

n
1 = SPI
0 = Not support
GPIO_SUS5 Security Flash Descriptors
1 = Normal operation

o
+V1P8A
1 = Normal operation
GPIO_SUS6 Halt Boot strap
(MUST be high at RSMRST# de-assert
to ensure proper platform operation
and use of GPIO_DFX[8:0] R174 R121 R127 R16 R222 R221 R164

C
*100K_4 *100K_4 *100K_4 *100K_4 *100K_4 *100K_4 *100K_4
0 = SUSDUG
GPIO_SUS7 DFX SUS DEBUG strap
1 = No SUSDUG NFC_PWR_MANAGE
(10) NFC_PWR_MANAGE
(10) NFC_FW_RESET# NFC_FW_RESET#
0 = Supply is 1.25V (10) TP_RSVD_STRAP3 TP_RSVD_STRAP3
GPIO_SUS8 PLLs.ICLK.USB2,DDI OBSFN_C0

a
B (8,16) OBSFN_C0 B
1 = Supply is 1.35V TP_RSVD_STRAP1
,SFR,supply select (8) TP_RSVD_STRAP1
TP_RSVD_STRAP2
(8) TP_RSVD_STRAP2
0 = No Bypass(Default) SOC_WAKE_SCI_N

t
(10,34) SOC_WAKE_SCI_N
GPIO_SUS9 ICLK.USB2,DDI,SFR Bypass
1 = Bypass with 1.05V

GPIO_CAMERASB08
0 = No Bypass(Default)
ICLK Xtal OSC Bypass

n
1 = Bypass
R170 R118 R122 R15 R214 R213 R165

GPIO_CAMERASB09
0 = No Bypass(Default) *100K_4 *100K_4 10K_4 *100K_4 *100K_4 *100K_4 *100K_4
CCU SUS RO Bypass
1 = Bypass

a
GPIO_CAMERASB11
0 = No Bypass(Default)
RTC OSC Bypass
1 = Bypass

u
A A

Q
Quanta Computer Inc.
PROJECT : ZHR
Size Document Number Rev
1A
STRAPS
Date: Monday, September 14, 2015 Sheet 23 of 47
5 4 3 2 1
 1 2 3 4 5 6 7 8

l
WIFI/BT COMBO NGFF E KEY(NGF)
WIFI/BT COMBO (NGFF E KEY)
+V3P3A_WIFI CN4

24
a
NGFF 75
GND

i
74 73 NFC_NOT_ALLOWED
3.3Vaux RESERVED TP78
72 71
70 3.3Vaux RESERVED 69

t
A A
WLAN_OFF_L POWER DOWN LAN CHIP from EC? NFC_ANT_N 68 NC GND 67
WIFI_DISABLE_L disable Antenna from PCH? TP33 NFC_ANT_P 66 NFC_ANT_N PETn1 65
TP35 NFC_ANT_P PETp1
NFC_VDDANT 64 63
TP30 NFC_VDDANT GND
62 61
PIN54: disable Antenna ALERT PERn1

n
60 59 WAKE/REQ 53, 55 is OD
PIN52: power down CHIP 58 I2C_CLK PERp1 57
I2C_DATA GND
(Low Active) RF_EN_CONN 3.3V/I 56
W_DISABLE# PEWake0#
55 3.3V/OD WLAN_WAKE_L
WLAN_WAKE_L (35)
(Low Active) PDN# 3.3V/I 54
PDN# CLKREQ0#
53 3.3V/OD PCIE_CLKREQ_WLAN#_Q R548 *Short_4
PCIE_CLKREQ_WLAN# (9)

e
R264 *Short_4 WLAN_RST# 3.3V/I 52 51
(30,31,32,33,34) PLTRST# 3.3V/I 50 PERST0# GND 49
(35) WIFI_SUSCLK LTE_SOUT 1.8V/IO 48 SUSCLK_32KHz REFCLKN0 47 CLK_PCIE_WLANN_DN (9)
(25) LTE_SOUT LTE_SIN 1.8V/IO 46 LTE_SOUT REFCLKP0 45 CLK_PCIE_WLANP_DP (9)
(25) LTE_SIN 44 LTE_SIN GND 43
COEX3

d
(25) COEX3 NFC_WI_IN 42 NC PETn0 41 PCIE_RX2_WLAN_DN (9)
TP20 NFC_WI_IN PETp0 PCIE_RX2_WLAN_DP (9)
NFC_SWP2_IO 40 39
TP21 NFC_SWP2_IO GND

i
NFC_ACTIVE 38 37
TP18 NC PERn0 PCIE_TX2_WLAN_DN (9)
NFC Security 36 35
34 UART_CTS PERp0 33 PCIE_TX2_WLAN_DP (9)
UART_RTS GND

f
WIFI_UART_RX 32
TP19 UART_Rx
B
R829 33_4 RF_EN_CONN 30
SLOT A-SD KEY
31
29
B

(35) RF_EN 28 KEY KEY 27

n
26 KEY KEY 25
C426 24 KEY KEY
KEY
180p/50V_4
23 WIFI_SDIO_RESET

o
SDIO_RESET TP64
WIFI_UART_TX 22 21 WIFI_SDIO_WAKE
TP17 UART_Tx SDIO_WAKE TP65
20 19 WIFI_SDIO_DAT3
UART_Wake SDIO_DAT3 TP62
BT_LED 18 17 WIFI_SDIO_DAT2
TP16 GND SDIO_DAT2 TP61
16 15 WIFI_SDIO_DAT1
LED#2 SDIO_DAT1 TP59
PCM_IN 14 13 WIFI_SDIO_DAT0
TP15 PCM_IN SDIO_DAT0 TP58
PCM_OUT 12 11 WIFI_SDIO_CMD

C
TP14 PCM_OUT SDIO_CMD TP57
PCM_SYNC 10 9 WIFI_SDIO_CLK
TP12 PCM_SYNC SDIO_CLK TP56
PCM_CLK 8 7
TP11 PCM_CLK GND
WLAN_LED1# 6 5
TP10 LED#1 USB_D- USBP4_DN (11)
4 3
2 3.3Vaux USB_D+ 1
USBP4_DP (11) BT

GND
GND
+V3P3A_WIFI 3.3Vaux GND

a
+V3P3A_WIFI
C D19 C

76
77
PDN# R556 10K_4 WLAN_NGFF CONN(Type 2230)_51745-0750P-005

t
(30) WLAN_OFF_L

RB500V-40

n
WL/BT NGFF Power +VBATA +V3P3A_WIFI +15V +V3P3A +V3P3A +V3P3A_WIFI

R314 0_8

a
R201 R494 R495
*1M_6 *22_8 *1M_6 C165 C162 C322 C323

3
10U/6.3V_6 0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4

u
WLAND 2
3

Q33
R565 *0_4 2 R197 *AO3404
(30) WIFI_PWREN
1
D D

Q
Q16 2 2
*DTC144EU *1M_6
Q57 Q58 C313
+V3P3A_WIFI
Quanta Computer Inc.
1

R188 *2N7002K *2N7002K

*100K/F_6 *2.2n/50V_4
TDC : 0.45A PROJECT : ZHR
1

PEAK : 0.6A Size Document Number Rev

1A
Width : 40mil WIFI/BT(NGFF)
Date: Monday, September 14, 2015 Sheet 24 of 47
1 2 3 4 5 6 7 8
 5 4 3 2 1

LTE NGFF Power(LTE)

LTE MultiMedia SIM (LTE)
25
l
SIM_DET C38 *3G@470P/50V_4

SIM_DET D1 1 2 *3G@5V/0.2P_4 UIM_PWR C32 *3G@27P/50V_4

Peak:2.75A UIM_RST RV3 1 2 *3G@EGA-0402 UIM_DATA C40 *3G@10P/50V_4

a
Normal:1.1A
+V3P3A UIM_VPP RV4 1 2 *3G@EGA-0402 UIM_CLK C33 *3G@10P/50V_4
+3V_LTE

i
UIM_CLK RV2 1 2 *3G@EGA-0402 UIM_RST C34 *3G@27P/50V_4
R486 *3G@SHORT_8
UIM_DATA RV1 1 2 *3G@EGA-0402 UIM_VPP C49 *[email protected]/10V_4

t
D R490 *3G@SHORT_8 D
H=0.9mm UIM_VPP C50 *3G@33P/50V_4

UIM_VPP_C R66 *3G@0_4 UIM_VPP

+VBATA +3V_LTE +15V +V3P3A

n
UIM_PWR

C35 C41
R207 R172 R498

5
*3G@1M_6 *3G@22_8 *3G@1M_6 *3G@1U/6.3V_4 *[email protected]/16V_4

e
Max: 7.5mA (Option)
R44

LTED 4 *3G@10K_4 JSIM1

UIM_VPP_C 6 1 UIM_PWR
VPP VCC
3

d
UIM_DATA 7 2 UIM_RST
Q15 8 I/O Serial date I/O RST 3 UIM_CLK

3
2
1
2 *3G@MDV1528Q SIM_DET 9 Reserved CLK 4
(30) LTE_PWREN (35) SIM_DET CD Reserved

i
2 2 5
GND

GND

GND
Q18 R199 Q17 Q59
+3V_LTE
1

R185 *3G@1M_6 *3G@2N7002K *3G@2N7002K C332

f
*100K/F_6 *3G@DTC144EU *[email protected]/50V_4 *3G@SIM-CONN
1

11

10
TDC : 1.875A <Layout Notes> Keep USIM signals
max length within 8000mils.
PEAK : 2.5A
Width : 80mil

n
C C

+3V_LTE
LTE NGFF (LTE)

o
R414 *3G@0_4 LTE_CFG3

0901 removed CMC L5 for SMT C124 C291 C292 C115 C128
*3G@1U/6.3V_4 *3G@10P/50V_4 *[email protected]/6.3V_4 *3G@10U/6.3V_6 *[email protected]/10V_4
request "no co-layout" CN1

C
R421 *3G@0_4
1
NGFF 2
3 CONFIG_3 3.3Vaux 4
5 GND 3.3Vaux 6 1.8V/I LTE_POWER_ON_OFF C45 C36
USBP1+_R 7 GND Power_On_Off 8 3.3V/I LTE_DISABLE_L_R *[email protected]/10V_4 *3G@22U/6.3V_8
(11) USBP1_DP USB_D+ W_DISABLE#
USBP1-_R 9 10 LTE_LED# TP1
(11) USBP1_DN USB_D- LED#
11
GND

a
13
15 NC KEY B NC
12
14 R65 *3G@0_4
NC PLATFORM PIN OUT NC LTE_DISABLE_L (35)
R425 *3G@0_4 17 16

t
19 NC NC 18 +3V_LTE
NC NC
NC at A stage, LTE card LTE_CFG0
HW not implement yet TP49
B 20 B
21 RESERVED 22 R55

n
R428 *3G@Short_4 LTE_WAKE_L_R 1.8V/O 23 CONFIG_0 RESERVED 24
(35) LTE_WAKE_L Wake_On_WWAN# RESERVED *3G@100K/F_4
TP50 LTE_BODYSAR# 25 26 GPS_DISABLE# TP2
27 BODYSAR_N GPS_DISABLE# 28 UIM_VPP
29 GND RESERVED 30 UIM_RST LTE_POWER_ON_OFF
31 NC UIM-RESET 32 UIM_CLK

a
33 NC UIM-CLK 34 UIM_DATA
35 GND UIM-DATA 36 UIM_PWR R60
37 NC UIM-PWR 38
NC NC *3G@124K/F_4
39 40 UART_MDM_RX TP3
41 GND RESERVED 42 MDM_WAKE_AP
NC RESERVED TP4

u
43 44 AP_WAKE_MDM TP5
45 NC RESERVED 46
UART_MDM_CTS 47 GND RESERVED 48
+3V_LTE TP51 NC RESERVED
49 50 COEX3_R R453 *3G@0_4
NC NC COEX3 (24)
51 52 UART_RX R110 *3G@0_4 LTE_SIN
GND NC LTE_SIN (24)
53 54 UART_TX R120 *3G@0_4 LTE_SOUT
NC NC LTE_SOUT (24)
55 56
57 NC NC 58 SIM_DET
GND NC

Q
R484 59 60 SUSCLK R132 *3G@Short_4 LTE_SUSCLK
ANTCTL0 RESERVED LTE_SUSCLK (35)
*3G@100K/F_4 61 62 1.8V/IO
63 ANTCTL1 UART_RX 64 1.8V/IO
65 ANTCTL2 UART_TX 66 1.8V/I
PLTRST#_3G 1.8V/I 67 ANTCTL3 SIM_DET 68 3.3V/I
LTE_CFG1 69 Reset# NC 70
TP53 CONFIG_1 3.3Vaux
71 72
R468 73 GND 3.3Vaux 74
A GND 3.3Vaux A
*3G@124K/F_4 C274 75
*3G@33P/50V_4 CONFIG_2
GND
GND

*3G@BWE_80149-1721
Quanta Computer Inc.
76
77

TP54
PROJECT :ZHR
Size Document Number Rev
1A
LTE(NGFF)
Date: Monday, September 14, 2015 Sheet 25 of 47
5 4 3 2 1
 1 2 3 4

Codec (ADO)

l 26
+V1P8S BOM Change to 0_4 due to material shortage +5VA

a
L4 *Short_4 PP1800_CODEC_AVDD

ti
A R597 *SHORT_6 PP1800_CODEC_DVDDIO C183 C190 C184 A
1U/16V_4 0.1U/10V_4 10U/6.3V_4

n
C377 C185 C180
0.1U/10V_4 1U/16V_4 1U/16V_4
C387 C179 C191
1U/16V_4 0.1U/10V_4 10U/6.3V_4

e
28

27

26

38

14
13
U31
Close to PIN26 Close to PIN38

d
DVDD

AVDD

SPKLVDD
SPKRVDD
DVDDIO

HPVDD
f i
R629 *Short_4 CODEC_CLK_IN 35 16 L_SPK+
(10) I2S_MCLK_R MCLK SPKLP 15 L_SPK-
33 SPKLN 12 R_SPK+
(9) I2S_BCLK_R BCLK SPKRP
(9) I2S_LRCLK_R 32 11 R_SPK-
LRCLK SPKRN

n
B 30 B
(9) I2S_DOUT_R SDIN
(9) I2S_DIN_R 31
SDOUT

o
(35) I2C_1_SDA_AUDIO 37
36 SDA 22 MICBIAS_1 R320 *Short_4 MICBIAS
(35) I2C_1_SCL_AUDIO SCL MICBIAS
C178
R622 *Short_4 CODEC_INT_OD_L 34 R319
(9) AUDIO_CODEC_IRQ IRQ_LOD 1U/10V_4 2.2K_4

C
DMIC_DAT R619 *Short_4 DMIC_DAT_L 19
(20) DMIC_DAT IN1/DMD
DMIC_CLK R624 *Short_4 DMIC_CLK_L 18 8
(20) DMIC_CLK IN2/DMC RCVP/LOUTL
20
21 IN3 9
RCVP C373 1U/10V_4 CODEC_MIC_L_P IN4 RCVN/LOUTR

a
(27) RCVP
(27) RCVN RCVN C374 1U/10V_4 CODEC_MIC_L_N
MAX98090AETL+T

t
CODEC_C1P 39 5 RCVN
C1P HPSNS
7 MIC_DET R642 *0_4 RCVP
C C389 JACKSNS C
Codec PWR 5V (ADO)

n
1U/16V_4
4 HPOUT-L R644 5.6_4 HPL
+V5S HPL HPL (27)
+5VA CODEC_C1N 40
C1N
DIGITAL ANALOG AVDD1 6 HPOUT-R R643 5.6_4 HPR HPR (27)

a
HPR
L8 HCB1005KF_1.5A_4
23
REF

u
C392 1U/10V_4 3
C386 C388 C188 C186 CPVDD 24
C393 1U/10V_4 2 BIAS C376 C375 R373 R374
*0.1U/10V_4 *10U/6.3V_6 0.1U/10V_4 10U/6.3V_4 CPVSS
1U/10V_4 2.2U/6.3V_4 *4.7K_4 *4.7K_4
SPKRGND
SPKLGND

Q
HPGND
DGND
AGND
TGND

Internal
L_SPK+ R367
Speaker
*SHORT_6
(ADO) L_SPK+_1
CN14
41

29
25
1
10
17

L_SPK- R366 *SHORT_6 L_SPK-_1 4 6

D 3 5 D
R_SPK- R368 *SHORT_6 R_SPK-_1
R_SPK+ R369 *SHORT_6 R_SPK+_1 2

C194 C198 C195

1
C196 SPK_CONN_4P
Quanta Computer Inc.
R674 *Short_4
10P/50V_4 10P/50V_4 10P/50V_4 10P/50V_4 PROJECT :ZHR
R645 *Short_4 Size Document Number Rev

40mil for each signal

Audio Codec/SPK 1A

Date: Monday, September 14, 2015 Sheet 26 of 47

1 2 3 4
 A B C D E

TPM/DAUGHTER BOARD CONNECTOR

l
TPM(TPM)
TPM DB(UIF)
DB CONNECTOR 4 x100nF (place close to
device VDD/GND pins) 27

a
+V3P3S TPM_VDD

i
BCRD says R38 is
4
stuffed R249 *0_6
4
+V5A

t
TPM_VDD +V3P3A_PRIME CN13
C367 C369 C151 C181
1
R240 *SHORT_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 C380 C381 2 1
2

n
Q *1U/6.3V_4 *1U/6.3V_4 3
4 3
5 4
RF 6 5
6

e
R607 R323 USB2_ILIM_SEL 7
(28) USB2_ILIM_SEL USB2_PWR_EN 8 7
CLK_PCI_EC_R2 R542 CLK_PCI_EC (30) USB2_PWR_EN USB_CTL1 9 8
*4.7K_4 *20K_4 22_4
CLK_PCI_EC (12,30) (28,30) USB_CTL1 USB2_STATUS_L 10 9
U14
TPM_VDD (28) USB2_STATUS_L USB_OC1# 11 10

d
TPM_GPIO 6 10 (11,34) USB_OC1# 12 11
GPIO OD VDD[4] 12
2 5 R324 *Short_4 RA (11) USBP0_DN R638 *Short_4 USBP0-_CONN 13
NC2 VDD[3] 13

i
24 near pin 21 as possible (11) USBP0_DP R640 *Short_4 USBP0+_CONN 14
TPM_PP 7 VDD[2] 19 R257 *Short_4 RB 15 14
PP ST VDD[1] 15
C152 10P/50V_4 R665 *Short_4 16
+V3P3A 16

f
3 13 DGND_CONN R666 *0_4 17 3
NC13 21 CLK_PCI_EC_R2 18 17
ST LCLK 18
R609 ST LFRAME# 22 C394 *1U/6.3V_4 19
14 LPC_LFRAME# (12,30) 20 19
*Short_4 NC14 +VRTC 20
TS 17 R646 1K_4 LID_OPEN# 21

n
0411 FAE : LAD3 20 LPC_LAD3 (12,30) (21,30) LID_OPEN_OUT1_L 22 21
TS R648 *Short_4 DGND_CONN
install R43 value LAD2 23 LPC_LAD2 (12,30) 23 22
TS R667 *Short_4
is 4K7, and PIN7 LAD1 26 LPC_LAD1 (12,30) AUDIO_SWITCH_INT_N_227 24 23
wo an internal PD
TS LAD0 LPC_LAD0 (12,30) 24
HP_JD_L 25
8 28 (35) HP_JD_L RCVP 26 25

o
NC8 NC28 (26) RCVP 27 26
RCVN
(26) RCVN 27
ST 16 RD TPM_PLTRST# (34) (26) HPL
HPL 28
LRESET#[1] 9 TPM_RST_R R262 *Short_4 HPR 29 28
ST LRESET#[2] (26) HPR 29
12 TPM SLB9655 AJACK_MICPRES_L_227 30
NC12 27 SERIRQ_R R254 *0_4 I2C_1_SCL_MIC 31 30
TS SERIRQ IRQ_SERIRQ (30,34) (35) I2C_1_SCL_MIC 31
3 15 I2C_1_SDA_MIC 32

C
GND[1]
GND[2]
GND[3]
GND[4]

NC3 NC15 (35) I2C_1_SDA_MIC 32

1 LID_OPEN_OUT2_L_CONN 33 36
NC1 R255 10K_4 34 33 PAD2 35
TPM_VDD (31) PWR_BT_YOGA 34 PAD1
Q
4
11
18
25

2 2
PROG IC OTHER(28P)SLB9655TT1.2FW4.32GOOG IO_CONN_34P
ST:Schmitt Trigger

a
TS:Tri-State
OD: Open Drain RE
R256 *Short_4

t
LID_OPEN_OUT2_L R675 *0_4 LID_OPEN_OUT2_L_CONN
(21,30) LID_OPEN_OUT2_L
+V3P3S R676 *0_4

0914 stuffed R675

n
+V1P8A
+V1P8A

a
+V1P8A
+V1P8A R570

2
*10K_4
R573 *PJA138K Q69 *PJA138K
2

*10K_4 1 3 AJACK_MICPRES_L_227

u
(9) AJACK_MICPRES_L
Q68
1 1 3AUDIO_SWITCH_INT_N_227 1
(9) AUDIO_SWITCH_INT_N
R563 *Short_4

R566 *Short_4
Quanta Computer Inc.
PROJECT : ZHR

Q
Size Document Number Rev
1A
DB /TPM
Date: Monday, September 14, 2015 Sheet 27 of 47
A B C D E
 5 4 3 2 1

USB3 CONN 0901 removed CMC L7 for SMT request "no co-layout"

28

l
R499 *Short_4
USB3.0 /HOLE
USB3.0 (UB3) USB3.0 (UB3)

a
USBP2-_L CN3
USB3PWR USB3.0 CONN
80 mils (Iout=2A) USB3PWR 1
VBUS
2 1

i
USBP2+_L USBP2-_C
D-
3 2

5
6

7
8
USB3PWR USBP2+_C
4 3 D+ (11) USB3_RXN2_DN 3 1 USB3_RXN2_R
+ C134 C314 D15 R502 *Short_4 USB3_RXN2_R 5 4 GND

t
D D
USB3_RXP2_R 6 5 SSRX- (11) USB3_RXP2_DP 4 2 USB3_RXP2_R
220U/6.3V/ESR35_3528 1000P/50V_4 TVM0G5R5M261R_4 7 6 SSRX+
USB3_TXN2_R 8 7 GND L3

9
10

11
12
USB3_TXP2_R 9 8 SSTX- *short_PCB_CMC
9 SSTX+

13
12
11
10
n
U29
USB3_TXN2_R 1

13
12
11
10
I/O 1 10 USB3_TXP2_R
2 I/O 6
USB3PWR VDD 9
GND_2

e
3
C416 NC_1 8
0.1U/16V_4 USBP2-_C 4 NC_2
I/O 2

5
6

7
8
7 USBP2+_C
USB3_RXP2_R 5 I/O 5 C136 0.1U/16V_4 USB3_TXN2_C 3 1 USB3_TXN2_R

GND_1
I/O 3 (11) USB3_TXN2_DN
6 USB3_RXN2_R

d
I/O 4 C135 0.1U/16V_4 USB3_TXP2_C 4 2 USB3_TXP2_R
(11) USB3_TXP2_DP
L2

11

9
10

11
12
i
*short_PCB_CMC
USB30_ESD_AZ1065-06F.R7G

f
USB Colay BOM option USB3.0 (UB3) USB PWR (Charger)
C C

n
+V5A USB3PWR
(11) USBP2_DN USBP2_DN R790 *0_4 USBP2-_L_OP R791 *0_4 USBP2-_L 80 mils (Iout=2A)
(11) USBP2_DP USBP2_DP R792 *0_4 USBP2+_L_OP R793 *0_4 USBP2+_L 80 mils (Iout=2A)

U1012

1
C418

o
1 12 USB3PWR D1005
USB PWR(non-Charger) 1U/10V_4 IN OUT

ILIM_LO
15 ILIM_LO
C320
0.1U/10V_4
BZT52-B5V6S(5.6V)

16 ILIM_HI

2
ILIM_HI
(RILIM_HI 1.96A)
9 R794 R795
(28) USB3_STATUS_L STATUS 17 25.5K/F_4 47K_4
GND_PAD

C
PAD14 *esd-6x3 PAD2 *esd-6x6 USB_OC0# 13
(11,34) USB_OC0# FAULT
USB3_ILIM_SEL 4 14
1 USBP2-_C 1 ILIM_SEL GND

USB3_PWR_EN 5 11 USBP2-_L
USB3PWR (30) USB3_PWR_EN EN DM_IN
PAD13 *esd-6x3 PAD4 *esd-6x6 10 USBP2+_L
+V5A 6 DP_IN
1 USBP2+_C 1 (27,30) USB_CTL1 USB3_CTL2 7 CTL1 2 USBP2_DN
+V3P3A

a
R796 10K_4 USB3_CTL3 8 CTL2 DM_OUT 3 USBP2_DP
80 mils (Iout=2A) 80 mils (Iout=2A) CTL3 DP_OUT
R797 10K_4
PAD12 *esd-6x3 PAD6 *esd-6x6 SN1408009RTER

t
B B
1USB3_RXN2_R 1 R789
C403 10K_4
*1U/10V_4
PAD11 *esd-6x3 PAD8 *esd-6x6 (28,30) USB_ILIM_SEL (28,30) USB_ILIM_SEL
U37 R798 10K_4 +V3P3A

n
2
5 1 1USB3_RXP2_R 1 R799 10K_4 +V3P3A
IN OUT

2
USB_OC0# 3 1 3USB2_ILIM_SEL R800 *Short_4
OC# USB3_STATUS_L (28)
PAD10 *esd-6x3 PAD16 *esd-6x6 1 3 USB3_ILIM_SEL R801 *Short_4
USB2_STATUS_L (27)
USB3_PWR_EN 4 2
USB2_ILIM_SEL (27)

a
EN GND 1USB3_TXN2_R 1 Q84 2N7002K
Q83 2N7002K
*G524A1T11U
PAD9 *esd-6x3 PAD15 *esd-6x6
Set limit current. 0910 changed Hole2/Hole3 Footprints HOLE2
Min 1.9A 1USB3_TXP2_R 1 *H-O112X108D112X108N

u
Nomal 2.1A 0911 changed Hole2 Footprints
Max 2.4A
HOLE10 HOLE3 HOLE6 HOLE7 HOLE1 HOLE4 HOLE8 HOLE9
Holes(OTH) MOUNTING HOLES *H-ZHR-6 *H-ZHR-7 *H-ZHR-4 *H-ZHR-4 *H-ZHR-5 *H-C236D59P2 *H-C217D98P2 *H-C217D98P2
EMI caps

1
1

Q
+VDDQ_M0_M1_R +V5A +V1P15A +V3P3S HOLE5

1
A *H-ZHR-2 A

1 3SPI_WP_R R291 10K_4

SPI_WP_ME (9,30)

C11 C129 C117 C114

Quanta Computer Inc.
2

C17 C104 C290 C79

*0.1U/16V_4 *1000P/50V_4 *0.1U/16V_4 *1000P/50V_4 *0.1U/16V_4 *1000P/50V_4 *0.1U/16V_4 *1000P/50V_4
PAD1 *PAD-ZHR-1
PROJECT : ZHR
ROM WP# 1 Size Document Number Rev
1A
USB3/Charger/Hole
Date: Monday, September 14, 2015 Sheet 28 of 47
5 4 3 2 1
 5 4 3 2 1

KBC TRACK PAD BOARD CONN

l
29
KB_PWR_L D10 1 2 *5V/0.2P_4

KBC(KBC)
CN11
KB_COL00 D11 1 2 *5V/0.2P_4
TP_PWR
30mil

a
30
29 30 31
31
32
Trackpad(TPD) +V3P3A
R24 *0_6 TP_PWR
28 29 32

i
27 28 C385
R362 0_4 26 27
R360 *0_4 KB_PWR_L 25 26 0.1U/10V_4 50503-0080n-001-8p-l

t
D (21,30,31) PWR_BTN_L 25 D
KB_COL01 24 U18 DFFC08FR027
(30) KB_COL01 23 24 1 6
KB_COL07 KB_ROW08 KB_ROW09 CN12
(30) KB_COL07 23 I/O 1 I/O 4
KB_COL06 22 1 10
(30) KB_COL06 21 22 2 5 2 9
KB_ROW07 TPCLK_CN
(30) KB_ROW07 21 GND VDD +V5A TP85
KB_COL04 20 TPDATA_CN 3

n
(30) KB_COL04 19 20 3 4 TP82 4
KB_COL05 KB_ROW11 KB_ROW10
(30) KB_COL05 18 19 I/O 2 I/O 3 5
KB_ROW00 (35) I2C_5_SDA_CONN I2C_5_SDA_CONN
(30) KB_ROW00 KB_COL02_SW 17 18 *AZC099 I2C_5_SCL_CONN 6
16 17 (35) I2C_5_SCL_CONN 7
KB_COL03 (10) TRACKPAD_INT#_R R331 *0_4 TRACKPAD_INT_L_CONN
(30) KB_COL03 16
KB_ROW04 15 U22 8

e
(30) KB_ROW04 KB_ROW01 14 15 KB_ROW06 1 6 KB_ROW03 TP_PWR TP86
(30) KB_ROW01 KB_COL00 13 14 I/O 1 I/O 4 S5 S0/S3 Touch_Pad_8P
(30) KB_COL00 13
KB_ROW02_SW 12 2 5
12 GND VDD +V5A

3
KB_ROW03 11 R329
(30) KB_ROW03 10 11 KB_ROW05 3 4 KB_ROW01 Q36 4.7K_4

d
KB_ROW06 9 10 I/O 2 I/O 3
(30) KB_ROW06 KB_ROW05 8 9 *AZC099 2
(30) KB_ROW05 8

3
7 R330

i
6 7 Q35 4.7K_4 I2C_5_SDA_CONN D23 2 1 *5V/0.2P_4
KB_ROW10 5 6 2N7002K
(30) KB_ROW10 KB_ROW11 4 5 2 I2C_5_SCL_CONN D22 2 1 *5V/0.2P_4

1
(30) KB_ROW11 KB_ROW09 3 4

f
(30) KB_ROW09 KB_ROW08 2 3
(30) KB_ROW08 KB_ROW12 1 2 2N7002K
(30) KB_ROW12 1
C C

1
CON30X1_2
U21 +VBATA TP_PWR +15V +V3P3A

n
KB_ROW07 1 6 KB_COL06
I/O 1 I/O 4

3
R826 360@100K_4
2 5 Q96
GND VDD +V5A
R401 R411 R410
KB_COL04 3 4 KB_COL07 1M_6 22_8 1M_6 2
I/O 2 I/O 3 TP_INT_DISABLE (30)

3
o
*AZC099 360@2N7002K
U20
KB_COL01 1 6 KB_COL02_SW TP_SHDND 2

1
I/O 1 I/O 4

3
2 5
GND VDD +V5A
Q8

C
KB_ROW12 3 4 KB_ROW02_SW 2 AO3404
(30) TRACKPAD_PWREN

1
I/O 2 I/O 3 2 2
*AZC099
TP_PWR
R419 Q44 Q45

1
U19 R417 Q7 1M_6 2N7002K 2N7002K
KB_ROW04 1 6 KB_ROW00 100K/F_6 DTC144EU C213 TDC: 0.008A

1
I/O 1 I/O 4 *2.2n/50V_4
2 5 PEAK : 0.01A

a
GND VDD +V5A
Width : 20mil
KB_COL03 3 4 KB_COL05
I/O 2 I/O 3

t
B B
*AZC099

+VRTC +VRTC +VRTC

HOLELESS RESET

n
R370 100K_4 KB_ROW02_SW

C192 R378 *4.7K_4 KB_COL02

1-CHIP(KBC) R359
0.1U/10V_4 R377 *4.7K_4 EC_IN_RW

a
10K_4

1
+VRTC +VRTC U23
SLG_EC_RST# (21)

VDD
R340 *Short_4 PWR_BTN_L_4350 2 12 SLG_EC_RST# D26 EC_RST#
(31) SMC_ONOFF_N PWR_BTN_L EC_RST_L EC_RST# (30,33)

u
R354 RB500V-40
BATT_ENABLE 3 11 EC_IN_RW
BATT_ENABLE EC_IN_RW EC_IN_RW (35)
R356 *4.7K_4
(30,31,35,36) BC_ACOK R357 *Short_4 ACPRESENT_4137 4 10 EC_ENTERING_RW
AC_PRESENT EC_ENTERING_RW EC_ENTERING_RW (30)
1M/F_4
BATT_EN# KB_ROW02_SW 5 9 KB_ROW02
BATT_EN# (36) KSO_SW KSO_INV KB_ROW02 (30)
3

R358 1M/F_4 pullup at EC side

Q39 KB_COL02_SW 6 PAD_GND 8 KB_COL02

Q
KSI_SW KSI KB_COL02 (30)
PJA138K
BATT_ENABLE 2
GND

A A
Pin 3,5,8,11 Open Drain
C193
7

13

2.2U/6.3V_4 SLG4K4350VTR(TDFN-12)
Quanta Computer Inc.
1

co-layout 4K4108 and 4K4137

SLG4K4108 (AL004108000)
SLG4K4137 (AL004137000) PROJECT : ZHR
4K4137 PIN3 is BATT_ENABLE Size Document Number Rev
4K4137 PIN4 is AC_PRESENT KB/TP/HW RST 1A

Date: Monday, September 14, 2015 Sheet 29 of 47

5 4 3 2 1
 5 4 3 2 1

KBC(KBC) +V3P3A_EC

EMBEDDED CONTROLLER
30

l
R322 10K_4

CLK_PCI_EC R596 22_4 CLK_PCI_EC_R1 Y4 32.768KHZ

(12,27) CLK_PCI_EC
1 2 EC_XTAL_IN

U17 EC_SERVO_JTAG_RST_N R317 *10K_4

R585 10M_4

a
B25 B38 EC_XTAL_OUT C366 C365 EC_ACIN R592 10K_4
(12,27) LPC_LAD0 LAD0/GPIO112 XTAL1
B26 B37 EC_XTAL_IN
(12,27) LPC_LAD1 LAD1/GPIO114 XTAL2
B27 12p/50V_4 12p/50V_4 EC_RST# R588 10K_4
(12,27) LPC_LAD2 A26 LAD2/GPIO113 B40 USB_ILIM_SEL
(12,27) LPC_LAD3 XTAL USB_ILIM_SEL (28)

i
CLK_PCI_EC_R1 B29 LAD3/GPIO111 32kHZ_OUT/GPIO13
B28 PCI_CLK/GPIO117
(12,27) LPC_LFRAME# LFRAME#/GPIO120
PLTRST# A27 R608 *Short_4 EC_ACIN
(24,31,32,33,34) PLTRST# A28 LRESET#/GPIO116 B34
(12) LPC_CLKRUN_L LID_OPEN_OUT1_R_EC LID_OPEN_OUT1_R_EC R301 10K_4
D CLKRUN#/GPIO14 GPIO27 D

t
LPC B57 EC_ACIN_R R668 100K_4
GPIO30 A16 EC_GPIO31 R365 *Short_4 VOLUME_UP TP47 SOC_EC_SPI_WP# (34) LID_OPEN_OUT2_R R611 10K_4
B16 GPIO31 B35 SPI_WP_ME_GPIO33 R653 *100K_4
(29) KB_COL00 A15 KSI0/GPIO125/TRACEDATA3 GPIO33 B64 EC_GPIO34 R626 *Short_4 VOLUME_DOWN SPI_WP_ME (9,28)
(29) KB_COL01 B15 KSI1/GPIO126/TRACEDATA2 GPIO34/PWM2/TACH2PWM_OUT A32 TP84
(29) KB_COL02 KSI2/GPIO144/TRACEDATA1 GPIO35 SMC_ONOFF_N_EC (31)
A14 B68
+V3P3A_EC (29) KB_COL03 KSI3/GPIO32/TRACEDATA0 GPIO36 USB2_PWR_EN (27)
B14 SPI_WP_ME R296 *100K_4
(29) KB_COL04 B13 KSI4/GPIO142/TRACECLK A30
EC_ENTERING_RW

n
(29) KB_COL05 KSI5/GPIO40 ADC_TO_PWM_OUT/GPIO41 (29)
A13 A51 VOLUME_UP R372 *10K_4
(29) KB_COL06 KSI6/GPIO42 GPIO45/A20M/PVT_CS1# USB_OC1_L (34)
RP1 10K_10P8R A12 B24 EC_GPIO56 R610 *Short_4 EC_ADC0
10 1 KB_COL02 (29) KB_COL07 B12 KSI7/GPIO43 ADC_TO_PWM_IN/ADC0/GPIO56 TP80 VOLUME_DOWN R625 *10K_4
(21) EC_JTAG_TCK KSO0/GPIO0/JTAG_TCK
KB_COL06 9 2 KB_COL05
(21) EC_JTAG_TMS
A11
KSO1/GPIO100/JTAG_TMS ADC1/GPIO57
A22 EC_GPIO57 R328 *Short_4 EC_ADC1 NOTE: Remove PUs on VOLUME signals
KB_COL03 8 3 KB_COL04 B11 GPIO TP41
KB_COL01 7 4 KB_COL07
(21) EC_JTAG_TDI
A10 KSO2/GPIO101/JTAG_TDI B23 BC_PMON
after testing
(21) EC_JTAG_TDO KSO3/GPIO102/JTAG_TDO ADC2/GPIO60 BC_PMON (36)
KB_COL00 6 5 B10 A20 WIFI_PWREN

e
(29) KB_ROW00 KSO4/GPIO103/TFDP_DATA/XNOR ADC3/GPIO61 WIFI_PWREN (24)
A9 B21 EC_GPIO62
(29) KB_ROW01 KSO5/GPIO104/TFDP_CLK ADC4/GPIO62
A6 TP42
(29) KB_ROW02 KSO6/GPIO1
B6 A62
(29) KB_ROW03 KSO7/GPIO2 GPIO66 PCH_WAKE_EC_L (34)
A4 A46 EC_GPIO105 R289 *Short_4 USB_CTL1 +V3P3A_EC
(29) KB_ROW04 KSO8/GPIO3 GPIO105/TACH1 USB_CTL1 (27,28)
B5 B39
(29) KB_ROW05 KSO9/GPIO106 GPIO110 EC_REST_L (34)
B4 SMB_BC_CLK R332 4.7K_4
(29) KB_ROW06 KSO10/GPIO4
A3 B8 SMB_BC_DATA R613 4.7K_4
(29) KB_ROW07 KSO11/GPIO107 GPIO67 USB3_PWR_EN (28)
B3 A8 BATT,Charger

d
(29) KB_ROW08 KSO12/GPIO5 GPIO55 USB_OC0_L (34)
A2 B9
(29) KB_ROW09 B43 KSO13/GPIO6 GPIO210 A18 SUSPWRDNACK_SOC_EC (31,42)
(29) KB_ROW10 KSO14/GPIO7 GPIO211 PCH_SLP_SX_L (31,34)
B44 A24
(29) KB_ROW11 KSO15/GPIO10 GPIO200 PCH_SLP_S4_L (31,34)
B2

i
(29) KB_ROW12 KSO16/GPIO11
R496 *0_4 EC_GPIO12 A54 KEYBOARD
TP90 GPIO12/KSO17 A56 +V3P3A_EC
I2C0_CLK0/GPIO15 SMB_BC_CLK (36)
SERIRQ- NOT USED B59 SMB_BC_DATA (36) BATT,Charger
A29 I2C0_DAT0/GPIO16 EC_SENSOR_I2C1_SCL_EC R327 10K_4
(27,34) IRQ_SERIRQ SERIRQ/GPIO115
B65 A55 BOARD_ID1 EC_SENSOR_I2C1_SDA_EC R294 10K_4

f
(34) EC_SMI_3P3_L GPIO44/NSMI I2C0_CLK1/GPIO134
(34) EC_SOC_WAKE_SCI_N
A38
NEC_SCI/GPIO26 I2C0_DAT1/GPIO17
B58 BOARD_ID2 G-Sensor +V3P3_THM
R594 47K_4 VCC1_RST# B32 B47
nRESET_OUT/GPIO121 GPIO22/I2C1_CLK0 EC_SENSOR_I2C1_SCL_EC (35)
C (29,33) EC_RST#
B41
VCC1_RST#/GPIO131 GPIO23/I2C1_DAT0
A44
EC_SENSOR_I2C1_SDA_EC (35) G-Sensor SMB_THRM_CLK R630 10K_4 C
B45 SMB_THRM_DATA R631 10K_4
(34) PCH_RSMRST_L GPIO143/RSMRST#
(42) RSMRST_N_PWRGD
A36 B48
VCC_PWRGD/GPIO63 GPIO20/I2C2_CLK0
GPIO21/I2C2_DAT0
A45 TP91 Thermal
R589 A25

n
(21) EC_SERVO_JTAG_RST_N TP96
JTAG_RST# B66 D9
GPIO25/I2C3_DAT0 SMB_THRM_DATA (33)
100K/F_4 CAP A7
CAP SIDEBAND SMBUS/I2C GPIO24/I2C3_CLK0
A63 SMB_THRM_CLK (33) Thermal LID_OPEN_OUT1_R RB500V-40 LID_OPEN_OUT1_L (21,27)
C197 pullup at HSR side
1u/6.3V_4 A43 can be wake up cntrl GPIO
(21) EC_UART0_RX GPIO162/RXD
(21) EC_UART0_TX
B46 UART B19 PROCHOT_EC LID_OPEN_OUT1_R_EC R830 33_4 LID_OPEN_OUT1_R
GPIO165/TXD/SHD_CS1# GPIO151

o
B60 BOARD_ID0
LED0/GPIO154 A57 EC_GPIO155 R578 *0_4 C427
A33 LED1/GPIO155 B61 LID_OPEN_OUT2_R CORE_PWROK_R (12,16,31)
R290 *0_4 EC_GPIO46 180p/50V_4
TP89 R308 *0_4 EC_GPIO47 B36 PS2CLK0/GPIO46 LED2/GPIO156
TP95 A31 PS2DAT0/GPIO47 A49
(33) TOUCHPANEL_PWREN PS2CLK1/GPIO50 GPIO157/BC_CLK PCH_SUSPWRDNACK (34)
B33 B53 D21
(31) DELAY_ALL_SYS_PWRGD B20 PS2DAT1/GPIO65 GPIO160/BC_DAT A50 PCH_PWRBTN_L (16,34)
GPIO LID_OPEN_OUT2_R RB500V-40 LID_OPEN_OUT2_L (21,27)
(34) PCH_SUS_STAT_L PS2CLK2/GPIO51 GPIO161/BC_INT# GYRO_INT1 (33)
B18
(29) TP_INT_DISABLE PS2DAT2/GPIO52
B55 D18
(29) TRACKPAD_PWREN GPIO53/PS2_CLK3

C
B56 A58 (29,31,35,36) BC_ACOK RB500V-40 EC_ACIN
(34) EC_KBD_IRQ# GPIO152/PS2_DAT3 GPIO163 VP9_CODEC_RESET# (32)

(33) GYRO_INT2 B17 GPIO A21

GPIO127/PECI_RDY GPIO206 PCH_SLP_S3_L (31,34,39,41)
ALL_SYS_PWRGD A37
(31) ALL_SYS_PWRGD GPIO130
EC_PLUG_DETECT A40 B30 EC_STRAP_GPIO1 C354
GPIO132/PECI_DAT GPIO123 EC_STRAP_GPIO1 (12)
TP36BATT_BLUE R355 *Short_4 EC_PWM0 A60 A41 0.1U/10V_4
(33) BAT_LED0 GPIO133/PWM0 GPIO202 EC_BL_DISABLE_L (20)
R361 *0_4 PROBE_DETECT_L A61 B51 USB_C_MUX_CROSS_BAR_POL R658 *Short_4
(25) LTE_PWREN GPIO135/KBRST GPIO201 STARTUP_LATCH_SET (31)
R352 *Short_4 EC_PWM1 A59 A52
(33) BAT_LED1 GPIO136/PWM1 GPIO203 B62 SMC_SHUTDOWN (31) PROCHOT# (12,21)
BATT_Amber GPIO204

3
THERMAL_PROBE_EN_L B54
TP79PWR_Blue R284 *Short_4 EC_PWM3 A39 GPIO140/TACH2/TACH2PWM_IN Q78
(33) PWR_LED0

a
B49 GPIO141/PWM3/LED3 B67
Suspend_Amber (33) PWR_LED1
R582 *Short_4 EC_GPIO145
GPIO145 GPIO54/PVT_MOSI
EC_SPI_MOSI_R R375 GD@100_4 EC_SPI_MOSI EC_SPI_MOSI (21)
A17 A47 EC_SPI_MISO_R R288 GD@100_4 EC_SPI_MISO EC_SPI_MISO (21) PROCHOT_EC 2
GPIO147 GPIO164/PVT_MISO B1 EC_SPI_CLK_R R376 GD@100_4 EC_SPI_CLK
GPIO153/PVT_SCLK EC_SPI_CLK (21)
B A48 EC_SPI_CS#_R R287 GD@100_4 EC_SPI_CS# EC_SPI_CS# (21) B
GPIO146/PVT_CS0#

t
R584 *Short_4 ALS_INT# R664 *Short_4 R635 2N7002K
(10) EC_KBD_ALERT EC_HIB_L (31)
B42 FLASH A64 SW_OPEN_EC
+VRTC

1
VREF_PECI GPIO64/SHD_MOSI B50 USB_CHG_DET_EC TP45 +V3P3A_EC 100K_4
GPIO124/SHD_MISO A1 USB_PD_EC_INT TP37
C378 0.1U/10V_4 GPIO122/SHD_SCLK B52 WLAN_OFF_L R285 10K_4 TP46
A34 GPIO150/SHD_CS0#
VBAT
B22
POWER

n
+V3P3A_EC_ANA AVCC WLAN_OFF_L (24)

+V3P3A_EC R618 *SHORT_6

B7
A19
B31
A42
VCC1_1
VCC1_2
VCC1_3
GND
VSS_VBAT
A35

A23
EC HIB WAKE SOURCES +VRTC

C383 C382 A53 VCC1_4 AVSS

VCC1_5 (31) EC_WAKE_L
B63 A5 R559

a
0.1U/10V_4 1000P/50V_4 VCC1_6 VSS
100K_4
133
THM-GND PWR_BTN_L D20 RB500V-40
(21,29,31) PWR_BTN_L
MEC1322-LZY DQFN132
EC_WAKE_L

+V3P3A

u
+V3P3A_EC
RAM ID - USE FOR BOARD ID

3
R636 2.2_6 +V3P3A_EC
1 2 Q63

3
R616 *100K_4 BOARD_ID0 R612 100K_4 Q62
C187 C390 C384 C371 C182 C362 R656 *100K_4 BOARD_ID1 R654 100K_4 LID_OPEN_OUT1_L C352 0.01U/50V_4 LID_OPEN_L_FET 2
R657 100K_4 BOARD_ID2 R655 *100K_4
0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 BC_ACOK C347 0.1U/10V_4 BC_ACOK_FET 2
0818 for PVT, changed board ID from 011 to 100 R540 PJA138K
47K_4

1
R510 PJA138K

Q
47K_4

1
A A

+V3P3A_EC_SPI
+V3P3A_EC_SPI SPI NOR FLASH +V3P3A_EC Q73 PJA138K +V3P3A_EC_SPI +V3P3A_EC_GD
U16
SOC_EC_SPI_WP# R286 *Short_4 EC_SPI_WP# R267 10K_4 EC_SPI_MISO_R 2 8 1 3 D1006 RB500V-40 Stage EC_ID3 EC_ID2 EC_ID1
EC_SPI_HOLD# R344 10K_4 SO VDD
EC_SPI_MOSI_R R342 10K_4 EC_SPI_MOSI_R 5 7 EC_SPI_HOLD#
EC_SPI_MISO_R R273 10K_4 SI HOLD C189 R804 *0_4 Proto 0 0 0
Quanta Computer Inc.
2

EC_SPI_CS#_R R280 10K_4 EC_SPI_CLK_R 6 3 EC_SPI_WP# 0.1u/10V_4

EC_SPI_CLK_R R343 10K_4 SCK WP pre-EVT 0 0 1
1 4 +V5A
EC_SPI_CS#_R
CE VSS EVT 0 1 0 PROJECT : ZHR
W25X40CLSSIG Size Document Number Rev
DVT 0 1 1 KBC 1A

Date: Monday, September 14, 2015 Sheet 30 of 47

5 4 3 2 1
 5 4 3 2 1

KBC(KBC) (30) EC_HIB_L

31

l
PWRBTN SMC_ONOFF_N (29)
R660 100K_4

+V3P3A_LDO U1010
C412 0.1u/10V_4

EC_HIB_L 1 8
A1 VDD +V3P3A_LDO
R5 10K_4 +V3P3A C413 0.1u/10V_4
+V3P3A_LDO D12 2 7 PP3300_DSW_EN_R R236 *Short_4 PP3300_DSW_EN
B1 Y1

a
RB500V-40 U1011
U1 SMC_ONOFF_N_EC (30) 1 5 5 3
C1 0.1U/10V_4
1 20 R8 10K_4 R223 *Short_4 EC_WAKE_L_R 2 A2 Y2
VDD SMC_ONOFF_N +V3P3A_PRIME (30) EC_WAKE_L 3 4 EC_WAKE 6 4
R3 10K_4 2 19 B2 VSS C411
+V3P3S

i
V1P8S_PWRGD COREPWROK CORE_PWROK_R (12,16,30)
TC7SZ14FU NL27WZ02USG
3 18 *0.1U/10V_4
(40) VDDQ_PWRGD VDDQ_PWRGD STARTUP_LATCH_SET STARTUP_LATCH_SET (30)
R2 10K_4 4 17
+V3P3S V1P5S_PWRGD DELAY_ALL_SYS_PWRGD DELAY_ALL_SYS_PWRGD (30)

t
+V3P3A_LDO R4 *100K_4
D 5 16 D
(21,29,30) PWR_BTN_L PS_ON_SW_N BC_ACOK BC_ACOK (29,30,35,36)
R1 *Short_4
(27) PWR_BT_YOGA 6 15
+VDDQ_VTT VDDQ_VTT PLTRST_3P3_N PLTRST# (24,30,32,33,34)
7 14 VR_ALW_EN
(30) ALL_SYS_PWRGD ALL_SYS_PWRGD VR_ALW_EN
R277 10K_4 8 13
+V3P3S VCC0_PWRGD DDR3_DRAM_PWRGD DDR3_DRAM_PWROK (6)

n
R824 *10K_4 R6 *Short_4 9 12 +V3P3A_LDO
+V3P3A_PRIME (38) VCC_PWRGD VCC1_PWRGD DDR3_VCCA_PWRGD R49 10K_4 +VDDQ_M0_M1_R
10 11
(30) SMC_SHUTDOWN SMC_SHUTDOWN GND
DDR3_VCCA_PWROK (7)
R12
SLG7NT4317 R52 10K_4
pin7,12,13,14,19,20 are OD +VDDQ_M0_M1_R 100K_4
R11 *0_4

e
D24
VR_ALW_EN RB500V-40
(43) VR_ALW_EN V5A_EN (37)
D25
PP3300_DSW_EN RB500V-40

R807
100K_4

id
KBC(KBC) POWER SEQUENCING

f
Dynamic VNN-->RB/RC/RD/QA stuff
RA/RE/QB unstuff RA (41) VNN_PWRGD
VNN_PWRGD

n
C C

Fixed VNN-->RA/RE/QB stuff If +VNN & +V1P05A Merge (41) VNN_EN

VNN_EN

RB/RC/RD/QA unstuff R456 *NVN@0_4

o
PCH_SLP_S4_L R561 *Short_4 VDDQ_EN
(30,34) PCH_SLP_S4_L VDDQ_EN (40)

V3P3A_PWRGD R469 *VN@Short_4 VNN_EN VNN_PWRGD R491 *VN@Short_4 V1P05A_EN

(37) V3P3A_PWRGD V1P05A_EN (42,43)
PCH_SLP_S3_L VGG_EN
RC RD (30,34,39,41) PCH_SLP_S3_L
R333 10K_4 VGG_EN (39)

R485
3
RB *VN@100K_4

3
Q50 VGG_PWRGD R177 *Short_4 VCC_EN VCC_EN (38)

C
(39) VGG_PWRGD

(30,42) SUSPWRDNACK_SOC_EC
SUSPWRDNACK_SOC_EC R483 *VN@Short_4 SUSPWRDNACK_SOC_EC_F1 2
SUSPWRDNACK_SOC_EC R489
RE *NVN@0_4 SUSPWRDNACK_SOC_EC_F2 2
Q53

QB PCH_SLP_SX_L R345 *0_4 VDDQ_VTT_EN

(30,34) PCH_SLP_SX_L VDDQ_VTT_EN (40)
VN@2N7002K

QA *NVN@2N7002K
1

1
PCH_SLP_S3_L R338 *Short_4

ta
SVID(CPU) CLK DATA ALERT +V1P05A_R_SOC +V1P05A_R_SVID

B B
R315 *Short_4

Dynamic VNN-->RE/RF/RG stuff 453 ohm Dynamic VNN-->RK stuff 49.9 ohm

n
Dynamic VNN-->RA/RB/RC stuff 301 ohm
RD stuff 200 ohm RJ stuff 16.9 ohm
Fixed VNN-->RE/RF stuff 301 ohm, Fixed VNN-->RK unstuff
Fixed VNN-->RA/RB stuff 200 ohm, RG/RJ unstuffed

a
RC/RD unstuffed +V1P05A_R_SVID

u
+V1P05A_R_SVID

RE R230
SP@453/F_4 R231
+V1P05A_R_SVID +V1P05A +V1P05A
200/F_4
(12) SVID_DATA VCC_ALERT_N
R217 49.9/F_4
SVID_DATA VCC_VDIO VCC_ALERT_N (38)
R216 16.9/F_4
VCC_VDIO (38)
R232 R438 R169 SVID_ALERT#
+V1P05A (12) SVID_ALERT#
SP@301/F_4 SP@301/F_4 VN@301/F_4

Q
RA RB RC R436 49.9/F_4 VGG_ALERT_N
VGG_ALERT_N (39)

RD VN@200/F_4 VNN_VCLK RK
R171
VNN_VCLK (41)
RF R427
SP@453/F_4 R175 [email protected]/F_4 VNN_ALERT_N
VNN_ALERT_N (41)
R215 200/F_4 VCC_VCLK
VCC_VCLK (38)
A A
R437 16.9/F_4 VGG_VDIO
SVID_CLK (12) VGG_VDIO (39)
SVID_CLK R442 200/F_4 VGG_VCLK
VGG_VCLK (39)
+V1P05A

Quanta Computer Inc.

RG R180
VN@453/F_4
RJ PROJECT :ZHR
Size Document Number Rev
R186 [email protected]/F_4 VNN_VDIO PWRBTN/PS/SVID 1A
VNN_VDIO (41)
Date: Monday, September 14, 2015 Sheet 31 of 47
5 4 3 2 1
 5 4 3 2 1

VIDEO CODEC

l
Video codec(VDC) U7A **VC@VP9 VIDEO CODEC

R218
R220
**VC@0_4
**VC@0_4
+V3P3S_CODEC
+V1P05A_CODEC
32

a
KEPL_GND C242 *[email protected]/16V_4 +V1P05A_CODEC_G12
+V3P3S_CODEC +V1P05A_CODEC_VDD
R472 *VC@0_6

i
J7 +V3P3S_USB_VP9 +V3P3S_CODEC
M11 VDD33_USB J9 +V1P05A_USB_VP9 C267 +V1P05A_CODEC
M10 RX_M_USB DVDD_USB H9 U7B **VC@VP9 VIDEO CODEC
RX_P_USB VP_USB *VC@1U/6.3V_4
D D
RD

t
M8 USB M4
M7 TX_M_USB DM_USB M5 R92 *VC@0_6 +V1P05A_CODEC_G12 G12 A1
TX_P_USB DP_USB +V1P05A_VPTX_PCIE H12 AVDD_PLL VSS A3
R86 *VC@200/F_4 RESREF_USB_R M9 AVSS_PLL VSS A6
RESREF_USB +V1P05A_VP_PCIE C268 B9 VSS A9
D9 IO_VDD VSS A12
**[email protected]/16V_4 IO_VDD VSS B4
VSS

n
A5 C9 +V3P3S_CODEC_C9 R439 *VC@0_6 B5
(9) PCIE_TX0_IMAGE_DN A4 RX0_PCIE_N VPH_PCIE C10 C7 VSS B6
(9) PCIE_TX0_IMAGE_DP RX0_PCIE_P VP_PCIE B10 C8 VDD VSS B7
C119 *[email protected]/16V_4 PCIE_RX0_IMAGE_C_DN A8 VPTX0_PCIE C11 C264 D7 VDD VSS B8
(9) PCIE_RX0_IMAGE_DN A7 TX0_PCIE_N VPTX1_PCIE D8 VDD VSS C5
C120 *[email protected]/16V_4 PCIE_RX0_IMAGE_C_DP
(9) PCIE_RX0_IMAGE_DP TX0_PCIE_P PCIE E7 VDD VSS C6
*VC@1U/6.3V_4
A11 E8 VDD VSS D2

e
C12 CLK_PCIE_N A10 CLK_PCIE_IMAGEN_DN (9,32) E9 VDD VSS D5
(9) PCIE_TX1_IMAGE_DN RX1_PCIE_N CLK_PCIE_P CLK_PCIE_IMAGEP_DP (9,32) VDD VSS
B12 E10 D6
(9) PCIE_TX1_IMAGE_DP RX1_PCIE_P B11 PCIE_CLKREQ_IMAGE#_R F7 VDD VSS D10
KEPL_GND
C76 *[email protected]/16V_4 PCIE_RX1_IMAGE_C_DN F12 CLKREQ_PCIE_N D12 RESREF_PCIE_R F8 VDD VSS D11
(9) PCIE_RX1_IMAGE_DN TX1_PCIE_N RESREF_PCIE VDD VSS
C80 *[email protected]/16V_4 PCIE_RX1_IMAGE_C_DP E12 F9 E2
(9) PCIE_RX1_IMAGE_DP TX1_PCIE_P VDD VSS
R105 F10 E5
F11 VDD VSS E6

d
*VC@200/F_4 VDD VSS
+V3P3S_CODEC G7 E11
R96 **[email protected]_4 VP9_GPIO0 L1 J2 ZQ1_DDR_R G8 VDD VSS F5
R100 **[email protected]_4 VP9_GPIO1 K2 GPIO0 ZQ1_DDR G9 VDD VSS F6
GPIO1 VDD VSS

2
R85 *VC@1M_4 R91 **[email protected]_4 VP9_GPIO2 L2 G5 +V1P8A OR +V1P8S? G10 G3

i
R88 **[email protected]_4 VP9_GPIO3 M2 GPIO2 ATO_DDR G6 R103 G11 VDD VSS H3
VP9_GPIO_R K1 GPIO3 DTO0_DDR H6 +V1P8_KEPL H7 VDD VSS H8
GPIO4 DTO1_DDR *VC@240/F_4 VDD VSS
M3 H10
L3 GPIO5 VSS H11
Y1 GPIO6 VSS

1
f
K3 L12 +V1P8A_DDR_CODEC R84 *VC@0_4 J8
CODEC_XO 1 3 CODEC_XI R87 J3 GPIO7 VDD1_DDR VSS J10
C 2 4 K4 GPIO8 A2 VSS J11 C
*VC@0_4 GPIO9 VDDQ_DDR VSS
L6 B1 K11
J6 GPIO10 VDDQ_DDR B2 VSS L4
C61 *VC@24MHz C60 K5 GPIO11 VDDQ_DDR B3 +V1P24A_CODEC VSS L5
*VC@33P/50V_4 *VC@33P/50V_4 K6 GPIO12 VDDQ_DDR C2 VSS L7
GPIO13 VDDQ_DDR VSS
K9 SYSTEM DDR C3 CAD NOTE: L8

n
VP9_SPI_CLK K7 GPIO14 VDDQ_DDR C4 VSS L10
GPIO15 VDDQ_DDR VSS
TP88 VP9_SPI_CS K8
GPIO16 VDDQ_DDR
D3 MAKE +V1P24A_CODEC A POWER SHAPE VSS
L11
TP92 VP9_SPI_MOSI L9 D4 M1
KEPL_GND KEPL_GND TP93 VP9_SPI_MISO K10 GPIO17 VDDQ_DDR E3
NEAR THE CODEC VSS M6
TP94 GPIO18 VDDQ_DDR E4 +V1P24A_CODEC VSS M12
CODEC_XI J12 VDDQ_DDR F3 VSS
CODEC_XO K12 OSC_XI VDDQ_DDR F4

o
OSC_XO VDDQ_DDR G4
VP9_RXD_UART E1 VDDQ_DDR H4
TP83 VP9_TXD_UART D1 RXD_UART VDDQ_DDR H5 R119
TXD_UART VDDQ_DDR J4
TP87
CODEC_RESET# J1
RESET_N
VDDQ_DDR
VDDQ_DDR
J5
*[email protected]/F_4
BCRD says RA/RB/RC/RD are EMI bead 75ohm at 100MHz
R168 *VC@0_4 H1 C1 VREF_DDR_R
(30) VP9_CODEC_RESET# JTAG_TCK VREF_DDR +V3P3S +V3P3S_CODEC +V1P0_KEPL +V1P05A_CODEC
F1
R138 **VC@0_4 F2 JTAG_TDI +V1P25_KEPL +V1P24A_CODEC
(24,30,31,33,34) PLTRST# JTAG_TDO

C
G1
H2 JTAG_TMS C109 R151 *VC@0_6 R461 *VC@0_6
G2 JTAG_TRST_N *VC@1U/6.3V_4 R128 R109 *VC@0_6
JTAG_TEST_MODE *[email protected]/F_4

R208 +V1P05A_CODEC +V1P05A_VP_PCIE +V1P05A_CODEC +V1P05A_VPTX_PCIE

*VC@0_4

R465 *VC@0_6 R467 *VC@0_6

a
B CLK_PCIE_IMAGEN_DN B
CLK_PCIE_IMAGEN_DN (9,32)
R141 RA C269
*[email protected]/16V_4 RA C262 C276
*VC@100/F_4 0909 changed Footprint of video codec *VC@1U/6.3V_4 *[email protected]/16V_4

t
CLK_PCIE_IMAGEP_DP
CLK_PCIE_IMAGEP_DP (9,32)

+V1P24A_CODEC
+V3P3S_CODEC

n
+V1P05A_CODEC +V1P05A_CODEC_VDD

+V1P05A_CODEC
C116 C118 C279 C278 C281 C280 R513 *VC@0_6
*VC@10U/6.3V_6 *[email protected]/16V_4 *[email protected]/16V_4 *[email protected]/16V_4 *[email protected]/16V_4 *[email protected]/16V_4 C99 C258 C246 C266 C261 C265

a
*VC@10U/6.3V_6 *[email protected]/16V_4 *[email protected]/16V_4 *[email protected]/16V_4 *[email protected]/16V_4 *[email protected]/16V_4
RC C417
C250 C102 C256 C257 *VC@1U/6.3V_4
*VC@10U/6.3V_6 *VC@10U/6.3V_6 *[email protected]/16V_4 *[email protected]/16V_4

u
+V3P3S_CODEC
+V1P8_KEPL
(9) PCIE_CLKREQ_IMAGE# +V1P05A_CODEC_VDD

A R825 A
3

*VC@10K_4
Q97

Q
C249 C248 C97 C263 C272 C251 C59 C55
2 *[email protected]/16V_4 *[email protected]/16V_4 *[email protected]/16V_4 *[email protected]/16V_4 *[email protected]/16V_4 *[email protected]/16V_4 *[email protected]/16V_4 *VC@10U/6.3V_6
3

Q98
*VC@2N7002K
2 PCIE_CLKREQ_IMAGE#_R Quanta Computer Inc.
1

*VC@2N7002K
PROJECT : ZHR
0818 unstuffed related RC components of Kepler Size Document Number Rev
1

1A
VIDEO CODEC
Date: Monday, September 14, 2015 Sheet 32 of 47
5 4 3 2 1
 5 4 3 2 1

Thermal (THM)
THERMAL SENSOR SENSORS/Touch screen Board/LED Board

l
Base: PIN 1
ACCELEROMETER
33
+V3P3A +V3P3_THM Emitter: PIN 2

a
+V3P3_THM Collector: PIN 3

Place oo PCB TOP G-Sensor (ACS) R822 *GS@Short_4

Remote Temp.

i
R481 *Short_4
C275 0.1U/10V_4 GYRO_INT1 D27 *GS@RB500V-40GYRO_INT1_D
(30) GYRO_INT1

3
t
D D
ADDR: 0X0F(Write: 0x1E,Read: 0x1F)

7
U9 TMP432ADGSR H_THRMDA 2 U15
R144 *Short_4 EC_SMB2_CLK_THM 10 1

INT
(30) SMB_THRM_CLK SCLK VCC MMBT3904 Q37 +V3P3A_SENSOR 5 10 EC_SENSOR_I2C1_SDA (33,35)

1
R145 *Short_4 EC_SMB2_DATA_THM 9 2 C288 Vdd SDA
(30) SMB_THRM_DATA SDA DP1 2200P/50V_4 1 9

n
IO Vdd SCL EC_SENSOR_I2C1_SCL (33,35) +V3P3S
TEMP_ALERT# 8 3 H_THRMDC
(12) TEMP_ALERT# ALERT# DN1

ADDR
OVERT# 7 4 H_THRMDA2 C172 C168 6 +V3P3A_SENSOR R297 *GS@0_4
OVERT# DP2 [email protected]/10V_4 GS@1U/6.3V_4 4 RSVD

NC
NC
6 5 GND

e
GND DN2

3
C270 GS@KXCJ9-1008 +V3P3A

2
3
8
ADDR=0x4C 2200P/50V_4 2
Place oo PCB BOT H_THRMDC2
MMBT3904 Q41
R672 *GS@Short_4
Local Temp.

1
d
close to pin1
R115 *Short_4 EC_RST#
EC_RST# (29,30) Place oo PCB ? R275
*GS@Short_4
Remote Temp.

f i
C
Touch screen(TSN) Touch screen(TSN)+VBATA PP5000_TS +15V +V5A
+V3P3A
C

R659 *TS@0_4

n
PLTRST# (24,30,31,32,34)
R568 *TS@0_4 SOC3V3_RSTOUT_R TDC : 0.038A R9 R22 R383
PEAK : 0.05A *TS@1M_6 *TS@22_8 *TS@1M_6

3
CN7 D29 *TS@RB500V-40 TOUCHPANEL_PWREN
TOUCHPANEL_PWREN (30) Width : 20mil R140 R194

o
13 1 *TS@10K_4 *TS@10K_4
14 2 SOC3V3_RSTOUT_L C14 [email protected]/50V_4 2
TOUCH_RSTD
3 TS_INT#
TS_INT# (35)

3
4 I2C_0_SDA_CONN TS
I2C_0_SDA_CONN (35)
5 I2C_0_SCL_CONN Q2 SOC3V3_RSTOUT_R
6 PP5000_TS I2C_0_SCL_CONN (35) TOUCHPANEL_PWREN_R 2 *TS@AO3404
PP5000_TS

1
7 2 2

3
8 DB_SENSOR_PWR

C
PP5000_TS
9 EC_SMB1_SENSOR_DATA_CONN R20 *GS@Short_4 EC_SENSOR_I2C1_SDA (33,35) R381 Q40 Q42 C199

1
10 EC_SMB1_SENSOR_CLK_CONN R21 *GS@Short_4 Accelerometer Q1 *TS@1M_6
EC_SENSOR_I2C1_SCL (33,35)
11 GYRO_INT2_D D28 *GS@RB500V-40 GYRO_INT2 (30) *TS@DTC144EU *[email protected]/50V_4 2

3
12 R823 *GS@Short_4 R677
*TS@47K_4 Q87
GS@TS@SENSOR_TS_B *TS@2N7002K
2

1
PP5000_TS +V5A

a
ADDR: 0X0E *TS@2N7002K*TS@2N7002K
R198 Q86
B R17 TS@0_6 *TS@100K/F_4 *TS@2N7002K B

1
C6 C4 C3
*TS@1U/6.3V_4 [email protected]/10V_4 [email protected]/10V_4

n
+V3P3A R673 *GS@Short_4

+V5S
+V3P3S R19 *GS@0_4 DB_SENSOR_PWR

a
R228 *TS@0_6
U1013
C7 +V5A A2 A1 R247 *TS@0_6
IN OUT PP5000_TS
[email protected]/10V_4 C421 C422

u
*[email protected]/10V_4 *[email protected]/10V_4 TOUCHPANEL_PWREN R572 *TS@0_4 TOUCHPANEL_PWREN_R B2 B1
EN GND

*TS@TPS22930
R7
*TS@100K/F_4 0819 unstuffed U1013

Q
A LED board(UIF) +V3P3A A

CN15
6 7
6 G1
BATT_BLUE BAT_LED0 5 8
BATT_Amber
(30)
(30)
BAT_LED0
BAT_LED1
BAT_LED1 4 5 G2
4
Quanta Computer Inc.
PWR_Blue (30) PWR_LED0
PWR_LED0 3
3
Suspend_Amber PWR_LED1 2
(30) PWR_LED1
1 2 PROJECT : ZHR
1 Size Document Number Rev
LED_B_6P 1A
SENSORS/LEDB
Date: Monday, September 14, 2015 Sheet 33 of 47
5 4 3 2 1
 5 4 3 2 1

LEVEL TRANSLATOR 1

l
SoC(CPU) PWRON SEQUENCE
+V1P8A
+V3P3A PWRON SEQUENCE 34

a
+V1P8A +V3P3A
R235
10K_4 +V1P8A R576

i
R550 10K_4 *10K_4

2
ILB_SERIRQ 1 3 IRQ_SERIRQ SOC_PWRBTN# 1 3
(12) ILB_SERIRQ IRQ_SERIRQ (27,30) (12) SOC_PWRBTN# PCH_PWRBTN_L (16,30)

t
D Q25 FDV301N Q71 PJA138K D

R571 *0_4

+V1P8A +V3P3A

R634 10K_4

n
PMC_SUS_STAT# 1 3
(12) PMC_SUS_STAT# PCH_SUS_STAT_L (30)
Q79 PJA138K SOC_RSMRST# R593 *Short_4
(12,16) SOC_RSMRST# PCH_RSMRST_L (30)

R586

e
*100K/F_4

GND
+V1P8A
+V1P8A +V3P3A

2
R316 10K_4 +V3P3A
R812 10K_4
2 PMC_SUSPWRDNACK 1 3
(12) PMC_SUSPWRDNACK PCH_SUSPWRDNACK (30)

i
PCH_WAKE_L 1 3
(12) PCH_WAKE_L PCH_WAKE_EC_L (30)
Q29 PJA138K
Q90 PJA138K

R813 *0_4

f
Q70A PJ4N3KDW
SLP_S3# 4 3 PCH_SLP_S3_L
(12,22,42,43) SLP_S3# PCH_SLP_S3_L (30,31,39,41)
+V1P8A +V3P3A

5
+V1P8A R579 *Short_4 SLP_S3_S4_GATE R564 10K_4
C R814 10K_4 +V3P3A_PRIME
C
2

n
R325 10K_4

2
SOC_WAKE_SCI_N 1 3
(10,23) SOC_WAKE_SCI_N EC_SOC_WAKE_SCI_N (30)
Q91 PJA138K SLP_S4# 1 6 PCH_SLP_S4_L
(12) SLP_S4# PCH_SLP_S4_L (30,31)
R815 *0_4 Q70B PJ4N3KDW

+V1P8A +V3P3A

o
R816 10K_4
2

EC_SMI_L 1 3 +V1P8A
(10,23) EC_SMI_L EC_SMI_3P3_L (30) +V3P3A
Q92 FDV301N
R313 *10K_4

2
R817 *0_4

C
+V1P8A +V3P3A SLP_S0IX# 1 3 PCH_SLP_SX_L
(12,42) SLP_S0IX# PCH_SLP_SX_L (30,31)

R818 10K_4 Q28 *PJA138K

2

KBD_IRQ# 1 3
(10,23) KBD_IRQ# EC_KBD_IRQ# (30)
Q93 FDV301N
+V3P3A_PRIME
R819 *0_4 +V1P8A +V3P3S +V3P3A_PRIME

a
+V1P8S
R14 10K_4
R337 *10K_4 R552 10K_4

2
+V1P8S +V1P8A +V3P3A

t
SOC_PLTRST# 1 3
(12,16,19) SOC_PLTRST# PLTRST# (24,30,31,32,33)
R820 *10K_4 SOC_PLTRST# 1 3
TPM_PLTRST# (27)
R821 10K_4
2

Q5 PJA138K R13
B *100K_4 Q24 PJA138K B
SOC_REST_BTN# 1 3
(12,16,21) SOC_REST_BTN# EC_REST_L (30) PLTRST# R575 *0_4
Q94 PJA138K

n
R452 *0_4

ROM WP +V1P8A_ME

a 2
SOC_SPI_WP# 1 3
(9) SOC_SPI_WP# SOC_EC_SPI_WP# (30)
pullup at EC ROM side
Q23 PJA138K

u
R259 *0_4

USB OC USB3 OC(UB3)

+V3P3A

Q
+V1P8A

R279 10K_4
2

(11,28) USB_OC0# USB_OC0# 1 3

USB_OC0_L (30)

A A
Q27 PJA138K

+V1P8A +V3P3A

R321 10K_4
USB2 OC(UB2) Quanta Computer Inc.
2

USB_OC1# 1 3
(11,27) USB_OC1# USB_OC1_L (30) PROJECT : ZHR
Size Document Number Rev
Q31 PJA138K LEVEL TRANSLATOR 1 1A

Date: Monday, September 14, 2015 Sheet 34 of 47

5 4 3 2 1
 5 4 3 2 1

NOTE:USE 4 BIT LEVEL TRANSLATORS

LEVEL TRANSLATOR 2
35

l
TRACK PAD I2C_5 SIGNALS
LTE(LTE) +V1P8A
LTE SIGNALS WiFi(NGF) +V1P8A
WIFI SIGNALS Trackpad(TPD)
+V1P8A +V1P8A
R95 U6 +3V_LTE U11 +V1P8A +V3P3A_WIFI

a
*3G@10K_4 R204
1 5 10K_4 1 5
NC VCC NC VCC Hugo had the level shifter also

2
1
C73 R104 R226
LTE SUSCLK WIFI SUSCLK

i
2 *[email protected]/10V_4 *3G@10K_4 2 C146 10K_4 I2C_5_SDA 1 3 I2C_5_SDA_CONN
(12,35) PMC_SUSCLK0 (12,35) PMC_SUSCLK0 (10) I2C_5_SDA I2C_5_SDA_CONN (29)

2
A A 0.1u/10V_4

2
3 4 3 4 Q76 FDV301N
GND Y LTE_SUSCLK (25) GND Y WIFI_SUSCLK (24)
R623 *0_4 R628 2.2K_4

t
D D
*3G@74AUP1G07GW LTE SUSCLK is must required for bruce modem 74AUP1G07GW +V1P8A
+V3P3A_WIFI (S5) R627 2.2K_4
TP_PWR
(S0/S3)

2
+V1P8A +3V_LTE +3V_LTE R507 I2C_5_SCL 1 3 I2C_5_SCL_CONN
+V3P3A_WIFI (10) I2C_5_SCL I2C_5_SCL_CONN (29)
*10K_4

n
WIFI WAKE(OD) Q75 FDV301N
R426 R515
WLAN_WAKE_L (24)
*3G@10K_4 R430 *10K_4 R620 *0_4
(12) SOC_PMC_WAKE#

5
*3G@100K/F_4

6
R429
*3G@10K_4 2 3 4

e
LTE_DISABLE Q61B
(9) LTE_DISABLE# LTE_DISABLE_L (25)

1
*PJ4N3KDW Q61A
Touch Screen(TSN) Note that there have pull up resistors on I2C/INT on touch controller board
5

*PJ4N3KDW

4 3 2 6 SOC_PMC_WAKE# R516 *Short_4 WLAN_WAKE_L Hugo had the level shifter also
Q46B TOUCH SCREEN I2C_0 SIGNALS
1

Q46A *3G@PJ4N3KDW

d
*3G@PJ4N3KDW
+V1P8A
+V3P3A_WIFI +V3P3A_WIFI
+V1P8A +3V_LTE +3V_LTE +V1P8A

i
R241 R225
10K_4 10K_4 R23 *TS@10K_4 +V3P3A
R435 +V1P8A R406 *TS@10K_4

2
R97 R434 *3G@10K_4 WIFI_DISABLE R229
10K_4 *3G@10K_4 10K_4 Q3 TS@PJA138K

f
(9) WIFI_DISABLE# 1 3
R276 *TS@0_4 TS_INT#
RF_EN (24) (9) TOUCH_INT# TS_INT# (33)

5
LTE_WAKE(OD) LTE_WAKE_L (25)

6
(9) LTE_WAKE#
5

4 3 2 R514 *Short_4
(10,23) MUX_AUD_INT1#
6

R18 *TS@0_4
2 3 4 Q22B
LTE WAKE pin of USI isn't OD,

1
Q22A PJ4N3KDW
C Q48B besides, the card might be able to PJ4N3KDW C
1

disappear if the GPIO goes high early

n
*3G@PJ4N3KDW Q48A +V1P8A
*3G@PJ4N3KDW than LTE core power, so for USI, this
feature isn't supported
eDP CONTROL PIN

2
LTE_WAKE# R440 *3G@0_4 LTE_WAKE_L Q6
+V3P3A +V3P3S
I2C_0_SDA_R 1 3 I2C_0_SDA_CONN
+V3P3A +V3P3S (10) I2C_0_SDA_R I2C_0_SDA_CONN (33)

LCD(LDS) TS@FDV301N

o
R113
R149 R482 R150 R31 *TS@0_4 R32 *[email protected]_4

+3V_LTE
+3V_LTE
10K_4 10K_4 10K_4
10K_4 (S5) +V1P8A R402 *[email protected]_4
+V3P3A
(S0/S3)
+V1P8A

2
PCH_DISP_ON (20) Q43

3
R124 EDP_BKLTEN_CONN (20)

3
*3G@10K_4 Q13 I2C_0_SCL_R 1 3 I2C_0_SCL_CONN
(10) I2C_0_SCL_R I2C_0_SCL_CONN (33)
R82 R80 Q52 PJA138K
10K_4 *3G@10K_4 PJA138K 2
2 TS@FDV301N
LTE_SIM DET

C
3
SIM_DET (25)

3
Q56 R403 *TS@0_4
(10) SIM_DET_C
5

Q12

1
6

2
(8) EDP_VDDEN
Audio(ADO)

1
2 3 4 2 +V1P8S
(8) EDP_BKLTEN
Q9B PJA138K
1

2
*3G@PJ4N3KDW Q9A PJA138K

1
*3G@PJ4N3KDW

1
I2C_1_SDA 3 1 I2C_1_SDA_AUDIO
(10,35) I2C_1_SDA I2C_1_SDA_AUDIO (26)
SIM_DET_C R73 *3G@0_4 SIM_DET

a
GND Q32 FDV301N
+V3P3S R336 *0_4 R326 2.2K_4
GND +V3P3A
(S5) +V1P8S
(S0)

t
+V1P8S
R444 R621 2.2K_4

2
R106
10K_4
B
KBC(KBC) 10K_4 (10,35) I2C_1_SCL
I2C_1_SCL 3 1 I2C_1_SCL_AUDIO
I2C_1_SCL_AUDIO (26)
B

AC DETECT +V1P8A
EDP_BKLTCTL_CONN (20)
Q77
R632
FDV301N
*0_4

n
3
Q49
2

PJA138K +V1P8A
2
1 3
(12) ACPRESENT BC_ACOK (29,30,31,36)
3

2
Q4 PJA138K Q10

a
1

2 I2C_1_SDA 1 3 I2C_1_SDA_MIC
(8) EDP_BKLTCTL (10,35) I2C_1_SDA I2C_1_SDA_MIC (27)
PJA138K
FDV301N Q34
R318 *0_4
1

+V1P8S
(S5)
+V1P8A (RTC)
KBC(KBC) HW RESET

u
Pullup at MIC IC side with 3.3V RTC

2
GND
2

Q67 *PJA138K
I2C_1_SCL 1 3 I2C_1_SCL_MIC
(10,35) I2C_1_SCL I2C_1_SCL_MIC (27)
1 3
(9) EC_IN_RW_Q EC_IN_RW (29)
FDV301N Q80
LS of XDP SMBUS R633 *0_4
R371 *Short_4
+V1P8A +V1P8A

Q
+V3P3S +V1P8A
LS of G-sensor R353

2
R639 10K_4
2

*10K_4 DET_TRIGGER 1 3 HP_JD_L

1 3 (10) DET_TRIGGER HP_JD_L (27)
SMB_SOC_DATA SMB_XDP_SDA
(10,16) SMB_SOC_DATA SMB_XDP_SDA (16)
Q38 *PJA138K
A (33) EC_SENSOR_I2C1_SDA R670 *Short_4 EC_SENSOR_I2C1_SDA_EC (30)
Active at falling edge, pullup at 227 side A
Q88 FDV301N
R810 2.2K_4 +VRTC

+V1P8A
+V3P3A
R363
R811 2.2K_4
2

+V3P3S 10K_4

SMB_SOC_CLK 1 3 SMB_XDP_SCL
(10,16) SMB_SOC_CLK SMB_XDP_SCL (16)

3
R669

*10K_4 Q89 FDV301N

2 2 Quanta Computer Inc.
(33) EC_SENSOR_I2C1_SCL R671 *Short_4 EC_SENSOR_I2C1_SCL_EC (30) Q66 Q65
PJA138K PJA138K
PROJECT : ZHR
Size Document Number Rev

1
LEVEL TRANSLATOR 2 1A

GND GND Date: Monday, September 14, 2015 Sheet 35 of 47

5 4 3 2 1
 5 4 3 2 1
+VDC_IN
VR PAGE: +VBATA

l
+VBATT 36

2
i
D PQ23
PD8
DA2J10100L
PD10
DA2J10100L +VCHGR_LDO
+VBATA
D
dcjk-2dc3079-001111f-2p PQ24

1
AON6414AL

t
AON6414AL PR59
+VDC_IN +VDC_IN1 0.01/F_0612 +VCHGR_VIN

10u/25V_8

10u/25V_8

10u/25V_8

10u/25V_8

10u/25V_8

10u/25V_8
PJ1

PC175

PC174

PC161

PC162

PC30

PC31
2 3 3 +V_CHGR_VCC_D
1 5 2 2 5 1 2 PD9 +VCHGR_VIN
3 1 1 *RB500V-40
2200p/50V_6

47n/50V_6
0.1u/50V_6

*0.01U/50V_4

*0.1U/25V_4
1

P4SMAFJ20A
PC33

PC35

PC276

PC277

PC278
BC_BST_R

1n/50V_4

10u/25V_8

10u/25V_8

10u/25V_8

10u/25V_8

0.1u/50V_6
PC166 PC173

4
PD1

PC275

PC191

PC192

PC63

PC59

PC193
POWER_JACK 1U/25V_6 PR166

n
PR228 BC_BST *SHORT_6

5
0.1u/50V_6 10_1206
2

PC164
0.1u/50V_6 CHG_AGND PC177
? +V_CHGR_VCC 47n/50V_6
PR242 4
CHG_AGND
1 PC169 +V_BC_SW PQ7

e
AC- 28

4.02K/F_4

4.02K/F_4
430K/F_4 PC165 1U/25V_6 CHG_AGND AON7410 PQ8
VCC

PR244

PR245
0.1u/50V_6 2 AOL1413

3
2
1
AC+ 24 PC190 1
REGN +VCHGR_LDO
1U/25V_6 2 5
PR246 *Short_4 CHGR_CMSRC 3 3
CMSRC

5
26 BC_HIDRV TG_VBATT PL10
PR243 *Short_4 CHGR_ACDRV 4 HIDRV PR164 *SHORT_6 2.2uH_7X7X3
ACDRV 25 BC_BST +V_BC_SW 1 2 +V_BC_SW_VBATT

4
12V will enable charger AC_DET 6 BTST
ACDET 27 +V_BC_SW 4 PC199
+V3P3A_LDO PHASE

PR231
*2.2_6
PU18 BG_VBATT PQ9 PR177
(30,36) SMB_BC_DATA SMB_BC_DATA PR165 *Short_4 BQ_SMB_DATA 11 23 BC_LODRV PR173 *SHORT_6 AON7752 0.01/F_0612
SDA LODRV

10u/25V_8

10u/25V_8
0.1u/25V_4
i
PR247 PC279 BQ24770RUYR 0.1u/25V_4

3
2
1
C

PC198

PC188

PC189
100K/F_4 1000p/50V_4 (30,36) SMB_BC_CLK
(29,30,31,35) BC_ACOK
SMB_BC_CLK PR167 *Short_4 BQ_SMB_CLK

BC_ACOK
12

5
SCL
SR+
20 CHGR_SRP_DP PR176 *Short_4
PC249 +V_BC_SW_R
CHG_AGND

PC195
C
PR159 100K/F_4 ACOK *2200p/50V_6 PC182 10u/25V_8
7 +VBATT

f
IADP 19 CHGR_SRN_DN PR175 *Short_4 0.1u/25V_4
8 SR- PC181 10u/25V_8
CHG_AGND +V3P3A_LDO IDCHG CHG_AGND
BC_PMON 9 18 BC_BATDRV PR174 *Short_4 BC_BATDRV_R
(30,36) BC_PMON PMON BATDRV
PR171 VBATA_VR_HOT_N 10 17 BC_BAT PR178 10/F_6
+VCHGR_LDO (12) VBATA_VR_HOT_N PROCHOT BAT
10K/F_4
15 BC_BATPRES

n
BATPRES

10u/25V_8

10u/25V_8

10u/25V_8

10u/25V_8
+V3P3A_LDO

PC183

PC184

PC185

PC186
PR229 BC_CMPIN 13
100K/F_4 CMPIN PC196
PR172 1M/F_4 BC_CMPOUT 14 29 0.1u/50V_6
CMPOUT GND_EPAD PR179
BC_CELL 16 22 PR158 100K/F_4
CELL GND CHG_AGND
21

G1
G2
G3
G4
G5
G6
G7
G8
G9
ILIM

o
*SHORT_6 2 cell: 9V (Default)
PR180 BQ24770RUYR Fsw: 800kHz (Default)

30
31
32
33
34
35
36
37
38
PC187 REV = 1 ?
*0_4
0.1u/50V_6 CHG_AGND
+VCHGR_LDO

PC179
*100p/50V_4 CHG_AGND

PR230

C
+VBATT 100K/F_4
B BATT_EN# B
C114F3-108A1-L_Batt_Conn

PJ2 BATT_EN# (29) ADPTR_ILIM

PR168 *0_4
9 8
7
6 PR182 100_4 TEMP_MBAT PR232 *Short_4 BC_BATPRES PR181
5
4 10.2K/F_4
3
2 +V3P3A_LDO

a
PR183 *1M_4
10 1

CHG_AGND

t
BC_PMON
(30,36) BC_PMON
PR169 PR170
100P/50V_4
30.1K/F_4

100_4 100_4
PR162

PC178

SMB_BC_CLK (30,36)

n
SMB_BC_DATA (30,36)
CHG_AGND
1

PC194 PC197
*47p/50V_4 *47p/50V_4

a
2

A PD6 PD5
A
PDZ5.6B PDZ5.6B

u
Quanta Computer Inc.
PROJECT :ZHR
Size Document Number Rev
+VBATA 1A

Date: Monday, September 14, 2015 Sheet 36 of 47

5 4 3 2 1

Q
 5 4 3 2 1

l
VR PAGE: +V5A & +V3P3A
37

a
+VBATA Place thermal VIAs (connected to VBATA plane)
close to VIN pin (PIN 1) PR5 PC9
V5A_BOOT_R

i
Input Capacitors *SHORT_6 0.1U/25V_4

10u/25V_8

10u/25V_8

10u/25V_8
PC29

PC26

PC18

PR197
*2.2_6
t
D D
V5A_BOOT +V5A_LX

+V5A_LX_R

*150p/50V_4
+V5A

PC210
10
n
1
PR10 +V5A

VIN

BOOT
100K/F_4
V5A_EN 13 8
PL1
Output Capacitors
(31) V5A_EN EN SW1 2.2uH_7X7X3

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8
PC6

PC7
4 9

PC209

PC207

PC10

PC206
V5A_PWRGD
PGOOD SW2
+V5A

e
3 15 PIMB061H-2R2MT
VBYP PU2 SW3
V5A_ENLDO 12
ENLDO
RT7291BGQUF
SW4
16 Imax =5A
+V5A_LDO 6 7 V5A_VOUT
PR1
OCP = 11A
Always ON w/ VBATA LDO VOUT

EN pin floating
+V5A_LDO 14 2 *Short_4 Fsw = 500kHz

d
AGND PGND Place thermal VIAs (connected to GROUND plane)

VCC
CLK
Ground EN to disable close to PGND pin (PIN 2)

*0.1u/10V_4
Maximum current = 100mA
+V5A_LDO
PR8

PC11
*Short_4

11
i
V5A_AGND
V5A_CLK Connect V3PA_AGND to System Ground with a VIA close to AGND pin (PIN 14)
Internal Input for Controller (5V)

*4.7u/10V_6

Charge Pump VCLK

PC12
+VCC_V5A
DO NOT CONNECT

PC14
1u/10V_4
PR7
*Short_4
f
V5A_AGND
V5A_AGND

+V5A

NOT USED
V5A_AGND V5A_AGND +V3P3A

n
C C
PC208 *10u/6.3V_6
PC120 *10u/6.3V_6

5
2
(42,43) SLP_S3D
V5A_VBYP PR13 *Short_4

o
SLP_S3D 4
TDC : A PQ19 PQ5
PEAK : A AO3404 MDV1528Q

1
Width : mil TDC : A

3
2
1
+V5S
+VBATA
PEAK : 4A
Width : mil +V3P3S

*22u/6.3V_6

*22u/6.3V_6
PC212

PC211
PR141 PC125

*22u/6.3V_6

*22u/6.3V_6
C

PC76

PC74
V3P3A_BOOT_R

*SHORT_6 0.1U/25V_4
Input Capacitors

PR221
*2.2_6
PR222 10K/F_4
10u/25V_8

10u/25V_8

10u/25V_8
PC147

PC150

PC142
0.1u/10V_4
PC138

a
+V3P3A_LX_R

*150p/50V_4
PC236
+V3P3A V3P3A_BOOT +V3P3A_LX

t
Place thermal VIAs (connected to VBATA plane)
V3P3A_AGND close to VIN pin (PIN 1) +V3P3A
10
1

PR149
Output Capacitors
VIN

BOOT

100K/F_4 PL7
B V3P3A_EN13 8 B
EN SW1 2.2uH_7X7X3

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8
n
4 9

PC226

PC96

PC107

PC229

PC221

PC102
V3P3A_PWRGD
(31) V3P3A_PWRGD PGOOD SW2
+V5A PR150 *Short_4 V3P3A_VBYP 3 15

12
VBYP PU15 SW3
16
+V3P3A
V3P3A_ENLDO RT7290AGQUF

6
ENLDO SW4
7 V3P3A_VOUT
PR133 Imax = 5A
OCP = 11A

a
LDO VOUT
14 2 *Short_4
+V3P3A_LDO AGND PGND Place thermal VIAs (connected to GROUND plane) Fsw = 500kHz
VCC
CLK

close to PGND pin (PIN 2)

+V5A_LDO
*0.1u/10V_4
PR146

PC128

Always ON w/ VBATA
Maximum current = 100mA
+V3P3A_LDO
*0_4

Intel requirement:
5

11

V3P3A_AGND
EN pin floating

u
Ground EN to disable Imax: 4A
4.7u/10V_6

V3P3A_CLK

+VCC_V3P3A
PC131

Rise time: 1ms

V3P3A_AGND
PR147

PC132
1u/10V_4
*0_4

Connect V3P3A_AGND to System Ground with a VIA close to AGND pin (PIN 14)

Q
V3P3A_AGND V3P3A_AGND

V3P3A_AGND

PC94 PC93 PC124

A 0.1u/50V_6 0.1u/50V_6 0.1u/50V_6 A

PD3 PD2 PD4

3

1PS302 1PS302 1PS302

1

+15V
Quanta Computer Inc.
PR120
22_8
PC114
0.1u/50V_6
PC115
0.1u/50V_6
PC136
0.1u/50V_6
PROJECT : ZHR
Size Document Number Rev
V5A_V3P3A 1A

Date: Monday, September 14, 2015 Sheet 37 of 47

5 4 3 2 1
 5 4 3 2 1

l
VR PAGE: VCC_CPU
SET1:
REQ = 19.43kohm
38

a
Comp. Ramp factor = 267% +VCC_VREF
PR91 PR92 PR93 Place Cin close to FET VIN pin
DVID width = 72us

i
130/F_4 18.2K/F_4 1.1K/F_4
(1uF closer to VIN) +VBATA
DVID threshold = 15mV SVID Interface

VCC_RIMON_2

VCC_RIMON_1
t
VCC_IMON
D D

0.47u/6.3V_4
SET2:

PC95

PR137
VCC_VCLK

100K/F_4
VCC_VCLK (31)

Icc,max = 7A VCC_VDIO
VCC_VDIO (31)

n
QR trigger = disable VCC_ALERT_N
VCC_ALERT_N (31)
Input Capacitors
QR width / Ton = 111% +VCC_VREF

1u/25V_6
10u/16V_6

10u/16V_6

10u/16V_6
(12) +VCC_SENSEN_DN +VCC_CPU

PC225

PC223

PC219

PC92
VCC_IBIAS
SET3: +VCC_VCC
Differential routing w/ VCC_SENSEP Imax =7 A

0.1U/10V_4
ZCD threshold = 75mV OCP = 8.96A (128%)

PC256
+VCC_SENSEN_DN

Load-line = 0ohm

d
PR127
Anti-overshoot = enabled PR112 GND near +VCC0_CPU GND

31

10

15

13

14
20K_4

5
PU14 100/F_4
Fsw > 500kHz

VCC_BOOT1
PR105 PC99

i
IMON

VREF

IBIAS

VCLK

VDIO

ALERT#

RGND
VCC_EN 26 VCC_BOOT_R
VR Address = 0 (31) VCC_EN
VCC_PWRGD 17
VRON
*SHORT_6 0.1U/25V_4
(31) VCC_PWRGD VR_READY 22

f
VCC_VR_HOT_N 12 BOOT1
(12) VCC_VR_HOT_N VR_HOT# CSD87381P +VCC0_CPU
PR99 JP8
25 VCC_UGATE1 *Short_4 2 0.002_1206
+VCC_VCC UGATE1 VCC_TG 1 VIN PL5
TG 5 +VCC_LX 1
+VCC_OUT 2
23 4 VSW 0.47uH_7X7x3
C C

n
PHASE1 BG 3
VCC_SET3 9 PGND
SET3 20 VCC_LGATE1 VCC_BG PU12 0.25W
+VCC_VCC 7 LGATE1

PR86
VCC_SET1 PR114 *Short_4 CSD87381P

*2.2_6
PR142 PR143 PR144 SET1
80.6K/F_4 28.7K/F_4 39.2K/F_4 VCC_SET2 8 19

o
SET2 PGND Max Current = 15A
PR94 Ron_HS = 15.7mohm
VCC_SETGND 24 Ron_LS = 7.0mohm
VCC_SET1_RU VCC_SET2_RU VCC_SET3_RU 100K/F_4
30 GND DRVEN2
VCC_DRVEN2 +VCC_LX_R

*150p/50V_4
SETGND

PC82
PR134 PR135 PR136 18
1.15K/F_4 432/F_4 432/F_4 VCC_VBOOTSEL 29 DRVEN1 PR123
Vbootsel *Short_4

C
PR95 PR85
VCC_SET1 PR207 VCC_DRVEN1 *Short_4 *Short_4

RT8175A
VBOOT = 1V VCC_SET2
100K/F_4 PR108 VCC_VSEN 4
VSEN Output Capacitors
*Short_4
VCC_SET3
VCC_SETGND

a
(12,38) +VCC_SENSEP_DP (12,38) +VCC_SENSEP_DP

PR210 PR211 PR216 Differential routing w/ VCC_SENSEN

t
23.7K/F_4 1.1K/F_4 13.7K/F_4
PR107 PR102 2
+VCC_SENSEP_DP VCC_COMP COMP TONSET
VCC_SET1_RD VCC_SET2_RD 3

ISEN1N

ISEN1P
B FB B

EGND
PVCC
VCC_SET3_RD 10K/F_4 75K/F_4
TSEN
VCC

NC

n
PR205 PR206 PR212
PR106

365/F_4 16.5/F_4 221/F_4

100/F_4

11

16

21

32

27

28

33
PC101 PC100
270p/50V_4 22p/50V_4
VCC_TONSET

Place Cout close to BGA loading point

a
+VCC_VCC
VCC_SETGND VCC_FB +VCC_PVCC VCC_ISEN1P_DP

Loop Compensation
*SHORT_6

+VCC0_CPU
Differential Routing
*SHORT_6
PR126

PR110

+VCC_VCC 2.2u/10V_4 VCC_ISEN1N_DN VCC_ISEN1N_R_DN

PC104

u
PR96
2.2u/10V_4

TP_VCC_NP
PC111

PR145 681/F_4
71.5K/F_4 +VCC0_CPU

0.1U/10V_4
PC85
+V5S +V5S

Q
VCC_TONSET_RTON

330u/2V_7343

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6
5.6K/F_4

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6
+
PR132

PC272

PC273

PC274

PC269

PC270

PC271

PC267

PC127

PC268

PC126

PC119

PC116

PC118

PC117
PR138
549K/F_4

A VCC_TSEN_R VCC_TSEN Fsw = 789.76kHz A

100K/F_4_4250NTC

VCC_TONSET_R
100K/F_4

2.2u/10V_4
6.65K/F_4
PR115

PR124

PR217

PC123

PR139
1/F_4 Quanta Computer Inc.
PROJECT : ZHR
Size Document Number Rev
+VBATA 1A
+VCC_VCC VCC_SETGND
VCC - RT8175A
Date: Monday, September 14, 2015 Sheet 38 of 47
5 4 3 2 1
 5 4 3 2 1

l
SET1: VR PAGE : +VGG
Comp. Ramp factor = 267%
39

a
DVID width = 72us
DVID threshold = 15mV

i
Place Cin close to FET VIN pin
SET2: (1uF closer to VIN)

t
PR48 PR47 PR46
D +VGG_VREF D
1/F_4 261/F_4 10.2K/F_4
Icc,max = 13A SVID Interface +VBATA

VGG_RIMON_2

VGG_RIMON_1
QR trigger = disable

VGG_IMON
n
QR width / Ton = 111%

0.47u/6.3V_4
PC40

PR52
VGG_VCLK

100K/F_4
VGG_VCLK (31)
VGG_VDIO
VGG_VDIO (31)
SET3: REQ = 10.462kohm Input Capacitors

e
VGG_ALERT_N
VGG_ALERT_N (31)
ZCD threshold = 75mV +VGG_VREF

10u/16V_6

10u/16V_6

10u/16V_6

1u/25V_6
Anti-overshoot = enabled (12) +VGG_SENSEN_DN

PC80

PC73

PC75

PC68
Fsw > 500kHz +VGG_VCC +VGG_CPU

d
Differential routing w/ VCC_SENSEP

VGG_IBIAS
VR Address = 5 +VGG_SENSEN_DN Imax =13 A

0.1U/10V_4
OCP = 16.64A (128%)

PC257
i
PR72
20K_4 PR23 GND near +VGG GND

PU6
100/F_4
PR74 PC65
Load-line = 0ohm

31

10

15

13

14
f

VGG_BOOT1
1

5
VGG_BOOT_R

IMON

VREF

IBIAS

VCLK

VDIO

ALERT#

RGND
+VGG_VCC VGG_EN 26 *Short_4 0.1U/25V_4
(31) VGG_EN VRON
VGG_PWRGD 17
(31) VGG_PWRGD VR_READY +VGG
C 22 PR71 CSD87381P JP6 C

n
VGG_VR_HOT_N 12 BOOT1 *Short_4 2 0.001_3720
(12) VGG_VR_HOT_N VR_HOT# VIN
VGG_TG 1 PL4
TG 1W
[ 1 ] UGATE1
25 VGG_UGATE1
4
BG
VSW
5 +VGG_LX
0.33uH_7X7X3
+VGG_OUT1 2

3
23 PGND

o
PHASE1

PR84
PU8

*2.2_6
+VGG_VCC VGG_SET3 9 CSD87381P
SET3 20 VGG_LGATE1 VGG_BG
PR22 PR31 PR49 VGG_SET1 7 LGATE1 PR73
80.6K/F_4 15K/F_4 976/F_4 SET1 *Short_4
VGG_SET2 8 19 Max Current = 15A
VGG_SET1_RU VGG_SET2_RU VGG_SET3_RU SET2 PGND Ron_HS = 15.7mohm +VGG_LX_R PR77 PR75
PR55 VGG_SETGND Ron_LS = 7.0mohm *Short_4 *Short_4

*150p/50V_4
C
24

PC83
PR37
PR34
1.15K/F_4 PR50
100K/F_4
30
SETGND GND DRVEN2
VGG_DRVEN2

PR76
1.15K/F_4 2/F_4 18 *Short_4
VBOOT = 1.0V VGG_VBOOTSEL 29 DRVEN1
VGG_SET1 Vbootsel VGG_DRVEN1
PR54
VGG_SET2 100K/F_4 PR38 VGG_SENSE_R

a
RT8175A
4
VGG_SET3 *Short_4 VSEN

t
(12,39) +VGG_SENSEP_DP VGG_SETGND (12,39) +VGG_SENSEP_DP
Differential routing w/ VCC_SENSEN
PR36 PR44
B B
23.7K/F_4 PR35 392/F_4
1.05K/F_4 PR18 PR39

0.1U/10V_4
n
Differential Routing

PC62
+VGG_SENSEP_DP VGG_COMP
VGG_SET1_RD VGG_SET2_RD 2
VGG_SET3_RD 10K/F_4 75K/F_4 COMP
TONSET

ISEN1N

ISEN1P
FB

EGND
PVCC
PR21 PR20 PR43
TSEN
VCC
PR24

365/F_4 2/F_4 27.4/F_4

a
100/F_4

NC
PC34 PC39
270p/50V_4 22p/50V_4
6

11

16

21

32

27

28

33
VGG_TONSET

+VGG_VCC
VGG_FB +VGG_PVCC VGG_ISEN1P_DP

u
VGG_SETGND
Place Cout close to BGA loading point
+VGGLoop Compensation
*SHORT_6

+VGG
PR32

PR200

VGG_ISEN1N_DN VGG_ISEN1N_R_DN
*SHORT_6

2.2u/10V_4

Output Capacitors
PC64

+VGG_VCC
PR66
TP_VGG_NP

681/F_4
2.2u/10V_4
PC38

PR70
+V5A +V5S_VGG 15K/F_4

Q
PR198 *0_6 +V5S_VGG +V5S_VGG

330u/2V_7343

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

*22u/6.3V_6

*22u/6.3V_6
+

PC280

PC266

PC265

PC264

PC263

PC261

PC262

PC259
Fsw = 803.43kHz

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6
5.6K/F_4
PR64

PC222

PC220

PC224

PC89

PC88

PC69
PC168 VGG_TONSET_RTON
PC213
0.1U/16V_4
0.1U/16V_4 PU26 PR68
A A2 A1 VGG_TSEN_R VGG_TSEN 634K/F_4 A
IN OUT
100K/F_4_4250NTC

B2 B1
EN GND VGG_TONSET_R
100K/F_4

6.65K/F_4
PR57

PR63

PR58

2.2u/10V_4
PC36

TPS22930
PR160
5.6K/F_4 PR41
1/F_4
Quanta Computer Inc.
BCRD 5.1K PROJECT : ZHR
Size Document Number Rev
(30,31,34,41) PCH_SLP_S3_L
1A
+VGG_VCC VGG_SETGND +VBATA
VGG - RT8175A
Date: Monday, September 14, 2015 Sheet 39 of 47
5 4 3 2 1
 5 4 3 2 1

VR PAGE: +VDDQ

l
Fsw=500kHz
40

a
+V3P3A
Non-Tracking Discharge
VDDQ_AGND

i
PR26

t
D 100K/F_4 D

(31) VDDQ_PWRGD

VDDQ_PWRGD
n
OCP~7.8A
+VBATA

33.2K/F_4

37.4K/F_4
PR27

PR28
e
VIH_OVT = 1.8V
0603 VIL_OVT = 0.5V
+V1P05A

VDDQ_MODE
VDDQ_VTT_EN (31)

VDDQ_TRIP
+VDDQ_VLDOIN

d
PR33

1u/25V_6

10u/16V_6

10u/16V_6

10u/16V_6
VDDQ_EN (31)

PC44

PC45

PC42

PC43
*SHORT_6

i
VIH_ONS = 1.8V
PC41 VIL_ONS = 0.5V

VDDQ_VTTSNS
PR30

20

19

18

17

16
10u/6.3V_6
0603 *SHORT_6 PC46

5
VDDQ_VBST_R 0.1u/50V_6 PQ1

PGOOD

MODE

TRIP

S3

S5
PR25 AON7410
VDDQ_VBST
*Short_4
1 15
VTTSNS VBST PR40 4
C C
*Short_4

n
+VDDQ_VTT 2 14 VDDQ_DRVH VDDQ_TG
PR62 VLDOIN DRVH +VDDQ_M0_M1_R

3
2
1
*SHORT_8 PL2
+VDDQ_VTT_OUT 3
VTT
TPS51716 SW
13 +VDDQ_LX
1uH_7X7X3

5
o
4 12 +VDDQ_V5IN
VTTGND V5IN

PR53
PR56

*2.2_6
10u/6.3V_6

10u/6.3V_6
PC48

PC51

*Short_4 PQ4

VDDQSNS
+VDDQ_VTTREF 5 11 VDDQ_DRVL VDDQ_BG 4 AON7752
VTTREF DRVL

REFIN

PGND
EGND
VREF

PC55
GND

0.22u/10V_4 +VDDQ_LX_R

C G1
G2
G3
G4
G5

3
2
1
PR51 +V5A
*SHORT_6

*150p/50V_4
6

10
21
22
23
24
25
26

PC58
VDDQ_AGND Ground Isolation
+VDDQ_VREF
0603 PR69
*SHORT_6
+VDDQ_VTT PC49

a
Imax_VTT = 200mA 1u/10V_4
VDDQ_VDDQSNS
Vout=1.35V

PC56

t
0.1u/10V_4

B B
VDDQ_AGND
PR61
PR60 *Short_4

n
10K/F_4

VDDQ_REFIN

a
0.01u/50V_4
PC57

PR65
30.1K/F_4

+VDDQ

u
Imax = 5A
+VDDQ_M0_M1_R
VDDQ_AGND

Q
22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6
PC1

PC2

PC3

PC4

PC5
PC19

PC17

PC22

PC254
A A

Place 47uF closer to VR Output Quanta Computer Inc.

PROJECT : ZHR
Size Document Number Rev
1A
VDDQ - TPS51716
Date: Monday, September 14, 2015 Sheet 40 of 47
5 4 3 2 1
 5 4 3 2 1

41

l
VR PAGE : +Vnn

a
JP12
*[email protected]_1206
+VNN +V1P05A
1 2

ti
D SET1: D
WW02.2 - Resistor value change :
Comp. Ramp factor = 267% R3A1PD -> 33.2K
R3A2PD -> 4.7K
DVID width = 72us R3A3PD -> 976

DVID threshold = 15mV

Place Cin close to FET VIN pin

n
SET2: +VNN_VREF PR104 PR204 PR101
(1uF closer to VIN)
Icc,max = 4.0 A SVID Interface
+VBATA

VNN_RIMON_2

VNN_RIMON_1
QR trigger = disable [email protected]/F_4 [email protected]/F_4 VN@976/F_4

VNN_IMON
e
QR width / Ton = 111%

[email protected]/6.3V_4
VNN_VCLK

PC103

PR203
VN@100K/F_4
VNN_VCLK (31)
VNN_VDIO
VNN_VDIO (31)
SET3: REQ = 38.86 kohm VNN_ALERT_N
VNN_ALERT_N
Input Capacitors
(31)
ZCD threshold = .75mV
+VNN : 0.78 -1.2v

d
+VNN_VREF
Anti-overshoot = enabled

PC108

PC112

PC105

PC106
VN@10u/16V_6

VN@10u/16V_6

VN@10u/16V_6

VN@1u/25V_6
Fsw > 500kHz +V3P3A PR208
Imax =3.5 A

VNN_IBIAS
OCP = 5.0 A (128%)

i
*VN@Short_4
VR Address = 01b VNN_RGND

PR81 GND near +VGG GND

Load-line = 0ohm
VN@10K/F_4

31

10

15

13

14
f
1

5
PU10 PR79 PC78

VNN_BOOT1
VNN_BOOT_R

IBIAS

VCLK

VDIO

ALERT#
IMON

VREF

RGND
VNN_EN 26
(31) VNN_EN VRON *VN@SHORT_6 [email protected]/25V_4
VNN_PWRGD 17
(31) VNN_PWRGD VR_READY 22
+VNN_VCC VNN_VR_HOT_N 12 BOOT1 PR98 CSD87381P JP11 +VNN
(12) VNN_VR_HOT_N VR_HOT#
WW02.2 - changed to +VNN_VCC *VN@Short_4 2 [email protected]_3720
C 25 VNN_UGATE1 VNN_TG 1 VIN PL6 C

n
UGATE1 TG 5 +VNN_LX 1
+VNN_OUT 2
4 VSW VN@1uH_7X7X3
23 BG 3
PHASE1 PGND
+VNN_VCC VNN_SET3 9
PR97
*VN@Short_4 PU13 1W

PR87
*[email protected]_6
WW02.2 - Resistor value change : PR131 SET3 20 VNN_LGATE1 VNN_BG VN@CSD87381P
R3A32PD -> 1.15K PR130 [email protected]/F_4 VNN_SET1 7 LGATE1
R3A33PD -> 681 PR129 [email protected]/F_4 SET1 Max Current = 15A

o
R3A30PD -> 392 VNN_SET2 8 19 Ron_HS = 15.7mohm
R3A31PD -> 221 [email protected]/F_4
VNN_SET3_RU SET2 PGND Ron_LS = 7.0mohm
R3A22PD -> 13.7 K
VNN_SET1_RU VNN_SETGND +VNN_LX_R PR89 PR88
VNN_SET2_RU PR119 PR202
GND 24 VNN_DRVEN2 *VN@Short_4 *VN@Short_4

*VN@150p/50V_4
30 DRVEN2

PC91
VN@681/F_4 VN@100K/F_4
SETGND
Design Note : -> PR117 PR118
[email protected]/F_4 [email protected]/F_4 18 PR201
optimized for standby current VBOOT = 1.0V VNN_VBOOTSEL 29 DRVEN1 *VN@Short_4
Vbootsel
VNN_SET1 PR116 VNN_DRVEN1
PR100 *VN@Short_4

C
RT8175A
VNN_SET2 VN@100K/F_4 4
VNN_SENSE_R
VSEN
VNN_SET3

PR214 (12,41,42) +VNN_SENSEP VNN_SETGND +VNN_SENSEP (12,41,42)

VN@976/F_4
PR213 PR215
[email protected]/F_4 VN@221/F_4
PR125 PR111
+VNN_SENSEP VNN_COMP 2
VNN_SET1_RD VNN_SET2_RD VNN_SET3_RD COMP

TONSET

a
3

ISEN1N
VN@10K/F_4 VN@75K/F_4

ISEN1P
FB

EGND
PVCC
TSEN
PR218
VCC

NC
VN@365/F_4 PR219 PR220
VN@221/F_4 VN@392/F_4
PR128
*VN@100/F_4

PC121 PC110

t
6

11

16

21

32

27

28

33
VN@270p/50V_4 VN@22p/50V_4

VNN_FB
VNN_TONSET

VNN_SETGND +VNN_VCC +VNN_VCC +VNN_PVCC VNN_ISEN1P_DP

B B
*VN@SHORT_6

*VN@SHORT_6
+VNN
VNN_ISEN1N_DN VNN_ISEN1N_R_DN Differential Routing
PR209

PR80
[email protected]/10V_4

[email protected]/10V_4

n
Loop Compensation
PC109

PC79
PR90

TP_VNN_NP
VN@681/F_4
PR83

[email protected]/10V_4
PC90
VN@15K/F_4
VNN OFFSET BACKUP CIRCUIT
[email protected]/F_4

+V5A +V5A
PR113

a
VNN_TONSET_RTON

VNN_TSEN_R VNN_TSEN
PR78
Fsw = 803.43kHz
VN@100K/F_4_4250NTC

VN@634K/F_4
VN@100K/F_4

[email protected]/F_4
PR121

PR140

PR109

B = 4250 +/- 1% VNN_TONSET_R

u
Trip at 100degC
[email protected]/10V_4

+V1P05A
PC77

PR82
VN@1/F_4
1

+VNN WW02.2 output caps are changed to 5X47 uF

2
VNN_SETGND Output Capacitors
PQ20 +VNN_VCC
(43) SLP_S3#_F_F
*VN@2N7002K +VBATA

VNN OFFSET CIRCUIT

Q
3

+VNN_SENSEP_F1
VN@22u/6.3V_6

VN@22u/6.3V_6

VN@22u/6.3V_6

VN@22u/6.3V_6

VN@22u/6.3V_6

VN@22u/6.3V_6

VN@22u/6.3V_6

VN@22u/6.3V_6

VN@22u/6.3V_6

VN@22u/6.3V_6
PC97

PC98
PC228

PC113

PC230

PC231

PC122

PC227

PC234

PC235
PR67
PR239
*VN@0_4 *VN@100/F_4

+VNN_SENSEP
+V3P3A_PRIME

A A
1

PR103
*VN@100K/F_4
PR240 *VN@Short_4
2 PQ22
(30,31,34,39) PCH_SLP_S3_L
+VNN_SENSEP_F2
VN@BSS84 Place Cout close to BGA loading point
3

PR248
SLP_S3#_F_R 2 PQ21
*VN@2N7002K *VN@100K/F_4 PR241

PC281
VN@309K/F_4
Quanta Computer Inc.
1

*[email protected]/10V_4 VNN_FB
PROJECT : ZHR
Size Document Number Rev
1A
VNN - RT8175A
Date: Monday, September 14, 2015 Sheet 41 of 47
5 4 3 2 1
 5 4 3 2 1

42

l
VR PAGE: MOIC
+V3P3A

a
To SOC VNN Package Sensing

i
(+VNN merge with +V1P05A) PR154
10K/F_4

t
(12,41) +VNN_SENSEP PR224 *0_4
D D

+V1P05A_R_SOC MOIC_RSMRST PR156 *Short_4

RSMRST_N_PWRGD (30)

n
PR161 *Short_4 MOIC_O_1P05A

*33n/25V_4
PC152
+V3P3A
V1P05A Output Sensing +V5A

V1P05A (Buck)

e
*0.1u/10V_4
1
Fsw = 1.2MHz

PC176
PR153
Imax = 1.9A +V1P05A
2
2.2_6

10u/6.3V_6

10u/6.3V_6

10u/6.3V_6
d
PC167

PC163

PC160

+V_MOIC_VCC
22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6
PC157

PC156

PC172

PC170

PC158

PC171
1
PC149

i
1u/10V_4
2
RT5041A V1P15A

f
20
21 IN_1P05A_20 VCC
11
LDO
IN_1P05A_21
PL9
+V_MOIC_LX_1P05A
22
23 LX_1P05A_22 19
+V1P15A
Imax = 700mA
1uH_7X7X3 LX_1P05A_23 O_1P05A_19
+V1P8A 8 6

10u/6.3V_6

10u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6
C C

n
IN_1P15A O_1P15A_6

PC145

PC144

PC134

PC139

PC141
+V3P3A 9 10 +V1P5S

22u/6.3V_6
IN_1P5S O_1P5S

PC237
V1P5S
1
2 IN_1P8_1 LDO
27 IN_1P8_2 3 Imax = 17mA
10u/6.3V_6

10u/6.3V_6

10u/6.3V_6

o
28 LX_1P8_27 O_V1P8
PC133

PC135

PC140
V1P8A (Buck) LX_1P8_28 +V1P24A
+V1P8A
Fsw = 1.2MHz 7
IN_1P24A O_1P24A
5

10u/6.3V_6

22u/6.3V_6

22u/6.3V_6
Imax = 1.8A 14 16 +V1P8A_PRIME

PC146

PC129

PC130
SW IN_1P8A SW O_1P8A V1P24A
17 18
LDO

V1P8A_PRIME
Load Switch
- NOT USED-
+V1P8A SW IN_3P3A SW O_3P3A

C
PL8
+V_MOIC_LX_1P8 15 EN_1P05A
26
24
MOIC_EN_1P05A
MOIC_SUSPWRDNACK
Imax = 550mA
1uH_7X7X3 PGND SUSPW RDNACK 25 MOIC_S0IX_B
22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

22u/6.3V_6

+V1P8A 12 S0IX_B 4
PC244

PC245

PC148

PC151

PC153

MOIC_SLP_S3_B
29 GND SLP_S3_B 13 MOIC_RSMRST
EPAD RSMRST
PU17 RT5041AGQW +V3P3A_PRIME

Imax = 200mA
2.2u/6.3V_6
PC155

V3P3A_PRIME
Load Switch
a
2.2u/6.3V_6
PC239
t
+V3P3A

2.2u/6.3V_6
PC159
2.2u/6.3V_6

B B
PC240

an PR152 *Short_4 V1P8A Output Sensing MOIC_O_1P8

u
+V_MOIC_LX_1P05A +V_MOIC_LX_1P8
PC143
*0.1u/10V_4
+V1P8A

PR163

PR148
*2.2_6

*2.2_6
PC243 *10u/6.3V_6
MOIC_EN_1P05A PR223 *Short_4
V1P05A_EN (31,43)

Q
MOIC_SUSPWRDNACK PR157 *Short_4
SUSPWRDNACK_SOC_EC (30,31)
3

MOIC_S0IX_B PR155 *Short_4

SLP_S0IX# (12,34)
MOIC_SLP_S3_B PR151 *Short_4
SLP_S3# (12,22,34,43)
+V1P05A_LX_R +V1P8A_LX_R
(37,43) SLP_S3D 2

*150p/50V_4

*150p/50V_4
PC180

PC137
A PQ6 A
AO3404
Intel requirement
1

Imax: 1A +V1P8S
*22u/6.3V_6

*22u/6.3V_6

Rise time: 1ms

PC238

PC242

Quanta Computer Inc.

TDC : A
PEAK : 1A PROJECT : ZHR
Size Document Number Rev
Width : mil MOIC_RT5041A 1A

Date: Monday, September 14, 2015 Sheet 42 of 47

5 4 3 2 1
 5 4 3 2 1

+VBATA +V5A
KEPLER VR
43

l
Thermal Protector PR249
*0_4
PR250
+V3P3A
*Short_4

Thermal Protection PR6

+VIN1_KEPL
Video codec(VDC)

a
(1) Need fine tune *VC@0_4 DESIGN NOTE: +V1P8_KEPL

*VC@1u/6.3V_4
for thermal protect point Delay 15 usec

PC15
PD7 ICC max-400 mA
DA2J10100L
(2) Note placement position

i
PU1
1 5
+V3P3S VIN VOUT
PR3

1
t
PR184 VEN1_KEPL 3

*VC@10u/6.3V_6
D EN 4 D

PC13
1M_6 PQ11 VFB1_KEPL
*VC@100K/F_4 2 FB PR4
AO3409

*[email protected]/10V_4
2 GND *VC@47K/F_4

PC8
+V3P3A_LDO PR236 *Short_4 +V5A_LDO_THRM *VC@RT9053AGB
H53295-001

3
+V5A_LDO PR237 *0_4 PCB FP = SOT23_5
PCB FP required

3
2

n
(31,42,43) V1P05A_EN
PR186 PR2
PQ10 *SHORT_6 *[email protected]/F_4

1
DTC144EUA

+V5A_LDO_THRM +V5A_LDO_THRM

e
PR238 *Short_4
VR_ALW_EN (31) 0818 unstuffed related RC components of Kepler

PR188 PC205 PR196

PR191 200K/F_4 0.1U/50V_6 200K_6

3
1.5K/F_4
Video codec(VDC)

d
PR122 2.469V 3
10K/F_4_3435NTC + 1 2
2 +V3P3A
- PQ17 PR12
3

i
PU20A PC204 2N7002K +VIN2_KEPL

4
AS393MTR-E1

1
0.1U/50V_6 *VC@0_4

*VC@1u/6.3V_4
2

PC21
(31,42,43) V1P05A_EN +V1P25_KEPL
PR189
PQ12 200K/F_4

f
2N7002K PU3
1 5
1

+V3P3S VIN VOUT

*VC@10u/6.3V_6

*VC@22uF/6.3V_6

*VC@22uF/6.3V_6

*VC@22uF/6.3V_6

*VC@22uF/6.3V_6
PR29

PC20
VEN2_KEPL 3

PC250

PC251

PC252

PC253
EN 4 VFB2_KEPL
5 *VC@100K/F_4 2 FB PR11

*[email protected]/10V_4
+ 7 GND *VC@22K/F_4
C 6 *VC@RT9187CGB C

PC16
n
- PCB FP required PCB FP = SOT23_5
PU20B
AS393MTR-E1

**[email protected]/10V_4
PC255
PR9
*[email protected]/F_4
For EC control thermal protection (output 3.3V)

o
+V1P25_KEPL_DIS

PU25 +V1P25_KEPL
1
+V5A S1
PR233 *VC@100K/F_4 2 6 +V1P25_KEPL_D1 PR234 *VC@100/F_4
G1 D1

C
4 3
S2 D2
(12,22,34,42,43) SLP_S3# SLP_S3#_KEPL 5
PR235 *VC@100K/F_4 G2
*VC@FDG6301N
0819 Changed PU25 QPN
0818 unstuffed related RC components of Kepler

a
Discharger of S0 power rails Video codec(VDC) SS_V1P0_KEPL DESIGN NOTE:
Delay 200 usec
Imax = 4A

t
PC23
*[email protected]/50V_4 V1P0_KEPL_FB
+VBATA +V5S +V3P3S +V1P8S +15V +VSW_KEPL_1P0_LX
+V1P0_KEPL
B +V5A +V3P3S Rating 11A B
KEPL_AGND PU4 PL3
PR193 PR194 PR187 PR185 PR190 1 9
VFB SW1

n
1M_4 22_8 22_8 22_8 1M_4 PR19 3 10 *VC@1uH_7X7X3
PC47 *VC@100K/F_4 EN_V1P0_KEPL 6 SS SW2 11

[email protected]/10V_4
*VC@10u/16V_6
*VC@22u/6.3V_8

*VC@22u/6.3V_8
**VC@22u/6.3V_8
12 EN SW3

PC67

PC66
+VSW_KEPL_1P0_LX VBST_KEPL VBST_KEPLER_1P1 PR17

PC216

PC218

PC217
SLP_S3D PR45 VBST *VC@100K/F_4
SLP_S3D (37,42) *[email protected]/25V_4 *VC@0_4 13 5 PG_KEPL PC24
VIN1 PG
3

14 *VC@1u/10V_4
VIN2
3

15 2 +VREG5_KEP PR16
PR192 VIN3 VREG5 *VC@0_4

a
(12,22,34,42,43) SLP_S3# 2 PQ18 1M_4 2 2 2 2 7 16 V0_V1P0_KEPL_FB
DTC144EU PC202 8 PGND1 VO
*VC@10u/16V_6

*VC@10u/16V_6

*[email protected]/25V_4
PQ14 PQ15 PQ13 PQ16 *2200p/50V_4 PGND2 26
PC27

PC28

PC37
2N7002K 2N7002K 2N7002K 2N7002K 4 TG9 25
1

PR195 17 GND TG8

*VC@22p/50V_4
TG1
TG2
TG3
TG4
TG5
TG6
TG7
1

EPAD

PC25
*100K/F_6
PR14
KEPL_AGND *VC@TPS54426RSAR *[email protected]/F_4

18
19
20
21
22
23
24
u
G58514-001
EN_V1P0_KEPL TPS54426 V1P0_KEPL_FB
LCC16_65MM_SQ4P10MM_106DIE
SLP_S3#_F_F (41)
**[email protected]/10V_4
PC32

PR15
*VC@22K/F_4
+VSW_KEPL_1P0_LX

R416 *VC@0_6

Q
R424 *VC@0_6

**[email protected]_6
KEPL_AGND

PR42
KEPL_AGND +V_SNB_KEPL

**VC@100P/50V_4
Design Note:

PC50
A Place Holders only, A
R-C values need to select

CAD NOTE:
place these component close to IC with the minimum loop.
0818 unstuffed related RC components of Kepler

Quanta Computer Inc.

PROJECT : ZHR
Size Document Number Rev
1A
Kepler VRs/Thermal
Date: Monday, September 14, 2015 Sheet 43 of 47
5 4 3 2 1
 5 4 3 2 1

44

l
INA DEVICES 1

tia D

en
f id
n
C C

Co
ta
B B

an
A

Q u 0818 unstuffed related RC components of current sensor

0819 Deleted all current sensor INA219

Size Document Number

Quanta Computer Inc.
PROJECT : ZHR
Rev
A

INA DEVICES 1 1A

Date: Monday, September 14, 2015 Sheet 44 of 47

5 4 3 2 1
 5 4 3 2 1

INA DEVICES 2

l
45
D

tia D

en
fid
n
C C

Co
ta
B B

an
A

Q u 0818 unstuffed related RC components of current sensor

0819 Deleted all current sensor INA219

Size Document Number

Quanta Computer Inc.
PROJECT : ZHR
Rev
A

INA DEVICES 2 1A

Date: Monday, September 14, 2015 Sheet 45 of 47

5 4 3 2 1
 5 4 3 2 1

Model Version CHANGE LIST 46

ZHR/ZHRA 1A

l
12/24
A01 Removed voltage divider of M0_OCAVREF and M0_ODQVREF,renamed M0_OCAVREF and M0_ODQVREF (Page 6)
A02 Removed voltage divider of M0_OCAVREF and M0_ODQVREF,renamed M0_OCAVREF and M0_ODQVREF(Page 7)
A03 Deleted RCOMP resistor (Page 8)
A04 changed damping resistors of SPI ROM from 22ohm to 10 ohm (Page 9)
A05 Swapped PCIe/CLKREQ/CLK between Video codec and WLAN (Page 9)
A06 Net name of WIFI_32KHz changed to SDCARD_WP (Page 10)
A07 Changed damping resistors of VCC sensing from 2.2ohm to 100 ohm(Page 12)
A08 Deleted C3130,C3137(Page 13)
A09 added 1K resistor on PWR_SD_GATE_EN,discharger of SD power supply made as placeholder (Page 19)

a
A10 Connected EC_SERVO_JTAG_RST_N signal from A25 of EC to pin 28 of Servo,Stuff R956/R958 (Page21)
A11 Net name of WIFI_32KHz changed to SDCARD_WP (Page23)
A12 Add power gating forWiFi power,Change PCIe mapping of WLAN (Page24)
A13 Add power gating for LTE power(Page 25)
A14 co-layout ST with Infineon TPM, if change to ST,RA,RB,RD,RE,RF are unstuffed , ST PN is T33ZP24AR28PVSM,Change the power option of TPM to +V3P3A_PRIME (Page 27)

i
A15 Add power gating for Track pad power(Page 29)
A16 Connected EC_SERVO_JTAG_RST_N signal from A25 of EC to pin 28 of Servo,remove RAMID1/2,unstuff R981,tie to WP pin of EC ROM,rename RAM_ID0 to BOARD_ID0(Page30)
A17 Change PCIe mapping of Video Codec (Page 32)
A18 Add power gating for Touch screen power (Page33)
A19 add voltage divider for SLP_S3#/SLP_S4# level shifter(Page34)
A20 Removed BC_IADP and BC_IDHG connections(Page 36)

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A21 Delete offpage of +V1P05A_OUT(Page 42)
D D
A22 Change sensing point to +V1P05A_R_SOC (Page 44)

12/26
A23 Add Footprint of Video codec (Page 32)
01/02
A24 stuff back Swapped Drain and source wiring of Q3057/Q3076(Page 9)
A25 Changed SD slot to push-push type (Copied from 0C7) (Page 19)
A26 Added one more 10uF to meet 1x 22uF closely,Changed R340 to 0 ohm,Added one more 0 ohm for suffering 1.5A rating(Page 20)
A27 unstuffed R64/R66 (Page 22)
A28 Added level shifters for MIC present pin and MIC INT,Add option path for I2C of MIC SW, default is USB charger path (Page 27)

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A29 added pullup for LID_OPEN_OUT2_R,Renamed from LID_OPEN_R to LID_OPEN_OUT1_R,Renamed to LID_OPEN_OUT2_R,added Diode of isolation for LID_OPEN_OUT2_L (Page 30)
A30 Changed Q35 to Level shifter,Added Level shifter for MIC I2C signals (Page 35)
A31 Changed slave address of current sensor in order to sync with BCRD(Page 44,45)
01/03
A32 changed C load of PCH 32,768K from 15pF to 18pF (Page 12)
A33 corrected the net name of PP3300_DSW(Page 16)
A34 corrected the net name of PP1800_PCH (Page 20)
A35 changed R3216 to 2.7K(Page 23)
A36 deleted external S0 pullip of AUDIO_CODEC_IRQ (Page 26)

e
A37 stuffed R353, unstuffed R591, depend on leakage debugging then decide on this(Page 27)
A38 corrected the net name of PP5000_DSW,stuffed R474 ,changed the power button of KB to Lock function,stuffed R475(Page29)
A39 moved pullup of thermal I2C to thermal IC page,merged SMBUS of BATT and Thermal, besides Sensor I2C is changed from SMBUS1 to I2C1,re-named for mergering SMBUS
of BATT and Thermal(Page 30)
A40 corrected the name name of RTC power,deleted reduntant R1053,Changed the damping resistor of SVID alert from 0 ohm to 49.9 (Page 31)
A41 Deleted diode which prevent leakage from going to sensor,Changed pull up power of GYRO_INT2 to +V3P3S,deleted RST pin of Touch screen, using VDD reset with RC
delay,removed option of G-Sensor power supply(Page 33)
A42 remove offpage of MOIC own signals and V105A_EN is input pin for MOIC(Page 42)

01/05

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A43 deleted external pull ups of I2C due to Intel mentioned there have strongly internal pullups in SoC (Page 10)
A44 changed Q3074 single MOSFET instead of dual, changed SDIO power circuitry to meet Intel's timing requirement for transistion between 1,8V and 3.3V (Page 19)
A45 Changed connection of EC WP (Page 30)
A46 Added "GS@" in value as a BOM option for G-sensor(Page 33)
A47 changed Level shifter of SERIRQ to MOSFET type,unstuffed pull down of PCH_RSMRST_L,Added level shifter for EC WP (Page 34)
A43 go for optional connection of Touch Pad I2C/INT directly,go for optional connection of Audio I2C thru level shifter (Page 35)

i
A44 Added 3 power units for Kepler (Page 43)
01/06
A45 Added the connection of LID_OPEN_OUT2_L(Page 26)
A46 Changed R144 to 4.7K(Page 29)
A47 correct net name for Wifi power(Page 35)
A48 reserve placeholder R212,R218 for additional RAM ID (Page 7)

f
01/07
A49 use 100K instead of 10k for empty resistor (Page 23)
A50 corrected net name of pin26 (Page 25)
A51 deleted the optional of USB charger (Page 27)
A52 Deleted USB charger IC,Stuffed USB power switch (Page 28)
A53 USB_ILIM_SEL to left NC,USB_CTL1 to left NC(Page 30)
A54 corrected PU21,PU31,PU32 Footprint(Page 43)
01/08
A55 added 4 pins for RAMID (Page 10)
A56 corrected Footprint of SDIO power IC(Page 19)
C
A57 for layout, changed +V3P3A_EC to +V3P3A (Page 21,31,34) C

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A58 Swapped COEX1 and COEX2 (Page 25)
A59 Changed USB CMC to PCB-CMC (Page 28)
A60 Lock works by KB matrix, not GPIO, remove connection (Page 29)
A61 added dedicated 1uF and 0 ohm (placeholder) on Ball C9,added 0 ohm (placeholder) on Ball G12/H12(Page 32)
A62 R837 is stuffed that based on M.2 spec(Page 35)
A63 removed +VDDQ_VTT_OUT (Page 40)
01/09
A64 change RAM ID0 form Ball AG1 to AF3,changed RAM ID1 form Ball V6 to AE4, RAM ID3 from Ball B8 to AD2,Removed VNN I2C due to VNN is SVID typePage9,10)
A65 added VNN_VR_HOT_N (Page12)
A66 changed Pin19 from +V3P3VA to GND(Page 27)

o
A67 Changed L5/L6 footprint (Page 28)
A68 VNN I2C disconnection due to VNN is SVID type (Page 30)
A69 Added VNN SVID ALERT connection,Added VNN SVID DATA connection,Added VNN SVID CLK connection(Page 31)
A70 Removed VNN level shifter due to VNN is SVID type(Page 35)
A71 added 9 GND pin on ORCAD library for PU10, PU32(Page 36,43)
A72 added placeholder cap for S0 power input (Page 37,42)
A73 added 5 GND pin on ORCAD library for PU22(Page 40)
01/12
A74 added soft start for ACIN,stuffed PR373 for 3 cell battery ,due to embeded battery, removed the TEMP_MBAT(Page36)
A75 swapped PR169 and PC69,swapped PR171 and PC110 (Page37)
A76 removed offpage of MOIC_RSMRST(Page 42)
A77 Add bridge resistors for Kepler AGND (Page 43)
A78 unstuffed R3722/R3723 due to w/o quad mode,Changed MOSFET with higer switching speed Q3075,Q3076 (Page 9)
A79 stuffed C199 (Page 16)

C
A80 added voltage inverter due to CD/WP are normal close,added 0 ohm for SDIO discharger circuitery ,changed SDMMC3_PWR_EN_N_G Pullup value to 10K(Page 19)
A81 deleted R42 due to level shifter was deleted(Page 24)
A82 added caps placeholder for EMI(Page 28)
A83 separated KBC_AGND,Changed KBC_AGND(Page 30)
A84 Added empty 0.1uF from Ball G12 to H12(Page32)
01/13
A85 changed Footprint of WiFi NGFF (Page24)
A86 swapped pins of KB ESD for layout(Page 29)
A87 Swapped pin of RP1 for layout (Page 30)
A88 defult un-stuff VNN components (Page 31,41,44)
01/15
A89 corrected net name of eMMC RCLK (Page 19)
A90 Swapped USBP/N for layout (Page 27)

a
A91 moved diode from input to output of USB load switch,added screw holes(Page 28)
A92 Merge KBC_AGND wtih DGND (Page 30)
A93 changed R1057,PR340 from 10K to 100K (Page 31,36)

01/16
A94 Changed PWR button connection (Page29,31)

t
A95 Changed SMC_ONOFF_N connection (Page31)
01/18
A96 added RAMID table, dfault optional of BOM is for Samsung 4GB (Page 10)
A97 Added eMMC table ,dfault optional of BOM is for Samsung 32G (Page 19)
A98 deleted TP189 for layout (Page 30)
01/19
A99 added back connection(USB_ILIM_SEL,USB_CTL1) for USB charger (Page 30)
B B
A100 PR42 Changed resistor value tolerance as 5% (Page43)
A101 changed the connector from 30 pin to 34 pin, and added back connection for USB charger (Page 27)
A102 added back USB charger controller (Page28)

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01/20
A103 Changed QPN for PU14 (Page 38)
A104 deleted jump of +V1P8A_PRIME for layout (Page42)
A105 C300/C310 are changed to 0402(Page 13)
A106 swapped L+/L- of SPK (Page26)
A107 Swapped pin of L4 for layout (Page 28)
A108 Changed QPN of USB charger IC (Page28)
01/21

a
A109 adding zero ohm x3 for +V1P05A_R_SOC layout improvement(Page 13)
A110 Changed pin14/15 of SD card to NPTH (Page19)
A111 Changed Hole2 to NPH (Page 28)
01/23
A112 Changed QPN of R86/R105/PR226/PR138/PR49/PR101/PR214 (Page32,36,38,39,41)
A113 Moved C10 from CHB to CHA for layout, exchanged VTT decoupling caps between CHA and CHB for layout(Page 17)
A114 Moved C8 from CHA to CHB for layout, but keep being stuffed in single channel SKU.exchanged VTT decoupling caps between CHA and CHB for layout (Page18)
01/28
A115 deleted SPI Quad mode connection (Page 9)
A116 JP20/JP1/JP7/JP6/JP11 is changed to 0.001 ohm(Page36,37,39,41)

u
A117 corrrected PU11 to be stuffed(Page45)
03/01
3A B01 Added BOARD_ID1/BOARD_ID2,and for DVT1,changed board ID from 000 to 001(R612 is stuffed, R616 is un-stuffed (Page 30)
B02 Added 100k series R on SPI_WP_ME to separate from EC pin for hacking(Page 30)
B03 Removed VBATA_VR_HOT_N from EC,added un-stuffed resistor and TP for debugging use(Page 30)
B04 Added EC_WAKE_L latch circuitry for EC HIB mode support (Page 30)
B05 Changed PR229 from 1M to 100K for battery cell configuration error (Page 36)
B06 Added 4x22uF on +V1P25_KEPL (Page 43)
03/02
B07 Moved STARTUP_LATCH_SET from GPIO46 to GPIO201(Page 30)
03/04
B08 added option of either power or GND connection for SoC Ball V29, added 2 caps (Page 13)
B09 added option of either power or GND connection for SoC Ball M41,P41, added 2 caps (Page 14)
B10 added option of either power or GND connection for SoC Ball T40,P40, added 2 caps (Page 14)
B11 changed back to non-USB charger SKU (Page 28)

Q
B12 Changed pullup on KB_ROW02_SW to 100K (Page 29)
B13 Changed pull down on KB_ACPRESENT_4137 to 1M (Page 29)
03/05
B14 added 4x1uF,4x22uF,1x10uF on DDR_V1P05A (Page 13)
B15 corrected source of power net of SoC Ball M41,P41(Page 14)
B16 unstuffed Q33,R565 stuffed R314,R188,WiFi power is connected to +V3P3A directly, not thru power gating (Page 24)
B17 unstuffed Q15, stuffed R185,R486,R490,LTE power is connected to +V3P3A directly, not thru power gating (Page 25)
B18 Changed C115 QPN (Page 25)
B19 Changed QPN of Track pad connector (Page 29)
B20 Changed power domain of G-sensor SMBUS pullup (Page 30)
B21 Added a TP for EC GPIO12,Deleted R308 (Page 30)
B22 Removed EC_VNN_I2C3_ALERT_N from EC, added un-stuffed resistor and TP for debugging use(Page 30)
B23 separated SMBUS of BATT and Thermal IC, renamed net name ,Moved Thermal SMBUS from I2C0_CLK0 to I2C3_CLK0 (Page 30)
B24 Changed GPIO123 from EC_WAKE_L to EC_STRAP_GPIO1,Changed pulllup on EC_WAKE)L to 100K,removed R337 and R341 (Page 30)
B25 unstuffed R361,LTE power is connected to +V3P3A directly, not thru power gating(Page 30)
A
B26 changed VDDQ_VTT enabled pin from SLP_SX to SLP_S3 (Page 31) A

B27 Added 0E resistor on TOUCHPANEL_PWREN,unstuffed R512, Q15, stuffed R7,R17Touch screen power is connected to +V5A directly, not thru power gating (Page 33)
B28 renamed the net name of thermal SMBUS and move the pull up to EC page (Page 33)
B29 SLP_SX related components are stuffed(Page 34)
B30 renamed the net name of Battery/Charger (Page 36)
B31 Change pullup on V5A_PWRGD from +V5A_LDO to +V5A (Page 37)
B32 Changed JP1 from 0.001 to 0.002 (Page 37)
B33 Changed pullup on V3A_PWRGD from +V3P3A_LDO to +V3P3A (Page 37)
B34 Changed 5V solution from RT7291A to RT7291B (Page 37
B35 Deleted pullup on VGG_VR_HOT_N,VNN_VR_HOT_N (Page 39,41)
B36 Added 22uF cap on +VDDQ_M0_M1_R(Page 40)
B37 Added net name VNN_RGND (Page 41)
B38 Changed the pin1 of PR161 from +V1P05A to +V1P05A_R_SOC,Changed PC176 from 1uF to 0.1uF (Page 42)
B39 Changed PC8,PC16 from 0.1uF to 0.047uF,and PC23 from 0.047uF to 0.01uF, and PR11 from 47K to 22K, PR15 from22.1K to 22K, and unstuff PR42/PC50 (Page 43)
B40 Added MOSFET on SRTCRST# and SoC_RTEST#,controllered by EC (Page 12)
03/06
B41 un-stuffed R246 (Page 9)
B42 Changed Footprint of Hole2(Page 28)
B43 Changed pullup on SPI_WPI_ME from 10K to 100K (Page 30)
B44 added pull down on VP9 JTAG_TEST_MODE,Added R513/C417 on VDD of Video codec,connected VDD power from +V1P05A_CODEC_VDD to +V1P05A_CODEC (Page 32)
B45 stuffed level shifts for Touch screen I2C/INT signals,Q3,Q6,Q43 are stuffed, R18,R31,R403 are unstuffed (Page 35)

PROJECT MODEL Quanta Computer Inc.

DOC NO.
: Chrome APPROVED BY: DATE:
PROJECT : ZHR
Size Docum ent Num ber Rev
PART NUMBER: DRAWING BY: REVISON: Change list-1 1A

Date: M onday, Septem ber 14, 2015 Sheet 46 of 47

5 4 3 2 1
 5 4 3 2 1

Model Version CHANGE LIST 47

ZHR/ZHRA B46 Connected Battery TEMP to charger IC present pin,and PR183 unstuffed (Page 36)

l
3A B47 Changed +V1P05A sensing point of current sensor PU16 (INA219) (Page 44)
03/09
B48 Deleted TP87,TP88 (Page 9)
B49 connected CORE_V1P15_S0ix,FUSE_V1P15_S0ix,VCCSRAMGEN_1P15 to +1P15A directly, and Deleted R168,R493(Page 13)
B50 unstuffed R254, stuff R255 for isolate SERIRQ from TPM (Page 27)
B51 Changed and stuffed ESD solution from Varistors to TVS for USB3 port (Page 28)
B52 added back and unstuffed the USB charger, keep reserving this feature, and Added option 0E on USB I/F, default stuff them for non-USB charger(Page 28)
B53 Stuffed C242, unstuffed C268 ,connected R92 to +V1P05A_CODEC(Page 32)
B54 changed power net of these caps to +V1P05A_CODEC_VDD (Page 32)

a
B55 renamed the net name of thermal SMBUS and move the pull up to EC page (Page 33)
03/10
B56 Added offpage on SMBUS for external level shifter(Page 16)
B57 added Discharge circuitry on +VSDIO (Page 19)
B58 Swap pin of L7 for layout and Swap pin5/6 of U29 for layout (Page 28)
B59 Added a diode for protection of draw current from sysytem to servo board (Page 30)

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B60 added OR gate for V5A_EN(Page 31)
B61 Added level shifter on CLKREQ of Video codec;unstuffed R96,R100,R91,R88;Changed R119/R128 from 5% to 1% tolerant resistors (Page 32)
B62 Changed drain PU of SLP_S3/SLP_S4 from +V3P3A_PRIME to +V3P3A for avoiding the glitch(Page 34)
B63 Added level shifter on SMBUS from SoC to XDP, it will be un-stuffed in MP(Page 35)
B64 Added Discharge Circuit for +V1P25_KEPL (Page 41)
03/11

t
D B65 changed connection of KB ESD power to +V5A(Page 29) D

B66 renamed EC_SMI_3P3_L ,EC_SOC_WAKE_SCI_N,EC_KBD_IRQ#,PCH_WAKE_EC_L,EC_REST_L for adding level shifters (Page 30)
B67 Added 5 FETs as level shifters on EC OD GPIOs (Page 34)
B68 stuffed PR8, and unstuffed PC12 to disable +V5A_LDOt (Page 37)
B69 Changed Acer thermal protection circuit--> changed the pullup power source of input pins of OP AMP from +V5A_LDO to +V3P3A_LDO, added option for them,
default is stuffed for +V3P3A_LDO(Page 43)
03/12
B70 stuffed R292/R261 for making connection of SPI_WP/SPI_HOLE from servo board(Page 9)
B71 added KBD_ALERT pin to notify SoC to lock ME FW Keep reserving this feature in DVT build (Page 10)
B72 unstuffed all VNN related components due to all SKUs in DVT1 are Fixed VNN(Page 12)
B73 Changed QPN of eMMC from samsung32G to Hynix32G(Page 19)

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B74 deleted R138 (Page 23)
B75 unstuffed R790/R791/R792/R793/U37/C403 for USB charger support(Page 28)
B76 added KBD_ALERT pin to notify SoC to lock ME FW (Page 30)
B77 unstuffed all VNN related components due to all SKUs in DVT1 are Fixed VNN, and stuff the option of Fixed VNN (Page 31)
B78 unstuffed R169,R171, changed the value of R232/R438 for Fixed VNN SKU (Page 31)
B79 unstuffed R180,R186,R175,changed the value of R230/R427 for Fixed VNN SKU(Page 31)
B80 unstuffed all VNN related components due to all SKUs in DVT1 are Fixed VNN, and stuff the option of Fixed VNN(Page 41,44)
B81 Added PR238 0E on VR_ALW_EN (Page 43)
B82 Added untuffed cap on pin4 of PU3(Page 43)
03/13

e
B83 Changed 620 ohm to 619 ohm for PUR request(Page 22)
03/27
3B C01 Changed some of 0 ohm to short pad
04/16
C02 Changed pullup on +VSDIO power switch enabled pin to +V3P3A_PRIME for SoC G3 leakage,Changed C419 from 0.01uF to 0.1uF (Page 19)
C03 Added VP9_CODEC_RESET# to reset VP9 (Page 30, 32)
C04 EC SMBUS and I2C PUs changed to 10K (Page 30)
C05 Connected EC_HIB_L between EC and Wake circuit (Page 29,31)
C06 Changed from OR Gate to diode OR for V5A_EN(Page 31)
C07 renamed GND_H12 to KEPL_GND,Added TP on VP9 UART and SPI,Added 0E options , but un-stuffed on VDD33_USB,DVDD_USB,VP_USB (Page 32)

d
C08 Changed VP9 X'tal C_load from DGND to KEPL_GND,Changed VP9 X'tal C_load to 33pF, it would be fine tuned on MP stuffed board(Page 32)
C09 Added +V5S options to Touch screen(Page 33)
C10 Provided option to pullup PLTRST# to +V3P3S, Changed pullup power of XDP SMBUS from +V3P3A to +V3P3S (Page 34,35)
04/20
C11 moved SDCARD_WP from GPIO_SUS5 to I2C_6_DAT, renamed the net of GPIO_SUS5 and made Q95 as stuff to enable ME lock feature (Page 10,23)
C12 moved SDCARD_WP to I2C_6_DAT, made option of EC I2C as unstuff (Page 10)

i
C13 added 100 ohm in series with +VNN_SENSEP(Page 12)
C14 made C409,C408,C410,C414 as un-stuffed (Page 13)
C15 Before making conclusion for power gate of WiFi to be stuffed or not,in order to prevent the leakage from this circuit, made the R201,R494,R495 as unstuff(Page 24)
C16 Before making conclusion for power gate of LTE to be stuffed or not,in order to prevent the leakage from this circuit, made the R207,R172,R498 as unstuff(Page 25)
C17 disconnected AGND between Audio code to CN13 (Page 26)
C18 Chnaged TPM power domain from S0 to S5 power for leakage issue (made R249 as unstuff and R240 as stuff, and made a dedicated TPM PLTRST#(Page 27)
C19 deleted AGND, connected to DGND directly thru 0 ohm resistor for recording noise, adjusted pin mapping of audio signals for adding one more GND, made GND option

f
on the pin of +V3P3A, default on pin19 is power pin(Page 27)
C20 added diode on EC_RST# to prevent back drive from HW RST IC to EC (Page 29)
C21 Changed Board_ID PU/PDs from 1K to 100K, removed BATT_EN# connection to EC GPIO62, made a disconnection on CORE_PWROK_R to EC (Page 30)
C22 Simplified VP9 CLKREQ level shifter (there has internal pull up in VP9) (Page 32)
C23 Added diode and removed PU on GYRO_INT1 and GYRO_INT2, Added option to +V3P3A for Gensor power(Page 33)
C24 made option of LS on EC I2C as unstuff, added a level shifter with gate at 1.8S added for TPM reset and added 0 ohm option between TPM_PLTRST# and PLTRST# (Page 34)
C25 Changed pullup power of XDP SMBUSback to V3P3A, and Touch INT connected to GPIO_SUS1(Page 35)
04/22
C26 added pullup R591 at 1.8V,made the pull up at 3.3V unstuffed, Changed Q26 from 2N7002 to PJA138K for changing Vg from 3.3V to 1.8V(Page 9)
C27 changed R291 from 1K to 10k (Page 28)
C
C28 unstuffed R296 due to added pullup at 1.8V closed to SPI ROM, added option on EC SPI WP, SPI_WP_ME is connected to screw driectly, let it NC from screw(Page 30) C

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C29 stuffed R584 for ME lock enabling, change PU on G-sensor I2C to +V3P3A_EC, made them un-stuufed, they are pulled up at the other side of level shifter(Page 30)
C30 added EC_ACDET_CTRL on GPIO50 (Page 30)
C31 Added level shifters option on Gensor I2C if sensors need to work in S3/S5, default design is working on S0 only as Cyan pre-EVT (Page 35)
C32 changed PR230 from 10K to 100K and PR181 from 1.02K to 10.2K (Page 36)
C33 Changed Charger soft start circuitry using P MOS, added AC detect disable circuit to minimise the power onsumption in S5(Page 36)
C34 added AC DET Disable cirucit which is used to minimise the power consumption in S5 in DC mode (Page 36)
C35 changed PR94/PR207 from 10K to 100K, and changed the net +V5A in VCC page to +VCC_VCC,changed pin6 of VCC0 from +V5A to +V5S,PR126 from 0.01ohm to 0 ohm(Page 38)
C36 added 0.1uF on VCC_EN, and changed one of decoupling caps of +VCC from 330uF_7343 to 22uF MLCC, made the MLCC as un-stuffed (Page 38)
C37 changed +V5A in VGG page to +VGG_VCC, added 0.1uF on VGG_EN,changed PR55/PR54 from 10K to 100K, changed pin6 of VGG from +V5A to +V5S,PR32 from 0.01 to 0 (Page 39)
C38 changed the decoupling caps of +VGG from 330uF_7343 to 22uF MLCC (Page 39)
C39 changed PR202/PR100 from 10K to 100K, Added offset circuit to the VNNSENSEP and added offset circuit to the VNN to support +VNN voltage to min in S3 (Page 41)

o
04/24
C40 added R674 for layout (Page 26)
C41 changed EC symbol to correct GPIO134 (Page 30)
C42 swapped TOUCHPANEL_PWREN and EC_ACDET_CTRL,removed R497 (Page 30)
C43 Changed FP of PQ23,PQ24 for layout estimation ,Changed the soft start circuit back to pre-EVT design(Page 36)
C44 Changed PQ22 to AO3409 P-MOS (Page 41)
04/27
C45 Changed Gate power of HDMI level shifters from +V1P8S to +V1P8S for leakage issue(Page 22)
C46 Changed PD of EC_HIB_L from 10K to 100K (Page 31)
04/28
C47 Deleted 0 ohm of I2C_6_SCL/ I2C_6_SDA (Page 10)
C48 Deletedd APS related circuit (Page 16)
C49 stuffed all caps on SD3 interface for EMI request, Deleted R205,R206,R198,R194 (Page 19)
C50 unstuffed R573 R570, there have internal PUs in SoC (Page 27)

C
C51 changed pullup of R798 and R799 from +V3P3A_EC to +V3P3A for layout (Page 28)
C52 changed PU option of G-Sensor I2C from +V3P3S to +V3P3A, disconnected I2C between EC and SoC (Page 30)
C53 corrected the mark of value of R9,R22,R383 as to be un-stuffed, changed power source of G-sensor from "S" to "A"(Page 33)
C54 Deleted level shifters between EC to SoC (Page 34)
C55 Deleted level shifters of G-sensor I2C, default power source of G-sensor changed from "S" to "A"(Page 35)
04/30
C56 changed Footprint of L2/L3 (Page 28)
C57 added the gate for disabling Trackpad INT during S3 if the lid angle>180, made un-stuff before EC is not ready (Page 29)
C58 replaced EC_ACDET_CTRL with TP_INT_DISABLE for disabling Trackpad INT during S3 in yoga mode (Page 30)
C59 deleted AC DET Disable cirucit (Page 36)
C60 Changed PQ22 pin1 from +V3P3A to +V3P3A_PRIME(Page 41)
05/04
C61 changed C load of Y2/Y3 from 18pF to 15pF(Page 10, 12)
C62 deleted option R251 of ball V29 to be grounded, deleted option R659 of ball M41/P41 to be grounded (Page 14)
C63 NC pin35 of Daughter board CONN, changed FP of Hole10 (Page 27, 28)

a
C64 stuffed PD R417 on TRACKPAD_PWREN (Page 29)
C65 added 0E option on GS2 INT, diode D28 is un-stuff, added 0E option on GS1 INT, diode D27 is un-stuffed (Page 33)
C66 deleted PC258,PC260, added back buck caps 330uF/7343 (Page 39)
C67 added 100k PD on pin2 of PQ22 , added 0.1uF on pin2 of PQ21(Page 41)
05/05
C68 stuffed variable VNN related part, R148 (Page 12)

t
C69 Added PAD1 (Page 28)
C70 changed PU PWR of COREPWROK from +V3P3A to +V3P3A_PRIME(Page 31)
C71 For variable VNN support, stuffed R171,R169, changed R232, R438 from 200 ohm to 301 ohm, stuffed R180,R186, changed R230, R427 from 301 ohm to 453 ohm,
stuffed R175,stuffed R483,R469,R491,Q50, unstuffed R456,R489,Q53(Page 31)
C72 changed PU PWR of ALL_SYS_PWRGD from +V3P3A to +V3P3S and added option PU to +V3P3A_PRIME (Page 31)
C73 changed back to double FETs LS for VP9 CLK REQ (Page 32)
C74 changed PU PWR of PLTRST from +V3P3A to +V3P3A_PRIME (Page 34)
C75 Changed PR242 from 392K to 430K, PR247 from 110K to 100K, changed PR174 from 4.02k to 0 ohm (Page 36)
B B
C76 changed PU PWR of VCC_PWRGD from +V3P3A to +VCC_VCC thru 20K (Page 38)
C77 unstuffed PC259, PC262, changed PU PWR of VGG_PWRGD from +V3P3A to +VGG_VCC thru 20K(Page 39)
C78 unstuffed all parts of VNN OFFSET BACKUP CIRCUIT, Changed PR67 to 100 ohm, made double star symbol as un-stuffed even on Dynamic VNN SKU (Page 41)

n
C79 unstuffed PR248 on dynamic VNN SKU,changed PR241 from 100K to 115K , BOM change for variable VNN support(Page 41)
C80 BOM change for variable VNN support, stuffed RC232,PC233,PU22E(Page 41)
05/06
C81 changed QPN of U1011(Page 31)
C82 changed QPN of PU3 from RT9053 to RT9187 (Page 43)
05/07
C83 changed Footprint of L2/L3 (Page 28)
C84 changed R356 to 1M (Page 29)
C85 stuffed Q96 for enabling this feature in EVT, added PD for default setting and added 360@ in front of value for BOM option for convertible SKU only (Page 29)

a
C86 changed connection of output of U1010, stuffed R236 (Page 31)
C87 revised the voltage rating of PC276 from 25V to 50V(Page 36)
C88 changed PQ22 to BSS84 (Page 41)

3C 07/03
D01 Changed some of 0 ohm to short pad
D02 for DVT, changed board ID from 010 to 011,stuffed R612 and un-stuffed R616 (Page 30)
D03 Changed pullups of Battery SMBUS to 4.7K (Page 30)
D04 Changed PR241 to 470K which was stuffed in EVT build already (Page 41)
D05 Added power option for thermal protector and stuff PR250 as default (Page 43)
07/06
D06 Added option resistors on LID_OPEN_OUT2_L_CONN for MIC detection issue, stuffing R675 as default (Page 27)

u
D07 added option path on Headset jack detection,stuffed double invertor as default, unstuffed Q38 (Page 35)
07/09
D08 Stuffed R454,R184 and unstuffed R460,R178 for DVT main SKU configuration (Page 10)
D09 added ESD protection on TRACKPAD_INT#,EDP_HPD,PCH_DISP_ON,RF_EN,LID_OPEN_OUT1_R lines (Page 10,20,24,30)
D10 Changed Footprint of removing mylar for factory side request (Page 27)
D11 Changed X'tal of EC chip from 12.5pF to 9pF,the C load C366,C365 are changed accordingly (Page 30)
D12 Changed R636 from 0 ohm to 2.2 ohm as ESD protection on EC power line (Page 30)
D13 changed power source of touch screen from +V5A to +V5S for S3 power saving, (Page 33)
D14 Changed QPN of 3V VR (Page 37)
07/13
D15 Changed resistors value of voltage divider R484,R468, R55,R60 for S3 power saving,Changed LTE related components to "no stuff" (Page 25,35)
D16 Changed R430 from 10K to 100K for S3 power saving (Page 35)
D17 changed PR35 to 1.05K and PR34 to 1.15K for OCP increasing (Page 39)
D18 Changed PR241 to 309K to get more power saving (Page 41)
07/14

Q
D19 changed resistors value of RAMID from 10K to 100K for power saving ,Changed Hole4 Footprint (Page 10, 28)
07/16
D20 Added PAD9~15 as ESD protection,Changed Hole4 Footprint (Page 28)
D21 added +V5S_VGG power switch for meeting RT8175A power sequence (Page 39)
07/17
D22 Changed Q39 to PJA138K (Page 29)
D23 Changed PU26 to TPS22930 (Page 39)
07/29
D24 changed R539 from 10 ohm to 200 ohm, and re-wired pin14 of header to HW reset IC,making a connection change on EC_RST# for Auto recovery mode issue (Page 21,29)
D25 unstuffed R188,Q16,R197,Q57,Q58 after the validation of S3 battery life is done and no issue on WiFi (Page 24)
D26 added PG circuitry for TS power if no separated PG pin is assigned (Page 33)
07/30
D27 added three pathes to reset touch screen, D29 is stuffed by default,changed power source to the output of load switch (Page 33)
D28 added one more path of touch power by additional load switch , it is stuffed by default (Page 33)
07/31
A
D29 unstuffed D29,R247 and R7,stuffed back R17 as by default (Page 33) A

3D 08/18
E01 Changed some of 0 ohm to short pad

PROJECT MODEL Quanta Computer Inc.

DOC NO.
: Chrome APPROVED BY: DATE:
PROJECT : ZHR
Size Docum ent Num ber Rev
PART NUMBER: DRAWING BY: REVISON: Change list-2 1A

Date: M onday, Septem ber 14, 2015 Sheet 47 of 47

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