MODULE 1: INTRODUCTION TO SWITCHING SYSTEMS

Digital Systems The Signal Chain

- used in communication, business
transactions, traffic control, spacecraft
guidance, medical treatment, and internet
- has the ability to represent and manipulate
discrete elements of information
- deal with discrete/digital signals
- has better noise immunity and robustness
compared to analog

Signals Decimal Number System

- are any physical quantity that varies with - is a positional system (the weight of each digit
time, space, or any other independent is determined by its position)
variable/s. - is said to be of base/radix 10
In electronics: - uses 10 digits (0, 1, 2, 3, 4, 5, 6, 7, 8, 9)
● physical quantity = voltage/current - the coefficients are multiplied by powers of 10
● Independent variable = time - the highest-valued symbol (9) is one less than
Classification of Signals: the base of the number system (10)
● Analog (continuous-valued)
Binary Number System
- is a number system of base 2
- uses 2 digits (0 and 1)
- the coefficients are multiplied by powers of 2
- the highest-valued symbol (1) is one less than
the base of the number system (2)
- binary digits are often called bits

● Digital (discrete-valued)
Number Base Conversions

● Case 1: Any Number System to Decimal

Rule: Multiply each digit by its positional
value then add the products
❖ Real world signals are analog. ● Case 2A: Decimal to any Number System
❖ The signals in most present-day electronic using Integer (whole number)
digital systems use just two discrete values and Rule: Divide the integer and all
are therefore said to be binary because circuits successive quotients by the desired base
can be manufactured economically because of until a zero quotient is reached. Read the
transistors. remainders in reverse order.
● Case 2B: Decimal to any Number System
using Fraction which is less than 1
Rule: Multiply the fraction and all
succeeding fractional parts of the
 products by the desired base until a whole Complements of Numbers
number is reached. Read the integers in - used in digital computers to simplify the
order. subtraction operation and for logical
● Case 2C: Decimal to any Number System manipulation.
using Integer + Fraction Two types of complements for each base-r system:
Rule: Convert the integer part and the 1. Radix Complement
fractional part separately. Add the results. - also called r’s complement (in base 2,
● Case 3: Any Number System to any other this is called 2’s complement)
Number System - also called true complement
- to determine the r’s complement of a
Number Case Conversions (Special Cases) number, first get the (r-1)’s complement
● Special Case 1 then add 1 to its rightmost digit (LSB)
2. Diminished Radix Complement
- also called (r-1)’s complement (in base 2,
Octal to Binary: Convert each octal digit to this is called 1’s complement)
its 3-digit binary equivalent (pad with leading zeros - also called radix-minus-one complement
if necessary) - formed by subtracting each digit from its r-1
Binary to Octal: Group the bits by 3’s - for binary, the 1’s complement is formed by
starting from the radix point, then convert each changing the 1’s to 0’s and 0’s to 1’s
group to octal.
● Special Case 2 Subtraction with Complements
● Subtraction using 1’s complement
STEP 1: Get the 1’s complement of the
Hexadecimal to Binary: Convert each subtrahend
hexadecimal digit to its 4-digit binary equivalent STEP 2: Add the result of Step 1 to the
(pad with zeros if needed) minuend
Binary to Hexadecimal: Group the bits by STEP 3: If there is any end carry, remove it
4’s (start from the binary point) then convert each and add 1 to the rightmost digit
group to hexadecimal (LSB). If there is no end carry, get
● Special Case 3 the 1’s complement of the sum and
affix a negative sign.
● Subtraction using 2’s complement
STEP 1: Get the 2’s complement of the
Binary Arithmetic
subtrahend
● Addition
STEP 2: Add the result of Step 1 to the
Adding two binary digits:
minuend
0+0=0
STEP 3: If there is any end carry, discard it. If
0+1=1
there is no end carry, get the 2’s
1+0=1
complement of the sum and affix a
1 + 1 = 0 with a carry of 1
negative sign.
● Subtraction
Subtracting two binary digits:
0-0=0
0 - 1 = 1 with a borrow of 1
1-0=1
1-1=0
Other Arithmetic Operations Binary-Coded Decimal (BCD)
● Multiplication - binary is the most natural system for digital
systems
- most people are accustomed to the decimal
system, and one way to resolve this is to convert
decimal numbers to binary. Another way is to use
binary codes to represent the decimal numbers
(the most common way is to use the scheme
called binary-coded decimal)
- to encode a decimal number using BCD, replace
each digit with its corresponding BCD code rather
than converting the entire number to binary
- a decimal number in BCD is the same as its
equivalent binary number only when the number is
between 0 and 9
- a decimal number in BCD generally uses more bits
than its straight binary representation
- binary combinations 1010 through 1111 have no
meaning in BCD
- a number with k-decimal digits will require 4k bits
in BCD
- to get the decimal value from a BCD number,
group the bits by 4’s and decode each group
Binary Codes
- electronic digital systems with binary signals
- digital systems deal with discrete elements of
information (numeric and non-numeric
information)
- any distinct discrete element of information can
be represented using a binary code (i.e., a
pattern of 1’s and 0’s)

ASCII
- American Standard Code for Information
Interchange
- 7 bits (128 characters)

- using a coding scheme that uses a group of EBCIDIC

n-bits, the number of distinct codes N is: - Extended Binary Coded Decimal Interchange
Code
- given M elements to be represented by a binary - 8 bits
code, the minimum number of bits m needed is: - used on IBM mainframes

Switching Circuit Theory- mathematical study of the

properties of networks of idealized switches
- no maximum number or bits
 MODULE 2A: DIGITAL LOGIC GATES

Logic Gates Types of Logic Gates

- is the basic building block of a digital system 1. Inverter
- are interconnected in order to produce a - one of the simplest digital logic gates in
logic circuit (a logic circuit may have one or terms of function. This gate simply
more binary inputs and will correspond to inverts the logic applied to its input. In
only one binary output) other words, this gate simply
- are primarily implemented by using diodes or complements the input.
transistors that acts as electronic switches in
order to realize a particular “logic function”

Binary Logic
(+) Logic (-) Logic

True 1 0

False 0 1
Inverter IC: 7404 (Hex Inverter)
Logic Symbol:
Signals
(+) Logic (-) Logic

1 5V 0V Truth Table:

0 0V 5V

Circuits
(+) Logic (-) Logic
Function: Complementation/Inversion
1 ON/Conducting OFF/
Non-conducting Logical Expression:

0 OFF/ ON/Conducting
Non-conducting 2. OR Gate
- a logic gate that produces a high logic
TRUTH TABLE output when at least one of its inputs is
- table of combination (inputs, output) at logic high level. Note that an OR
𝑛
- number of combination = 2 (n is the number gate may have two or more inputs.
of inputs)

OR Gate IC: 7432 (Quad 2-input OR Gate)

 Logic Symbol:

Truth Table:

NOR Gate IC: 7402 (Quad 2-input NOR Gate)

Logic Symbol:
Function: Logical Addition/OR Operation
Logical Expression:
Truth Table:

3. AND Gate
- another basic logic gate whose output
is at a high logic level only when all
inputs are high.
Function: Not - OR Operation
Logical Expression:

5. NAND Gate
- produces a low logic output only if all its
inputs are high. This gate complements
the AND gate’s output. The NAND
AND Gate IC: 7408 (Quad 2-input AND Gate)
simply means NOT AND.
Logic Symbol:

Truth Table:

NAND Gate IC: 7400 (Quad 2-input NAND Gate)

Function: Logical Multiplication/AND Operation Logic Symbol:
Logical Expression:

Truth Table:

4. NOR Gate
- derived from the OR gate. It produces a
high logic output when all inputs are at
a low logic level and a low logic output
when at least one input is at high level.
 Function: Not - AND Operation 3-Input Gates
Logical Expression:

6. XOR Gate
- is an “exclusive” OR gate that produces
a high logic output only when one but
not all its inputs is high. When the
inputs are all high or low, the output is
low.
XOR Gate IC: 7486 (Quad 2-input XOR Gate)
Logic Symbol:
Operator Precedence (for evaluating Boolean
expression)
Truth Table: ● NOT
● AND
● OR

Function: Inequality/Exclusive - OR Operation

Logical Expression:

7. XNOR Gate
XNOR Gate IC: 74266 (Quad 2-input XNOR Gate)
Logic Symbol:

Truth Table:

Function: Equivalence/Exclusive- NOR Operation

Logical Expression:
 MODULE 2B: BOOLEAN ALGEBRA

Boolean Algebra 7. Laws of Absorption

- is the branch of mathematics used for digital ➔ X + XZ = X
logic systems ➔ X(X + Y) = X
- is used to study and analyze a digital logic ➔ X + X’Y = X + Y
circuit and was formulated by an English 8. Laws of Expansion
Mathematician in 1847 by the name of ➔ X • Y + X • Y’ = X
George Boole ➔ (X + Y) • (X + Y’) = X
- the basic rules of Boolean algebra are used
to represent a complex logic circuit into a De Morgan’s Theorem
more simplified form - the “+” symbols are replaced with “•”
symbols, and “•” is replaced with “+”
Boolean Algebra Rules symbols, each of the term in the expression
1. Logical OR is then complemented
(X + Y)’ = X’ • Y’
(X • Y)’ = X’ + Y’
➔ X+0=X
➔ X+1=1 Consensus Theorem
➔ X+X=X - is formed by multiplying the original terms
➔ X + X’ = 1 together, leaving out the selected variable
2. Logical AND and the complement.
XZ + X’Y + YZ = XZ + X’Y
[where YZ is a consensus term or redundant term]
(X + Z) (X’ + Y) (Y + Z) = (X + Z) (X’ + Y)
➔ X•0=0 [where (Y + Z) is a consensus term or redundant term]
➔ X•1=X
➔ X•X=X Proof of Consensus Theorem
➔ X • X’ = 0
3. Double Inversion

➔ X’’ = X
4. Commutative Laws
➔ X+Y=Y+X
➔ X•Y=Y•X
5. Associative Laws

➔ X + (Y + Z) = (X + Y) + Z

➔ X(YZ) = (XY)Z
6. Distributive Laws
➔ X(Y + Z) = XY + XZ
➔ X + YZ = (X + Y) (X + Z)
Universality of Gates: NAND - none of the standard symbols have bubble
on their inputs, all the alternate symbols do
- the standard and alternate symbols for each
gate represent the same physical circuit,
there is no difference in the circuits
represented by the two symbols
- NAND and NOR gates are inverting gates,
and so both standard and alternate symbols
for each will have a bubble on either the
input or the output.
- AND and OR are non-inverting gates, and
so the alternate symbols for each will have
bubbles on both inputs and outputs.
Universality of Gates: NOR
Product Term - a single variable or the logical
product of several variables (A, X’ , A’BC’ , XY’Z)

Sum Term - a single variable or the logical sum of

several variables (A, Z, B’ , A’ + B’ + C, X + Y + Z’)

Minterm (m) - the logical product of all variables

(ABC, A’BC’ , XY’Z, X’YZ’)

Maxterm (M) - the logical sum of all variables

(A +B +C, A’ + B + C’ , X + Y’ + Z, X’ + Y + Z’)

Alternate Logic Gate Representation Forms of Boolean Functions

- the alternate symbol for each gate is 1. Standard Form
obtained from the standard symbol by doing ● Sum of the Product (SOP)
the following: - a product term or several product
1. Change the operation symbol from terms logically added together
AND to OR, or from OR to AND (in ● Product of the Sum (POS)
case of the inverter, the operation is - a sum term or several sum terms
not changed) logically multiplied together
2. Invert each input and output of the 2. Canonical Form
standard symbol ● Sum of Minterms (Σ𝑚)
- consists of several minterms
logically added together
● Product of Maxterms (Π𝑀)
- consists of several maxterms
logically multiplied together

- the equivalences are valid for gates with

any number of inputs
Minterms and Maxterms for 3 Variables

Reducing Truth Table into a Logical Expression

Steps in Designing a Logic Circuit

1. Problem Analysis
a. Identify the inputs
b. Identify the output
c. Determine the relationship between
the input and output
2. Truth Table
3. Logic Expression
4. Logic Circuit
 MODULE 3: KARNAUGH MAP & QUINE-MCCLUSKEY METHOD

Module 3A: Karnaugh Map Don’t Care Condition

Karnaugh Map - combination of variables whose logical value
- also known as K-Map is not specified
- provides a simple straightforward procedure - can be used to provide further simplification
for minimizing Boolean functions of the Boolean expression in K-map.
- graphical representation of truth table
- a diagram made up of squares, each square
represents one minterm

Steps in K-Mapping Module 3B: Quine McCluskey Method

1. Determine the number of squares or cells of Quine-McCluskey Method
𝑛
the K-map 2 = 𝑁 - also known as Tabulation Method
2. Place 1’s or 0’s in its respective cells - specific step-by-step procedure that is
3. Form subcubes from the plotted 1’s or 0’s guaranteed to produce a simplified standard
➔ Subcube - a group of 1’s or 0’s that are form of expression for a function
adjacent to each other - Consists of two parts:
➔ Adjacent Cells - only one variable 1. Find all the terms that are candidates
changes as you transfer from one cell to for inclusion in the simplified function.
another These terms are called prime
𝑛 implicants
➔ only group or subcube of 2 can be
2. Choose among the prime implicants
𝑛
formed (2 is the size of subcube, also those that given an expression with the
indicate the no. of 1/0’s that was formed) least number of literals (essential
4. Write the corresponding expression based prime implicants)
on each subcube formed
➔ If 1’s are used, expression must be in Steps in Quine-McCluskey Method
minterms, then eliminate the variable/s 1. List down all the given minterms with its
that changed binary equivalent. Count the number of 1’s
➔ If 0’s are used, expression must be in in each minterm
maxterms, then eliminate the variable/s 2. Make the 0-cube column
that changed 3. Make the 1-cube column
4. Make the 2-cube column
Rules in K-Mapping 5. Make a prime implicant table to determine
1. Encircle any “1” square which cannot be the essential prime implicants
combined with any other “1” square 6. Write the expression
2. Encircle any “1” square which can be
combined with another “1” square to form a
group of 2. If a “1” square can be combined
in 2 or more ways, leave until later
3. Repeat step 2 for group of 4, 8, 16
4. Inspect if there are any uncovered “1”
squares. Combine them with other “1”
squares to form the biggest group possible
 MODULE 4: COMBINATIONAL LOGIC CIRCUIT

Combinational Logic Circuit 2. Full Adder - adds 3 bits mathematically

- consists of logic gates whose outputs at any
time are determined directly from the present
combination of inputs without regard to
previous inputs.
- does not use any memory. The previous
state of input does not have any effect on the
present state of the circuit.
Block Diagram:

Full Adder Truth Table

Examples of Combinational Logic Circuit

1. Half Adder - adds 2 bits mathematically Full Adder Circuit

3. Half Subtracter - subtracts 2 bits mathematically

Half Adder Truth Table

Half Subtracter Truth Table

Half Adder Circuit

Half Subtracter Circuit

4. Full Subtracter - subtracts 3 bits mathematically

Half Adder Circuit Implementations

Full Subtracter Truth Table

 ● 2-Bit Magnitude Comparator - compares
two 2-bit numbers
Input Output

● 𝐴1𝐴0 ● 𝐴>𝐵
● 𝐵1𝐵0 ● 𝐴<𝐵
● 𝐴=𝐵
Full Subtracter Circuit

5. Parallel Adder
● Binary Parallel Adder - produces the
arithmetic sum of two binary numbers
in parallel
● 4-Bit Full Adder

2-Bit Magnitude Comparator Truth Table

6. Magnitude Comparator - compares two

numbers, A and B, and determines their
relative magnitude. It has 3 outputs:
𝐴 < 𝐵, 𝐴 = 𝐵, 𝐴>𝐵
● Single Bit Magnitude Comparator -
compares 2 bits

Single Bit Magnitude Comparator Truth Table 2-Bit Magnitude Comparator Circuit

7. Decoder - converts binary information from n

𝑛
input lines to a maximum of 2 unique output
lines

Single Bit Magnitude Comparator Circuit

 9. Multiplexer - selects binary information from
one of many input lines and directs it to a
𝑛
single output line; 2 input lines, n selection
lines whose bit combinations determine
which input is selected; data selector.

2x4 Decoder

2x1 Decoder Multiplexer

3x8 Decoder
(can be used for Binary to Octal Conversion)

𝑛
8. Encoder - has 2 input lines and n output
lines

4x1 Decoder Multiplexer

10. Demultiplexer - a circuit that receives

information on a single line and transmits this
information to one of 2 n possible output lines
Block Diagram:

8x3 Encoder
Combinational Logic Implementaion
- any Boolean function can be expressed in
sum of minterms
- use a decoder to generate the minterms and
an external OR gate to form the sum

Examples of Combinational Logic Implementation

1. Decoder Implementation
2. Multiplexer Implementation - choose your select
lines (n-1) from your input variables (any of the
input variables) and determine the size of the
multiplexer (depends on the # of select lines)
STEPS:
● Create an implementation table based on
the variable not used as select line.
● Inspect each column of the implementation
table. If the minterms in a column are not
circled, apply 0 to the corresponding MUX
input. If the minterms are circled, apply 1
to the corresponding MUX input. If the top
minterm is circled and the bottom
minterm is not circled, apply A’ to the
corresponding MUX input. If the top
minterm is not circled and the bottom
minterm is circled, apply A to the
corresponding MUX input.
 MODULE 5: SEQUENTIAL LOGIC CIRCUITS

Sequential Logic Circuit 2. Asynchronous

- consists of a combinational circuit to which - depends upon the input signals at any
memory elements are connected to form a instant of time and the order in which the
feedback path inputs change
- receives binary information from external inputs
together with the present state of the memory NOR Latch
elements to determine the binary value at the
output terminals
- acts as storage elements and have memory
Block Diagram:

Transition Table for NOR Latch:

Latches
- storage elements that operate with signal levels
- level-sensitive devices
- are the basic circuits from which all flip-flops are
constructed

Flip-flops
- controlled by a clock transition
- edge-sensitive devices NAND Latch
- a device with two stable states
- can maintain a binary state indefinitely until
directed by an input signal to switch states
- remains in one of these states until triggered into
the other

Types of Sequential Logic Circuit

1. Synchronous
Transition Table for NAND Latch:
- a system whose behavior can be defined
from the knowledge of its signals at discrete
instants of time
- synchronization is achieved by a timing
device called a clock generator, which
provides a clock signal having the form of a
periodic train of clock pulses
Types of Flip-Flops JK Flip-Flop Transition Table
1. RS or SR Flip-Flop

3. D Flip-Flop

SR Flip-Flop Transition Table

D Flip-Flop Transition Table

2. JK Flip-Flop

4. T Flip-Flop
T Flip-Flop Transition Table

Flip-Flop Parameters
( )
● Propagation Delay Time 𝑡𝑝 - this represents
the amount of time it takes for the output of a
gate or flip-flop to change states
● ( )
Setup Time 𝑡𝑆𝐸𝑇𝑈𝑃 - is the minimum length of
time the data bit must be present before the
Level Clocking CLK edge hits
- output of the flip-flop responds during the high ● ( )
Hold Time 𝑡𝐻𝑂𝐿𝐷 - is the minimum length of
(or low) level of the clock signal
time the data bit must be present after the CLK
- positive or negative level clocking
edge has struck
Schematic Symbol:
JK Master-Slave Flip-Flop

Edge Triggering
- the flip-flop produces output only on the rising
(or falling) edge of the clock signal
- positive or negative edge triggering
Schematic Symbol:

Preset and Clear

- two external inputs that initiate the condition or
state of the flip-flop
- priority inputs
MODULE 6: DESIGN OF DIGITAL SYSTEMS Excitation Table of SR Flip Flop
(SYNCHRONOUS SEQUENTIAL LOGIC
CIRCUIT DESIGN)

Combinational Logic Circuit

- it’s output depends only and immediately on
their inputs
- has no memory element

Excitation Table of JK Flip Flop

Sequential Logic Circuits

- acts as storage elements and have memory

Block Diagram of a Sequential Circuit

Excitation Table of DFlip Flop

Forms of Triggering or Clocking

Excitation Table of T Flip Flop

Excitation Table
- lists the required inputs for a given change of
state
- is important in the design process to determine
Design Modelling
the flip flop input conditions that will cause the
- the relationship that exists among the inputs,
required transition
outputs, present states, and next states can be
specified by any of the following:
1. State Diagram - a graphical rrepresentation
wherein a state is represented by a circle;
and the transition between states is
indicated by directed lines (or arcs)
connecting the circles.
 variables. Other name for Characteristic
Equation.

2. State Table - is a tabulated representation

which consists of input, present state, next
state, and output

State Reduction Algorithms

- are concerned with procedures for reducing the
number of states in state table, while keeping
the external input-output requirements
unchanged

● Two states are said to be equivalent if, for each

member of the set of inputs, they give exactly
the same output and send the circuit either to
the same state or to an equivalent state.

Registers
- are composed of group of flip flops, each one
shares a common clock and is capable of
storing one bit of information or modify stored
binary word

3. State Equation - is an expression that specifies

the conditions of flip flop’s next state transition
as function of the present state and input
 Design of Binary Counters
- are typically done using either T or JK Flip Flop

Counters
- are registers that go through a predetermined
sequence of binary states. It counts the number
of clock pulses arriving at its input