Dr. B. R.

Ambedkar National Institute of Technology,

Jalandhar, Punjab

Branch : - CSE
Computer Organization & Architecture (CSPC- 208 &
CSMI-202)
Lecture – 6
Central Processing Unit
Presenter – Dr. D. K. Meena
CENTRAL PROCESSING UNIT
Introduction

General Register Organization

Stack Organization

Instruction Formats

Addressing Modes

Data Transfer and Manipulation

Program Control

Reduced Instruction Set Computer (RISC)

2
 CENTRAL PROCESSING UNIT
A Central Processing Unit is also called a processor, central processor, or
microprocessor.
It carries out all the important functions of a computer.
It receives instructions from both the hardware and active software and
produces output accordingly.
It stores all important programs like operating systems and application
software.
CPU also helps Input and output devices to communicate with each
other. Owing to these features of CPU, it is often referred to as the brain
of the computer.
CPU is installed or inserted into a CPU socket located on the motherboard.
CPU is provided with a heat sink to absorb and dissipate heat to keep the
CPU cool and functioning smoothly.
 CENTRAL PROCESSING UNIT
Generally, a CPU has three components:
1. ALU (Arithmetic Logic Unit)
2. Control Unit
3. Memory or Storage Unit
 CENTRAL PROCESSING UNIT
Control Unit: It is the circuitry in the control unit, which makes use
of electrical signals to instruct the computer system for executing
already stored instructions.
It takes instructions from memory and then decodes and executes
these instructions.
So, it controls and coordinates the functioning of all parts of the
computer.
The Control Unit's main task is to maintain and regulate the flow of
information across the processor.
It does not take part in processing and storing data.
 CENTRAL PROCESSING UNIT
ALU (Arithmetic Logic Unit) : It is the arithmetic logic unit, which
performs arithmetic and logical functions.
Arithmetic functions include addition, subtraction, multiplication
division, and comparisons.
Logical functions mainly include selecting, comparing, and merging
the data.
A CPU may contain more than one ALU.
Furthermore, ALUs can be used for maintaining timers that help run
the computer.
 CENTRAL PROCESSING UNIT
Memory or Storage Unit/ Registers: It is called Random access
memory (RAM).
It temporarily stores data, programs, and intermediate and final
results of processing.
So, it acts as a temporary storage area that holds the data
temporarily, which is used to run the computer.
GENERAL REGISTER ORGANIZATION
Input
Clock

R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB
3x8
A bus B bus
decoder

SELD
OPR ALU

Output
 OPERATION OF CONTROL UNIT
The control unit directs the information flow through ALU by:
- Selecting various Components in the system
- Selecting the Function of ALU
Example: R1 <- R2 + R3

[1] MUX A selector (SELA): BUS A ← R2

[2] MUX B selector (SELB): BUS B ← R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1 ← Out Bus
3 3 3 5
Control Word SELA SELB SELD OPR

Encoding of register selection fields Binary

Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
 ALU CONTROL
Encoding of ALU operations OPR
Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 ADD A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA

Examples of ALU Microoperations

Symbolic Designation
Microoperation SELA SELB SELD OPR Control Word
R1 ← R2 - R3 R2 R3 R1 SUB 010 011 001 00101
R4 ← R4 ∨ R5 R4 R5 R4 OR 100 101 100 01010
R6 ← R6 + 1 R6 - R6 INCA 110 000 110
00001
R7 ← R1 R1 - R7 TSFA 001 000 111 00000
Output ← R2 R2 - None TSFA 010 000 000 00000
Output ← Input Input - None TSFA 000 000 000 00000
R4 ← shl R4 R4 - R4 SHLA 100 000 100
11000
R5 ← 0 R5 R5 R5 XOR 101 101 101 01100
 REGISTER STACK ORGANIZATION
Stack
Very useful feature for nested subroutines, nested loops control
Also efficient for arithmetic expression evaluation
Storage which can be accessed in LIFO
Pointer: SP
Only PUSH and POP operations are applicable
Zero Address Instructions stack Address

Register Stack Flags 63

FULL EMPTY

Stack pointer 4
SP C 3
B 2
A 1
Push, Pop operations 0
DR
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */

PUSH POP
SP ← SP + 1 DR ← M[SP]
M[SP] ← DR SP ← SP - 1
If (SP = 0) then (FULL ← 1) If (SP = 0) then (EMPTY ←
1)
cpe 252: Computer Organization 11
EMPTY ← 0 FULL ← 0
 MEMORY STACK ORGANIZATION
Memory with Program, Data and Stack Segments 1000
Program
PC (instructions)

Data
AR (operands)

SP 3000
stack
A portion of memory is used as a stack with a processor
3997
register as a stack pointer 3998
3999
4000
PUSH: SP ← SP - 1 4001
M[SP] ← DR
DR
POP: DR ← M[SP]
SP ← SP + 1

Most computers do not provide hardware to check stack

overflow (full stack) or underflow(empty stack)

12
 REVERSE POLISH NOTATION

Arithmetic Expressions: A + B
A+B Infix notation
+AB Prefix or Polish notation
AB+ Postfix or reverse Polish notation
The reverse Polish notation is very suitable for stack manipulation

Evaluation of Arithmetic Expressions

Any arithmetic expression can be expressed in parenthesis-free
Polish notation, including reverse Polish notation

(3 * 4) + (5 * 6) ⇒ 34*56*+

6
4 5 5 30
3 3 12 12 12 12 42
3 4 * 5 6 * +
 INSTRUCTION FORMAT
Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(s) or a processor register(s)
Mode field - specifies the way the operand or the effective address is
determined
The number of address fields in the instruction format depends on the
internal organization of CPU
The three most common CPU organizations:
Single accumulator organization:
ADD X /* AC ← AC + M[X] */
General register organization:
ADD R1, R2, R3 /* R1 ← R2 + R3 */
ADD R1, R2 /* R1 ← R1 + R2 */
MOV R1, R2 /* R1 ← R2 */
ADD R1, X /* R1 ← R1 + M[X] */
Stack organization:
PUSH X /* TOS ← M[X] */
ADD
THREE, and TWO-ADDRESS INSTRUCTIONS
Three-Address Instructions:

Program to evaluate X = (A + B) * (C + D) :
ADDR1, A, B /* R1 M[A] + M[B] */
ADDR2, C, D /* R2 M[C] + M[D] */
MULX, R1, R2 /* M[X] R1 * R2 */

- Results in short programs

- Instruction becomes long (many bits)

Two-Address Instructions:
Program to evaluate X = (A + B) * (C + D) :

MOV R1, A /* R1 M[A] */

ADD R1, B /* R1 R1 + M[B] */
MOV R2, C /* R2 M[C] */
ADD R2, D /* R2 R2 + M[D] */
MUL R1, R2 /* R1 R1 * R2 */
MOV X, R1 /* M[X] R1 */
ONE, and ZERO-ADDRESS INSTRUCTIONS
One-Address Instructions:
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC M[A] */
ADD B /* AC AC + M[B] */
STORE T /* M[T] AC */
LOAD C /* AC M[C] */
ADD D /* AC AC + M[D] */
MUL T /* AC AC * M[T] */
STORE X /* M[X] AC */
Zero-Address Instructions:
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS A */
PUSH B /* TOS B */
ADD /* TOS (A + B) */
PUSH C /* TOS C */
PUSH D /* TOS D */
ADD /* TOS (C + D) */
MUL /* TOS (C + D) * (A + B) */
POP X /* M[X] TOS */
 ADDRESSING MODES
Addressing Modes:
Specifies a rule for interpreting or modifying the address field of
the instruction (before the operand is actually referenced)

Variety of addressing modes

✔ to give programming flexibility to the user

✔ to use the bits in the address field of the instruction

efficiently
ADDRESSING MODES
 TYPES OF ADDRESSING MODES
Implied Mode
Address of the operands are specified implicitly in the definition of the instruction
✔ No need to specify address in the instruction
✔ EA = AC, or EA = Stack[SP], EA: Effective Address.

Immediate Mode
Instead of specifying the address of the operand, operand itself is specified
✔ No need to specify address in the instruction
✔ However, operand itself needs to be specified
✔ Sometimes, require more bits than the address
✔ Fast to acquire an operand
Register Mode
Address specified in the instruction is the register address
✔Designated operand need to be in a register
✔Shorter address than the memory address
✔Saving address field in the instruction
✔Faster to acquire an operand than the memory addressing
✔EA = IR(R) (IR(R): Register field of IR)
 TYPES OF ADDRESSING MODES
Register Indirect Mode
Instruction specifies a register which contains the memory address of
the operand
Saving instruction bits since register address is shorter than the
memory address
Slower to acquire an operand than both the register addressing or
memory addressing
EA = [IR(R)] ([x]: Content of x)
Auto-increment or Auto-decrement features:
Same as the Register Indirect, but: When the address in the register is
used to access memory, the value in the register is incremented or
decremented by 1 (after or before the execution of the instruction)
 TYPES OF ADDRESSING MODES
Direct Address Mode
Instruction specifies the memory address which can be used directly to
the physical memory
✔ Faster than the other memory addressing modes
✔ Too many bits are needed to specify the address for a large physical
memory space
✔ EA = IR(address), (IR(address): address field of IR)
Indirect Addressing Mode
The address field of an instruction specifies the address of a memory
location that contains the address of the operand
✔ When the abbreviated address is used, large physical memory can
be addressed with a relatively small number of bits
✔ Slow to acquire an operand because of an additional memory
access
- EA = M[IR(address)]
 TYPES OF ADDRESSING MODES
Relative Addressing Modes
The Address fields of an instruction specifies the part of the address
(abbreviated address) which can be used along with a designated
register to calculate the address of the operand
PC Relative Addressing Mode(R = PC)
- EA = PC + IR(address)
Address field of the instruction is short
Large physical memory can be accessed with a small number of address
bits
Indexed Addressing Mode
XR: Index Register:
- EA = XR + IR(address)
Base Register Addressing Mode
BAR: Base Address Register:
- EA = BAR + IR(address)
 ADDRESSING MODES - EXAMPLES
In relative address mode the value in PC after
fetch phase and during the execute phase is Address Memory
202 200 Load to AC Mode
PC = 200 201 Address = 500
202 Next instruction
R1 = 400

399 450
XR = 100
400 700

AC
500 800

600 900
Addressing Effective Content
Mode Address of AC
Direct address 500 /* AC ← (500) */ 800 702 325
Immediate operand - /* AC ← 500 */ 500
Indirect address 800 /* AC ← ((500)) */ 300
Relative address 702 /* AC ← (PC+500) */ 800 300
325
Indexed address 600 /* AC ← (XR+500) */
900
Register - /* AC ← R1 */ 400
Register indirect 400 /* AC ← (R1) */ 700
Autoincrement400 /* AC ← (R1)+ */ 700
Autodecrement 399 /* AC ← -(R) */ 450
 Data Transfer and Manipulation
Computer instruction are classified in to three category:-
1. Data transfer instructions Data Transfer Instructions
2. Data manipulation instructions Name Mnemonic
3. Program control instructions Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
Data Transfer Instructions with Different Addressing Modes
Assembly
Mode Convention Register Transfer
Direct address LD ADR AC M[ADR]
Indirect address LD @ADR AC M[M[ADR]]
Relative address LD $ADR AC M[PC + ADR]
Immediate operand LD #NBR AC NBR
Index addressing LD ADR(X) AC M[ADR + XR]
Register LD R1 AC R1
Register indirect LD (R1) AC M[R1]
Autoincrement LD (R1)+ AC M[R1], R1 R1 + 1
Autodecrement LD -(R1) R1 R1 - 1, AC
M[R1]
 DATA MANIPULATION INSTRUCTIONS
Three Basic Types: Arithmetic instructions
Logical and bit manipulation instructions
Shift instructions
Arithmetic Instructions
Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with Carry ADDC
Subtract with Borrow SUBB
Negate(2’s Complement) NEG

Logical and Bit Manipulation Instructions Shift Instructions

Name Mnemonic Name Mnemonic
Clear CLR Logical shift right SHR
Complement COM Logical shift left SHL
AND AND Arithmetic shift right SHRA
OR OR Arithmetic shift left SHLA
Exclusive-OR XOR Rotate right ROR
Clear carry CLRC Rotate left ROL
Set carry SETC Rotate right thru carry RORC
Complement carry COMC Rotate left thru carry ROLC
Enable interrupt EI
Disable interrupt DI
 PROGRAM CONTROL INSTRUCTIONS
Program control instructions provide decision making capabilities and change the
path taken by program when executed in the computer.

Program Control Instructions

Name Mnemonic
CMP and TST instructions do not retain their
Branch BR
Jump JMP results of operations(- and AND, respectively).
Skip SKP They only set or clear certain Flags.
Call CALL
Return RTN
Compare(by - ) CMP
Test (by AND) TST

Status Flag Circuit A B

8 8
c7
c8 8-bit ALU
F7 - F0
V Z S C
F7
Check for 8
zero output
F
CONDITIONAL BRANCH INSTRUCTIONS
Mnemonic Branch condition Tested
condition
BZ Branch if zero Z = 1
BNZ Branch if not zero Z=0
BC Branch if carry C = 1
BNC Branch if no carry C=0
BP Branch if plus S = 0
BM Branch if minus S = 1
BV Branch if overflow V=1
BNV Branch if no overflowV = 0
Unsigned compare conditions (A - B)
BHI Branch if higherA > B
BHE Branch if higher or equal A ≥ B
BLO Branch if lower A < B
BLOE Branch if lower or equal A ≤ B
BE Branch if equal A = B
BNE Branch if not equal A ≠ B
Signed compare conditions (A - B)
BGT Branch if greater than A>B
BGE Branch if greater or equal A ≥ B
BLT Branch if less than A < B
BLE Branch if less or equal A≤B
BE Branch if equal A = B
BNE Branch if not equal A ≠ B
 PROGRAM INTERRUPT
External interrupts
External Interrupts initiated from the outside of CPU and Memory
- I/O Device -> Data transfer request or Data transfer complete
- Timing Device -> Timeout
- Power Failure
Internal interrupts (traps)
Internal Interrupts are caused by the currently running program
- Register, Stack Overflow
- Divide by zero
- OP-code Violation
- Protection Violation
Software Interrupts
Both External and Internal Interrupts are initiated by the computer Hardware.
Software Interrupts are initiated by texecuting an instruction.
- Supervisor Call
-> Switching from a user mode to the supervisor mode
-> Allows to execute a certain class of operations which are not allowed in the
user mode
RISC: REDUCED INSTRUCTION SET COMPUTERS
The main idea behind this is to make hardware simpler by using an
instruction set composed of a few basic steps for loading, evaluating,
and storing operations just like a load command will load data, a store
command will store the data.
Reduce the cycles per instruction at the cost of the number of
instructions per program.

Example – Suppose we have to add two 8-bit numbers:

Here programmer will write the first load command to load data in
registers then it will use a suitable operator and then it will store the
result in the desired location.
So, add operation is divided into parts i.e. load, operate, store due to
which RISC programs are longer and require more memory to get
stored but in CISC require fewer transistors due to less complex
command.
 CISC: Complex Instruction Set Computers
1. The main idea is that a single instruction will do all loading, evaluating,
and storing operations just like a multiplication command will do stuff like
loading data, evaluating, and storing it, hence it’s complex.
2. The CISC approach attempts to minimize the number of instructions per
program but at the cost of an increase in the number of cycles per
instruction.

3. Earlier when programming was done using assembly language, a need

was felt to make instruction do more tasks because programming in
assembly was tedious and error-prone due to which CISC architecture
evolved but with the uprise of high-level language dependency on
assembly reduced RISC architecture prevailed.
Example – Suppose we have to add two 8-bit numbers:
CISC approach: There will be a single command or instruction for this
like ADD which will perform the task.
in CISC require fewer transistors due to less complex command.
 Characteristic of RISC and CISC
Characteristic of RISC –
Simpler instruction, hence simple instruction decoding.
Instruction comes undersize of one word.
Instruction takes a single clock cycle to get executed.
More general-purpose registers.
Simple Addressing Modes.
Fewer Data types.
A pipeline can be achieved.

Characteristic of CISC –
Complex instruction, hence complex instruction decoding.
Instructions are larger than one-word size.
Instruction may take more than a single clock cycle to get executed.
Less number of general-purpose registers as operations get performed
in memory itself.
Complex Addressing Modes.
More Data types.
 Difference between RISC and CISC
RISC CISC
Focus on software Focus on hardware

Uses both hardwired and

Uses only Hardwired control unit
microprogrammed control unit

Transistors are used for storing complex

Transistors are used for more registers
Instructions

Fixed sized instructions Variable sized instructions

Can perform only Register to Register Can perform REG to REG or REG to MEM
Arithmetic operations or MEM to MEM

Requires more number of registers Requires less number of registers

Code size is large Code size is small

An instruction executed in a single clock Instruction takes more than one clock
cycle cycle

Instructions are larger than the size of one

An instruction fit in one word
word