FPGA Design for Communication

Applications using VHDL

Henrik Wessing, Michael Berger

Networks Technology and Service Platforms

Purpose of lecture
• Assumptions
– You should have general knowledge of VHDL coding although it might
be a bit rusty
– You should have basic understanding of digital design.
• After this lecture you should:
– Be able to write synthesisable code
– Be able to improve and optimise code towards speed
– Be able to develope a test bench and test your design
– Have an overview of the syntax, possibilities and limitations of VHDL
– Gained a general improved coding style

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Why designing FPGA through VHDL?
• Market demands
– Time to market important aspect.
– Full custom design costly and time consuming
• Flexibility
– FPGAs suitable for smaller functions as well as complex circuitry

FPGA design using VHDL is flexible

with low time-to-market
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Outline
• Design flow (from VHDL to silicon)
• VHDL coding syntax
• Small exercise
• Synthesising code and coding style
• Examples of circuits
• Pipelining
• Small exercise
• Testbench concepts

Feel free to ask questions

during the lecture

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Design flow

VHDL (RTL) Simulation (ModelSim)

Synthesis Gate level Simulation

Place & Route Simulation

(wire+gate delay)

Delay & Area info

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VHDL Features
• Behavioural modelling
– Focus on the functionality of the design
– Processes, signal assignments
– May include non-synthesisable blocks (relevant for testing)
– Example: “clk <= ‘1’ after 10 ns, ‘0’ after 20 ns
• Structural modelling
– Approach to introduce structure and hierarchy in a VHDL description.
– Represents a structural module in the design.
– Using components, it is possible to describe a netlist in VHDL.
– Connecting blocks and create design hierarchies
– Example: Next slides
• Event driven simulation

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Structure of simple VHDL block

--- Copyright COM, 2005

use ieee.std_logic_1164.all;
entity vhdl is
port (
clk, in : in std_logic;
out : out std_logic);
end vhdl;
architecture struc of vhdl is
signal internal : std_logic;
begin
out <= internal;
process(clk)
begin
if rising_edge(clk) then
internal <= internal and in;
end if;
end process;
end struc;

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 Component instantiation (I)

ENTITY SHAPER IS • Defining components from other

port ( entities
CLK : in std_logic;
RESET : in std_logic; • Defining internal signals
DATAIN : in std_logic_vector(7 downto 0);
DATAOUT : out std_logic_vector(7 downto 0));
• Mapping components and signals
END SHAPER;

ARCHITECTURE struc OF SHAPER IS

component RAM
port (
Reset : in std_logic;
clk : in std_logic; component scheduler
Address : in std_logic_vector(7 downto 0); port (
Data : out std_logic_vector(7 downto 0)); Reset : in std_logic;
END component; Clk : in std_logic;
Grant : out std_logic_vector(3 downto 0);
component buffer_control Newpacket : in std_logic_vector(3 downto 0);
port ( lengthin : in std_logic_vector(3 downto 0));
Reset : in std_logic; END component;
clk : in std_logic;
MemAddr : out std_logic_vector(7 downto 0); component change_header
port (
MemData : in std_logic_vector(7 downto Reset : in std_logic;
0); clk : in std_logic;
Queue : in std_logic_vector(3 downto 0); datain : in std_logic_vector(7 downto 0);
Newpck : out std_logic_vector(3 downto 0); dataout : out std_logic_vector(7 downto 0);
Datain : in std_logic_vector(7 downto 0); length : out std_logic_vector(3 downto 0));
Dataout : out std_logic_vector(7 downto 0)); END component;
END component;

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Component instantiation (II)

signal RAMaddr, RAMdata : std_logic_vector(7 downto 0);

signal SCHEDnew, SCHEDgrant : std_logic_vector(3 downto 0);
signal lengthinfo : std_logic_vector(3 downto 0);
signal data_internal : std_logic_vector(7 downto 0);
sched : scheduler
BEGIN port map (
clk => clk,
ramblock : ram reset => reset,
port map ( Grant => SCHEDgrant,
clk => clk, Newpacket => SCHEDnew,
reset => reset, lengthin => lengthinfo);
address => RAMaddr,
data => RAMdata); header : change_header
port map (
bufferctrl : buffer_control clk => clk,
port map ( reset => reset,
clk => clk, datain => data_internal,
reset => reset, dataout => dataout,
MemAddr => RAMAddr, lengthfield => lengthinfo);
MemData => RAMData,
Queue => SCHEDgrant, END struc;
Newpck => SCHEDnew,
Datain => datain,
dataout => data_internal);

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Component instantiation (III)

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Concurrent statements
• Signal assignments
• Component instantiation
• Process statements
• Procedure and function calls
• Evaluated in parallel – independent of order
– a <= b; c <= a – equal to
– c <= a; a <= b
• Example: The AND gate : c <= a & b

ENTITY and2 IS
port (
a : in std_logic;
b : in std_logic;
c : out std_logic);
END and2;

ARCHITECTURE assign OF and2 IS

BEGIN
c <= a and b;
END assign;

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Sequential statements
• Control structures within processes
– If and case statements
– For loops
– Null and exit statements
– Variables
– Report and assert
• Often a way to describe several instantiations
• Should be synthesised to logic devices
– Flip/Flops and Latches
– Counters
– Statemachines

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Processes
• Event list to activate code : process(a,b,c,d)
• Processes can include sequential code
• Processes may contain many programming language constructions:
• Processes can be used to describe both combinatoric and sequential logic
• The And gate : c <= a & b

ENTITY and2 IS
port (
a : in std_logic;
b : in std_logic;
c : out std_logic);
END and2;

ARCHITECTURE procbased OF and2 IS

BEGIN

process(a,b)
begin
c <= a and b;
end process;

END procbased;

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Variables
• Local within a process What you write:
• Can be used to hold temporary values process(a,b,c)
variable temp : integer range 0 to 255;
• Updated and replaced before synthesis begin
• Syntax for assign: A := B temp := a+b;
d <= c + temp;
• Note: end process;
– B := A; C := B not equal to
How the synthesis tool see this:
– C := B; B := A; process(a,b,c)
• Take care and/or avoid begin
d <= c + a + b;
end process;

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Exercise 1
• Comparing delivered code
• All four circuits share the same entity description as circuit 1
• What is the output C after one clock cycle?
• Initial conditions
– A = 25
– B= 37
– K = 100
– L = 120

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 Exercise 1
CIRCUIT 1
ENTITY Circuit1 IS
port (clk : in std_logic; CIRCUIT 3
A : in integer range 0 to 255; SIGNAL K : integer range 0 to 255;
B : in integer range 0 to 255;
C : out integer range 0 to 255); ARCHITECTURE struc of circuit1 IS
END Circuit1; BEGIN
process(clk)
SIGNAL K : integer range 0 to 255; variable L : integer range 0 to 255;
SIGNAL L : integer range 0 to 255; BEGIN
ARCHITECTURE struc of circuit1 IS if rising_edge(clk) then
BEGIN
K <= A;
c <= K + L; L := B;
process(clk)
c <= K + L
BEGIN
END if;
if rising_edge(clk) then
END process;
K <= A; L <= B; END struc;
END if;
END process;
CIRCUIT 4
END struc;
ARCHITECTURE struc of circuit1 IS
BEGIN
CIRCUIT 2
SIGNAL K : integer range 0 to 255;
process(clk)
SIGNAL L : integer range 0 to 255;
variable L,K : integer range 0 to 255;
ARCHITECTURE struc of circuit1 IS
BEGIN
BEGIN
if rising_edge(clk) then
process(clk)
begin K := A;
if rising_edge(clk) then L := B;
K <= A; c <= K + L
END if;
L <= B;
END process;
c <= K + L
END if; END struc
END process;
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END DTU Fotonik, Technical University of Denmark
Bad or good constructs?
• Example of bad code as seen in report
• Why doesn’t it work?

process(clk,data_ready,cpu_req,done_trans)
begin
if (cpu_req='1' and cpu_req'event and clk'event and clk='1') then
...
end if;
if (data_ready and clk'event and clk='0') then
...
end if;
if (done_trans='1' and clk'event and clk='0') then
...
end if;
if (cpu_req'event and clk='1' and clk'event and cpu_req='0') then
...
end if;
end process;

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 Synthesis of bad code
process(clk, cpu_req,done_trans)
begin
• Code changed slightly
if clk'event then
• Result in level triggered latch
if (cpu_req='1' and clk='1') then
• No well defined clock
dummy1 <= '1';
• Slower
dummy2 <= '0';
end if;
if (done_trans='1' and clk='0') then
dummy2 <= '1';
dummy1 <= '0';
end if;
end if;
end process;

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 Synthesis of better code

process(reset,clk)
begin • Still using both rising and falling clock edges.
if reset = '0' then • Well defined clock
dummy1 <= '0'; • 30-40% faster
dummy2 <= '0';
elsif rising_edge(clk) then
if cpu_req = '1' then
dummy1 <= '1';
else
dummy1 <= '0';
end if;
elsif falling_edge(clk) then
if done_trans='1' then
dummy2 <='1';
else
dummy2 <= '0';
end if;
end if;
end process;

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Coding style: Sensitivity lists
(Combinatorical logic)
ARCHITECTURE Behavior OF mux2to1 IS
BEGIN
PROCESS ( V, W, Sel )
BEGIN
IF Sel = '0' THEN
F <= V ;
ELSE
F <= W ;
END IF ;
END PROCESS ;
END Behavior ;

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Coding Style: Clocked process
PROCESS (Clock )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Areg <= A;
Breg <= B;
Creg <= Areg+Breg;

IF Reset = '1' THEN

Areg <= (OTHERS => '0');
Breg <= (OTHERS => '0');
END IF;
END IF ;

END PROCESS ;

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Coding Style: Good practises
• Always use sync. Reset on clocked processes.
– Remember to reset only necessary registers.
• Always define all outputs in combinatorial blocks.
– Otherwise a latch is created.
• Avoid variables
– Unless you know what you are doing.
• Always have all inputs on the sensitivity list for combinatorial
statements.
• May Use “AFTER 1ns” in Clocked processes to improve simulation
visibility

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Recommended VHDL libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;

signal a,b,c : std_logic_vector(7 downto 0);

..
a <= x"00" + 17; --set a to integer value 17, (a <= 17 not allowed)
b <= std_logic_vector(to_unsigned(58,8)); -- set b to integer value 58
..

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Recommended VHDL libraries (cont)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;

signal a,b,c : std_logic_vector(7 downto 0);

signal i : integer range 0 to 255;
..
if b = 15 then
c <= a + 2;
else
c <= a + c;
end if;
..
i <= to_integer(unsigned(a));

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Counter (4 bit)
• Process for counting
• Enable and up-down function implemented

count1: process(clk,reset)
begin
if (reset = '1') then
count_int <= "0000";
elsif rising_edge(clk) then
if (en = '1') then
if (up_down = '1') then
count_int <= count_int + '1' after 1 ns;
else
count_int <= unsigned(count_int) - '1' after 1 ns;
end if;
end if;
end if;
end process count1;

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State Machines (I)

• Moore
– Output depending only
on state
– Easy to control
– Often recommended
• Mealy
– Output also dependent
on asynchronous input
– Hard to control delay

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State Machines (II)

hec_ok

Hunt
Ok = 0

hec_error
Presync
a_hec_error Ok = 0

Sync
Ok = 1
b_hec_ok

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 State Machine (III)
--combinatorial logic
comp : process
(state,hec_ok,hec_error,a_hec_error,b_hec_ok)
BEGIN
entity statemachine is case (state) is
port ( when HUNT =>
reset : in std_logic ; if (hec_ok = '1') then
clk : in std_logic ; next_state <= PRESYNC;
hec_ok : in std_logic ; else
hec_error : in std_logic ; next_state <= HUNT;
a_hec_error : in std_logic ; end if;
b_hec_ok : in std_logic ; ok <= '0';
ok : out std_logic); when PRESYNC =>
end statemachine; if (hec_error = '1') then
next_state <= HUNT;
architecture statemachine of statemachine elsif (b_hec_ok = '1') then
is next_state <= SYNC;
else
type state_type is (HUNT,PRESYNC,SYNC); next_state <= PRESYNC;
signal state,next_state : state_type; end if;
ok <= '0';
BEGIN when SYNC =>
--sequential logic if (a_hec_error = '1') then
seq : process (clk,reset) next_state <= HUNT;
BEGIN else
if (reset = '1') then next_state <= SYNC;
state <= HUNT; end if;
elsif (clk'event and clk = '1') then ok <= '1';
state <= next_state after 1 ns; when others =>
end if; next_state <= HUNT;
end process seq; ok <= '0';
end case;
end process comp;
end statemachine;
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 Pipelining (I)
• Register Transfer Latch – design
• Less mistakes!
• Pipelining possible
– Dividing functions to reduce delay
– Increasing clock rate

Register

Datain Dataout
Combinational
Register logic Register

Clock

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Pipelining (II)

Do expression: Y=A+B-C+D

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Exercise 2
• Improve this process for higher clock speed
– Rewrite process for two clock cycles
• ”CTRL” is a std_logic control signal
• A, B, C and D are integers

process(clk)
begin
if rising_edge(clk) then
if (CTRL = '1') then
D <= A+B after 1 ns;
else
D <= B+C after 1 ns;
end if;
end if;
end process;

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Exercise 2 - Solution
• The propagation delay is divided in two
• Higher area-consumption but 15-20% higher clock rate
• Use this method to reduce critcal paths

process(clk)
begin
if rising_edge(clk) then
if (CTRL = '1') then
D <= D1 after 1 ns;
else
D <= D2 after 1 ns;
end if;
D1 <= A+B after 1 ns;
D2 <= B+C after 1 ns;
end if;
end process;
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Simulation and Testbench

TestBench

Stimuli / Verification

DUT (device under test)

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Testing Methodology
• Designing everything and testing it all
– WRONG – it never works
• Testing every single entity thoroughly
– CORRECT
• Functional testing
– Each step
– Overall
• Performance testing
• Device under test (DUT) instantiated
• Stimulus driver instantiated
• Output compared to expected output

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Different testbench approaches
• Stimulus only
– No result verification
• Full testbench
– Compares result with expected results
• Hybrid testbench
– Combination of techniques

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Case Example
• Loadable counter
– Load signal to indicate new load
– Signal to indicate whether up or down-counting
– Clock enable signal
– Data in and out
– Clock

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Stimulus only
• Verification left to designer
• Useful for quick test in beginning of project
• Entity declaration
• DUT component declaration and mapping
• Test process generating test sequences -- Example of vectorfile
-- time clk ld up_down en din
• Reading file with test vectors
10 0001 0
– readline(vectorfile, line) – textio procedures 20 1101 50
– Include test vector and when to assert them 30 0001 0
– Assign vector to input signals .
• Test monitored through simulation window .
.
150 0001 0
160 1001 0

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Full testbench
• Input part similar to “Stimulus Only”
• Except
– Capability to check output
– Comparing output
-- Example of vectorfile
• Reporting mismatch
-- time clk ld up_down en din dout
– e.g. assert tmpqout = qout REPORT 0 0001 0 0
“Vector mismatch” 10 1001 0 255
• Vector file 20 0001 10 255
– Include expected output 30 1001 0 10
– Shown with red .
.
.
150 0001 0 98
160 1001 0 97

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Summary
• Architecture of VHDL code
• VHDL has to be synthesised – always consider how your code is
synthesised!!!
• Remember to add delay in clocked assignments
• Pipelining essential in communication electronics to increase speed
• Examples:
– Counter
– State Machine
• Test bench methodology

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