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EAD410 Practical 1 Theoretical

The document describes a DC-DC buck converter circuit and provides various component values and specifications. It includes: 1) Constants and component values for the converter circuit. 2) Derivation of the output voltage expression and calculations of output voltage and inductor current ripple for different duty cycles. 3) Design considerations for the PWM controller and calculations to determine appropriate inductor and capacitor values.

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0% found this document useful (0 votes)
52 views5 pages

EAD410 Practical 1 Theoretical

The document describes a DC-DC buck converter circuit and provides various component values and specifications. It includes: 1) Constants and component values for the converter circuit. 2) Derivation of the output voltage expression and calculations of output voltage and inductor current ripple for different duty cycles. 3) Design considerations for the PWM controller and calculations to determine appropriate inductor and capacitor values.

Uploaded by

u18348794
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as XLSX, PDF, TXT or read online on Scribd
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Constants i)

Vdc 5
Vfwd 1
Io,max
rL 0.1
Vce,sat 1
Io 1
Tsw 0.00005 ii)
L 0.00015
C 0.00094
RL(0,5) 11
RL(0,6) 11
RL(0,4) 7.3 iii)

iv)

v)

vi)

vii)

viii)
Derive an expression relating the output voltage to the input
voltage of the converter topology. In addition, predict the 0.4 0.5
magnitude of the output voltage and inductor current ripple IL(A) 1.667 2.000
for the given values of L, C and fsw and at δ = 0.4, δ = 0.5, and Vo(V) 6.389 7.667
δ = 0.6.
Io,avg 0.875 0.697
∆Vo ripple(V) 0.021 0.027
∆Ilpk,pk(A) 0.511 0.633
VL(V) 3.833 3.800
Design a PWM modulator (based on the UC3524 chip) to Choose CT as: 0.000000001
control the duty-ratio of the converter IGBT switch and
ensure a switching frequency of 20 kHz using the provided Thus RT(ohm): 59000
PWM integrated chip. Great care should be exercised to
ensure that the maximum and minimum pulse-widths of the
IGBT gate signal device are within acceptable limits.
For duty ratios of δ = 0.4, δ = 0.5, and δ = 0.6; and the given
capacitance, determine an inductance to keep the peak-peak 0.4 0.5
inductor ripple current at less than 20% of the average ∆ILpk,pk(A) 0.10502 0.06970
inductor current at the respective duty ratio. Among the L 0.00073 0.00136
three inductance values, which one corresponds to the
worst-case scenario? How does this value compare with the
given value?
For duty ratios of δ = 0.4, δ = 0.5, and δ = 0.6; and the given 0.4 0.5
inductance, determine the size of output capacitor that will ∆Vc,pkpk 0.1278 0.1533
ensure that output ripple voltage is not more than 2% of the
average output voltage at the respective duty ratio. Among C 0.0001370 0.0001136
the three capacitance values, which one corresponds to the
worst-case scenario? How does this compare with the given
value?

Using the specified component values, design a DC-DC


converter that meets the output voltage and load current
specifications.

13mOhm
Determine from manufacturer’s data sheets the equivalent The higher the ESR the higher the losses due t
series resistance of the capacitor. Why is this an important By keeping the ESR as low as possible the con
parameter in switch-mode converters? can operate at a efficient rate
0.4 0.5
Vo,rms
Calculate the RMS value of the input and output voltage and
current when δ = 0.4, 0.5 and 0.6 Vin,rms 5 5
Io,rms 1 1
Iin,rms 1.673184785 2.0083390963
0.4 0.5
Pin 8.333 10.000
Pout 6.389 7.667
Calculate the input and output apparent, distortion and Sin
active power as well as corresponding power factors when δ Sout
= 0.4, 0.5 and 0.6. Qin
Qout
PF distortion
PF distortion
0.6 Lmax 4.29E-02
2.500 Lmin 2.31E-02
9.583 Cmax 2.86E-04
0.871 Cmin 1.54E-04
0.032
0.750
3.750

0.4 0.5 0.6


Lmax 0.0017871 0.0017716 0.0017483
Lmin 0.0033189 0.00329 0.0032468
Cmax 0.0612021 0.0609239 0.0913859
0.6 Cmin 0.0027632 0.0043175 0.0062172
0.06970
0.00161
H

0.6
0.1917 0
0.0001364

SR the higher the losses due to heat.


ESR as low as possible the converter
operate at a efficient rate
0.6

5
1
2.5093574875
0.6
12.500
9.583
output voltage vs duty ratio
Duty Ratio(%) Vo (mean) Vo (RMS)
40 8.09 8.16
45 8.56 8.63
50 9.31 9.38
55 9.67 9.72
60 10.4 10.4

Output voltage VS Duty ratio 94

12 92

10 90

Efficiency(%)
8 88
Voltage(v)

6 86
4 84
2 82
0 80
40 45 50 55 60 40
Duty Ratio(%)

Vo (mean) Vo(RMS)

Converter losses()W
4

0
40
Converter losses and effiency vs duty ratio
Pin Pout Efficiency(%) Converter loss(W) Duty ratio(%)
27.007 22.852 84.615099789 4.155 40
38.5 33.584 87.231168831 4.916 50
39.5 36.34 92 3.16 60

Efficiency vs Duty ratio


94

92

90
Efficiency(%)

88

86

84

82

80
40 50 60
Duty ratio(%)

Converter loss(W)
6

5
Converter losses()W

0
40 50 60
Duty Ratio(%)

Converter loss(W)

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