Digital design and computer

organization
BCS302
Module 1
Introduction to Digital Design
By,

Dr. Ashwini N
Assistant Professor
Dept. of Information Science & Engineering
BMS Institute of Technology, Bengaluru.

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Basic Gates
• A logic gate is a digital circuit with 1 or more input voltages but only 1 output voltage.
• Logic gates are the fundamental building blocks of digital systems.
• By connecting the different gates in different ways, we can build circuits that perform
arithmetic and other functions associated with the human brain.
• Because the circuits simulate mental processes, gates are often called logic circuits.
NOT, OR & AND gates are the basic types of gates.
• The inter-connection of gates to perform a variety of logical operations is called logic
design.
• The operation of a logic gate can be easily understood with the help of "truth table".
• A truth table lists all possible combinations of inputs and the corresponding outputs.

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Basic Gates
NOT GATE (INVERTER)
• It is a gate with only 1 input and a complemented output.

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Basic Gates

AND GATE
• This is a gate with 2 or more inputs.
• The output is HIGH only when all inputs are HIGH.

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Basic Gates
OR GATE
• This is a gate with 2 or more inputs.
• The output is HIGH when any input is HIGH.

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Universal Gates
NOR GATE
• This represents an OR gate followed by an inverter.

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Universality of NOR Gate

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Universal Gates
NAND GATE
• This represents an AND gate followed by an inverter.

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Universality of NAND Gate

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EXCLUSIVE-OR GATES
• The exclusive-OR gate has a high output only when an odd number of inputs is
high.

• OR
• Y = A⨁B

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EXCLUSIVE-OR GATES

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EXCLUSIVE-NOR GATES

A B Y
A
0 0 1 Y
B
0 1 0
1 0 0
1 1 1

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Introduction

• Each gate input is labelled with a variable.

• Each appearance of a variable or its complement in an expression will
be referred to as a literal.

• The following expression, which has three variables, has 10

literals
• ab′c + a′b + a′bc′ + b′c′

• A truth table (also called a table of combinations) specifies the

values of a Boolean expression for every possible combination of
values of the variables in the expression.

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Introduction

• An expression is said to be in sum-of-products (SOP) form when all products are

the products of single variables.
• E.g. AB′ + CD′E + AC′E′
• A sum-of-products expression can be realized using one or more AND
gates feeding a single OR gate at the circuit output.
• An expression is in product-of-sums (POS) form when all sums are the sums of
single variables.
• E.g. (A + B′)(C + D′ + E)(A + C′ + E′)
• A product-of-sums expression can be realized using one or more OR
gates feeding a single AND gate at the circuit output.

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Introduction

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Introduction

• Redundant Terms: The Term not or no longer needed or useful.

(A + BC)(A + D + E)
= A + AD + AE + ABC + BCD + BCE
= A(1 + D + E + BC) + BCD + BCE
= A + BCD + BCE

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SUM-Of-PRODUCTS (SOP)
• Possible ways to AND two or more input signals that are in
complement and uncomplement form.
• A SOP expression is two or more AND functions ORed together.

Example: XY + X′Z + YZ

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SUM-Of-PRODUCTS (SOP)

• ANDing two variables and their complements

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SUM-Of-PRODUCTS (SOP)
•

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SUM-Of-PRODUCTS (SOP)

• Example:
• Fundamental Products for Three Inputs

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SUM-Of-PRODUCTS (SOP)

• The above three variable minterms can alternatively be represented by

mo, m1, m2, m3, m4, m5, m6, and m7 respectively. Note that, for n
variable problem there can be 2n number of minterms.

• The fundamental products by listing each one next to the input

condition that results in a high output.

• For instance, when A = 1, B = 0 and C = 0, the fundamental product

results in an output of

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Sum-of-Products Equation

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Sum-of-Products Equation

• To get the sum-of-products equation, all you have to do is OR the

fundamental products

• Alternate representation

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Sum-of-Products Equation-3

• where '∑:' symbolizes summation or logical OR operation that is

performed on corresponding minterm’s and Y = F (A, B, C) means Y
is a function of three Boolean variables A, B and C. This kind of
representation of a truth table is also known as canonical sum form.

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Logic Circuit

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PRODUCT-Of-SUMS METHOD

• Given a truth table, identify the fundamental sums needed for a logic
design. Then by ANDing these sums, will get the product-of-sums
equation corresponding to the truth table.
• But, in the sum-of-products method, the fundamental product
produces an output l for the corresponding input condition.
• But with the product of- sums method, the fundamental sum produces
an output 0 for the corresponding input condition.

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PRODUCT-Of-SUMS METHOD-2
• Converting a Truth Table to an Equation

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PRODUCT-Of-SUMS METHOD-3

• Logic Circuit

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PRODUCT-Of-SUMS METHOD-4

• Conversion between SOP and POS

• SOP and POS occupy complementary locations in a truth table.
•Identifying complementary locations,
•Changing minterm to maxterm or reverse, and
•Changing summation by product or reverse.

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DON'T-CARE CONDITIONS

• In digital systems, certain input conditions never occur during normal

operation; therefore, the corresponding output never appears. Since the
output never appears, it is indicated by an X in the truth table.
• The X is called a don 't-care condition. Whenever you see an X in a truth
table, you can let it equal either 0 or 1, whichever produces a simpler
logic circuit.

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DON'T-CARE CONDITIONS

• Truth Table with Don’t-Cares

• In Minterm form
F =Σ m(0, 3, 7) +Σ d(1, 6)
• In Maxterm form
F =Π M(2, 4, 5)· Π D(1, 6)

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DON'T-CARE CONDITIONS

Truth Table with Don't-Care Conditions

Y=F(A,B,C,D) = ∑m (9) + d(10,11,12,13,14,15)

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Karnaugh Maps

• Switching functions can generally be simplified by using the algebraic techniques.

• However, two problems arise when algebraic procedures are used:
1. The procedures are difficult to apply in a systematic way.
2. It is difficult to tell when you have arrived at a minimum solution.
• The Karnaugh map method and the Quine-McCluskey procedure used to
overcome these difficulties by providing systematic methods for simplifying
switching functions.
• The Karnaugh map is useful tool for simplifying and manipulating switching
functions of three or four variables (Literals).

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 Karnaugh Maps
TwoVariable Karnaugh Maps

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 Karnaugh Maps
Three-Variable Karnaugh Maps

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 Karnaugh Maps
Four-Variable Karnaugh Maps

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Two Variable K-MAP

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Three Variable K-MAP

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FOUR Variable K-MAP

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K-MAP for given truth table

Y=A’B’+A’B

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K-MAP for given truth table

Y=A’BC’+ABC’+ABC

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K-MAP for given truth table

Y=A’B’C’D+A’BCD+A’BCD’+ABCD’

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K-MAP Grouping Pairs

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K-MAP Grouping Pairs

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K-MAP Grouping QUAD

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K-MAP Grouping QUAD

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K-MAP Grouping OCtETS

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K-MAP Grouping Symmetric

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 Problems on K-map

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Problems on K-map

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Problems on K-map

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 Problems on K-map

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Problems on K-map

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Problems on K-map

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Problems on K-map with DON'T-CARE CONDITIONS

• Truth Table with Don’t-Cares

• In Minterm form
F =Σ m(0, 3, 7) +Σ d(1, 6)
• In Maxterm form
F =Π M(2, 4, 5)· Π D(1, 6)

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 Problems on K-map with DON'T-CARE CONDITIONS

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 Problems on K-map with DON'T-CARE CONDITIONS

F(A,B,C,D)= Σ m(1,5,6,12,13,14) +Σ d(4)

PI= BC’,BD’,A’C’D
Y= BC’+BD’+A’C’D

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 Problems on K-map with DON'T-CARE CONDITIONS

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 Problems on K-map with DON'T-CARE CONDITIONS

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 Problems on K-map with DON'T-CARE CONDITIONS

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 Problems on K-map with DON'T-CARE CONDITIONS

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 Problems on K-map with DON'T-CARE CONDITIONS

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 Problems on K-map with DON'T-CARE CONDITIONS

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 Problems on K-map

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 Problems on K-map

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 Problems on K-map

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 Problems on K-map

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 Problems on K-map

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 Problems on K-map

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 Problems on K-map

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 Problems on K-map

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 Problems on K-map

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Determination of Minimum Expressions Using Essential Prime
Implicants

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QUINE-McCLUSKY METHOD

• Drawbacks of K Map method

• Karnaugh map method is very simple and intuitively appealing is
somewhat subjective.
• It depends on the user's ability to identify patterns that gives largest
size.
• Also the method becomes difficult to adapt for simplification of 5 or
more variables.

• QM method is Tabular Method of Minimisation

• Quine-McClusky method involves preparation of two tables; one
determines prime implicants and the other selects essential prime
implicants to get minimal expression.
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QUINE-McCLUSKY METHOD

• The Quine-McCluskey method reduces the minterm expansion (standard

sumof-products form) of a function to obtain a minimum sum of products. The
procedure consists of two main steps:

1. Eliminate as many literals as possible from each term by

systematically applying the theorem XY + XY′ = X. The resulting
terms are called prime implicants.
2. Use a prime implicant chart to select a minimum set of prime
implicants which, when ORed together, are equal to the function
being simplified and which contain a minimum number of literals.

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 Quine-McClusky Method
F(A,B,C) =Σ m(0, 1, 2, 5, 6, 7)

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QUINE-McCLUSKY METHOD

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 QUINE-McCLUSKY METHOD- Finding essential Prime
Implicants

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 QUINE-McCLUSKY METHOD

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 QUINE-McCLUSKY

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 QUINE-McCLUSKY METHOD- Finding essential Prime Implicants

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 QUINE-McCLUSKY METHOD

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 QUINE-McCLUSKY METHOD- Finding essential Prime Implicants

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 QUINE-McCLUSKY METHOD

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 QUINE-McCLUSKY METHOD- Finding essential Prime Implicants

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 QUINE-McCLUSKY
METHOD

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 QUINE-McCLUSKY
METHOD
F(A,B,C) = ∏ M(0, 5,6,7,8,9,13,15)

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 QUINE-McCLUSKY
METHOD

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 QUINE-McCLUSKY
METHOD

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 NAND – NAND Realization
Convert the following circuit using NAND gates only.

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 NAND – NAND Realization

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 NAND – NAND Realization

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 NAND – NAND Realization

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 NOR – NOR Realization
Convert the following circuit using NAND gates only.

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 NOR – NOR Realization

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 NOR – NOR Realization

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 Hardware Description Language
• In computer engineering, a hardware description language (HDL)
is a specialized computer language used to describe the structure and
behavior of electronic circuits, and most commonly, digital
logic circuits.
• There are two major hardware description
languages: VHDL and Verilog.

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 Hardware Description Language
• VHDL
• The Very High Speed Integrated Circuit (VHSIC) Hardware
Description Language (VHDL) is a language that describes the
behavior of electronic circuits, most commonly digital circuits.
• There are different types of description in them: "dataflow, behavioral
and structural".

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 Structure of VHDL Program
Structure of VHDL Program
Every VHDL program consists of at least one entity/architecture pair. In a large design, you will typically
write many entity/architecture pairs and connect them together to form a complete circuit. An entity
declaration describes the circuit as it appears from the “outside” - from the perspective of its input and
output interfaces. The second part of a minimal VHDL design description is the architecture declaration.
ENTITY:
ENTITY is the list with specifications of all input and output pins of the circuit. Its syntax is shown below :
ENTITY name IS
PORT (
port_name : signal_mode signal_type;
port_name : signal_mode signal_type;
...
);
END name;
The mode of the signal used may be IN, OUT, INOUT or BUFFER. IN and OUT are unidirectional pins,
while INOUT is bidirectional. BUFFER, is used when the output signal is used internally in the design. The
type of the signal may be BIT, STD_LOGIC, INTEGER, etc. The name of the entity should be not use the
VHDL reserved words.

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 Structure of VHDL Program

• ARCHITECTURE:
The ARCHITECTURE is the description of how the circuit of design
works. Its syntax is as follows,
• ARCHITECTURE architecture_name OF entity_name IS
[declarations] BEGIN (code) END architecture_name;

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 Refer all Lab Programs on simulation

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