Es ZG626 Course Handout

BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI
WORK INTEGRATED LEARNING PROGRAMMES

Digital Learning
Part A: Content Design
Course Title HARDWARE AND SOFTWARE CO-DESIGN
Course No(s) AEL ZG626/ ES ZG626/MEL ZG651/SS ZG626/ SE ZG626
Credit Units 5
Credit Model Theory
Content Authors PAWAN SHARMA & PARESH JOSHI
Course Objectives
No
CO1 To provide an understanding of system-level design of embedded systems comprised of both

hardware and software
CO2 Introduction to hardware software implementation, Complex system modeling and simulation
CO3 To investigate topics such as Hardware Software partitioning, mapping and scheduling, Co-
simulation, synthesis and verification relevant to co-design
CO4 Introduction to hardware software partitioning and estimation, hardware software interfaces
CO5 To explore, analysis and optimization processes in support of algorithmic and architectural
design decisions; gain design experience with case studies using contemporary high-level
methods and tools.
Text Book(s)
T1 Daniel D Gajski, Frank Vahid, Sanjay Narayan, Jie Gong, Specification and Design of Embedded
Systems, Prentice Hall, 1994.
T2 Patrick R. Schaumont, A Practical Introduction to Hardware/Software Codesign, Springer, 2 nd
ed. 2013
Reference Book(s) & other resources

R1 Jorgen Staunstrup, Wayne Wolf, Hardware / Software Co-Design: Principles and Practice,
Kluwer Academic, 1997
R2 Peter Marwedel, Embedded System Design, Springer 2003
R3 G. DeMicheli, R. Ernst and W. Wolf, Readings in Hw/Sw Co-design, M. Kaufmann, 2002,
R4 Ahmed A. Jerraya and Jean Mermet eds.: System Level Synthesis, Kluwer 1999.
R5 Hardware/Software Codesign. G. DeMicheli and M. Sami (eds.), NATO ASI Series E, Vol. 310,
1996.
R6 Sanjaya Kumar, James H. Aylor, Barry W. Johnson, and Wm. A. Wulf. The Codesign of
Embedded Systems. Kluwer, 1995
R7 Proceedings of IEEE, IEEE Transactions, ACM Transactions
Learning Outcomes:
No Learning Outcomes. Knowledge in the following areas
LO1 System modeling and simulation
LO2 hardware software implementation of complex systems
LO3 hardware software interfaces
LO4 hardware software partitioning and estimation techniques
LO5 hardware software co-synthesis
Part B: Learning Plan

Academic Term First Semester 2023-2024
Course Title HARDWARE AND SOFTWARE CO-DESIGN
Course No AEL ZG626/ ES ZG626/MEL ZG651/SS ZG626/ SE ZG626
Lead Instructor PAWAN SHARMA
Instructor PARESH JOSHI
Content Structure
Contact List of Topic Title Reference

Seesion
1  Introduction to Embedded System Design, High Level T1 Ch 1
Design T2 Ch1
 Introduction to Hardware/ Software Codesign
 Dualism of Hardware and Software designs T1 Ch 2
 Concept of system modeling, Need for Concurrent T2 Ch1
Models
2  State Oriented Models T1 Ch2
 FSM, Petri Net R2 Ch2
 Petri Net
 HCFSM or State Charts
3  Activity Oriented Models, Data Flow Graph T1 Ch2
 Analyzing Synchronous Data Flow Graphs, Control Flow T2 Ch2
Modeling and the Limitations of Data Flow Models
 Adding Time and Resources, Data Flow Transformations
4  Data Flow Transformations T2 Ch2
 Data Flow Implementation in Software T2 Ch3
5  Data Flow Implementation in Hardware T2 Ch3
 Data and Control Edges of a C Program, Implementing
Data and Control Edges, Construction of the Control T2 Ch4
Flow Graph and Data Flow Graph
6  Construction of the Data Flow Graph, Application: T2 Ch4
Translating C to Hardware
 Introduction to Specification Languages, Characteristics
of Conceptual Models, Survey of Specification T1 Ch3
Languages
7  System c or any other example
8 Review session
9  Application Specific Architectures T2 Ch5
 Controller Architecture, Datapath Architecture , Finite T1 Ch2
State Machine with Datapath (FSMD)
 Simulation and Synthesis of FSMD
 Language Mapping for FSMD
10  Microprogrammed Architectures T2 Ch6

 Microprogrammed Control
 Microinstruction Encoding
 Microprogrammed Datapath
 Implementation
 System-on-Chip Concept
 Connecting Hardware and Software, On-Chip Bus T2 Ch8, 10
Systems, Bus Transfers
11  The Hardware/Software Communication, T1 Ch9
Synchronization schemes
 Software/Microprocessor Interfaces, Memory-Mapped
Interfaces T1 Ch11
12  Coprocessor Interfaces , Custom Instruction Interfaces T1 Ch11
 Hardware Interface
 Coprocessor Hardware Interface T1 Ch12
 Partitioning Issues, Partitioning algorithms
 Partitioning Issues, Partitioning algorithms
T1 Ch6
13  Functional partitioning for Hardware, Hardware and T1 Ch6
Software Partitioning Algorithms
14  Hardware / Software Co-Synthesis T1 Ch 6
 Introduction, Classification
 Examples: Vulcan, Cosyma, SpecSyn, etc...
 Design Quality Estimation , Quality Metrics, Hardware
Estimation, Software Estimation
T1 Ch7
15  Design Quality Estimation , Quality Metrics, Hardware T1 Ch7
Estimation, Software Estimation
 Recent Trends and Examples
16 Review session
Laboratory Details:
Evaluation Scheme:
Legend: EC = Evaluation Component; AN = After Noon Session; FN = Fore Noon Session
No Name Type Duration Weight Day, Date, Session, Time
EC-1 Assignment-I Online - 15% February 19-28, 2024
Assignment-II Online - 15% March 19-28, 2024
EC-2 Mid-Semester Test Closed Book 2 hours 30% Friday, 15/03/2024 (AN)
EC-3 Comprehensive Exam Open Book 2½ 40% Friday, 17/05/2024 (AN)
hours
Syllabus for Mid-Semester Test (Closed Book): Topics in Session Nos. 1 to 8
Syllabus for Comprehensive Exam (Open Book): All topics (Session Nos. 1 to 16)
Important links and information:
Elearn portal: https://elearn.bits-pilani.ac.in
Students are expected to visit the Elearn portal on a regular basis and stay up to date with the latest announcements and
deadlines.
Contact sessions: Students should attend the online lectures as per the schedule provided on the Elearn portal.
Evaluation Guidelines:
1. EC-1 consists of either two Assignments. Students will attempt them through the course pages on the Elearn portal.
Announcements will be made on the portal, in a timely manner.
2. For Closed Book tests: No books or reference material of any kind will be permitted.
3. For Open Book exams: Use of books and any printed / written reference material (filed or bound) is permitted. However,
loose sheets of paper will not be allowed. Use of calculators is permitted in all exams. Laptops/Mobiles of any kind are
not allowed. Exchange of any material is not allowed.
4. If a student is unable to appear for the Regular Test/Exam due to genuine exigencies, the student should follow the
procedure to apply for the Make-Up Test/Exam which will be made available on the Elearn portal. The Make-Up
Test/Exam will be conducted only at selected exam centres on the dates to be announced later.
It shall be the responsibility of the individual student to be regular in maintaining the self study schedule as given in the course
handout, attend the online lectures, and take all the prescribed evaluation components such as Assignment/Quiz, Mid-Semester
Test and Comprehensive Exam according to the evaluation scheme provided in the handout.

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BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI

WORK INTEGRATED LEARNING PROGRAMMES

CO1 To provide an understanding of system-level design of embedded systems comprised of both

Reference Book(s) & other resources

LO1 System modeling and simulation

LO2 hardware software implementation of complex systems

LO3 hardware software interfaces

LO4 hardware software partitioning and estimation techniques

LO5 hardware software co-synthesis

Part B: Learning Plan

Contact List of Topic Title Reference

10  Microprogrammed Architectures T2 Ch6

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