VLSI Design
VLSI Design
Reviewed AICTE Model Curriculum for Undergraduate degree in Electrical & Electronics Engineering (Engineering & Technology)
Module 2: CMOS inverter, static characteristics, noise margin, effect of process variation, supply scaling, dynamic
characteristics, inverter design for a given VTC and speed, effect of input rise time and fall time, static and dynamic
power dissipation, energy & power delay product, sizing chain of inverters, latch up effect-Simulation of static and
dynamic characteristics, layout, post layout simulation (10 hours)
Module 3: Static CMOS design, Complementary CMOS, static properties, propagation delay, Elmore delay model,
power consumption, low power design techniques, logical effort for transistor sizing, ratioed logic, pseudo NMOS
inverter, DCVSL, PTL, DPTL & Transmission gate logic, dynamic CMOS design, speed and power considerations,
Domino logic and its derivatives, C2MOS, TSPC registers, NORA CMOS – Course project (10 hours)
Module 4: Circuit design considerations of Arithmetic circuits, shifter, CMOS memory design - SRAM and DRAM,
BiCMOS logic - static and dynamic behaviour -Delay and power consumption in BiCMOS Logic. (10 hours)
Text / References:
1. David A. Hodges, Horace G. Jackson, and Resve A. Saleh, “Analysis and Design of Digital
Integrated Circuits”, McGraw-Hill, Third edition, 2004..
2. R. J. Baker, H. W. Li, and D. E. Boyce, “MOS circuit design, layout, and simulation”, Wiley-IEEE
Press, 2007.
3. Sung-Mo Kang & Yusuf Leblebici, “CMOS Digital Integrated Circuits - Analysis & Design”, Tata
McGraw Hill, Third edition, 2003.
4. Wayne Wolf, “Modern VLSI design”, Pearson Education, 2003
5. Christopher Saint and Judy Saint, “IC layout basics: A practical guide”, Tata McGraw Hill
Professional, 2001.
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