Verilog tutorial

ELE/COS 475
P R I NCE TON UN I V ERSITY
PAU L JACKS ON
FA L L 2 0 1 5

Slides adapted from Alexey Lavrov

 Agenda
• Purposes of HDL
• Verilog HDL
• Paradigm
• Differences from programming languages
• Syntax
• Types of variables
• Types of assignments
• Common styles
• Module structure
• Parametrization
• Synthesizable VS not synthesizable constructs
• Design verification
• Common Errors
• Design guidelines

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Purposes of HDL

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 Purposes of HDL
• Initially was created to simplify design simulation and verification

Verilog = Verification + Logic

VHDL = VHSIC Hardware Description Language

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 Purposes of HDL
• Initially was created to simplify design simulation and verification

Verilog = Verification + Logic

VHDL = VHSIC Hardware Description Language

• Increasing logic complexity drove added support for

synthesis

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 Purposes of HDL
• Initially was created to simplify design simulation and verification

Verilog = Verification + Logic

VHDL = VHSIC Hardware Description Language

• Increasing logic complexity drove added support for

synthesis

• Nowadays SystemVerilog 2012 is an

extension of Verilog designed with
emphasis on verification

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Verilog HDL

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 Poll #1

1. Who knows Verilog HDL?

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 Poll #1

1. Who knows Verilog HDL?

2. Who can write a synthesizable FIFO?

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 Poll #1

1. Who knows Verilog HDL?

2. Who can write a synthesizable FIFO?

3. Who can write a parameterized FIFO?

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 Verilog paradigm
 Design consists of hierarchical modules connected on
the same level of hierarchy

 Each module is a set of

interconnected
wires, flip-flops, and
combinational logic

 Only a subset of Verilog is synthesizable

 Non synthesizable part is used for testing

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 Differences from programming languages

Verilog C/C++
Variable declaration
wire [7:0] sum; int sum;
Procedural blocks
if (a == 8’b0) begin if (a == 0) {
… …
end }
else begin else {
… …
end }

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 Differences from programming languages
Verilog C/C++
For statement
wire [N-1:0] a;
generate
for (i=0; i<N; i=i+1) for (i=0; i<N; i++) {
begin a[i] = b + c;
assign a[i] = b & c; }
end
endgenerate
a[0] = b+c;
a[1] = b+c;
a[2] = b+c; Describes
Describes
… Sequence of
Hardware
a[N-2] = b+c; Instructions
a[N-1] = b+c;

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Verilog
Syntax

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 Syntax
• Logic values:
‘0’, ‘1’
‘x’ – unknown value (‘0’, ‘1’ or ‘z’)
‘z’ – high-impedance

• Literals <width>’<base><number>
Binary: 1’b0, 4’b1100, 8’b1001_1101
Decimal: 8’d7
Hexadecimal: 32’hBAC007

• Integer
int i; - 32 bit signed value;

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 Syntax
• Wires
wire single_wire;
wire [7:0] one_dimensional_bus_1; or
wire [0:7] one_dimensional_bus_2;
wire [31:0] two_dimensional_bus [7:0];

• Slicing
wire [31:0] bus; - declare 4 byte bus
bus[7:0] – lowest byte of bus

• Concatenation
{bus[7:0], bus[15:8], bus[23:16], bus[31:24]}

• Replication
{8{4’b1010}}; - replicate binary value 4’b1010 8 times

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 Syntax

• Register – same declaration as for wires

Slicing and concatenation also works for registers
reg empty;
reg [15:0] state;
reg [63:0] buffer [2:0];
{state[15], state[7], state[0]}

• Declaration of a register does not always imply flip-flop

implementation (see following slides)
• Depends on assignment type

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 Syntax
• Operators
Operator Type Symbols Example
Bitwise ~ & | ^ 4’b1010 & 4’b0100

Logical ! && || 4’b1010 && 4’b0100

Reduction & ~& | ~| ^ ~^ |4’b0001

Arithmetic + - * / ** % 4’b1110 – 1

Relational > < >= <= == != === !=== 4’d5 < 4’d3

Shift >> << >>> <<< 4’0110 << 1

Concatenation {,} {2’b10, 2’b01}

Replication {n{m}} {8{1’b1}}

Conditional ? : empty ? 1’b1 : 1’b0

Note: operators are not listed in descending precedence order

Always use parentheses if a code can cause ambiguity

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 Syntax
• Basic Verilog statements: always block

always @( <sensitivity list>) begin

<statements>
end Important notes:
reg stage_1_val, stage_0_val;  all always blocks are
always @(posedge clk) begin executed in parallel
stage_1_val <= stage_0_val;  LHS of an always block is
end always a register
 Can describe either a flip-
reg ready;
flop or combinational logic
wire empty;
reg [3:0] next_addr, curr_addr[3:0];
always @(*) begin
ready = ~empty;
next_addr = curr_addr + 1;
end

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 Syntax
• Blocking VS non-blocking assignments
= - blocking
<= - non blocking, used only in always blocks

Blocking Non Blocking

Statements inside always block are Statements inside always block are
executed sequentially executed in parallel. Value assigned to
LHS are taken from “previous” values of
RHS

always @(*) begin always @(posedge clk) begin

b = a; b <= a;
c = b; c <= b;
d = b; d <= b;
end end

d =? a d =? a

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 Syntax
Blocking Non Blocking

always @(*) begin always @(posedge clk) begin

out = a & b; out <= a & b
end end

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 Syntax
• Assignment statement (block)

wire any_val;
wire in_val_1, in_val_2, in_val_3;
assign any_val = in_val_1 | in_val_2 | in_val_3;

Important notes:
 all assign statements are executed in parallel
 LHS of assign block is always a wire
 Describes only combinational logic

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 Syntax

• Initial block Important notes:

initial begin
clk = 0;  Starts execution at
rst_n = 0;
time 0
init = 0;
forever begin  Executed only once
#5 clk = ~clk;  Non synthesizable,
end used for simulation
end and verification

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 Syntax
• Conditional statements Important notes:
if <condition> begin
<statement1>
 Used in always, initial
end
[else if <condition> begin blocks
<statement2>  A latch will be
end] generated instead of
[Else begin a flip-flop if there is
<statement3>
no else statement
end]

always @(posedge clk) begin

if (~rst_n)
data_out <= {64{1’b0}};
else
data_out <= data_stage_4;
end

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 Syntax
• Case statement Important notes:
case (addr):
0: out = a;  Used in always, initial
1: out = b; blocks
2: out = c;  A latch will be
default: begin end generated instead of
endcase a flip-flop if case is
not full and there is
• casez: treats z as don’t care no default statement
casex: treats x and z as don’t care
Used in simulation

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 Syntax
• Conditional (ternary) operator

wire [7:0] data_out = r_val & w_val ? data_in :

r_val & ~empty ? buffer[id] :
{8{1’b0}} ;

always @(posedge clk) begin

if (~rst_n) begin
cmd_out <= {3{1’b0}};
end
else begin
cmd_out <= val_0_in ? cmd0 :
val_1_in ? cmd1 : cmd_default;
end
end

 Good thing: always has default case

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 Common styles
Style 1 Style 2
Combinational logic

reg empty;
wire empty;
always @(*) begin
assign empty = (cnt==0) & ~wr_val; empty = (cnt==0) & ~wr_val;
end
Sequential logic
reg state, state_next;
reg [ST_W-1:0] state;
always @(*) begin
always @(posedge clk) begin if (val_1_in)
if (~rst_n) state_next = ACCEPT_ST;
state <= {ST_W{1’b0}}; else if (val_2_in)
else state_next = WAIT_ST;
state <= val_1_in ? ACCEPT_ST : else
val_2_in ? WAIT_ST : state_next = state;
state ; End
end
always @(posedge clk) begin
if (~rst_n)
state <= {ST_W{1’b0}};
else
state <= state_next;
end
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 Syntax
• Module structure • Module instantiation
module <module name> ( <module name> <instance name> (
input clk, .clk (rst_n ),
input rst_n, .rst_n (rst_n ),

input [31:0] data_in, .data_in (data_in ),

input w_val, .w_val (w_val ),

output reg data_out, .data_out (data_out),

output reg r_val .r_val (r_val )
); );

// Register declaration
reg [3:0] position;
// Wire declaration
wire [3:0] position_next;

// Sequential logic

// Combinational logic

endmodule

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 Syntax
• Parametrization
Verilog has preprocessor – can use defines

`include <defines.h>

module example(
input clk,
input rst_n,

input [`DATA_IN_W-1:0] data_in,

output reg [`DATA_OUT_W-1:0] data_out
);

always @(posedge clk) begin

if (~rst_n)
data_out <= {`DATA_OUT_W{1’b0}};
else
data_out <= data_in[`DATA_OUT_W-1:0];
end

endmodule

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 Syntax
• Parametrization
Parameters • Overwriting parameters
module example #( example exmpl_inst #
parameter WIDTH = 16 .WIDTH (32)
) )
( (
input clk, .clk (clk ),
input rst_n, .rst_n (rst_n ),
input [`WIDTH-1:0] data_in,
output reg [`WIDTH-1:0] data_out .data_in (data_in ),
); .data_out (data_out )
);
...
endmodule

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 Verilog
• Parametrization
Local parameters
`define WIDTH 16 Notes:
module example (  Parameters can be
input clk,
input rst_n,
overwritten from outside,
localparms can not
input [`WIDTH-1:0] cmd
);
localparam INIT_ST = 0;
localparam WAIT_DATA_ST = 1;
localparam WAIT_CMD_ST = 2;

parameter BUF_SIZE = 64;

...
endmodule

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Non-synthesizable Verilog &
Other topics

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 Verilog
• Nonsynthesizable part of Verilog is used to:
• Simulate delays
• Monitor signal values
• Model external signals
• Stop/continue simulation
• Simulation time precision
`timescale 1ns/1ps
module tb_top();
...
endmodule

• Model external signals, delays

initial begin
clk = 0;
rst = 0;
#200
rst = 1;
end

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 Verilog
• Generate system clock
initial begin
forever
clk = #10 ~clk;
end

• Monitor signal values

always @(posedge clk) begin
if (val_in)
$display(“Data written: %x”, data_in, $time);
end

• Dump waveforms*
initial begin
$dumpfile("waves.vcd");
$dumpvars(0, fpga_top.cmp_top.mc_top.pkt_trans_dp_wide);
$dumpvars(0, fpga_top.cmp_top.mem_io_splitter);
end
*for loop may be required to dump multidimensional buses

• Finish simulation
always @(posedge clk)
if ($time >= MAX_SIM_TIME)
$finish;

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 Verilog
… and many others:
 Tasks
 Functions
 While, for loops
 $reset, $stop
 $random
 $fopen, $fdisplay, $fwrite

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 Python Preprocessor for Verilog
 PyHP preprocessor can run Python code to generate Verilog
code
 Simplifies verbose Verilog code
 Can use Python functions and/or loops to dynamically
generate Verilog
 Useful for
 Connecting large modules together
 Filling out a complex control signal table
 Instantiating code that is difficult to create using a
generate statement

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 Python Preprocessor for Verilog

 Available on adroit for your use in labs or the final project:

 /home/ee475/dropbox/pyhp.tar.gz
 Extract the tarball
 tar -zxvf pyhp.tar.gz
 The main script for compiling .pyv to .v is pyhp.py
 Example is in verilog_test/
 Enter “make set_of_slices.v” to compile the provided
.pyv to .v

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 Job Scheduling on Adroit
• Logging into Adroit logs into the head node
• The head node should be used for small tasks like file
editing, compilation, etc.
• Simulations should not run on the head node

• SLURM – Simple Linux Utility for Resource Management

• Manages hardware resources
• Schedules when jobs run on which machines

• Why use SLURM?

• Takes advantage of the entire cluster
• Don’t want to unfairly take compute resources away
from others

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 Job Scheduling on Adroit
• sinfo – displays cluster resources
• Squeue – displays job queue

[pjj@adroit3 ~]$ sinfo

PARTITION AVAIL TIMELIMIT NODES STATE NODELIST
all* up 15-00:00:0 3 mix adroit-[01,05-06]
all* up 15-00:00:0 5 alloc adroit-[02-04,07-08]

[pjj@adroit3 ~]$ squeue

JOBID PARTITION NAME USER ST TIME NODES NODELIST(REASON)
380774_[9] all ffs-ar9 hajakbar PD 0:00 1 (Resources)
380775_[10] all ffs-ar10 hajakbar PD 0:00 1 (Priority)
380370_[4] all ffs-ar4 hajakbar PD 0:00 1 (Priority)
380778_[5] all ffs-ar5 hajakbar PD 0:00 1 (Priority)
380779_[6] all ffs-ar6 hajakbar PD 0:00 1 (Priority)
380780_[7] all ffs-ar7 hajakbar PD 0:00 1 (Priority)
380752_[11] all ffs-ar11 hajakbar PD 0:00 1 (Dependency)
380753_[12] all ffs-ar12 hajakbar PD 0:00 1 (Dependency)
380760_[11] all ffs-ar11 hajakbar PD 0:00 1 (Dependency)
...

Reference: http://www.ceci-hpc.be/slurm_tutorial.html
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 Job Scheduling on Adroit
• A submission script is used to define what commands
are needed in order to run the job
• srun indicates a command to be run
• Submission scripts also contain information about the
job itself
• Use SBATCH parameters
(http://slurm.schedmd.com/sbatch.html)
#!/bin/bash
#
#SBATCH --job-name=pjjtest // Job name
#SBATCH --output=result.txt // Log file for console output
#SBATCH --ntasks=1 // Number of tasks (>1 when parallelizing tasks)
#SBATCH --time=10:00 // Allocated time to complete job
#SBATCH --mem-per-cpu=100 // Memory allocation per cpu(MB)

srun make clean

srun make
srun make check
srun sleep 60
Reference: http://www.ceci-hpc.be/slurm_tutorial.html
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 Job Scheduling on Adroit
• Submit jobs using sbatch command
• Information about submitted jobs can be found using
sstat command
[pjj@adroit3 build]$ sbatch submit.sh
Submitted batch job 407990
[pjj@adroit3 build]$ sstat 407990
JobID MaxVMSize MaxVMSizeNode MaxVMSizeTask AveVMSize MaxRSS MaxRSSNode MaxRSSTask AveRSS MaxPages
MaxPagesNode MaxPagesTask AvePages MinCPU MinCPUNode MinCPUTask AveCPU NTasks AveCPUFreq ReqCPUFreqMin
ReqCPUFreqMax ReqCPUFreqGov ConsumedEnergy MaxDiskRead MaxDiskReadNode MaxDiskReadTask AveDiskRead MaxDiskWrite
MaxDiskWriteNode MaxDiskWriteTask AveDiskWrite
------------ ---------- -------------- -------------- ---------- ---------- ---------- ---------- ---------- -------- --
---------- -------------- ---------- ---------- ---------- ---------- ---------- -------- ---------- ------------- -----
-------- ------------- -------------- ------------ --------------- --------------- ------------ ------------ -----------
----- ---------------- ------------
407990.4 214764K adroit-06 0 4080K 1288K adroit-06 0 548K 0
adroit-06 0 0 00:00.000 adroit-06 0 00:00.000 1 2.50M Unknown
Unknown Unknown 0 0.02M adroit-06 0 0.02M 0.00M
adroit-06

Reference: http://www.ceci-hpc.be/slurm_tutorial.html
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 Design verification
Make sure that the module is doing what it supposed to do

• For labs:
• Check all functions, performed by a module
• Check corner case
• Explain why those test cases are corner cases

• For real-world designs:

• Coverages: by lines, by brances, by FSM states
• Formal verification

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 Common Errors

• No clock signal
• Wrong reset level
• If-else, case statements without default case
• No initial values for registers (which do require it)
• Blocking assignment (=) in @(posedge clk) blocks
• Describing a combinational logic instead of flip-flop
• Width mismatch
• Counter overlow/undeflow (do no assume all counter to
be power of 2, especially in parametrized modules)
• Deadlock on val/rdy interface (circular dependence)

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 Design guidelines
• Use version control

• Think in terms of hardware

• Write unit tests for every module

• Use incremental development

• START EARLY!! Do not postpone labs till the last day 

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 Have more questions?

 Refer to recommended Verilog book

 Come to office hours !

 Tuesdays/Thursdays 12:30-1:30pm
 Message me if you are coming and need access to
F210
 Also by appointment

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