Module 1 DDCO

Digital Design & Computer Organization (BCS302) Module:1 Introduction to Digital Design
Digital Design and Computer Organization BCS301
MODULE-1
Introduction to Digital Design: Binary Logic, Basic Theorems and Properties of Boolean
Algebra, Boolean Functions, Digital Logic Gates, Introduction, The Map Method, Four-
Variable Map, Don’t-Care Conditions, NAND and NOR Implementation, Other Hardware
Description Language – Verilog Model of a simple circuit.
Definition of Binary Logic:

Binary logic consists of binary variables and a set of logical operations. The variables are
designated by letters of the alphabet, such as A, B, C, x, y, z, etc., with each variable having
two and only two distinct possible values: 1 and 0. There are three basic logical operations:
AND, OR, and NOT.
Logic Gates:
Logic gates are electronic circuits that operate on one or more input signals to produce
an output signal. Electrical signals such as voltages or currents exist as analog signals having
values ranging, from 0 to 3 V, are interpreted as 0 or 1 in digital.
Fig 1: Signal levels for binary logic values.
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Mrs. Arjuman Nasreen Banu, Assistant Professor, Dept. of CSE, GCE
The timing diagrams shows the idealized response of each gate as shown in fig 2. The horizontal
axis of the timing diagram represents the time, and the vertical axis shows the signal as it
changes between the two possible voltage levels.
➢ The low level represents logic 0, the high level represents logic.
➢ The AND gate responds with a logic 1 output signal when both input signals are
logic 1.
➢ The OR gate responds with a logic 1 output signal if any input signal is logic 1.
➢ The NOT gate is commonly referred to as an inverter. The reason for this name is
that the output signal inverts the logic sense of the input signal.
Fig 2: Input–output signals for gates.

➢ AND and OR gates may have more than two inputs. An AND gate with three inputs
and an OR gate with four inputs is shown below:
Fig 3: Symbols for digital logic circuits.

➢ The three‐input AND gate responds with logic 1 output if all three inputs are logic 1. The
output produces logic 0 if any input is logic 0.
➢ The four‐input OR gate responds with logic 1 if any input is logic 1; its output becomes
logic 0 only when all inputs are logic 0.
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Basic Theorems and Properties of Boolean Algebra:

Duality Principle:
It states that every algebraic expression deducible from the postulates of Boolean
algebra remains valid if the operators and identity elements are interchanged. If the dual of
an algebraic expression is desired. We simply interchange OR and AND operators and
replace 1’s by 0’s and 0’s by 1’s. Note: Identity element for AND operator is 1 and Identity
element for OR operator is 0.
Two‐Valued Boolean Algebra :
A two‐valued Boolean algebra is defined on a set of two elements, B = {0, 1}, with rules for
the binary operators ‘+’, ‘.’ and NOT as shown in the below table.
The table lists the six theorems of Boolean algebra and four of its postulates.
The theorems and postulates listed are the most basic relationships in Boolean algebra.
The theorems, like the postulates, are listed in pairs; each relation is the dual of the one
paired with it.
The postulates are basic axioms of the algebraic structure and need no proof.
The theorems must be proven from the postulates.
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Table 1
Proofs:
The theorem 1(b) is the dual of theorem 1(a) and that each step of the proof in part (b) is the
dual of its counterpart in part (a). Any dual theorem can be similarly derived from the proof of
its corresponding theorem.
Theorem 3:
(x’)’◻ = x. From postulate 5, we have x + x’ = 1 and x .x’◻ = 0, which together define the
complement of x. The complement of x◻ is x and is also (x’)’.
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The theorems of Boolean algebra can be proven by means of truth tables. The following
truth table verifies the first absorption theorem ie., x= x + xy
The truth table for the first DeMorgan’s theorem, (x + y)’ = x’y’, is as follows:
Operator Precedence:
The operator precedence for evaluating Boolean expressions is
1) Parentheses,
2) NOT
3) AND
4) OR
The expressions inside parentheses must be evaluated before all other operations. The next
operation that holds precedence is the complement, and then follows the AND and, finally, the
OR. Example, consider the truth table for one of DeMorgan’s theorems. The left side of the
expression is (x + y)’. Therefore, the expression inside the parentheses is evaluated first and
the result then complemented. The right side of the expression is x’y’, so the complement of x
and the complement of y are both evaluated first and the result is then ANDed.
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Boolean Functions:
Boolean algebra is an algebra that deals with binary variables and logic operations. A
Boolean function described by an algebraic expression consists of binary variables, the
constants 0 and 1, and the logic operation symbols. For a given value of the binary variables,
the function can be equal to either 1 or 0. Consider the Boolean function F1 = x + y’z . The
function F1 is equal to 1 if x is equal to 1 or if both y’ and z are equal to 1. F1 is equal to 0
otherwise.
• A Boolean function can be represented in a truth table.
• The no. of rows in the truth table is 2n , where n is the no. of variables in the function.
• The binary combinations for the truth table are from 0 through 2n - 1.
Below table shows the truth table for the function F1. There are eight possible binary
combinations for assigning bits to the three variables x, y, and z.
Fig: Gate implementation of F1= x + y’z
There is only one way that a Boolean function can be represented in a truth table. However,
when the function is in algebraic form, it can be expressed in a variety of ways, all of which
have equivalent logic.
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How & why?

• By manipulating a Boolean expression according to the rules of Boolean algebra.
• Thus reduce the number of gates in the circuit and the number of inputs to the gate.
• Designers are motivated to reduce the complexity and number of gates because their
effort reduces the cost of a circuit.
For example, F2 = x’y’z + x’yz + xy’
The possible simplification of above by applying some of the identities of Boolean algebra:
F2 = x’y’z + x’yz + xy’ --- (a)
= x’z(y’ + y) + xy’
= x’z + xy’ ---(b)
The function is reduced to only two terms and can be implemented with gates as shown
below:
Since both expressions produce the same truth table, they are equivalent. Therefore, the two
circuits have the same outputs for all the inputs of the three variables. Each circuit implements
the same identical function, but the one with fewer gates and fewer inputs to gates is preferable
because it requires fewer wires and components. In general, there are many equivalent
representations of a logic function. Finding the most economic representation of the logic is an
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important design task.

Algebraic Manipulation:
• When a Boolean expression is implemented with logic gates, each term requires a gate
and each variable within the term designates an input to the gate.
• Literal to be a single variable within a term, in complemented or uncomplemented form.
• The function F2 = x’y’z + x’yz + xy’ has three terms and eight literals, and the
function x’z + xy’ has two terms and four literals.
• By reducing the number of terms, the number of literals, or both in a Boolean
expression, we obtain a simpler circuit.
• The manipulation of Boolean algebra consists of reducing an expression for obtaining a
simpler circuit.
• For complex Boolean functions and many different outputs, designers of digital circuits
use computer minimization programs that are capable of producing optimal circuits
with millions of logic gate.
Complement of a Function:
The complement of a function F is F’ and is obtained from an interchange of 0’s for 1’s
and 1’s for 0’s in the value of F.
• The complement of a function is derived algebraically through DeMorgan’s theorems.
• DeMorgan’s theorems can be extended to three or more variables.
• The three‐variable form of the first DeMorgan’s theorem is derived as follows.
DeMorgan’s theorems for any number of variables is same as the two‐variable case in form.
These theorems can be generalized as follows
The generalized form of DeMorgan’s theorems states that the complement of a function is
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obtained by interchanging AND and OR operators and complementing each literal.
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DIGITAL LOGIC GATES:

Boolean functions are expressed in terms of AND, OR, and NOT operations, it is easier
to implement a Boolean function with these types of gates.
Factors to be considered for the construction of other types of logic gates are
• The feasibility and economy of producing the gate with physical components,
• The possibility of extending the gate to more than two inputs,
• The basic properties of the binary operator, such as commutativity and
associativity, and the ability of the gate to implement Boolean functions alone or in
conjunction with other gates.
• The graphic symbols and truth tables of the eight gates are shown below. Each gate has
one or two binary input variables, designated by x and y, and one binary output variable
F.
• The inverter circuit inverts the input value, producing the NOT, or complement,
function. The small circle in the output of the graphic symbol of an inverter (referred
to as a bubble) designates the logic complement.
• The triangle symbol by itself designates a buffer circuit. A buffer produces the transfer
function, but does not produce a logic operation. This circuit is used for power
amplification of the signal and is equivalent to two inverters connected in cascade.
• The NAND function is the complement of the AND function.
• The NOR function is the complement of the OR function.
• NAND and NOR gates are used extensively as standard logic gates and are more
popular than the AND and OR gates. This is because NAND and NOR gates are easily
constructed with transistor circuits and because digital circuits can be easily
implemented with them.
Extension to Multiple Inputs:
The gates shown below - except for the inverter and buffer can be extended to have
more than two inputs. A gate can be extended to have multiple inputs if the binary operation
it represents is commutative and associative. The AND and OR operations, defined in
Boolean algebra, possess these two properties.
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Positive and Negative Logic:

The binary signal at the inputs and outputs of any gate has one of two values, except
during transition. One signal value represents logic 1 and the other logic 0. Since two signal
values are assigned to two logic values, there exist two different assignments of signal level to
logic value, as shown in below figure. The higher signal level is designated by H and the lower
signal level by L.
Choosing the high‐level H to represent logic 1 defines a positive logic system. Choosing the
low‐level L to represent logic 1 defines a negative logic system. Hardware digital gates are
defined in terms of signal values such as H and L. It is up to the user to decide on a positive or
negative logic polarity. Consider, for example, the electronic gate shown below in Fig. (b). The truth
table for this gate is listed in Fig. (a). It specifies the physical behavior of the gate when H is 3 V and L
is 0 V. The truth table of Fig. (c) assumes a positive logic assignment, with H = 1 and L =0. This truth
table is the same as the one for the AND operation. The graphic symbol for a positive logic AND gate
is shown in Fig. (d).
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Now consider the negative logic assignment for the same physical gate with L = 1 and H= 0.
The result is the truth table of Fig. (e). This table represents the OR operation, even though the
entries are reversed. The graphic symbol for the negative logic OR gate is shown in Fig. (f).
The small triangles in the inputs and output designate a polarity indicator, the presence of which
along a terminal signifies that negative logic is assumed for the signal.
Thus, the same physical gate can operate either as a positive‐logic AND gate or as a negative‐
logic OR gate. The conversion from positive logic to negative logic and vice versa is essentially
an operation that changes 1’s to 0’s and 0’s to 1’s in both the inputs and the output of a gate.
Now onwards, we will not use negative logic gates and will assume that all gates operate with
a positive logic assignment.
The Map Method:

Gate-level minimization is the design task of finding an optimal gate-level implementation
of the Boolean functions describing a digital circuit. This task is well understood, but is difficult
to execute by manual methods when the logic has more than a few inputs. Fortunately,
computer-based logic synthesis tools can minimize a large set of Boolean equations efficiently
and quickly. Nevertheless, it is important that a designer understand the underlying
mathematical description and solution of the problem.
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NAND and NOR Implementation:

Digital circuits are constructed with NAND or NOR gates rather than with AND and OR
gates.
Why?
NAND and NOR gates are easier to fabricate with electronic components and are the
basic gates used in all IC digital logic families. Because of the prominence of NAND and NOR
gates in the design of digital circuits, rules and procedures have been developed for the
conversion from Boolean functions given in terms of AND, OR, and NOT into equivalent
NAND and NOR logic diagrams.
NAND Circuits:
The NAND gate is said to be a universal gate because any logic circuit can be
implemented with it. A convenient way to implement a Boolean function with NAND gates is
to obtain the simplified Boolean function in terms of Boolean operators and then convert the
function to NAND logic. The conversion of an algebraic expression from AND, OR, and
complement to NAND can be done by simple circuit manipulation techniques that change
AND–OR diagrams to NAND diagrams.
Fig: Logic operations with NAND gates
Fig: Two graphic symbols for a three-input NAND gates
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NOR Implementation:
The NOR operation is the dual of the NAND operation. Therefore, all procedures and
rules for NOR logic are the duals of the corresponding procedures and rules developed for
NAND logic. The implementation of the complement(NOT), OR, and AND operations with
NOR gates is shown below.
Fig: Logic operations with NOR gates
Fig: Two graphic symbols for the NOR Gate.

The general procedure for converting a multilevel AND–OR diagram into an NAND or NOR
gates is as follows:
1. Write the logic diagram for the given expression.
2. Replace the basic gates (NOT, OR and AND gates with the its equivalent NAND/NOR
gates).
3. Check for the 2 inverters connected one after the other.
4. If you find so, remove those and rewrite the circuit diagram.
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Other Hardware Description Language – Verilog Model of a simple circuit.

Manual methods for designing logic circuits are feasible only when the circuit is small.
For practical circuit, designers use computer-based design tools.
Why Computer-based design tools?

• Computer-based design tools decreases the effort of a designer.
• Reduce the risk of producing a flawed design.
• Prototype integrated circuits are too expensive and time consuming to build.
• So, all modern design tools rely on a hardware description language to describe, design, and test
a circuit in software before it is ever manufactured.
A Hardware Description Language (HDL):

Is a computer-based language that describes the hardware of digital systems in a textual
form. It resembles an ordinary computer programming language, such as C, but is specifically
oriented to describing hardware structures and the behavior of logic circuits. It can be used to
represent logic diagrams, truth tables, Boolean expressions, and complex abstractions of the
behavior of a digital system. Example, an HDL description of an AND gate describes how the logic
value of the gate’s output is determined by the logic values of its inputs.
Why HDL?
As a documentation language, an HDL is used to represent and document digital systems
in a form that can be read by both humans and computers. It is suitable as an exchange language
between designers. The language content can be stored, retrieved, edited, and transmitted
easily and processed by computer software in an efficient manner.
Where we use HDL ?

• HDLs are used in several major steps in the design flow of an integrated circuit: design
entry, functional simulation or verification, logic synthesis, timing verification, and
fault simulation.
• Design entry creates an HDL-based description of the functionality that is to be
implemented in hardware. It may be Boolean logic equations, truth tables etc.
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• Logic simulation displays wave forms of the input and the output signals. Simulation
detects functional errors in a design without having to physically create and operate the
circuit.
• Logic synthesis is the process of deriving a list of physical components and their
interconnections (called a netlist) from the model of a digital system described in an
HDL. It produces a database describing the elements and structure of a circuit. The
netlist is used to fabricate an integrated circuit.
• Timing verification confirms that the fabricated, integrated circuit will operate at a
specified speed. Because each logic gate in a circuit has a propagation delay, a signal
transition at the input of a circuit cannot immediately cause a change in the logic value
of the output of a circuit.
• Fault simulation compares the behavior of an ideal circuit with the behavior of a circuit
that contains a process-induced flaw. Dust and other particulates in the atmosphere of
the clean room can cause a circuit to be fabricated with a fault.
There are two standard HDLs that are supported by the IEEE: VHDL and Verilog.
VHDL:
• VHDL is a Department of Defense–mandated language.
• The V in VDHL stands for VHSIC, an acronym for Very High-Speed Integrated
Circuit.
• VHDL is more difficult to learn than Verilog.
• Because Verilog is an easier language than VHDL to describe, learn, and use.
Verilog HDL:
The Verilog HDL was initially approved as a standard HDL in 1995; revised
and enhanced versions of the language were approved in 2001 and 2005.
Programming in Verilog HDL:

A Verilog model is composed of text using keywords, of which there are about 100.
Keywords are predefined lowercase identifiers that define the language constructs. Examples
of keywords are:
⚫ module,
⚫ endmodule,
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⚫ input,
⚫ output,
⚫ wire,
⚫ and,
⚫ or, &
⚫ not.
Any text between two forward slashes ( // ) and the end of the line is a comment and will have
no effect on a simulation. Multiline comments begin with / * and terminate with * /. Blank
spaces are ignored, but they may not appear within the text of a keyword, a user-specified
identifier, an operator, or the representation of a number. Verilog is case sensitive. e.g., not is
not the same as NOT. A module is the fundamental descriptive or declaration unit in the
Verilog language. It is declared by the keyword module and must always be terminated by the
keyword endmodule.
Example:
The HDL description of the above circuit is given below.
• The keyword module is followed by a name and a list of ports.

• The name ( Simple_Circuit) is an identifier. Identifiers are names given to modules,
variables and other elements of the language. In general, we choose meaningful names
for modules.
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• Identifiers are composed of alpha numeric characters and the underscore (_), and are
case sensitive. Identifiers must start with an alphabetic character or an underscore, but
they cannot start with a number.
• The ports are the inputs and outputs of the circuit.
• The port list is enclosed in parentheses, and commas are used to separate elements of the
list. The statement is terminated with a semicolon (;).
• The keywords input and output specify which of the ports are inputs and which are
outputs.
• Internal connections are declared as wires.
• The keywords and, not, & or are the (predefined) primitive gates.
• Each gate instantiation consists of an optional name (such as G1, G2 , etc.) followed by
the gate output and inputs separated by commas and enclosed within parentheses.
• Note: The output of a primitive must be listed first, but the inputs and outputs of a module
may be listed in any order.
• Each statement must be terminated with a semicolon. but there is no semicolon after
• endmodule.
• The module description ends with the keyword endmodule.
Distinction between the terms declaration and instantiation.

• Declaration specifies the input–output behavior of the hardware that it represents.
• Instantiation of the Predefined primitives (eg. Gates like and, or, not) are used since
their definition(declaration) is specified by the language and is not subject to change by
the user.
• The input–output behavior of the circuit is specified by the description because the
behavior of each logic gate is defined. Thus, an HDL-based model can be used to
simulate the circuit that it represents.
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Gate Delays:
• All physical circuits exhibit a propagation delay between the input and the output.
• When an HDL model of a circuit is simulated, it is sometimes necessary to specify the
amount of delay from the input to the output of its gates.
• The timescale directive (‘timescale 1 ns / 1 ps) specifies that the numerical values in the
model are to be interpreted in units of nanosecond swith a precision of picoseconds.
• Eg: and G1 #30 (w1, A, B); // Propagation delay: 30 ns.
Boolean Expressions:
Boolean equations describing combinational logic are specified in Verilog with a
continuous assignment statement consisting of the keyword assign followed by a Boolean
expression. Verilog uses the symbols & ( AND) / (OR) ~ NOT (complement).
Write the Verilog HDL for the following two boolean expressions:
E = A + BC + B’D
F = B’C + BC’D’
module Circuit_Boolean_CA (E, F, A, B, C, D); output E, F;

input A, B, C, D;
assign E = A || (B && C) || ((!B) && D);
assign F = ((!B) && C) || (B && (!C) && (!D)); endmodule
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Digital Design & Computer Organization (BCS302) Module:1 Introduction to Digital Design

Digital Design and Computer Organization BCS301

Definition of Binary Logic:

Fig 1: Signal levels for binary logic values.

Fig 2: Input–output signals for gates.

Fig 3: Symbols for digital logic circuits.

Basic Theorems and Properties of Boolean Algebra:

Fig: Gate implementation of F1= x + y’z

How & why?

important design task.

obtained by interchanging AND and OR operators and complementing each literal.

DIGITAL LOGIC GATES:

Positive and Negative Logic:

The Map Method:

NAND and NOR Implementation:

Fig: Logic operations with NAND gates

Fig: Two graphic symbols for a three-input NAND gates

Fig: Logic operations with NOR gates

Fig: Two graphic symbols for the NOR Gate.

Other Hardware Description Language – Verilog Model of a simple circuit.

Why Computer-based design tools?

A Hardware Description Language (HDL):

Where we use HDL ?

Programming in Verilog HDL:

The HDL description of the above circuit is given below.

• The keyword module is followed by a name and a list of ports.

Distinction between the terms declaration and instantiation.

module Circuit_Boolean_CA (E, F, A, B, C, D); output E, F;

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