PIPELINING

SHREYA – 22X046
SHREENITHI- 22X045
SRI HARINI- 22X050
NIVIKA- 22X028
RIVENTHIGA- 22X038
AGENDA
Parallel Processing
Pipelining
Arithmetic Pipeline
Instruction Pipeline
RISC Pipeline
 PARALLEL
PROCESSING
Parallel processing is a term used to denote a large
class of techniques that are used to provide simultaneous
data-processing tasks for the purpose of increasing the
computational speed of a computer system .
Instead of processing each instruction sequentially
as in a convention computer, a parallel processing system
is able to perform concurrent data processing to archieve
faster execution time.

For example , While an instruction is being executed in

the ALU , the next instruction can be read from memory.
 FLYNN’S CLASSIFICATION
Flynn’s classification divides computers into four major groups as
follows

1. Single instruction stream , Single data stream

2. Single instruction stream , Multiple data stream
3. Mutiple instruction stream , Single data stream
4. Mutiple instruction stream , Multiple data stream

One type of parallel processing that does not fit Flynn’s classification is
Pipelining
Under this parallel processing there are 3 main topics they are
as follows
1. Pipeline processing
2. Vector processing
3. Array processors

• Pipelining processing is an implementation technique

where arithmetic suboperations or the phases of a
computer instruction cycle overlap in execution.

• Vector processing deals with computations involving

large vectors and matrices

• Array processors perform computations on large arrays

of data
 PIPELINING
technique of decomposing a sequential
process into suboperations
 PIPELINING
• Pipelining is a technique of decomposing a sequential process into suboperations,
with each subprocess being executed in a special dedicated segment that operates
concurrently with all other segments.
• The result obtained from the computation in each segment is transferred to the
next segment in the pipeline
• The overlapping of computation is made possible b associating a register with each
segment in the pipeline
• The register provide isolation between each segment so that each can operate on
distinct data simultaneously
Example
for i = 1, 2, 3, ……., 7
( Ai* Bi + Ci )
Input Ai, and Bi
Stored in R1 ← Ai, R2 ← Bi
Multiply, and input Ci
Stored in R3 ← R1 * R2, R4 ← Ci
Add Ci to the product
Stored in R5 ← R3 + R4
 WHY PIPELINE ?
• Any operations that can be decomposed into a sequence of suboperations of about the same
complexity can be implemented by a pipeline processor. The technique is efficient for those
applications that need to repeat the same task many times with different sets of data.

• The behaviour of the pipeline can be illustrated with a space- time diagram. This is a diagram that
shows the segment utilization as a function of time. The horizontal axis displays the time in clock
cycles and the vertical axis gives the segment number.

• There are various reasons why the pipeline cannot operate at its maximum theoretical rate.
Different segments may take different times to complete their suboperation. The clock cycle must
be chosen to equal the time delay of the segment with the maximum propagation time.
SPACE – TIME DIAGRAM FOR PIPELINE
Two types of pipeline :

1. ARITHMETIC PIPELINE
2. INSTRUCTION PIPELINE
 ARITHMETIC PIPELINE
Pipeline arithmetic units are found in very high speed computers. They are used to
implement floating-point
Operations, multiplication of fixed –point numbers, and similar computations
encountered in scientific problems.

A pipeline multiplier is essentially an array multiplier

Example of a pipeline unit for floating point addition and subtraction

The inputs to the floating-point adder pipeline are two normalized floating
point binary numbers

X=A*2^a

Y=B*2^b
 ARITHMETIC PIPELINE
The floating- point addition and subtraction can be performed in four segments. The
registers labeled R are placed between the segments to store intermediate results.

The suboperations that are performed in the four segments are:

1.Compare the exponents.

2.Align the mantissas.

3.Add or subtract the mantissas.

4.Normalize the result.

 INSTRUCTION PIPELINE
Pipeline processing can occur not only in the data stream but in the instruction
stream as well.

An instruction pipeline reads consecutive instructions from memory while

previous instructions are being executed in other segments.

This causes the instruction fetch and execute phases to overlap and perform
simultaneous operations.

Degression: Instruction may cause a branch out of sequence.

In that case the pipeline must be emptied and all the instructions that have been
read from memory after the branch instruction must be discarded.

Eg: FOUR SEGMENT PIPELINE

 SEQUENCE OF STEPS

FETCH DECODE CALCULATE EXECUTE STORE

& FETCH

Calculate the
Fetch the instruction Decode the effective address & Execute the Store the result in the
from memory instruction fetch operands from instruction proper place
memory
4 SEGMENT INSTRUCTION PIPELINE
•
 CONFLICTS

In general, There are three major difficulties that cause the instruction
pipeline to deviate from its normal operation.
RESOURCE CONFLICTS caused by access to memory by two segments at
the same time, Most of these conflicts can be resolved by using separate
instruction and data memories
DATA DEPENDENCY conflicts arise when an instruction depends on the
result of a previous instruction, but this result is not yet available
BRANCH DIFFICULTIES arise from branch and other instructions that
change the value of PC.
 CONFLICTS
DATA DEPENDENCY OPERAND FORWARDING
HARDWARE INTERLOCKS DELAYED LOAD

HANDLING BRANCH INSTRUCTIONS

PREFETCH TARGET LOOP BUFFER

INSTRUCTION BRANCH PREDICTION
BRANCH TARGET BUFFER DELAYED BRANCH
 RISC PIPELINE
The reduced instruction set computer ( RISC ) . Among
characteristics attributed to RISC is its ability to use an efficient
instruction pipeline.
The simplicity of the instruction set can be utilized to
implement an instruction pipeline using a small number of
suboperations, with each being executed in a one clock cycle.
All data manipulation instructions have register-to-register
operations.
Since all operands are in registers , there is no need for
calculating an effective address or fetching operands from
memory.
The data transfer instructions in RISC are limited to load and
store instructions.
3 SEGMENT INSTRUCTION PIPELINE
 DELAYED LOAD

DELAY 4 INSTRUCTIONS ADVANTAGE

The advantage of the
If the three segment
delayed load approach
pipeline proceeds without LOAD : R1 <- M[address 1 ] is that the data
interruptions , there will LOAD: R2 <- M[address 2 ] dependency is taken
be a data conflict in
ADD: R3 <- R1 + R2 care of by the
instruction 3 because the
STORE: M[ADDRESS 3] <- complier rather than
operand in R2 is not yet
R3 the hardware. This
available in the A
results in a simpler
segment.
hardware segment
Presentation title 28

DELAYED BRANCH

DELAYED BRANCH REARRANGE PROCESS

• The method used in most • The complier for a • Load from memory to R1
RISC processors is to rely processor that uses delayed • Increment R2
on the complier redefine branched is designed to
• Add R3 to R4
the branches so that they analyze the instructions
effect at the proper time in before and after the branch • Subtract R5 from R6
the pipeline. This method is and rearrange the program • Branch to address X
referred to as Delayed sequence by inserting
branch useful instructions in the
delay steps
QUESTIONS
1. WHICH GENERATION INTRODUCED THE
CONCEPT OF PARALLEL PROCESSING ?
2. WHAT ARE FIVE SEQUENCE STEPS IN
PIPELINING ?
3. WHAT ARE TWO TYPES OF PIPELINING ?
4. WHAT IS PIPELINING EFFICIENCY ?
QUESTIONS

5. ANY TWO DISADVANTAGES OF

PIPELINING ?
6. WHAT IS MAIN USE OF ARITHMETIC
PIPELINE ?
7. HOW MANY PROCESSORS ARE USED
IN PIPELINING ?
THANK
YOU