Operating Systems:

Instruction Processing

Dr Wilson Sakpere
Department of Computer Science
Lead City University, Ibadan, Nigeria
- 09137792962; - [email protected]
 Contents
• Instruction Execution
• Instruction Categories
• Interrupts
• Instruction Cycle with Interrupts
• Program Timing: I/O Wait
• Interrupt Processing
• Memory
• The Memory Hierarchy
• Cache Memory
• Cache Principles
• Cache Design
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 Instruction Execution
• A program to be executed by a processor consists of a set of instructions
stored in memory. In its simplest form, instruction processing consists of two
steps: The processor reads (fetches) instructions from memory one at a time
and executes each instruction. Program execution consists of repeating the
process of instruction fetch and instruction execution. Instruction execution
may involve several operations and depends on the nature of the instruction.
The processing required for a single instruction is called an instruction cycle.
Using a simplified two-step description, the instruction cycle is depicted below.

Basic Instruction Cycle

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 Instruction Execution…
• The two steps are referred to as the fetch stage and the execute stage.
Program execution halts only if the processor is turned off, some sort of
unrecoverable error occurs, or a program instruction that halts the
processor is encountered.
• At the beginning of each instruction cycle, the processor fetches an
instruction from memory. Typically, the program counter (PC) holds the
address of the next instruction to be fetched. Unless instructed
otherwise, the processor always increments the PC after each
instruction fetch so it will fetch the next instruction in sequence (i.e., the
instruction located at the next higher memory address).
• For example, consider a simplified computer in which each instruction
occupies one 16-bit word of memory. Assume that the program counter
is set to location 300. The processor will next fetch the instruction at
location 300. On succeeding instruction cycles, it will fetch instructions
from locations 301, 302, 303, and so on. This sequence may be altered.
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 Instruction Categories
• The fetched instruction is loaded into the instruction register (IR). The
instruction contains bits that specify the action the processor is to take.
The processor interprets the instruction and performs the required
action. In general, these actions fall into four categories:
Processor-memory: Data may be transferred from processor to memory, or from
memory to processor.
Processor-I/O: Data may be transferred to or from a peripheral device by
transferring between the processor and an I/O module.
Data processing: The processor may perform some arithmetic or logic operation
on data.
Control: An instruction may specify that the sequence of execution be altered.
For example, the processor may fetch an instruction from location 149, which
specifies that the next instruction be from location 182. The processor sets the
program counter to 182. Thus, on the next fetch stage, the instruction will be
fetched from location 182 rather than 150.
• An instruction’s execution may involve a combination of these actions.
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 Interrupts
• Virtually all computers provide a mechanism by which other modules (I/O,
memory) may interrupt the normal sequencing of the processor. The Table
below lists the most common classes of interrupts.
Program Generated by some condition that occurs as a result of an
instruction execution, such as arithmetic overflow, division by
zero, attempt to execute an illegal machine instruction, or
reference outside a user’s allowed memory space.
Timer Generated by a timer within the processor. This allows the
operating system to perform certain functions on a regular basis.
I/O Generated by an I/O controller, to signal normal completion of an
operation or to signal a variety of error conditions.
Hardware failure Generated by a failure, such as power failure or memory parity
error.
Classes of Interrupts
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 Interrupts…
• Interrupts are provided primarily to improve processor utilisation. For
example, most I/O devices are much slower than the processor.
• Suppose that the processor is transferring data to a printer using the
instruction cycle, after each write operation, the processor must pause
and remain idle until the printer catches up. The length of this pause
may be on the order of many thousands or even millions of instruction
cycles. Clearly, this is a very wasteful use of the processor.
• To give a specific example, consider a PC that operates at 1 GHz, which
would allow roughly 109 instructions per second. A typical hard disk has
a rotational speed of 7200 revolutions per minute for a half-track
rotation time of 4 ms, which is 4 million times slower than the processor.

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Program Flow With and Without Interrupts

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 Interrupts and the Instruction Cycle
• With interrupts, the processor can be engaged in executing other
instructions while an I/O operation is in progress.
• From the Figure in slide 8, the user program reaches a point at which it
makes a system call in the form of a WRITE call. The I/O program that is
invoked in this case consists only of the preparation code and the actual
I/O command. After these few instructions have been executed, control
returns to the user program.
• Meanwhile, the external device is busy accepting data from computer
memory and printing it. This I/O operation is conducted concurrently
with the execution of instructions in the user program.

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 Interrupts and the Instruction Cycle…
• When the external device becomes ready to be serviced (that
is, when it is ready to accept more data from the processor) the
I/O module for that external device sends an interrupt request
signal to the processor.
• The processor responds by suspending operation of the current
program; branching off to a routine to service that I/O device
(known as an interrupt handler); and resuming the original
execution after the device is serviced.
• An interrupt can occur at any point in the main program, not
just at one specific instruction.

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 Interrupts and the Instruction Cycle…
• For the user program, an interrupt suspends the normal sequence of execution. When the
interrupt processing is completed, execution resumes. Thus, the user program does not have
to contain any special code to accommodate interrupts; the processor and the OS are
responsible for suspending the user program, then resuming it at the same point.
• To accommodate interrupts, an interrupt stage is added to the instruction cycle.

Instruction Cycle with Interrupts

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 Instruction Cycle with Interrupts
• In the interrupt stage, the processor checks to see if any interrupts have
occurred, indicated by the presence of an interrupt signal.
• If no interrupts are pending, the processor proceeds to the fetch stage
and fetches the next instruction of the current program. If an interrupt is
pending, the processor suspends execution of the current program and
executes an interrupt-handler routine.
• The interrupt-handler routine is generally part of the OS. Typically, this
routine determines the nature of the interrupt and performs whatever
actions are needed.
• In the example we have been using, the handler determines which I/O
module generated the interrupt and may branch to a program that will
write more data out to that I/O module.
• When the interrupt-handler routine is completed, the processor can
resume execution of the user program at the point of interruption.
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 Instruction Cycle with Interrupts…
• There is some overhead involved in this process.
• Extra instructions must be executed (in the interrupt handler)
to determine the nature of the interrupt and to decide on the
appropriate action.
• However, because of the relatively large amount of time that
would be wasted by simply waiting on an I/O operation, the
processor can be employed much more efficiently with the use
of interrupts.

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Program Timing: I/O Wait
• To appreciate the gain in efficiency, the time required
for the I/O operation is relatively short: less than the
time to complete the execution of instructions
between write operations in the user program. The
more typical case, especially for a slow device such as
a printer, is that the I/O operation will take much more
time than executing a sequence of user instructions.
The user program reaches the second WRITE call
before the I/O operation spawned by the first call is
complete. The result is that the user program is hung
up at that point. When the preceding I/O operation is
completed, this new WRITE call may be processed,
and a new I/O operation may be started.
• The Figure shows the timing for this situation with and
without the use of interrupts. There is still a gain in
efficiency, because part of the time during which the
I/O operation is underway overlaps with the execution
of user instructions.
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 Simple Interrupt Processing
• An interrupt triggers several events,
both in the processor hardware
and in software. The Figure shows a
typical sequence. When an I/O
device completes an I/O operation,
the following sequence of
hardware events occurs:
1. The device issues an interrupt signal
to the processor.
2. The processor finishes execution of
the current instruction before
responding to the interrupt.
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 Interrupt Processing
3. The processor tests for a pending interrupt request, determines there
is one, and sends an acknowledgment signal to the device that issued
the interrupt. The acknowledgment allows the device to remove its
interrupt signal.
4. The processor next needs to prepare to transfer control to the
interrupt routine. To begin, it saves information needed to resume the
current program at the point of interrupt. The minimum information
required is the program status word (PSW) and the location of the
next instruction to be executed, which is contained in the program
counter (PC). The PSW contains status information about the currently
running process, including memory usage information, condition
codes, and other status information such as an interrupt
enable/disable bit and a kernel/user-mode bit.
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 Interrupt Processing…
5. The processor then loads the program counter with the entry location of the
interrupt-handling routine that will respond to this interrupt. Depending on
the computer architecture and OS design, there may be a single program,
one for each type of interrupt, or one for each device and each type of
interrupt. If there is more than one interrupt-handling routine, the processor
must determine which one to invoke. This information may have been
included in the original interrupt signal, or the processor may have to issue a
request to the device that issued the interrupt to get a response that
contains the needed information.
• Once the program counter has been loaded, the processor proceeds
to the next instruction cycle, which begins with an instruction fetch.
Because the instruction fetch is determined by the contents of the
program counter, control is transferred to the interrupt-handler
program. The execution of this program results in the following
operations:
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 Interrupt Processing…
6. At this point, the program counter and PSW relating to the
interrupted program have been saved on the control stack. However,
there is information that is considered part of the state of the
executing program. In particular, the contents of the processor
registers need to be saved, because these registers may be used by
the interrupt handler. So, all these values, plus any other state
information, need to be saved. Typically, the interrupt handler will
begin by saving the contents of all registers on the stack.
7. The interrupt handler may now proceed to process the interrupt.
This includes an examination of status information relating to the I/O
operation or other event that caused an interrupt. It may also involve
sending additional commands or acknowledgments to the I/O device.

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 Interrupt Processing…
8. When interrupt processing is complete, the saved register values are
retrieved from the stack and restored to the registers.
9. The final act is to restore the PSW and program counter values from
the stack. As a result, the next instruction to be executed will be from
the previously interrupted program.
• It is important to save all the state information about the
interrupted program for later resumption. This is because the
interrupt is not a routine called from the program. Rather, the
interrupt can occur at any time, and therefore at any point in
the execution of a user program. Its occurrence is
unpredictable.
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 Memory
• The design constraints on a computer’s memory can be summed up by
three questions: How much? How fast? How expensive?
• The question of how much is somewhat open-ended. If the capacity is
there, applications will likely be developed to use it. The question of
how fast is, in a sense, easier to answer. To achieve greatest
performance, the memory must be able to keep up with the processor.
That is, as the processor is executing instructions, we would not want it
to have to pause waiting for instructions or operands. The final question
must also be considered. For a practical system, the cost of memory
must be reasonable in relationship to other components.
• As might be expected, there is a trade-off among the three key
characteristics of memory: capacity, access time, and cost.

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 The Memory Hierarchy
• A variety of technologies are used to implement memory systems. And
across this spectrum of technologies, the following relationships hold:
Faster access time, greater cost per bit
Greater capacity, smaller cost per bit
Greater capacity, slower access speed
• The dilemma facing the designer is clear. The designer would like to use
memory technologies that provide for large-capacity memory, both
because the capacity is needed and because the cost per bit is low.
However, to meet performance requirements, the designer needs to use
expensive, relatively lower-capacity memories with fast access times.
• The way out of this dilemma is to not rely on a single memory component
or technology, but to employ a memory hierarchy.

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The Memory Hierarchy…

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 The Memory Hierarchy…
• A typical hierarchy is illustrated in the Figure on the following slide. As one
goes down the hierarchy, the following occur:
a. Decreasing cost per bit
b. Increasing capacity
c. Increasing access time
d. Decreasing frequency of access to the memory by the processor
• Thus, smaller, more expensive, faster memories are supplemented by larger,
cheaper, slower memories. The key to the success of this organisation is the
decreasing frequency of access at lower levels.
• The fastest, smallest and most expensive type of memory consists of the
registers internal to the processor. Typically, a processor will contain a few
dozen such registers, although some processors contain hundreds of
registers.

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 The Memory Hierarchy…
• Skipping down two levels, main memory is the principal internal memory
system of the computer. Each location in main memory has a unique
address, and most machine instructions refer to one or more main
memory addresses.
• Main memory is usually extended with a higher-speed, smaller cache.
The cache is not usually visible to the programmer or, indeed, to the
processor. It is a device for staging the movement of data between main
memory and processor registers to improve performance.
• The three forms of memory just described are typically volatile and
employ semiconductor technology. The use of three levels exploits the
fact that semiconductor memory comes in a variety of types, which
differ in speed and cost.
• Data are stored more permanently on external mass storage devices, of
which the most common are hard disk and removable media, such as
removable disk, tape, and optical storage.
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 The Memory Hierarchy…
• External, nonvolatile memory is also referred to as secondary memory or
auxiliary memory. These are used to store program and data files. They are
usually visible to the programmer only in terms of files and records, as opposed
to individual bytes or words. A hard disk is also used to provide an extension to
main memory known as virtual memory.
• Additional levels can be effectively added to the hierarchy in software. For
example, a portion of main memory can be used as a buffer to temporarily hold
data that are to be read out to disk. Such a technique, sometimes referred to as
a disk cache, improves performance in two ways:
1. Disk writes are clustered. Instead of many small transfers of data, we have a few
large transfers of data. This improves disk performance and minimizes processor
involvement.
2. Some data destined for write-out may be referenced by a program before the next
dump to disk. In that case, the data are retrieved rapidly from the software cache
rather than slowly from the disk.
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 Cache Memory
• Although cache memory is invisible to the OS, it interacts with
other memory management hardware. Also, many of the principles
used in virtual memory schemes are also applied in cache memory.
• On all instruction cycles, the processor accesses memory at least
once, to fetch the instruction, and often one or more additional
times, to fetch operands and/or store results.
• The rate at which the processor can execute instructions is clearly
limited by the memory cycle time (the time it takes to read one
word from or write one word to memory). This limitation has been
a significant problem because of the persistent mismatch between
processor and main memory speeds.

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 Cache Memory…
• Over the years, processor speed has consistently increased more rapidly
than memory access speed. We are faced with a trade-off among speed,
cost, and size. Ideally, main memory should be built with the same
technology as that of the processor registers, giving memory cycle times
comparable to processor cycle times. This has always been too
expensive a strategy. The solution is to exploit the principle of locality by
providing a small, fast memory between the processor and main
memory, namely the cache.
• Cache memory is intended to provide memory access time approaching
that of the fastest memories available, and at the same time support a
large memory size that has the price of less expensive types of
semiconductor memories.

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 Cache Principles
• There is a
relatively large
and slow main
memory
together with
a smaller,
faster cache
memory. The
cache contains
a copy of a
portion of
main memory.
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 Cache Principles…
• When the processor attempts to read a byte or word of memory, a
check is made to determine if the byte or word is in the cache. If so,
the byte or word is delivered to the processor. If not, a block of
main memory, consisting of some fixed number of bytes, is read
into the cache then the byte or word is delivered to the processor.
• Because of the phenomenon of locality of reference, when a block
of data is fetched into the cache to satisfy a single memory
reference, it is likely that many of the near-future memory
references will be to other bytes in the block.
• The Figure in the previous slide depicts the use of multiple levels of
cache. The L2 cache is slower and typically larger than the L1 cache,
and the L3 cache is slower and typically larger than the L2 cache.
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 Cache Design
• Key elements of cache are briefly summarised. Similar design issues
must be addressed in dealing with virtual memory and disk cache
design. They fall into the following categories:
Cache size
Block size
Mapping function
Replacement algorithm
Write policy
Number of cache levels
• Reasonably small caches can have a significant impact on performance.
Another size issue is that of block size: the unit of data exchanged
between cache and main memory.
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 Cache Design…
• Consider beginning with a relatively small block size, then increasing
the size. As the block size increases, more useful data are brought
into the cache with each block transfer.
• The result will be that the hit ratio increases because of the principle
of locality: the high probability that data in the vicinity of a
referenced word are likely to be referenced in the future.
• When a new block of data is read into the cache, the mapping
function determines which cache location the block will occupy. Two
constraints affect the design of the mapping function.

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 Cache Design…
• First, when one block is read in, another may have to be replaced in such a
way as to minimise the probability that we will replace a block that will be
needed in the future. The more flexible the mapping function, the more
scope we must design a replacement algorithm to maximise the hit ratio.
• Second, the more flexible the mapping function, the more complex is the
circuitry required to search the cache to determine if a given block is in the
cache.
• The replacement algorithm chooses (within the constraints of the mapping
function) which block to replace when a new block is to be loaded into the
cache and the cache already has all slots filled with other blocks.
• We would like to replace the block that is least likely to be needed again in
the future. Although it is impossible to identify such a block.
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 Cache Design…
• A reasonably effective strategy is to replace the block that has been in
the cache longest with no reference to it. This policy is referred to as the
least-recently-used (LRU) algorithm. Hardware mechanisms are needed
to identify the LRU block.
• If the contents of a block in the cache are altered, then it is necessary to
write it back to main memory before replacing it. The write policy
dictates when the memory write operation takes place. At one extreme,
the writing can occur every time that the block is updated. At the other
extreme, the writing occurs only when the block is replaced. The latter
policy minimises memory write operations but leaves main memory in
an obsolete state. This can interfere with multiple-processor operation,
and with direct memory access by I/O hardware modules. Finally, it is
now commonplace to have multiple levels of cache, labeled L1 (cache
closest to the processor), L2, and in many cases L3.
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 Homework 2
• Discuss extensively on the history of operating systems
development.

• Submit a word or pdf file on piazza in the hw2 folder and

name the file in the following format: LastName-Initials-
MatricNo-hw2.

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